Eric Lee / smarc-uboot

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Commit 8cb3be2d23991245fcc9cf6486274260365ba94c

Authored by Ye Li
1 parent 8c97ac54bb
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-18456-2 DTS: mx6sx_arm2: Add board DTS for iMX6SX 14x14 ARM2 

Add DTS file for the iMX6SX 14x14 ARM2 from v2017.03

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 6a09251091354b132280010f8156b83c799d618e)
(cherry picked from commit b67bfab4a0699dba9ff55393b19277c4c104f832)

Showing 2 changed files with 1373 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 8cb3be2
... ... @@ -542,6 +542,7 @@
542 542 dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
543 543  
544 544 dtb-$(CONFIG_MX6SX) += \
  545 + imx6sx-14x14-arm2.dtb \
545 546 imx6sx-17x17-arm2.dtb \
546 547 imx6sx-17x17-arm2-ecspi.dtb \
547 548 imx6sx-17x17-arm2-gpmi-weim.dtb \
arch/arm/dts/imx6sx-14x14-arm2.dts
Diff comments   View file @ 8cb3be2
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "imx6sx.dtsi"
  12 +
  13 +/ {
  14 + model = "Freescale i.MX6 SoloX 14x14 ARM2 Board";
  15 + compatible = "fsl,imx6sx-14x14-lpddr2-arm2", "fsl,imx6sx";
  16 +
  17 + backlight {
  18 + compatible = "pwm-backlight";
  19 + pwms = <&pwm3 0 5000000>;
  20 + brightness-levels = <0 4 8 16 32 64 128 255>;
  21 + default-brightness-level = <6>;
  22 + };
  23 +
  24 + clocks {
  25 + codec_osc: codec_osc {
  26 + #clock-cells = <0>;
  27 + compatible = "fixed-clock";
  28 + clock-frequency = <12000000>;
  29 + };
  30 + };
  31 +
  32 + max7322_reset: max7322-reset {
  33 + compatible = "gpio-reset";
  34 + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  35 + reset-delay-us = <1>;
  36 + #reset-cells = <0>;
  37 + };
  38 +
  39 + pxp_v4l2_out {
  40 + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  41 + status = "okay";
  42 + };
  43 +
  44 + regulators {
  45 + compatible = "simple-bus";
  46 +
  47 + reg_3p3v: 3p3v {
  48 + compatible = "regulator-fixed";
  49 + regulator-name = "3P3V";
  50 + regulator-min-microvolt = <3300000>;
  51 + regulator-max-microvolt = <3300000>;
  52 + regulator-always-on;
  53 + };
  54 +
  55 + reg_sdb_vmmc: sdb_vmmc{
  56 + compatible = "regulator-fixed";
  57 + regulator-name = "SD2_SPWR";
  58 + regulator-min-microvolt = <3300000>;
  59 + regulator-max-microvolt = <3300000>;
  60 + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
  61 + off-on-delay = <20000>;
  62 + };
  63 +
  64 + reg_usb_otg1_vbus: usb_otg1_vbus {
  65 + compatible = "regulator-fixed";
  66 + regulator-name = "usb_otg1_vbus";
  67 + regulator-min-microvolt = <5000000>;
  68 + regulator-max-microvolt = <5000000>;
  69 + gpio = <&gpio1 9 0>;
  70 + enable-active-high;
  71 + };
  72 +
  73 + reg_usb_otg2_vbus: usb_otg2_vbus {
  74 + compatible = "regulator-fixed";
  75 + regulator-name = "usb_otg2_vbus";
  76 + regulator-min-microvolt = <5000000>;
  77 + regulator-max-microvolt = <5000000>;
  78 + gpio = <&gpio1 12 0>;
  79 + enable-active-high;
  80 + };
  81 +
  82 + reg_vref_3v3: regulator@0 {
  83 + compatible = "regulator-fixed";
  84 + regulator-name = "vref-3v3";
  85 + regulator-min-microvolt = <3300000>;
  86 + regulator-max-microvolt = <3300000>;
  87 + };
  88 + };
  89 +
  90 + memory {
  91 + reg = <0x80000000 0x40000000>;
  92 + };
  93 +
  94 + sound {
  95 + compatible = "fsl,imx6sx-arm2-sgtl5000",
  96 + "fsl,imx-audio-sgtl5000";
  97 + model = "imx6sx-arm2-sgtl5000";
  98 + cpu-dai = <&ssi1>;
  99 + audio-codec = <&codec>;
  100 + audio-routing =
  101 + "LINE_IN", "Line In Jack",
  102 + "Headphone Jack", "HP_OUT";
  103 + mux-int-port = <1>;
  104 + mux-ext-port = <4>;
  105 + };
  106 +};
  107 +
  108 +&adc1 {
  109 + vref-supply = <&reg_vref_3v3>;
  110 + status = "okay";
  111 +};
  112 +
  113 +&adc2 {
  114 + vref-supply = <&reg_vref_3v3>;
  115 + status = "okay";
  116 +};
  117 +
  118 +&audmux {
  119 + pinctrl-names = "default";
  120 + pinctrl-0 = <&pinctrl_audmux_2>;
  121 + status = "okay";
  122 +};
  123 +
  124 +&cpu0 {
  125 + operating-points = <
  126 + /* kHz uV */
  127 + 996000 1250000
  128 + 792000 1175000
  129 + 396000 1175000
  130 + >;
  131 + fsl,soc-operating-points = <
  132 + /* ARM kHz SOC uV */
  133 + 996000 1250000
  134 + 792000 1175000
  135 + 396000 1175000
  136 + >;
  137 + fsl,arm-soc-shared = <1>;
  138 +};
  139 +
  140 +&reg_arm {
  141 + vin-supply = <&sw1a_reg>;
  142 + regulator-allow-bypass;
  143 +};
  144 +
  145 +&reg_soc {
  146 + vin-supply = <&sw1a_reg>;
  147 + regulator-allow-bypass;
  148 +};
  149 +
  150 +&ecspi4 {
  151 + fsl,spi-num-chipselects = <1>;
  152 + cs-gpios = <&gpio7 4 0>;
  153 + pinctrl-names = "default";
  154 + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
  155 + status = "disabled"; /* pin conflict with USDHC3 */
  156 +
  157 + flash: m25p80@0 {
  158 + #address-cells = <1>;
  159 + #size-cells = <1>;
  160 + compatible = "st,m25p32";
  161 + spi-max-frequency = <20000000>;
  162 + reg = <0>;
  163 + };
  164 +};
  165 +
  166 +&fec1 {
  167 + pinctrl-names = "default";
  168 + pinctrl-0 = <&pinctrl_enet1_1>;
  169 + phy-mode = "rgmii";
  170 + phy-id = <1>;
  171 + fsl,num_tx_queues=<3>;
  172 + fsl,num_rx_queues=<3>;
  173 + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
  174 + fsl,magic-packet;
  175 + status = "okay";
  176 +};
  177 +
  178 +&fec2 {
  179 + pinctrl-names = "default";
  180 + pinctrl-0 = <&pinctrl_enet2_1>;
  181 + phy-mode = "rgmii";
  182 + phy-id = <0>;
  183 + fsl,num_tx_queues=<3>;
  184 + fsl,num_rx_queues=<3>;
  185 + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
  186 + fsl,magic-packet;
  187 + status = "okay";
  188 +};
  189 +
  190 +&flexcan1 {
  191 + pinctrl-names = "default";
  192 + pinctrl-0 = <&pinctrl_flexcan1_1>;
  193 + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
  194 + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  195 + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
  196 + status = "okay";
  197 +};
  198 +
  199 +&flexcan2 {
  200 + pinctrl-names = "default";
  201 + pinctrl-0 = <&pinctrl_flexcan2_1>;
  202 + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
  203 + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  204 + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
  205 + status = "okay";
  206 +};
  207 +
  208 +&gpc {
  209 + fsl,cpu_pdnscr_iso2sw = <0x1>;
  210 + fsl,cpu_pdnscr_iso = <0x1>;
  211 + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
  212 +};
  213 +
  214 +&gpmi {
  215 + pinctrl-names = "default";
  216 + pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  217 + status = "disabled"; /* pin conflict with qspi*/
  218 + nand-on-flash-bbt;
  219 +};
  220 +
  221 +&i2c1 {
  222 + clock-frequency = <100000>;
  223 + pinctrl-names = "default", "gpio";
  224 + pinctrl-0 = <&pinctrl_i2c1_1>;
  225 + pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
  226 + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
  227 + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
  228 + status = "okay";
  229 +
  230 + pmic: pfuze100@08 {
  231 + compatible = "fsl,pfuze200";
  232 + reg = <0x08>;
  233 +
  234 + regulators {
  235 + sw1a_reg: sw1ab {
  236 + regulator-min-microvolt = <300000>;
  237 + regulator-max-microvolt = <1875000>;
  238 + regulator-boot-on;
  239 + regulator-always-on;
  240 + regulator-ramp-delay = <6250>;
  241 + };
  242 +
  243 + sw2_reg: sw2 {
  244 + regulator-min-microvolt = <800000>;
  245 + regulator-max-microvolt = <3300000>;
  246 + regulator-boot-on;
  247 + regulator-always-on;
  248 + };
  249 +
  250 + sw3a_reg: sw3a {
  251 + regulator-min-microvolt = <400000>;
  252 + regulator-max-microvolt = <1975000>;
  253 + regulator-boot-on;
  254 + regulator-always-on;
  255 + };
  256 +
  257 + sw3b_reg: sw3b {
  258 + regulator-min-microvolt = <400000>;
  259 + regulator-max-microvolt = <1975000>;
  260 + regulator-boot-on;
  261 + regulator-always-on;
  262 + };
  263 +
  264 + swbst_reg: swbst {
  265 + regulator-min-microvolt = <5000000>;
  266 + regulator-max-microvolt = <5150000>;
  267 + };
  268 +
  269 + snvs_reg: vsnvs {
  270 + regulator-min-microvolt = <1000000>;
  271 + regulator-max-microvolt = <3000000>;
  272 + regulator-boot-on;
  273 + regulator-always-on;
  274 + };
  275 +
  276 + vref_reg: vrefddr {
  277 + regulator-boot-on;
  278 + regulator-always-on;
  279 + };
  280 +
  281 + vgen1_reg: vgen1 {
  282 + regulator-min-microvolt = <800000>;
  283 + regulator-max-microvolt = <1550000>;
  284 + };
  285 +
  286 + vgen2_reg: vgen2 {
  287 + regulator-min-microvolt = <800000>;
  288 + regulator-max-microvolt = <1550000>;
  289 + };
  290 +
  291 + vgen3_reg: vgen3 {
  292 + regulator-min-microvolt = <1800000>;
  293 + regulator-max-microvolt = <3300000>;
  294 + regulator-always-on;
  295 + };
  296 +
  297 + vgen4_reg: vgen4 {
  298 + regulator-min-microvolt = <1800000>;
  299 + regulator-max-microvolt = <3300000>;
  300 + regulator-always-on;
  301 + };
  302 +
  303 + vgen5_reg: vgen5 {
  304 + regulator-min-microvolt = <1800000>;
  305 + regulator-max-microvolt = <3300000>;
  306 + regulator-always-on;
  307 + };
  308 +
  309 + vgen6_reg: vgen6 {
  310 + regulator-min-microvolt = <1800000>;
  311 + regulator-max-microvolt = <3300000>;
  312 + regulator-always-on;
  313 + };
  314 + };
  315 + };
  316 +};
  317 +
  318 +&i2c2 {
  319 + clock-frequency = <100000>;
  320 + pinctrl-names = "default", "gpio";
  321 + pinctrl-0 = <&pinctrl_i2c2_1>;
  322 + pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
  323 + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  324 + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
  325 + status = "okay";
  326 +
  327 + max7322_1: gpio@68 {
  328 + compatible = "maxim,max7322";
  329 + reg = <0x68>;
  330 + gpio-controller;
  331 + #gpio-cells = <2>;
  332 + resets = <&max7322_reset>;
  333 + };
  334 +
  335 + max7322_2: gpio@69 {
  336 + compatible = "maxim,max7322";
  337 + reg = <0x69>;
  338 + gpio-controller;
  339 + #gpio-cells = <2>;
  340 + resets = <&max7322_reset>;
  341 + };
  342 +
  343 + codec: sgtl5000@0a {
  344 + compatible = "fsl,sgtl5000";
  345 + reg = <0x0a>;
  346 + clocks = <&codec_osc>;
  347 + VDDA-supply = <&vgen4_reg>;
  348 + VDDIO-supply = <&reg_3p3v>;
  349 + };
  350 +};
  351 +
  352 +
  353 +&i2c3 {
  354 + clock-frequency = <100000>;
  355 + pinctrl-names = "default", "gpio";
  356 + pinctrl-0 = <&pinctrl_i2c3_1>;
  357 + pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
  358 + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
  359 + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  360 + status = "okay";
  361 +};
  362 +
  363 +&i2c4 {
  364 + clock-frequency = <100000>;
  365 + pinctrl-names = "default", "gpio";
  366 + pinctrl-0 = <&pinctrl_i2c4_1>;
  367 + pinctrl-1 = <&pinctrl_i2c4_1_gpio>;
  368 + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  369 + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  370 + status = "okay";
  371 +};
  372 +
  373 +&iomuxc {
  374 + pinctrl-names = "default";
  375 + pinctrl-0 = <&pinctrl_hog_1>;
  376 +
  377 + hog {
  378 + pinctrl_hog_1: hoggrp-1 {
  379 + fsl,pins = <
  380 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059
  381 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059
  382 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
  383 + /* CAN1_2_EN */
  384 + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
  385 + /* CAN1_2_STBY_B */
  386 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
  387 + /* CAN1_ERR_B */
  388 + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
  389 + /* CAN2_ERR_B */
  390 + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
  391 + /* SD2_PWROFF */
  392 + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
  393 + >;
  394 + };
  395 + };
  396 +};
  397 +
  398 +&lcdif1 {
  399 + pinctrl-names = "default";
  400 + pinctrl-0 = <&pinctrl_lcdif_dat_0
  401 + &pinctrl_lcdif_ctrl_0>;
  402 + display = <&display0>;
  403 + status = "okay";
  404 +
  405 + display0: display@0 {
  406 + bits-per-pixel = <16>;
  407 + bus-width = <24>;
  408 +
  409 + display-timings {
  410 + native-mode = <&timing0>;
  411 + timing0: timing0 {
  412 + clock-frequency = <33500000>;
  413 + hactive = <800>;
  414 + vactive = <480>;
  415 + hback-porch = <89>;
  416 + hfront-porch = <164>;
  417 + vback-porch = <23>;
  418 + vfront-porch = <10>;
  419 + hsync-len = <10>;
  420 + vsync-len = <10>;
  421 + hsync-active = <0>;
  422 + vsync-active = <0>;
  423 + de-active = <1>;
  424 + pixelclk-active = <0>;
  425 + };
  426 + };
  427 + };
  428 +};
  429 +
  430 +&mlb {
  431 + pinctrl-names = "default";
  432 + pinctrl-0 = <&pinctrl_mlb_1>;
  433 + status = "disabled";/* pin conflict with usdhc2*/
  434 +};
  435 +
  436 +&pwm3 {
  437 + pinctrl-names = "default";
  438 + pinctrl-0 = <&pinctrl_pwm3_0>;
  439 + status = "okay";
  440 +};
  441 +
  442 +&pxp {
  443 + status = "okay";
  444 +};
  445 +
  446 +&qspi2 {
  447 + pinctrl-names = "default";
  448 + pinctrl-0 = <&pinctrl_qspi2_1>;
  449 + status = "okay";
  450 + ddrsmp=<2>;
  451 +
  452 + flash0: n25q256a@0 {
  453 + #address-cells = <1>;
  454 + #size-cells = <1>;
  455 + compatible = "micron,n25q256a", "jedec,spi-nor";
  456 + spi-max-frequency = <29000000>;
  457 + reg = <0>;
  458 + };
  459 +
  460 + flash1: n25q256a@1 {
  461 + #address-cells = <1>;
  462 + #size-cells = <1>;
  463 + compatible = "micron,n25q256a", "jedec,spi-nor";
  464 + spi-max-frequency = <29000000>;
  465 + reg = <1>;
  466 + };
  467 +};
  468 +
  469 +&sai2 {
  470 + pinctrl-names = "default";
  471 + pinctrl-0 = <&pinctrl_sai2_1>;
  472 + status = "disabled";
  473 +};
  474 +
  475 +&spdif {
  476 + pinctrl-names = "default";
  477 + pinctrl-0 = <&pinctrl_spdif_1>;
  478 + status = "disabled";
  479 +};
  480 +
  481 +&ssi1 {
  482 + fsl,mode = "i2s-slave";
  483 + status = "okay";
  484 +};
  485 +
  486 +&snvs_poweroff {
  487 + status = "okay";
  488 +};
  489 +
  490 +&uart1 {
  491 + pinctrl-names = "default";
  492 + pinctrl-0 = <&pinctrl_uart1_1>;
  493 + status = "okay";
  494 +};
  495 +
  496 +&uart2 {
  497 + pinctrl-names = "default";
  498 + pinctrl-0 = <&pinctrl_uart2_1>;
  499 + status = "okay";
  500 +};
  501 +
  502 +&usbh {
  503 + pinctrl-names = "idle", "active";
  504 + pinctrl-0 = <&pinctrl_usbh_1>;
  505 + pinctrl-1 = <&pinctrl_usbh_2>;
  506 + osc-clkgate-delay = <0x3>;
  507 + pad-supply = <&vgen1_reg>;
  508 + status = "okay";
  509 +};
  510 +
  511 +&usbotg1 {
  512 + vbus-supply = <&reg_usb_otg1_vbus>;
  513 + pinctrl-names = "default";
  514 + pinctrl-0 = <&pinctrl_usbotg1_1>;
  515 + disable-over-current;
  516 + status = "okay";
  517 +};
  518 +
  519 +&usbotg2 {
  520 + /*
  521 + * Pin conflict with others, need to switch R580 & R579
  522 + * to B and disable pwm3 to enable it.
  523 + */
  524 + vbus-supply = <&reg_usb_otg2_vbus>;
  525 + disable-over-current;
  526 + pinctrl-names = "default";
  527 + pinctrl-0 = <&pinctrl_usbotg2_1>;
  528 + status = "disabled";
  529 +};
  530 +
  531 +&usdhc2 {
  532 + pinctrl-names = "default";
  533 + pinctrl-0 = <&pinctrl_usdhc2_1>;
  534 + non-removable;
  535 + /* need hw rework to enable signal voltage switch */
  536 + no-1-8-v;
  537 + keep-power-in-suspend;
  538 + enable-sdio-wakeup;
  539 + status = "okay";
  540 +};
  541 +
  542 +&usdhc3 {
  543 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  544 + pinctrl-0 = <&pinctrl_usdhc3_1>;
  545 + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
  546 + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
  547 + bus-width = <8>;
  548 + cd-gpios = <&gpio2 10 0>;
  549 + wp-gpios = <&gpio2 15 0>;
  550 + keep-power-in-suspend;
  551 + enable-sdio-wakeup;
  552 + vmmc-supply = <&reg_sdb_vmmc>;
  553 + status = "okay";
  554 +};
  555 +
  556 +&usdhc4 {
  557 + pinctrl-names = "default";
  558 + pinctrl-0 = <&pinctrl_usdhc4_1>;
  559 + bus-width = <8>;
  560 + non-removable;
  561 + /* need hw rework to enable signal voltage switch */
  562 + no-1-8-v;
  563 + status = "okay";
  564 +};
  565 +
  566 +&wdog1 {
  567 + pinctrl-names = "default";
  568 + pinctrl-0 = <&pinctrl_wdog>;
  569 + fsl,wdog_b;
  570 +};
  571 +
  572 +&iomuxc {
  573 + audmux {
  574 + pinctrl_audmux_1: audmuxgrp-1 {
  575 + fsl,pins = <
  576 + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0
  577 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0
  578 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0
  579 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0
  580 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
  581 + >;
  582 + };
  583 +
  584 + pinctrl_audmux_2: audmuxgrp-2 {
  585 + fsl,pins = <
  586 + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0
  587 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0
  588 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
  589 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0
  590 + >;
  591 + };
  592 +
  593 + pinctrl_audmux_3: audmux-3 {
  594 + fsl,pins = <
  595 + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0
  596 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0
  597 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0
  598 + >;
  599 + };
  600 + };
  601 +
  602 + ecspi4 {
  603 + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
  604 + fsl,pins = <
  605 + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
  606 + >;
  607 + };
  608 +
  609 + pinctrl_ecspi4_1: ecspi4grp-1 {
  610 + fsl,pins = <
  611 + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
  612 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
  613 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
  614 + >;
  615 + };
  616 + };
  617 +
  618 + csi {
  619 + pinctrl_csi_0: csigrp-0 {
  620 + fsl,pins = <
  621 + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
  622 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
  623 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
  624 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
  625 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
  626 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
  627 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
  628 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
  629 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
  630 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
  631 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
  632 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
  633 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
  634 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
  635 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
  636 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
  637 + >;
  638 + };
  639 +
  640 + pinctrl_csi_1: csigrp-1 {
  641 + fsl,pins = <
  642 + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0
  643 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0
  644 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0
  645 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0
  646 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0
  647 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0
  648 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0
  649 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0
  650 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0
  651 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0
  652 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0
  653 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0
  654 +
  655 + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000
  656 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000
  657 + >;
  658 + };
  659 + };
  660 +
  661 + enet1 {
  662 + pinctrl_enet1_1: enet1grp-1 {
  663 + fsl,pins = <
  664 + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
  665 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
  666 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
  667 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
  668 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
  669 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
  670 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
  671 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
  672 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
  673 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
  674 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
  675 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
  676 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
  677 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
  678 + >;
  679 + };
  680 +
  681 + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
  682 + fsl,pins = <
  683 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
  684 + >;
  685 + };
  686 + };
  687 +
  688 + enet2 {
  689 + pinctrl_enet2_1: enet2grp-1 {
  690 + fsl,pins = <
  691 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
  692 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
  693 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
  694 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
  695 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
  696 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
  697 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
  698 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
  699 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
  700 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
  701 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
  702 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
  703 + >;
  704 + };
  705 + };
  706 +
  707 + esai {
  708 + pinctrl_esai_1: esaigrp-1 {
  709 + fsl,pins = <
  710 + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030
  711 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
  712 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
  713 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
  714 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
  715 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
  716 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
  717 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
  718 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
  719 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
  720 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
  721 + >;
  722 + };
  723 +
  724 + pinctrl_esai_2: esaigrp-2 {
  725 + fsl,pins = <
  726 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
  727 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
  728 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
  729 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
  730 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
  731 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
  732 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
  733 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
  734 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
  735 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
  736 + >;
  737 + };
  738 + };
  739 +
  740 + flexcan1 {
  741 + pinctrl_flexcan1_1: flexcan1grp-1 {
  742 + fsl,pins = <
  743 + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
  744 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
  745 + >;
  746 + };
  747 + };
  748 +
  749 + flexcan2 {
  750 + pinctrl_flexcan2_1: flexcan2grp-1 {
  751 + fsl,pins = <
  752 + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
  753 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
  754 + >;
  755 + };
  756 + };
  757 +
  758 + gpmi-nand {
  759 + pinctrl_gpmi_nand_1: gpmi-nand-1 {
  760 + fsl,pins = <
  761 + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
  762 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
  763 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
  764 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
  765 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
  766 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
  767 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
  768 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
  769 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
  770 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
  771 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
  772 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
  773 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
  774 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
  775 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
  776 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
  777 + >;
  778 + };
  779 + };
  780 +
  781 + i2c1 {
  782 + pinctrl_i2c1_1: i2c1grp-1 {
  783 + fsl,pins = <
  784 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
  785 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
  786 + >;
  787 + };
  788 +
  789 + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
  790 + fsl,pins = <
  791 + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1
  792 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1
  793 + >;
  794 + };
  795 +
  796 + pinctrl_i2c1_2: i2c1grp-2 {
  797 + fsl,pins = <
  798 + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
  799 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
  800 + >;
  801 + };
  802 + };
  803 +
  804 + i2c2 {
  805 + pinctrl_i2c2_1: i2c2grp-1 {
  806 + fsl,pins = <
  807 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
  808 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
  809 + >;
  810 + };
  811 +
  812 + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
  813 + fsl,pins = <
  814 + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1
  815 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1
  816 + >;
  817 + };
  818 + };
  819 +
  820 + i2c3 {
  821 + pinctrl_i2c3_1: i2c3grp-1 {
  822 + fsl,pins = <
  823 + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
  824 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
  825 + >;
  826 + };
  827 +
  828 + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
  829 + fsl,pins = <
  830 + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1
  831 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1
  832 + >;
  833 + };
  834 +
  835 + pinctrl_i2c3_2: i2c3grp-2 {
  836 + fsl,pins = <
  837 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
  838 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
  839 + >;
  840 + };
  841 + };
  842 +
  843 + i2c4 {
  844 + pinctrl_i2c4_1: i2c4grp-1 {
  845 + fsl,pins = <
  846 + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
  847 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
  848 + >;
  849 + };
  850 +
  851 + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio {
  852 + fsl,pins = <
  853 + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1
  854 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1
  855 + >;
  856 + };
  857 +
  858 + pinctrl_i2c4_2: i2c4grp-2 {
  859 + fsl,pins = <
  860 + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1
  861 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1
  862 + >;
  863 + };
  864 + };
  865 +
  866 + lcdif1 {
  867 + pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
  868 + fsl,pins = <
  869 + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
  870 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
  871 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
  872 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
  873 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
  874 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
  875 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
  876 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
  877 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
  878 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
  879 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
  880 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
  881 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
  882 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
  883 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
  884 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
  885 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
  886 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
  887 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
  888 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
  889 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
  890 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
  891 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
  892 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
  893 + >;
  894 + };
  895 +
  896 + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
  897 + fsl,pins = <
  898 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
  899 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
  900 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
  901 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
  902 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0
  903 + >;
  904 + };
  905 + };
  906 +
  907 + mlb {
  908 + pinctrl_mlb_1: mlbgrp-1 {
  909 + fsl,pins = <
  910 + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31
  911 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31
  912 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31
  913 + >;
  914 + };
  915 +
  916 + pinctrl_mlb_2: mlbgrp-2 {
  917 + fsl,pins = <
  918 + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31
  919 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31
  920 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31
  921 + >;
  922 + };
  923 + };
  924 +
  925 + mqs {
  926 + pinctrl_mqs_1: mqsgrp-1 {
  927 + fsl,pins = <
  928 + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000
  929 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000
  930 + >;
  931 + };
  932 + };
  933 +
  934 + pwm3 {
  935 + pinctrl_pwm3_0: pwm3grp-0 {
  936 + fsl,pins = <
  937 + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
  938 + >;
  939 + };
  940 +
  941 + pinctrl_pwm3_1: pwm3grp-1 {
  942 + fsl,pins = <
  943 + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
  944 + >;
  945 + };
  946 + };
  947 +
  948 + pwm4 {
  949 + pinctrl_pwm4_0: pwm4grp-0 {
  950 + fsl,pins = <
  951 + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
  952 + >;
  953 + };
  954 + };
  955 +
  956 + qspi1 {
  957 + pinctrl_qspi1_1: qspi1grp_1 {
  958 + fsl,pins = <
  959 + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
  960 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
  961 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
  962 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
  963 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
  964 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
  965 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
  966 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
  967 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
  968 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
  969 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
  970 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
  971 + >;
  972 + };
  973 + };
  974 +
  975 + qspi2 {
  976 + pinctrl_qspi2_1: qspi2grp_1 {
  977 + fsl,pins = <
  978 + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1
  979 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1
  980 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1
  981 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1
  982 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1
  983 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1
  984 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1
  985 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1
  986 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1
  987 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1
  988 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1
  989 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1
  990 + >;
  991 + };
  992 + };
  993 +
  994 + sai1 {
  995 + pinctrl_sai1_1: sai1grp_1 {
  996 + fsl,pins = <
  997 + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030
  998 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030
  999 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030
  1000 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030
  1001 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030
  1002 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030
  1003 + >;
  1004 + };
  1005 +
  1006 + pinctrl_sai1_2: sai1grp_2 {
  1007 + fsl,pins = <
  1008 + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0
  1009 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0
  1010 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0
  1011 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0
  1012 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
  1013 + >;
  1014 + };
  1015 + };
  1016 +
  1017 + sai2 {
  1018 + pinctrl_sai2_1: sai2grp_1 {
  1019 + fsl,pins = <
  1020 + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030
  1021 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030
  1022 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030
  1023 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030
  1024 + >;
  1025 + };
  1026 + };
  1027 +
  1028 +
  1029 + spdif {
  1030 + pinctrl_spdif_1: spdifgrp-1 {
  1031 + fsl,pins = <
  1032 + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0
  1033 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
  1034 + >;
  1035 + };
  1036 +
  1037 + pinctrl_spdif_2: spdifgrp-2 {
  1038 + fsl,pins = <
  1039 + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
  1040 + >;
  1041 + };
  1042 +
  1043 + pinctrl_spdif_3: spdifgrp-3 {
  1044 + fsl,pins = <
  1045 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
  1046 + >;
  1047 + };
  1048 + };
  1049 +
  1050 + uart1 {
  1051 + pinctrl_uart1_1: uart1grp-1 {
  1052 + fsl,pins = <
  1053 + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
  1054 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
  1055 + >;
  1056 + };
  1057 +
  1058 + pinctrl_uart1_2: uart1grp-2 {
  1059 + fsl,pins = <
  1060 + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
  1061 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
  1062 + >;
  1063 + };
  1064 + };
  1065 +
  1066 + uart2 {
  1067 + pinctrl_uart2_1: uart2grp-1 {
  1068 + fsl,pins = <
  1069 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
  1070 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
  1071 + >;
  1072 + };
  1073 +
  1074 + pinctrl_uart2_2: uart2grp-2 {
  1075 + fsl,pins = <
  1076 + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
  1077 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
  1078 + >;
  1079 + };
  1080 + };
  1081 +
  1082 + uart5 {
  1083 + pinctrl_uart5_1: uart5grp-1 {
  1084 + fsl,pins = <
  1085 + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
  1086 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
  1087 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
  1088 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
  1089 + >;
  1090 + };
  1091 +
  1092 + pinctrl_uart5dte_1: uart5dtegrp-1 {
  1093 + fsl,pins = <
  1094 + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
  1095 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
  1096 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
  1097 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
  1098 + >;
  1099 + };
  1100 + };
  1101 +
  1102 + usbh {
  1103 + pinctrl_usbh_1: usbhgrp-1 {
  1104 + fsl,pins = <
  1105 + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030
  1106 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
  1107 + >;
  1108 + };
  1109 +
  1110 + pinctrl_usbh_2: usbhgrp-2 {
  1111 + fsl,pins = <
  1112 + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030
  1113 + >;
  1114 + };
  1115 + };
  1116 +
  1117 + usbotg1 {
  1118 + pinctrl_usbotg1_1: usbotg1grp-1 {
  1119 + fsl,pins = <
  1120 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
  1121 + >;
  1122 + };
  1123 +
  1124 + pinctrl_usbotg1_2: usbotg1grp-2 {
  1125 + fsl,pins = <
  1126 + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
  1127 + >;
  1128 + };
  1129 +
  1130 + pinctrl_usbotg1_3: usbotg1grp-3 {
  1131 + fsl,pins = <
  1132 + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
  1133 + >;
  1134 + };
  1135 + };
  1136 +
  1137 + usbotg2 {
  1138 + pinctrl_usbotg2_1: usbotg2grp-1 {
  1139 + fsl,pins = <
  1140 + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
  1141 + >;
  1142 + };
  1143 +
  1144 + pinctrl_usbotg2_2: usbotg2grp-2 {
  1145 + fsl,pins = <
  1146 + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
  1147 + >;
  1148 + };
  1149 +
  1150 + pinctrl_usbotg2_3: usbotg2grp-3 {
  1151 + fsl,pins = <
  1152 + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
  1153 + >;
  1154 + };
  1155 + };
  1156 +
  1157 + usdhc1 {
  1158 + pinctrl_usdhc1_1: usdhc1grp-1 {
  1159 + fsl,pins = <
  1160 + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
  1161 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
  1162 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  1163 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  1164 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  1165 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  1166 + >;
  1167 + };
  1168 + };
  1169 +
  1170 + usdhc2 {
  1171 + pinctrl_usdhc2_1: usdhc2grp-1 {
  1172 + fsl,pins = <
  1173 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
  1174 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
  1175 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
  1176 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
  1177 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
  1178 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
  1179 + >;
  1180 + };
  1181 + };
  1182 +
  1183 + usdhc3 {
  1184 + pinctrl_usdhc3_1: usdhc3grp-1 {
  1185 + fsl,pins = <
  1186 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
  1187 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
  1188 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
  1189 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
  1190 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
  1191 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
  1192 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
  1193 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
  1194 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
  1195 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
  1196 + >;
  1197 + };
  1198 +
  1199 + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
  1200 + fsl,pins = <
  1201 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
  1202 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
  1203 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
  1204 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
  1205 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
  1206 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
  1207 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
  1208 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
  1209 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
  1210 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
  1211 + >;
  1212 + };
  1213 +
  1214 + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
  1215 + fsl,pins = <
  1216 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
  1217 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
  1218 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
  1219 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
  1220 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
  1221 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
  1222 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
  1223 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
  1224 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
  1225 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
  1226 + >;
  1227 + };
  1228 +
  1229 + };
  1230 +
  1231 + usdhc4 {
  1232 + pinctrl_usdhc4_1: usdhc4grp-1 {
  1233 + fsl,pins = <
  1234 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
  1235 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
  1236 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
  1237 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
  1238 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
  1239 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
  1240 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
  1241 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
  1242 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
  1243 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
  1244 + >;
  1245 + };
  1246 +
  1247 + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
  1248 + fsl,pins = <
  1249 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
  1250 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
  1251 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
  1252 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
  1253 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
  1254 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
  1255 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
  1256 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
  1257 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
  1258 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
  1259 + >;
  1260 + };
  1261 +
  1262 + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
  1263 + fsl,pins = <
  1264 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
  1265 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
  1266 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
  1267 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
  1268 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
  1269 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
  1270 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
  1271 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
  1272 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
  1273 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
  1274 + >;
  1275 + };
  1276 +
  1277 + pinctrl_usdhc4_2: usdhc4grp-2 {
  1278 + fsl,pins = <
  1279 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
  1280 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
  1281 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
  1282 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
  1283 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
  1284 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
  1285 + >;
  1286 + };
  1287 +
  1288 + pinctrl_usdhc4_3: usdhc4grp-3 {
  1289 + fsl,pins = <
  1290 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
  1291 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
  1292 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
  1293 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
  1294 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
  1295 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
  1296 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
  1297 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
  1298 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
  1299 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
  1300 + >;
  1301 + };
  1302 +
  1303 + };
  1304 +
  1305 + wdog {
  1306 + pinctrl_wdog: wdoggrp {
  1307 + fsl,pins = <
  1308 + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
  1309 + >;
  1310 + };
  1311 + };
  1312 +
  1313 + weim {
  1314 + pinctrl_weim_cs0_1: weim_cs0grp-1 {
  1315 + fsl,pins = <
  1316 + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
  1317 + >;
  1318 + };
  1319 +
  1320 + pinctrl_weim_nor_1: weim_norgrp-1 {
  1321 + fsl,pins = <
  1322 + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
  1323 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
  1324 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
  1325 + /* data */
  1326 + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
  1327 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
  1328 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
  1329 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
  1330 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
  1331 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
  1332 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
  1333 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
  1334 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
  1335 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
  1336 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
  1337 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
  1338 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
  1339 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
  1340 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
  1341 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
  1342 + /* address */
  1343 + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
  1344 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
  1345 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
  1346 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
  1347 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
  1348 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
  1349 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
  1350 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
  1351 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
  1352 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
  1353 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
  1354 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
  1355 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
  1356 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
  1357 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
  1358 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
  1359 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
  1360 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
  1361 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
  1362 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
  1363 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
  1364 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
  1365 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
  1366 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
  1367 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
  1368 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
  1369 + >;
  1370 + };
  1371 + };
  1372 +};