Commit 8cc3246a0854e33ae2de951257700415374225dd
Committed by
Larisa Grigore
Larisa Grigore
1 parent
680fbd3551
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
mpxs32v234: pci: fixed PCIe clocking
SBC-S32VEVB has external PCIe clocking. Note that it is not an option to make this configuration available via setting the environment variable 'hwconfig'. The reason is that the variable 'hwconfig' could be deleted by mistake from the persistent storage. In that case U-Boot would hang when initializing the PCIe subsystem. Signed-off-by: Costin Carabas <costin.carabas@nxp.com>
Showing 2 changed files with 27 additions and 0 deletions Side-by-side Diff
drivers/pci/pcie_s32v2xx.c
| ... | ... | @@ -5,6 +5,7 @@ |
| 5 | 5 | * Copyright (C) 2016 Heinz Wrobel <heinz.wrobel@nxp.com> |
| 6 | 6 | * Copyright (C) 2015 Aurelian Voicu <aurelian.voicu@nxp.com> |
| 7 | 7 | * Copyright 2016-2017,2020 NXP |
| 8 | + * (C) Copyright 2018 MicroSys Electronics GmbH | |
| 8 | 9 | * |
| 9 | 10 | * Based on upstream iMX U-Boot driver: |
| 10 | 11 | * pcie_imx.c: Marek Vasut <marex@denx.de> |
| ... | ... | @@ -742,6 +743,31 @@ |
| 742 | 743 | epmode = 0; |
| 743 | 744 | #endif |
| 744 | 745 | |
| 746 | +#if defined CONFIG_MPXS32V234_R1 || defined CONFIG_MPXS32V234_R2 | |
| 747 | +#ifdef CONFIG_PCIE_EXT_CLOCK | |
| 748 | + /* | |
| 749 | + * SBC-S32VEVB has external PCIe clocking. | |
| 750 | + * Note that it is not an option to make this configuration available | |
| 751 | + * via setting the environment variable 'hwconfig'. The reason is that | |
| 752 | + * the variable 'hwconfig' could be deleted by mistake from the | |
| 753 | + * persistent storage. In that case U-Boot would hang when | |
| 754 | + * initializing the PCIe subsystem. | |
| 755 | + */ | |
| 756 | + clockexternal = 1; | |
| 757 | +#else | |
| 758 | + clockexternal = 0; | |
| 759 | + /* For CUT2.0 we MUST use external clock, since there is no | |
| 760 | + * internal clock available. | |
| 761 | + * This must be done for backwards compatibility, so that | |
| 762 | + * PCIe works the same way with the default settings on | |
| 763 | + * all CUTs, old and new. | |
| 764 | + */ | |
| 765 | + if (get_siul2_midr1_major() >= 1) | |
| 766 | + clockexternal = 1; | |
| 767 | + else | |
| 768 | + clockexternal = 0; | |
| 769 | +#endif | |
| 770 | +#endif | |
| 745 | 771 | /* We have a build time default, but we allow a custom |
| 746 | 772 | * override for configuration flexibility |
| 747 | 773 | */ |