Commit 8d67c3685e3b4bea8524e2e25b1443b62a69352b
Committed by
York Sun
1 parent
6b7679c8d2
Exists in
v2017.01-smarct4x
and in
48 other branches
powerpc/t2080rdb: Add T2080PCIe-RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 16 changed files with 1777 additions and 0 deletions Side-by-side Diff
- board/freescale/t208xrdb/Makefile
- board/freescale/t208xrdb/README
- board/freescale/t208xrdb/cpld.c
- board/freescale/t208xrdb/cpld.h
- board/freescale/t208xrdb/ddr.c
- board/freescale/t208xrdb/ddr.h
- board/freescale/t208xrdb/eth_t208xrdb.c
- board/freescale/t208xrdb/law.c
- board/freescale/t208xrdb/pci.c
- board/freescale/t208xrdb/t2080_pbi.cfg
- board/freescale/t208xrdb/t2080_rcw.cfg
- board/freescale/t208xrdb/t208xrdb.c
- board/freescale/t208xrdb/t208xrdb.h
- board/freescale/t208xrdb/tlb.c
- boards.cfg
- include/configs/T208xRDB.h
board/freescale/t208xrdb/Makefile
1 | +# | |
2 | +# Copyright 2014 Freescale Semiconductor, Inc. | |
3 | +# | |
4 | +# SPDX-License-Identifier: GPL-2.0+ | |
5 | +# | |
6 | + | |
7 | +obj-$(CONFIG_T2080RDB) += t208xrdb.o | |
8 | +obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o | |
9 | +obj-$(CONFIG_T2080RDB) += cpld.o | |
10 | +obj-$(CONFIG_PCI) += pci.o | |
11 | +obj-y += ddr.o | |
12 | +obj-y += law.o | |
13 | +obj-y += tlb.o |
board/freescale/t208xrdb/README
1 | +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. | |
2 | +It can work in two mode: standalone mode and PCIe endpoint mode. | |
3 | + | |
4 | +T2080 SoC Overview | |
5 | +------------------ | |
6 | +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power | |
7 | +Architecture processor cores with high-performance datapath acceleration | |
8 | +logic and network and peripheral bus interfaces required for networking, | |
9 | +telecom/datacom, wireless infrastructure, and mil/aerospace applications. | |
10 | + | |
11 | +T2080 includes the following functions and features: | |
12 | + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz | |
13 | + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) | |
14 | + - Hierarchical interconnect fabric | |
15 | + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving | |
16 | + - Data Path Acceleration Architecture (DPAA) incorporating acceleration | |
17 | + - 16 SerDes lanes up to 10.3125 GHz | |
18 | + - 8 Ethernet interfaces, supporting combinations of the following: | |
19 | + - Up to four 10 Gbps Ethernet MACs | |
20 | + - Up to eight 1 Gbps Ethernet MACs | |
21 | + - Up to four 2.5 Gbps Ethernet MACs | |
22 | + - High-speed peripheral interfaces | |
23 | + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) | |
24 | + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz | |
25 | + - Additional peripheral interfaces | |
26 | + - Two serial ATA (SATA 2.0) controllers | |
27 | + - Two high-speed USB 2.0 controllers with integrated PHY | |
28 | + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) | |
29 | + - Enhanced serial peripheral interface (eSPI) | |
30 | + - Four I2C controllers | |
31 | + - Four 2-pin UARTs or two 4-pin UARTs | |
32 | + - Integrated Flash Controller supporting NAND and NOR flash | |
33 | + - Three eight-channel DMA engines | |
34 | + - Support for hardware virtualization and partitioning enforcement | |
35 | + - QorIQ Platform's Trust Architecture 2.0 | |
36 | + | |
37 | +Differences between T2080 and T2081 | |
38 | +----------------------------------- | |
39 | + Feature T2080 T2081 | |
40 | + 1G Ethernet numbers: 8 6 | |
41 | + 10G Ethernet numbers: 4 2 | |
42 | + SerDes lanes: 16 8 | |
43 | + Serial RapidIO,RMan: 2 no | |
44 | + SATA Controller: 2 no | |
45 | + Aurora: yes no | |
46 | + SoC Package: 896-pins 780-pins | |
47 | + | |
48 | + | |
49 | +T2080PCIe-RDB board Overview | |
50 | +---------------------------- | |
51 | + - SERDES Configuration | |
52 | + - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) | |
53 | + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) | |
54 | + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) | |
55 | + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) | |
56 | + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) | |
57 | + - SerDes-2 Lane G-H: to SATA1 & SATA2 | |
58 | + - Ethernet | |
59 | + - Two on-board 10M/100M/1G RGMII ethernet ports | |
60 | + - Two on-board 10Gbps XFI fiber ports | |
61 | + - Two on-board 10Gbps Base-T copper ports | |
62 | + - DDR Memory | |
63 | + - Supports 72bit 4GB DDR3-LP SODIMM | |
64 | + - PCIe | |
65 | + - One PCIe x4 gold-finger | |
66 | + - One PCIe x4 connector | |
67 | + - One PCIe x2 end-point device (C293 Crypto co-processor) | |
68 | + - IFC/Local Bus | |
69 | + - NOR: 128MB 16-bit NOR Flash | |
70 | + - NAND: 512MB 8-bit NAND flash | |
71 | + - CPLD: for system controlling with programable header on-board | |
72 | + - SATA | |
73 | + - Two SATA 2.0 onnectors on-board | |
74 | + - USB | |
75 | + - Supports two USB 2.0 ports with integrated PHYs | |
76 | + - Two type A ports with 5V@1.5A per port. | |
77 | + - SDHC | |
78 | + - one TF-card connector on-board | |
79 | + - SPI | |
80 | + - On-board 64MB SPI flash | |
81 | + - Other | |
82 | + - Two Serial ports | |
83 | + - Four I2C ports | |
84 | + | |
85 | + | |
86 | +System Memory map | |
87 | +----------------- | |
88 | +Start Address End Address Description Size | |
89 | +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB | |
90 | +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB | |
91 | +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB | |
92 | +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB | |
93 | +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB | |
94 | +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB | |
95 | +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB | |
96 | +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB | |
97 | +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB | |
98 | +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB | |
99 | +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB | |
100 | +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB | |
101 | +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB | |
102 | +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB | |
103 | +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB | |
104 | +0x0_0000_0000 0x0_ffff_ffff DDR 4GB | |
105 | + | |
106 | + | |
107 | +128M NOR Flash memory Map | |
108 | +------------------------- | |
109 | +Start Address End Address Definition Max size | |
110 | +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB | |
111 | +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB | |
112 | +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB | |
113 | +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB | |
114 | +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB | |
115 | +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB | |
116 | +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB | |
117 | +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB | |
118 | +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB | |
119 | +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB | |
120 | +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB | |
121 | +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB | |
122 | +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB | |
123 | +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB | |
124 | +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB | |
125 | +0xE8000000 0xE801FFFF RCW (current bank) 128KB | |
126 | + | |
127 | + | |
128 | +T2080PCIe-RDB Ethernet Port Map | |
129 | +------------------------------- | |
130 | +Label In Uboot In Linux FMan Address Comments PHY | |
131 | +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) | |
132 | +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) | |
133 | +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) | |
134 | +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) | |
135 | +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) | |
136 | +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) | |
137 | + | |
138 | + | |
139 | +T2080PCIe-RDB Default DIP-Switch setting | |
140 | +---------------------------------------- | |
141 | +SW1[1:8] = '00010011' | |
142 | +SW2[1:8] = '10111111' | |
143 | +SW3[1:8] = '11100001' | |
144 | + | |
145 | +Software configurations and board settings | |
146 | +------------------------------------------ | |
147 | +1. NOR boot: | |
148 | + a. build NOR boot image | |
149 | + $ make T2080RDB | |
150 | + b. program u-boot.bin image to NOR flash | |
151 | + => tftp 1000000 u-boot.bin | |
152 | + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize | |
153 | + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot | |
154 | + | |
155 | + Switching between default bank and alternate bank on NOR flash | |
156 | + To change boot source to vbank4: | |
157 | + via software: run command 'cpld reset altbank' in u-boot. | |
158 | + via DIP-switch: set SW3[5:7] = '011' | |
159 | + | |
160 | + To change boot source to vbank0: | |
161 | + via software: run command 'cpld reset' in u-boot. | |
162 | + via DIP-Switch: set SW3[5:7] = '111' | |
163 | + | |
164 | +2. NAND Boot: | |
165 | + a. build PBL image for NAND boot | |
166 | + $ make T2080RDB_NAND_config | |
167 | + $ make u-boot.pbl | |
168 | + b. program u-boot.pbl to NAND flash | |
169 | + => tftp 1000000 u-boot.pbl | |
170 | + => nand erase 0 d0000 | |
171 | + => nand write 1000000 0 $filesize | |
172 | + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot | |
173 | + | |
174 | +3. SPI Boot: | |
175 | + a. build PBL image for SPI boot | |
176 | + $ make T2080RDB_SPIFLASH_config | |
177 | + $ make u-boot.pbl | |
178 | + b. program u-boot.pbl to SPI flash | |
179 | + => tftp 1000000 u-boot.pbl | |
180 | + => sf probe 0 | |
181 | + => sf erase 0 d0000 | |
182 | + => sf write 1000000 0 $filesize | |
183 | + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot | |
184 | + | |
185 | +4. SD Boot: | |
186 | + a. build PBL image for SD boot | |
187 | + $ make T2080RDB_SDCARD_config | |
188 | + $ make u-boot.pbl | |
189 | + b. program u-boot.pbl to TF card | |
190 | + => tftp 1000000 u-boot.pbl | |
191 | + => mmc write 1000000 8 1650 | |
192 | + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot | |
193 | + | |
194 | + | |
195 | +How to update the ucode of Cortina CS4315/CS4340 10G PHY | |
196 | +-------------------------------------------------------- | |
197 | +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt | |
198 | +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize | |
199 | + | |
200 | + | |
201 | +How to update the ucode of Freescale FMAN | |
202 | +----------------------------------------- | |
203 | +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin | |
204 | +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize | |
205 | + | |
206 | + | |
207 | +For more details, please refer to T2080PCIe-RDB User Guide and access | |
208 | +website www.freescale.com and Freescale QorIQ SDK Infocenter document. |
board/freescale/t208xrdb/cpld.c
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + * | |
6 | + * Freescale T2080RDB board-specific CPLD controlling supports. | |
7 | + */ | |
8 | + | |
9 | +#include <common.h> | |
10 | +#include <command.h> | |
11 | +#include "cpld.h" | |
12 | + | |
13 | +u8 cpld_read(unsigned int reg) | |
14 | +{ | |
15 | + void *p = (void *)CONFIG_SYS_CPLD_BASE; | |
16 | + | |
17 | + return in_8(p + reg); | |
18 | +} | |
19 | + | |
20 | +void cpld_write(unsigned int reg, u8 value) | |
21 | +{ | |
22 | + void *p = (void *)CONFIG_SYS_CPLD_BASE; | |
23 | + | |
24 | + out_8(p + reg, value); | |
25 | +} | |
26 | + | |
27 | +/* Set the boot bank to the alternate bank */ | |
28 | +void cpld_set_altbank(void) | |
29 | +{ | |
30 | + u8 reg = CPLD_READ(flash_csr); | |
31 | + | |
32 | + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; | |
33 | + CPLD_WRITE(flash_csr, reg); | |
34 | + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); | |
35 | +} | |
36 | + | |
37 | +/* Set the boot bank to the default bank */ | |
38 | +void cpld_set_defbank(void) | |
39 | +{ | |
40 | + u8 reg = CPLD_READ(flash_csr); | |
41 | + | |
42 | + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; | |
43 | + CPLD_WRITE(flash_csr, reg); | |
44 | + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); | |
45 | +} | |
46 | + | |
47 | +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
48 | +{ | |
49 | + int rc = 0; | |
50 | + | |
51 | + if (argc <= 1) | |
52 | + return cmd_usage(cmdtp); | |
53 | + | |
54 | + if (strcmp(argv[1], "reset") == 0) { | |
55 | + if (strcmp(argv[2], "altbank") == 0) | |
56 | + cpld_set_altbank(); | |
57 | + else | |
58 | + cpld_set_defbank(); | |
59 | + } else { | |
60 | + rc = cmd_usage(cmdtp); | |
61 | + } | |
62 | + | |
63 | + return rc; | |
64 | +} | |
65 | + | |
66 | +U_BOOT_CMD( | |
67 | + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, | |
68 | + "Reset the board or alternate bank", | |
69 | + "reset: reset to default bank\n" | |
70 | + "cpld reset altbank: reset to alternate bank\n" | |
71 | +); |
board/freescale/t208xrdb/cpld.h
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +/* | |
8 | + * CPLD register set of T2080RDB board-specific. | |
9 | + */ | |
10 | +struct cpld_data { | |
11 | + u8 chip_id1; /* 0x00 - Chip ID1 register */ | |
12 | + u8 chip_id2; /* 0x01 - Chip ID2 register */ | |
13 | + u8 hw_ver; /* 0x02 - Hardware Revision Register */ | |
14 | + u8 sw_ver; /* 0x03 - Software Revision register */ | |
15 | + u8 res0[12]; /* 0x04 - 0x0F - not used */ | |
16 | + u8 reset_ctl; /* 0x10 - Reset control Register */ | |
17 | + u8 flash_csr; /* 0x11 - Flash control and status register */ | |
18 | + u8 thermal_csr; /* 0x12 - Thermal control and status register */ | |
19 | + u8 led_csr; /* 0x13 - LED control and status register */ | |
20 | + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ | |
21 | + u8 misc_csr; /* 0x15 - Misc control and status register */ | |
22 | + u8 boot_or; /* 0x16 - Boot config override register */ | |
23 | + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ | |
24 | + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ | |
25 | +} cpld_data_t; | |
26 | + | |
27 | +u8 cpld_read(unsigned int reg); | |
28 | +void cpld_write(unsigned int reg, u8 value); | |
29 | + | |
30 | +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) | |
31 | +#define CPLD_WRITE(reg, value) \ | |
32 | + cpld_write(offsetof(struct cpld_data, reg), value) | |
33 | + | |
34 | +/* CPLD on IFC */ | |
35 | +#define CPLD_LBMAP_MASK 0x3F | |
36 | +#define CPLD_BANK_SEL_MASK 0x07 | |
37 | +#define CPLD_BANK_OVERRIDE 0x40 | |
38 | +#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ | |
39 | +#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ | |
40 | +#define CPLD_LBMAP_RESET 0xFF | |
41 | +#define CPLD_LBMAP_SHIFT 0x03 | |
42 | +#define CPLD_BOOT_SEL 0x80 |
board/freescale/t208xrdb/ddr.c
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or | |
5 | + * modify it under the terms of the GNU General Public License | |
6 | + * Version 2 or later as published by the Free Software Foundation. | |
7 | + */ | |
8 | + | |
9 | +#include <common.h> | |
10 | +#include <i2c.h> | |
11 | +#include <hwconfig.h> | |
12 | +#include <asm/mmu.h> | |
13 | +#include <fsl_ddr_sdram.h> | |
14 | +#include <fsl_ddr_dimm_params.h> | |
15 | +#include <asm/fsl_law.h> | |
16 | +#include "ddr.h" | |
17 | + | |
18 | +DECLARE_GLOBAL_DATA_PTR; | |
19 | + | |
20 | +void fsl_ddr_board_options(memctl_options_t *popts, | |
21 | + dimm_params_t *pdimm, | |
22 | + unsigned int ctrl_num) | |
23 | +{ | |
24 | + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; | |
25 | + ulong ddr_freq; | |
26 | + | |
27 | + if (ctrl_num > 1) { | |
28 | + printf("Not supported controller number %d\n", ctrl_num); | |
29 | + return; | |
30 | + } | |
31 | + if (!pdimm->n_ranks) | |
32 | + return; | |
33 | + | |
34 | + pbsp = udimms[0]; | |
35 | + | |
36 | + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr | |
37 | + * freqency and n_banks specified in board_specific_parameters table. | |
38 | + */ | |
39 | + ddr_freq = get_ddr_freq(0) / 1000000; | |
40 | + while (pbsp->datarate_mhz_high) { | |
41 | + if (pbsp->n_ranks == pdimm->n_ranks && | |
42 | + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { | |
43 | + if (ddr_freq <= pbsp->datarate_mhz_high) { | |
44 | + popts->clk_adjust = pbsp->clk_adjust; | |
45 | + popts->wrlvl_start = pbsp->wrlvl_start; | |
46 | + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
47 | + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
48 | + goto found; | |
49 | + } | |
50 | + pbsp_highest = pbsp; | |
51 | + } | |
52 | + pbsp++; | |
53 | + } | |
54 | + | |
55 | + if (pbsp_highest) { | |
56 | + printf("Error: board specific timing not found"); | |
57 | + printf("for data rate %lu MT/s\n", ddr_freq); | |
58 | + printf("Trying to use the highest speed (%u) parameters\n", | |
59 | + pbsp_highest->datarate_mhz_high); | |
60 | + popts->clk_adjust = pbsp_highest->clk_adjust; | |
61 | + popts->wrlvl_start = pbsp_highest->wrlvl_start; | |
62 | + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
63 | + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
64 | + } else { | |
65 | + panic("DIMM is not supported by this board"); | |
66 | + } | |
67 | +found: | |
68 | + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" | |
69 | + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " | |
70 | + "wrlvl_ctrl_3 0x%x\n", | |
71 | + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, | |
72 | + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, | |
73 | + pbsp->wrlvl_ctl_3); | |
74 | + | |
75 | + /* | |
76 | + * Factors to consider for half-strength driver enable: | |
77 | + * - number of DIMMs installed | |
78 | + */ | |
79 | + popts->half_strength_driver_enable = 0; | |
80 | + /* | |
81 | + * Write leveling override | |
82 | + */ | |
83 | + popts->wrlvl_override = 1; | |
84 | + popts->wrlvl_sample = 0xf; | |
85 | + | |
86 | + /* | |
87 | + * Rtt and Rtt_WR override | |
88 | + */ | |
89 | + popts->rtt_override = 0; | |
90 | + | |
91 | + /* Enable ZQ calibration */ | |
92 | + popts->zq_en = 1; | |
93 | + | |
94 | + /* DHC_EN =1, ODT = 75 Ohm */ | |
95 | + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); | |
96 | + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); | |
97 | +} | |
98 | + | |
99 | +phys_size_t initdram(int board_type) | |
100 | +{ | |
101 | + phys_size_t dram_size; | |
102 | + | |
103 | + puts("Initializing....using SPD\n"); | |
104 | + | |
105 | + dram_size = fsl_ddr_sdram(); | |
106 | + | |
107 | + dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
108 | + dram_size *= 0x100000; | |
109 | + | |
110 | + puts(" DDR: "); | |
111 | + return dram_size; | |
112 | +} |
board/freescale/t208xrdb/ddr.h
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +#ifndef __DDR_H__ | |
8 | +#define __DDR_H__ | |
9 | +struct board_specific_parameters { | |
10 | + u32 n_ranks; | |
11 | + u32 datarate_mhz_high; | |
12 | + u32 rank_gb; | |
13 | + u32 clk_adjust; | |
14 | + u32 wrlvl_start; | |
15 | + u32 wrlvl_ctl_2; | |
16 | + u32 wrlvl_ctl_3; | |
17 | +}; | |
18 | + | |
19 | +/* | |
20 | + * These tables contain all valid speeds we want to override with board | |
21 | + * specific parameters. datarate_mhz_high values need to be in ascending order | |
22 | + * for each n_ranks group. | |
23 | + */ | |
24 | + | |
25 | +static const struct board_specific_parameters udimm0[] = { | |
26 | + /* | |
27 | + * memory controller 0 | |
28 | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | | |
29 | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | | |
30 | + */ | |
31 | + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, | |
32 | + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, | |
33 | + {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, | |
34 | + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, | |
35 | + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, | |
36 | + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, | |
37 | + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, | |
38 | + {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, | |
39 | + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, | |
40 | + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, | |
41 | + {} | |
42 | +}; | |
43 | + | |
44 | +static const struct board_specific_parameters *udimms[] = { | |
45 | + udimm0, | |
46 | +}; | |
47 | +#endif |
board/freescale/t208xrdb/eth_t208xrdb.c
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * Shengzhou Liu <Shengzhou.Liu@freescale.com> | |
5 | + * | |
6 | + * SPDX-License-Identifier: GPL-2.0+ | |
7 | + */ | |
8 | + | |
9 | +#include <common.h> | |
10 | +#include <command.h> | |
11 | +#include <netdev.h> | |
12 | +#include <asm/mmu.h> | |
13 | +#include <asm/processor.h> | |
14 | +#include <asm/immap_85xx.h> | |
15 | +#include <asm/fsl_law.h> | |
16 | +#include <asm/fsl_serdes.h> | |
17 | +#include <asm/fsl_portals.h> | |
18 | +#include <asm/fsl_liodn.h> | |
19 | +#include <malloc.h> | |
20 | +#include <fm_eth.h> | |
21 | +#include <fsl_mdio.h> | |
22 | +#include <miiphy.h> | |
23 | +#include <phy.h> | |
24 | +#include <asm/fsl_dtsec.h> | |
25 | +#include <asm/fsl_serdes.h> | |
26 | + | |
27 | +int board_eth_init(bd_t *bis) | |
28 | +{ | |
29 | +#if defined(CONFIG_FMAN_ENET) | |
30 | + int i, interface; | |
31 | + struct memac_mdio_info dtsec_mdio_info; | |
32 | + struct memac_mdio_info tgec_mdio_info; | |
33 | + struct mii_dev *dev; | |
34 | + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
35 | + u32 srds_s1; | |
36 | + | |
37 | + srds_s1 = in_be32(&gur->rcwsr[4]) & | |
38 | + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; | |
39 | + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; | |
40 | + | |
41 | + dtsec_mdio_info.regs = | |
42 | + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; | |
43 | + | |
44 | + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; | |
45 | + | |
46 | + /* Register the 1G MDIO bus */ | |
47 | + fm_memac_mdio_init(bis, &dtsec_mdio_info); | |
48 | + | |
49 | + tgec_mdio_info.regs = | |
50 | + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; | |
51 | + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; | |
52 | + | |
53 | + /* Register the 10G MDIO bus */ | |
54 | + fm_memac_mdio_init(bis, &tgec_mdio_info); | |
55 | + | |
56 | + /* Set the two on-board RGMII PHY address */ | |
57 | + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); | |
58 | + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); | |
59 | + | |
60 | + switch (srds_s1) { | |
61 | + case 0x66: | |
62 | + case 0x6b: | |
63 | + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); | |
64 | + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); | |
65 | + fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); | |
66 | + fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); | |
67 | + break; | |
68 | + default: | |
69 | + printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", | |
70 | + srds_s1); | |
71 | + break; | |
72 | + } | |
73 | + | |
74 | + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { | |
75 | + interface = fm_info_get_enet_if(i); | |
76 | + switch (interface) { | |
77 | + case PHY_INTERFACE_MODE_RGMII: | |
78 | + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); | |
79 | + fm_info_set_mdio(i, dev); | |
80 | + break; | |
81 | + default: | |
82 | + break; | |
83 | + } | |
84 | + } | |
85 | + | |
86 | + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { | |
87 | + switch (fm_info_get_enet_if(i)) { | |
88 | + case PHY_INTERFACE_MODE_XGMII: | |
89 | + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); | |
90 | + fm_info_set_mdio(i, dev); | |
91 | + break; | |
92 | + default: | |
93 | + break; | |
94 | + } | |
95 | + } | |
96 | + | |
97 | + cpu_eth_init(bis); | |
98 | +#endif /* CONFIG_FMAN_ENET */ | |
99 | + | |
100 | + return pci_eth_init(bis); | |
101 | +} | |
102 | + | |
103 | +void fdt_fixup_board_enet(void *fdt) | |
104 | +{ | |
105 | + return; | |
106 | +} |
board/freescale/t208xrdb/law.c
1 | +/* | |
2 | + * Copyright 2008-2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * (C) Copyright 2000 | |
5 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +#include <common.h> | |
11 | +#include <asm/fsl_law.h> | |
12 | +#include <asm/mmu.h> | |
13 | + | |
14 | +struct law_entry law_table[] = { | |
15 | + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), | |
16 | +#ifdef CONFIG_SYS_BMAN_MEM_PHYS | |
17 | + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), | |
18 | +#endif | |
19 | +#ifdef CONFIG_SYS_QMAN_MEM_PHYS | |
20 | + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), | |
21 | +#endif | |
22 | +#ifdef CONFIG_SYS_CPLD_BASE_PHYS | |
23 | + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), | |
24 | +#endif | |
25 | +#ifdef CONFIG_SYS_DCSRBAR_PHYS | |
26 | + /* Limit DCSR to 32M to access NPC Trace Buffer */ | |
27 | + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), | |
28 | +#endif | |
29 | +#ifdef CONFIG_SYS_NAND_BASE_PHYS | |
30 | + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), | |
31 | +#endif | |
32 | +}; | |
33 | + | |
34 | +int num_law_entries = ARRAY_SIZE(law_table); |
board/freescale/t208xrdb/pci.c
1 | +/* | |
2 | + * Copyright 2007-2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +#include <common.h> | |
8 | +#include <command.h> | |
9 | +#include <pci.h> | |
10 | +#include <asm/fsl_pci.h> | |
11 | +#include <libfdt.h> | |
12 | +#include <fdt_support.h> | |
13 | +#include <asm/fsl_serdes.h> | |
14 | + | |
15 | +void pci_init_board(void) | |
16 | +{ | |
17 | + fsl_pcie_init_board(0); | |
18 | +} | |
19 | + | |
20 | +void pci_of_setup(void *blob, bd_t *bd) | |
21 | +{ | |
22 | + FT_FSL_PCI_SETUP; | |
23 | +} |
board/freescale/t208xrdb/t2080_pbi.cfg
1 | +# | |
2 | +# Copyright 2013 Freescale Semiconductor, Inc. | |
3 | +# | |
4 | +# SPDX-License-Identifier: GPL-2.0+ | |
5 | +# | |
6 | +# Refer doc/README.pblimage for more details about how-to configure | |
7 | +# and create PBL boot image | |
8 | +# | |
9 | + | |
10 | +#PBI commands | |
11 | +#Initialize CPC1 | |
12 | +09010000 00200400 | |
13 | +09138000 00000000 | |
14 | +091380c0 00000100 | |
15 | +#512KB SRAM | |
16 | +09010100 00000000 | |
17 | +09010104 fff80009 | |
18 | +09010f00 08000000 | |
19 | +#enable CPC1 | |
20 | +09010000 80000000 | |
21 | +#Configure LAW for CPC1 | |
22 | +09000d00 00000000 | |
23 | +09000d04 fff80000 | |
24 | +09000d08 81000012 | |
25 | +#Initialize eSPI controller, default configuration is slow for eSPI to | |
26 | +#load data, this configuration comes from u-boot eSPI driver. | |
27 | +09110000 80000403 | |
28 | +09110020 2d170008 | |
29 | +09110024 00100008 | |
30 | +09110028 00100008 | |
31 | +0911002c 00100008 | |
32 | +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ | |
33 | +094fc030 00008148 | |
34 | +094fd030 00008148 | |
35 | +#Configure alternate space | |
36 | +09000010 00000000 | |
37 | +09000014 ff000000 | |
38 | +09000018 81000000 | |
39 | +#Flush PBL data | |
40 | +09138000 00000000 | |
41 | +091380c0 00000000 |
board/freescale/t208xrdb/t2080_rcw.cfg
board/freescale/t208xrdb/t208xrdb.c
1 | +/* | |
2 | + * Copyright 2009-2013 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +#include <common.h> | |
8 | +#include <command.h> | |
9 | +#include <i2c.h> | |
10 | +#include <netdev.h> | |
11 | +#include <linux/compiler.h> | |
12 | +#include <asm/mmu.h> | |
13 | +#include <asm/processor.h> | |
14 | +#include <asm/immap_85xx.h> | |
15 | +#include <asm/fsl_law.h> | |
16 | +#include <asm/fsl_serdes.h> | |
17 | +#include <asm/fsl_portals.h> | |
18 | +#include <asm/fsl_liodn.h> | |
19 | +#include <fm_eth.h> | |
20 | +#include "t208xrdb.h" | |
21 | +#include "cpld.h" | |
22 | + | |
23 | +DECLARE_GLOBAL_DATA_PTR; | |
24 | + | |
25 | +int checkboard(void) | |
26 | +{ | |
27 | + struct cpu_type *cpu = gd->arch.cpu; | |
28 | + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; | |
29 | + | |
30 | + printf("Board: %sRDB, ", cpu->name); | |
31 | + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", | |
32 | + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); | |
33 | + | |
34 | +#ifdef CONFIG_SDCARD | |
35 | + puts("SD/MMC\n"); | |
36 | +#elif CONFIG_SPIFLASH | |
37 | + puts("SPI\n"); | |
38 | +#else | |
39 | + u8 reg; | |
40 | + | |
41 | + reg = CPLD_READ(flash_csr); | |
42 | + | |
43 | + if (reg & CPLD_BOOT_SEL) { | |
44 | + puts("NAND\n"); | |
45 | + } else { | |
46 | + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); | |
47 | + printf("NOR vBank%d\n", ~reg & 0x7); | |
48 | + } | |
49 | +#endif | |
50 | + | |
51 | + puts("SERDES Reference Clocks:\n"); | |
52 | + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); | |
53 | + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); | |
54 | + | |
55 | + return 0; | |
56 | +} | |
57 | + | |
58 | +int board_early_init_r(void) | |
59 | +{ | |
60 | + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; | |
61 | + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); | |
62 | + /* | |
63 | + * Remap Boot flash + PROMJET region to caching-inhibited | |
64 | + * so that flash can be erased properly. | |
65 | + */ | |
66 | + | |
67 | + /* Flush d-cache and invalidate i-cache of any FLASH data */ | |
68 | + flush_dcache(); | |
69 | + invalidate_icache(); | |
70 | + | |
71 | + /* invalidate existing TLB entry for flash + promjet */ | |
72 | + disable_tlb(flash_esel); | |
73 | + | |
74 | + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, | |
75 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
76 | + 0, flash_esel, BOOKE_PAGESZ_256M, 1); | |
77 | + | |
78 | + set_liodns(); | |
79 | +#ifdef CONFIG_SYS_DPAA_QBMAN | |
80 | + setup_portals(); | |
81 | +#endif | |
82 | + | |
83 | + return 0; | |
84 | +} | |
85 | + | |
86 | +unsigned long get_board_sys_clk(void) | |
87 | +{ | |
88 | + return CONFIG_SYS_CLK_FREQ; | |
89 | +} | |
90 | + | |
91 | +unsigned long get_board_ddr_clk(void) | |
92 | +{ | |
93 | + return CONFIG_DDR_CLK_FREQ; | |
94 | +} | |
95 | + | |
96 | +int misc_init_r(void) | |
97 | +{ | |
98 | + return 0; | |
99 | +} | |
100 | + | |
101 | +void ft_board_setup(void *blob, bd_t *bd) | |
102 | +{ | |
103 | + phys_addr_t base; | |
104 | + phys_size_t size; | |
105 | + | |
106 | + ft_cpu_setup(blob, bd); | |
107 | + | |
108 | + base = getenv_bootm_low(); | |
109 | + size = getenv_bootm_size(); | |
110 | + | |
111 | + fdt_fixup_memory(blob, (u64)base, (u64)size); | |
112 | + | |
113 | +#ifdef CONFIG_PCI | |
114 | + pci_of_setup(blob, bd); | |
115 | +#endif | |
116 | + | |
117 | + fdt_fixup_liodn(blob); | |
118 | + fdt_fixup_dr_usb(blob, bd); | |
119 | + | |
120 | +#ifdef CONFIG_SYS_DPAA_FMAN | |
121 | + fdt_fixup_fman_ethernet(blob); | |
122 | + fdt_fixup_board_enet(blob); | |
123 | +#endif | |
124 | +} |
board/freescale/t208xrdb/t208xrdb.h
board/freescale/t208xrdb/tlb.c
1 | +/* | |
2 | + * Copyright 2008-2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * (C) Copyright 2000 | |
5 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +#include <common.h> | |
11 | +#include <asm/mmu.h> | |
12 | + | |
13 | +struct fsl_e_tlb_entry tlb_table[] = { | |
14 | + /* TLB 0 - for temp stack in cache */ | |
15 | + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, | |
16 | + CONFIG_SYS_INIT_RAM_ADDR_PHYS, | |
17 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
18 | + 0, 0, BOOKE_PAGESZ_4K, 0), | |
19 | + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
20 | + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, | |
21 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
22 | + 0, 0, BOOKE_PAGESZ_4K, 0), | |
23 | + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
24 | + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, | |
25 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
26 | + 0, 0, BOOKE_PAGESZ_4K, 0), | |
27 | + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
28 | + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, | |
29 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
30 | + 0, 0, BOOKE_PAGESZ_4K, 0), | |
31 | + | |
32 | + /* TLB 1 */ | |
33 | + /* *I*** - Covers boot page */ | |
34 | +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) | |
35 | + /* | |
36 | + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the | |
37 | + * SRAM is at 0xfff00000, it covered the 0xfffff000. | |
38 | + */ | |
39 | + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, | |
40 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
41 | + 0, 0, BOOKE_PAGESZ_1M, 1), | |
42 | +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) | |
43 | + /* | |
44 | + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the | |
45 | + * space is at 0xfff00000, it covered the 0xfffff000. | |
46 | + */ | |
47 | + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, | |
48 | + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, | |
49 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, | |
50 | + 0, 0, BOOKE_PAGESZ_1M, 1), | |
51 | +#else | |
52 | + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, | |
53 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
54 | + 0, 0, BOOKE_PAGESZ_4K, 1), | |
55 | +#endif | |
56 | + | |
57 | + /* *I*G* - CCSRBAR */ | |
58 | + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
59 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
60 | + 0, 1, BOOKE_PAGESZ_16M, 1), | |
61 | + | |
62 | + /* *I*G* - Flash, localbus */ | |
63 | + /* This will be changed to *I*G* after relocation to RAM. */ | |
64 | + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, | |
65 | + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, | |
66 | + 0, 2, BOOKE_PAGESZ_256M, 1), | |
67 | + | |
68 | + /* *I*G* - PCIe 1, 0x80000000 */ | |
69 | + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, | |
70 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
71 | + 0, 3, BOOKE_PAGESZ_512M, 1), | |
72 | + | |
73 | + /* *I*G* - PCIe 2, 0xa0000000 */ | |
74 | + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, | |
75 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
76 | + 0, 4, BOOKE_PAGESZ_256M, 1), | |
77 | + | |
78 | + /* *I*G* - PCIe 3, 0xb0000000 */ | |
79 | + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, | |
80 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
81 | + 0, 5, BOOKE_PAGESZ_256M, 1), | |
82 | + | |
83 | + | |
84 | + /* *I*G* - PCIe 4, 0xc0000000 */ | |
85 | + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, | |
86 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
87 | + 0, 6, BOOKE_PAGESZ_256M, 1), | |
88 | + | |
89 | + /* *I*G* - PCI I/O */ | |
90 | + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, | |
91 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
92 | + 0, 7, BOOKE_PAGESZ_256K, 1), | |
93 | + | |
94 | + /* Bman/Qman */ | |
95 | +#ifdef CONFIG_SYS_BMAN_MEM_PHYS | |
96 | + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, | |
97 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
98 | + 0, 9, BOOKE_PAGESZ_16M, 1), | |
99 | + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, | |
100 | + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, | |
101 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
102 | + 0, 10, BOOKE_PAGESZ_16M, 1), | |
103 | +#endif | |
104 | +#ifdef CONFIG_SYS_QMAN_MEM_PHYS | |
105 | + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, | |
106 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
107 | + 0, 11, BOOKE_PAGESZ_16M, 1), | |
108 | + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, | |
109 | + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, | |
110 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
111 | + 0, 12, BOOKE_PAGESZ_16M, 1), | |
112 | +#endif | |
113 | +#ifdef CONFIG_SYS_DCSRBAR_PHYS | |
114 | + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, | |
115 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
116 | + 0, 13, BOOKE_PAGESZ_32M, 1), | |
117 | +#endif | |
118 | +#ifdef CONFIG_SYS_NAND_BASE | |
119 | + /* | |
120 | + * *I*G - NAND | |
121 | + * entry 14 and 15 has been used hard coded, they will be disabled | |
122 | + * in cpu_init_f, so we use entry 16 for nand. | |
123 | + */ | |
124 | + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
125 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
126 | + 0, 16, BOOKE_PAGESZ_64K, 1), | |
127 | +#endif | |
128 | +#ifdef CONFIG_SYS_CPLD_BASE | |
129 | + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, | |
130 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
131 | + 0, 17, BOOKE_PAGESZ_4K, 1), | |
132 | +#endif | |
133 | +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
134 | + /* | |
135 | + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for | |
136 | + * fetching ucode and ENV from master | |
137 | + */ | |
138 | + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, | |
139 | + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, | |
140 | + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, | |
141 | + 0, 18, BOOKE_PAGESZ_1M, 1), | |
142 | +#endif | |
143 | +#if defined(CONFIG_SYS_RAMBOOT) | |
144 | + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, | |
145 | + MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
146 | + 0, 19, BOOKE_PAGESZ_2G, 1) | |
147 | +#endif | |
148 | + | |
149 | +}; | |
150 | + | |
151 | +int num_tlb_entries = ARRAY_SIZE(tlb_table); |
boards.cfg
... | ... | @@ -983,6 +983,11 @@ |
983 | 983 | Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 |
984 | 984 | Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 |
985 | 985 | Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 |
986 | +Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 | |
987 | +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 | |
988 | +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 | |
989 | +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 | |
990 | +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 | |
986 | 991 | Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - |
987 | 992 | Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - |
988 | 993 | Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - |
include/configs/T208xRDB.h
1 | +/* | |
2 | + * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +/* | |
8 | + * T2080 RDB/PCIe board configuration file | |
9 | + */ | |
10 | + | |
11 | +#ifndef __T2080RDB_H | |
12 | +#define __T2080RDB_H | |
13 | + | |
14 | +#define CONFIG_T2080RDB | |
15 | +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
16 | +#define CONFIG_MMC | |
17 | +#define CONFIG_SPI_FLASH | |
18 | +#define CONFIG_USB_EHCI | |
19 | +#define CONFIG_FSL_SATA_V2 | |
20 | + | |
21 | +/* High Level Configuration Options */ | |
22 | +#define CONFIG_PHYS_64BIT | |
23 | +#define CONFIG_BOOKE | |
24 | +#define CONFIG_E500 /* BOOKE e500 family */ | |
25 | +#define CONFIG_E500MC /* BOOKE e500mc family */ | |
26 | +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
27 | +#define CONFIG_MP /* support multiple processors */ | |
28 | +#define CONFIG_ENABLE_36BIT_PHYS | |
29 | + | |
30 | +#ifdef CONFIG_PHYS_64BIT | |
31 | +#define CONFIG_ADDR_MAP 1 | |
32 | +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
33 | +#endif | |
34 | + | |
35 | +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
36 | +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
37 | +#define CONFIG_FSL_IFC /* Enable IFC Support */ | |
38 | +#define CONFIG_FSL_LAW /* Use common FSL init code */ | |
39 | +#define CONFIG_ENV_OVERWRITE | |
40 | + | |
41 | +#ifdef CONFIG_RAMBOOT_PBL | |
42 | +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
43 | +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
44 | +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xrdb/t2080_pbi.cfg | |
45 | +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xrdb/t2080_rcw.cfg | |
46 | +#endif | |
47 | + | |
48 | +#define CONFIG_SRIO_PCIE_BOOT_MASTER | |
49 | +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
50 | +/* Set 1M boot space */ | |
51 | +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
52 | +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
53 | + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
54 | +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
55 | +#define CONFIG_SYS_NO_FLASH | |
56 | +#endif | |
57 | + | |
58 | +#ifndef CONFIG_SYS_TEXT_BASE | |
59 | +#define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
60 | +#endif | |
61 | + | |
62 | +#ifndef CONFIG_RESET_VECTOR_ADDRESS | |
63 | +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
64 | +#endif | |
65 | + | |
66 | +/* | |
67 | + * These can be toggled for performance analysis, otherwise use default. | |
68 | + */ | |
69 | +#define CONFIG_SYS_CACHE_STASHING | |
70 | +#define CONFIG_BTB /* toggle branch predition */ | |
71 | +#define CONFIG_DDR_ECC | |
72 | +#ifdef CONFIG_DDR_ECC | |
73 | +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
74 | +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
75 | +#endif | |
76 | + | |
77 | +#ifdef CONFIG_SYS_NO_FLASH | |
78 | +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) | |
79 | +#define CONFIG_ENV_IS_NOWHERE | |
80 | +#endif | |
81 | +#else | |
82 | +#define CONFIG_FLASH_CFI_DRIVER | |
83 | +#define CONFIG_SYS_FLASH_CFI | |
84 | +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
85 | +#endif | |
86 | + | |
87 | +#if defined(CONFIG_SPIFLASH) | |
88 | +#define CONFIG_SYS_EXTRA_ENV_RELOC | |
89 | +#define CONFIG_ENV_IS_IN_SPI_FLASH | |
90 | +#define CONFIG_ENV_SPI_BUS 0 | |
91 | +#define CONFIG_ENV_SPI_CS 0 | |
92 | +#define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
93 | +#define CONFIG_ENV_SPI_MODE 0 | |
94 | +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
95 | +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
96 | +#define CONFIG_ENV_SECT_SIZE 0x10000 | |
97 | +#elif defined(CONFIG_SDCARD) | |
98 | +#define CONFIG_SYS_EXTRA_ENV_RELOC | |
99 | +#define CONFIG_ENV_IS_IN_MMC | |
100 | +#define CONFIG_SYS_MMC_ENV_DEV 0 | |
101 | +#define CONFIG_ENV_SIZE 0x2000 | |
102 | +#define CONFIG_ENV_OFFSET (512 * 1658) | |
103 | +#elif defined(CONFIG_NAND) | |
104 | +#define CONFIG_SYS_EXTRA_ENV_RELOC | |
105 | +#define CONFIG_ENV_IS_IN_NAND | |
106 | +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
107 | +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
108 | +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) | |
109 | +#define CONFIG_ENV_IS_IN_REMOTE | |
110 | +#define CONFIG_ENV_ADDR 0xffe20000 | |
111 | +#define CONFIG_ENV_SIZE 0x2000 | |
112 | +#elif defined(CONFIG_ENV_IS_NOWHERE) | |
113 | +#define CONFIG_ENV_SIZE 0x2000 | |
114 | +#else | |
115 | +#define CONFIG_ENV_IS_IN_FLASH | |
116 | +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
117 | +#define CONFIG_ENV_SIZE 0x2000 | |
118 | +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
119 | +#endif | |
120 | + | |
121 | +#ifndef __ASSEMBLY__ | |
122 | +unsigned long get_board_sys_clk(void); | |
123 | +unsigned long get_board_ddr_clk(void); | |
124 | +#endif | |
125 | + | |
126 | +#define CONFIG_SYS_CLK_FREQ 66660000 | |
127 | +#define CONFIG_DDR_CLK_FREQ 133330000 | |
128 | + | |
129 | +/* | |
130 | + * Config the L3 Cache as L3 SRAM | |
131 | + */ | |
132 | +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
133 | + | |
134 | +#define CONFIG_SYS_DCSRBAR 0xf0000000 | |
135 | +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
136 | + | |
137 | +/* EEPROM */ | |
138 | +#define CONFIG_ID_EEPROM | |
139 | +#define CONFIG_SYS_I2C_EEPROM_NXID | |
140 | +#define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
141 | +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
142 | +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
143 | + | |
144 | +/* | |
145 | + * DDR Setup | |
146 | + */ | |
147 | +#define CONFIG_VERY_BIG_RAM | |
148 | +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
149 | +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
150 | +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
151 | +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
152 | +#define CONFIG_DDR_SPD | |
153 | +#define CONFIG_SYS_FSL_DDR3 | |
154 | +#undef CONFIG_FSL_DDR_INTERACTIVE | |
155 | +#define CONFIG_SYS_SPD_BUS_NUM 0 | |
156 | +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ | |
157 | +#define SPD_EEPROM_ADDRESS1 0x51 | |
158 | +#define SPD_EEPROM_ADDRESS2 0x52 | |
159 | +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
160 | +#define CTRL_INTLV_PREFERED cacheline | |
161 | + | |
162 | +/* | |
163 | + * IFC Definitions | |
164 | + */ | |
165 | +#define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
166 | +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
167 | +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
168 | +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
169 | + CSPR_PORT_SIZE_16 | \ | |
170 | + CSPR_MSEL_NOR | \ | |
171 | + CSPR_V) | |
172 | +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
173 | + | |
174 | +/* NOR Flash Timing Params */ | |
175 | +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
176 | + | |
177 | +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
178 | + FTIM0_NOR_TEADC(0x5) | \ | |
179 | + FTIM0_NOR_TEAHC(0x5)) | |
180 | +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
181 | + FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
182 | + FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
183 | +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
184 | + FTIM2_NOR_TCH(0x4) | \ | |
185 | + FTIM2_NOR_TWPH(0x0E) | \ | |
186 | + FTIM2_NOR_TWP(0x1c)) | |
187 | +#define CONFIG_SYS_NOR_FTIM3 0x0 | |
188 | + | |
189 | +#define CONFIG_SYS_FLASH_QUIET_TEST | |
190 | +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
191 | + | |
192 | +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
193 | +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
194 | +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
195 | +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
196 | +#define CONFIG_SYS_FLASH_EMPTY_INFO | |
197 | +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } | |
198 | + | |
199 | +/* CPLD on IFC */ | |
200 | +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
201 | +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
202 | +#define CONFIG_SYS_CSPR2_EXT (0xf) | |
203 | +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ | |
204 | + | CSPR_PORT_SIZE_8 \ | |
205 | + | CSPR_MSEL_GPCM \ | |
206 | + | CSPR_V) | |
207 | +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
208 | +#define CONFIG_SYS_CSOR2 0x0 | |
209 | + | |
210 | +/* CPLD Timing parameters for IFC CS2 */ | |
211 | +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
212 | + FTIM0_GPCM_TEADC(0x0e) | \ | |
213 | + FTIM0_GPCM_TEAHC(0x0e)) | |
214 | +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
215 | + FTIM1_GPCM_TRAD(0x1f)) | |
216 | +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
217 | + FTIM2_GPCM_TCH(0x0) | \ | |
218 | + FTIM2_GPCM_TWP(0x1f)) | |
219 | +#define CONFIG_SYS_CS2_FTIM3 0x0 | |
220 | + | |
221 | +/* NAND Flash on IFC */ | |
222 | +#define CONFIG_NAND_FSL_IFC | |
223 | +#define CONFIG_SYS_NAND_BASE 0xff800000 | |
224 | +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
225 | + | |
226 | +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
227 | +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
228 | + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
229 | + | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
230 | + | CSPR_V) | |
231 | +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
232 | + | |
233 | +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
234 | + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
235 | + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
236 | + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
237 | + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ | |
238 | + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ | |
239 | + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
240 | + | |
241 | +#define CONFIG_SYS_NAND_ONFI_DETECTION | |
242 | + | |
243 | +/* ONFI NAND Flash mode0 Timing Params */ | |
244 | +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
245 | + FTIM0_NAND_TWP(0x18) | \ | |
246 | + FTIM0_NAND_TWCHT(0x07) | \ | |
247 | + FTIM0_NAND_TWH(0x0a)) | |
248 | +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
249 | + FTIM1_NAND_TWBE(0x39) | \ | |
250 | + FTIM1_NAND_TRR(0x0e) | \ | |
251 | + FTIM1_NAND_TRP(0x18)) | |
252 | +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
253 | + FTIM2_NAND_TREH(0x0a) | \ | |
254 | + FTIM2_NAND_TWHRE(0x1e)) | |
255 | +#define CONFIG_SYS_NAND_FTIM3 0x0 | |
256 | + | |
257 | +#define CONFIG_SYS_NAND_DDR_LAW 11 | |
258 | +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
259 | +#define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
260 | +#define CONFIG_MTD_NAND_VERIFY_WRITE | |
261 | +#define CONFIG_CMD_NAND | |
262 | +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
263 | + | |
264 | +#if defined(CONFIG_NAND) | |
265 | +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
266 | +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
267 | +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
268 | +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
269 | +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
270 | +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
271 | +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
272 | +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
273 | +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
274 | +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
275 | +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
276 | +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
277 | +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
278 | +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
279 | +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
280 | +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
281 | +#else | |
282 | +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
283 | +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
284 | +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
285 | +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
286 | +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
287 | +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
288 | +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
289 | +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
290 | +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
291 | +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
292 | +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
293 | +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
294 | +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
295 | +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
296 | +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
297 | +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
298 | +#endif | |
299 | + | |
300 | +#if defined(CONFIG_RAMBOOT_PBL) | |
301 | +#define CONFIG_SYS_RAMBOOT | |
302 | +#endif | |
303 | + | |
304 | +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
305 | +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
306 | +#define CONFIG_MISC_INIT_R | |
307 | +#define CONFIG_HWCONFIG | |
308 | + | |
309 | +/* define to use L1 as initial stack */ | |
310 | +#define CONFIG_L1_INIT_RAM | |
311 | +#define CONFIG_SYS_INIT_RAM_LOCK | |
312 | +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
313 | +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
314 | +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 | |
315 | +/* The assembler doesn't like typecast */ | |
316 | +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
317 | + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
318 | + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
319 | +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
320 | +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
321 | + GENERATED_GBL_DATA_SIZE) | |
322 | +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
323 | +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
324 | +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
325 | + | |
326 | +/* | |
327 | + * Serial Port | |
328 | + */ | |
329 | +#define CONFIG_CONS_INDEX 1 | |
330 | +#define CONFIG_SYS_NS16550 | |
331 | +#define CONFIG_SYS_NS16550_SERIAL | |
332 | +#define CONFIG_SYS_NS16550_REG_SIZE 1 | |
333 | +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
334 | +#define CONFIG_SYS_BAUDRATE_TABLE \ | |
335 | + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
336 | +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
337 | +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
338 | +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
339 | +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
340 | + | |
341 | +/* Use the HUSH parser */ | |
342 | +#define CONFIG_SYS_HUSH_PARSER | |
343 | +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
344 | + | |
345 | +/* pass open firmware flat tree */ | |
346 | +#define CONFIG_OF_LIBFDT | |
347 | +#define CONFIG_OF_BOARD_SETUP | |
348 | +#define CONFIG_OF_STDOUT_VIA_ALIAS | |
349 | + | |
350 | +/* new uImage format support */ | |
351 | +#define CONFIG_FIT | |
352 | +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
353 | + | |
354 | +/* | |
355 | + * I2C | |
356 | + */ | |
357 | +#define CONFIG_SYS_I2C | |
358 | +#define CONFIG_SYS_I2C_FSL | |
359 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
360 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
361 | +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F | |
362 | +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
363 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
364 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
365 | +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
366 | +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
367 | +#define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
368 | +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
369 | +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 | |
370 | +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 | |
371 | +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
372 | +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ | |
373 | +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ | |
374 | +#define I2C_MUX_CH_DEFAULT 0x8 | |
375 | + | |
376 | + | |
377 | +/* | |
378 | + * RapidIO | |
379 | + */ | |
380 | +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
381 | +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
382 | +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
383 | +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
384 | +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
385 | +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
386 | +/* | |
387 | + * for slave u-boot IMAGE instored in master memory space, | |
388 | + * PHYS must be aligned based on the SIZE | |
389 | + */ | |
390 | +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull | |
391 | +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull | |
392 | +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ | |
393 | +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull | |
394 | +/* | |
395 | + * for slave UCODE and ENV instored in master memory space, | |
396 | + * PHYS must be aligned based on the SIZE | |
397 | + */ | |
398 | +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull | |
399 | +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull | |
400 | +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
401 | + | |
402 | +/* slave core release by master*/ | |
403 | +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
404 | +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
405 | + | |
406 | +/* | |
407 | + * SRIO_PCIE_BOOT - SLAVE | |
408 | + */ | |
409 | +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
410 | +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
411 | +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
412 | + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
413 | +#endif | |
414 | + | |
415 | +/* | |
416 | + * eSPI - Enhanced SPI | |
417 | + */ | |
418 | +#ifdef CONFIG_SPI_FLASH | |
419 | +#define CONFIG_FSL_ESPI | |
420 | +#define CONFIG_SPI_FLASH_STMICRO | |
421 | +#define CONFIG_SPI_FLASH_BAR | |
422 | +#define CONFIG_CMD_SF | |
423 | +#define CONFIG_SF_DEFAULT_SPEED 10000000 | |
424 | +#define CONFIG_SF_DEFAULT_MODE 0 | |
425 | +#endif | |
426 | + | |
427 | +/* | |
428 | + * General PCI | |
429 | + * Memory space is mapped 1-1, but I/O space must start from 0. | |
430 | + */ | |
431 | +#define CONFIG_PCI /* Enable PCI/PCIE */ | |
432 | +#define CONFIG_PCIE1 /* PCIE controler 1 */ | |
433 | +#define CONFIG_PCIE2 /* PCIE controler 2 */ | |
434 | +#define CONFIG_PCIE3 /* PCIE controler 3 */ | |
435 | +#define CONFIG_PCIE4 /* PCIE controler 4 */ | |
436 | +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
437 | +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
438 | +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
439 | +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
440 | +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
441 | +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
442 | +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
443 | +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
444 | +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
445 | +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
446 | +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
447 | + | |
448 | +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
449 | +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
450 | +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
451 | +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
452 | +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
453 | +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
454 | +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
455 | +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
456 | +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
457 | + | |
458 | +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
459 | +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
460 | +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
461 | +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull | |
462 | +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
463 | +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
464 | +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
465 | +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
466 | +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
467 | + | |
468 | +/* controller 4, Base address 203000 */ | |
469 | +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 | |
470 | +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
471 | +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull | |
472 | +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
473 | +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
474 | +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
475 | +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
476 | + | |
477 | +#ifdef CONFIG_PCI | |
478 | +#define CONFIG_PCI_INDIRECT_BRIDGE | |
479 | +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ | |
480 | +#define CONFIG_NET_MULTI | |
481 | +#define CONFIG_E1000 | |
482 | +#define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
483 | +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
484 | +#define CONFIG_DOS_PARTITION | |
485 | +#endif | |
486 | + | |
487 | +/* Qman/Bman */ | |
488 | +#ifndef CONFIG_NOBQFMAN | |
489 | +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
490 | +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 | |
491 | +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
492 | +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
493 | +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
494 | +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 | |
495 | +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
496 | +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
497 | +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
498 | + | |
499 | +#define CONFIG_SYS_DPAA_FMAN | |
500 | +#define CONFIG_SYS_DPAA_PME | |
501 | +#define CONFIG_SYS_PMAN | |
502 | +#define CONFIG_SYS_DPAA_DCE | |
503 | +#define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
504 | +#define CONFIG_SYS_INTERLAKEN | |
505 | + | |
506 | +/* Default address of microcode for the Linux Fman driver */ | |
507 | +#if defined(CONFIG_SPIFLASH) | |
508 | +/* | |
509 | + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
510 | + * env, so we got 0x110000. | |
511 | + */ | |
512 | +#define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
513 | +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 | |
514 | +#define CONFIG_CORTINA_FW_ADDR 0x120000 | |
515 | + | |
516 | +#elif defined(CONFIG_SDCARD) | |
517 | +/* | |
518 | + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
519 | + * about 825KB (1650 blocks), Env is stored after the image, and the env size is | |
520 | + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
521 | + */ | |
522 | +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
523 | +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) | |
524 | +#define CONFIG_CORTINA_FW_ADDR (512 * 1808) | |
525 | + | |
526 | +#elif defined(CONFIG_NAND) | |
527 | +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
528 | +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
529 | +#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
530 | +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) | |
531 | +/* | |
532 | + * Slave has no ucode locally, it can fetch this from remote. When implementing | |
533 | + * in two corenet boards, slave's ucode could be stored in master's memory | |
534 | + * space, the address can be mapped from slave TLB->slave LAW-> | |
535 | + * slave SRIO or PCIE outbound window->master inbound window-> | |
536 | + * master LAW->the ucode address in master's memory space. | |
537 | + */ | |
538 | +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
539 | +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 | |
540 | +#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 | |
541 | +#else | |
542 | +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
543 | +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 | |
544 | +#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 | |
545 | +#endif | |
546 | +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
547 | +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
548 | +#endif /* CONFIG_NOBQFMAN */ | |
549 | + | |
550 | +#ifdef CONFIG_SYS_DPAA_FMAN | |
551 | +#define CONFIG_FMAN_ENET | |
552 | +#define CONFIG_PHYLIB_10G | |
553 | +#define CONFIG_PHY_CORTINA | |
554 | +#define CONFIG_PHY_AQ1202 | |
555 | +#define CONFIG_PHY_REALTEK | |
556 | +#define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
557 | +#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ | |
558 | +#define RGMII_PHY2_ADDR 0x02 | |
559 | +#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ | |
560 | +#define CORTINA_PHY_ADDR2 0x0d | |
561 | +#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ | |
562 | +#define FM1_10GEC4_PHY_ADDR 0x01 | |
563 | +#endif | |
564 | + | |
565 | + | |
566 | +#ifdef CONFIG_FMAN_ENET | |
567 | +#define CONFIG_MII /* MII PHY management */ | |
568 | +#define CONFIG_ETHPRIME "FM1@DTSEC3" | |
569 | +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
570 | +#endif | |
571 | + | |
572 | +/* | |
573 | + * SATA | |
574 | + */ | |
575 | +#ifdef CONFIG_FSL_SATA_V2 | |
576 | +#define CONFIG_LIBATA | |
577 | +#define CONFIG_FSL_SATA | |
578 | +#define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
579 | +#define CONFIG_SATA1 | |
580 | +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
581 | +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
582 | +#define CONFIG_SATA2 | |
583 | +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
584 | +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
585 | +#define CONFIG_LBA48 | |
586 | +#define CONFIG_CMD_SATA | |
587 | +#define CONFIG_DOS_PARTITION | |
588 | +#define CONFIG_CMD_EXT2 | |
589 | +#endif | |
590 | + | |
591 | +/* | |
592 | + * USB | |
593 | + */ | |
594 | +#ifdef CONFIG_USB_EHCI | |
595 | +#define CONFIG_CMD_USB | |
596 | +#define CONFIG_USB_STORAGE | |
597 | +#define CONFIG_USB_EHCI_FSL | |
598 | +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
599 | +#define CONFIG_CMD_EXT2 | |
600 | +#define CONFIG_HAS_FSL_DR_USB | |
601 | +#endif | |
602 | + | |
603 | +/* | |
604 | + * SDHC | |
605 | + */ | |
606 | +#ifdef CONFIG_MMC | |
607 | +#define CONFIG_CMD_MMC | |
608 | +#define CONFIG_FSL_ESDHC | |
609 | +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
610 | +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
611 | +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
612 | +#define CONFIG_GENERIC_MMC | |
613 | +#define CONFIG_CMD_EXT2 | |
614 | +#define CONFIG_CMD_FAT | |
615 | +#define CONFIG_DOS_PARTITION | |
616 | +#endif | |
617 | + | |
618 | +/* | |
619 | + * Environment | |
620 | + */ | |
621 | + | |
622 | +/* | |
623 | + * Command line configuration. | |
624 | + */ | |
625 | +#include <config_cmd_default.h> | |
626 | + | |
627 | +#define CONFIG_CMD_DHCP | |
628 | +#define CONFIG_CMD_ELF | |
629 | +#define CONFIG_CMD_MII | |
630 | +#define CONFIG_CMD_I2C | |
631 | +#define CONFIG_CMD_PING | |
632 | +#define CONFIG_CMD_ECHO | |
633 | +#define CONFIG_CMD_SETEXPR | |
634 | +#define CONFIG_CMD_REGINFO | |
635 | +#define CONFIG_CMD_BDI | |
636 | + | |
637 | +#ifdef CONFIG_PCI | |
638 | +#define CONFIG_CMD_PCI | |
639 | +#define CONFIG_CMD_NET | |
640 | +#endif | |
641 | + | |
642 | +/* | |
643 | + * Miscellaneous configurable options | |
644 | + */ | |
645 | +#define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
646 | +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
647 | +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
648 | +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
649 | +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
650 | +#ifdef CONFIG_CMD_KGDB | |
651 | +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
652 | +#else | |
653 | +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
654 | +#endif | |
655 | +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
656 | +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
657 | +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
658 | +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ | |
659 | + | |
660 | +/* | |
661 | + * For booting Linux, the board info and command line data | |
662 | + * have to be in the first 64 MB of memory, since this is | |
663 | + * the maximum mapped by the Linux kernel during initialization. | |
664 | + */ | |
665 | +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
666 | +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
667 | + | |
668 | +#ifdef CONFIG_CMD_KGDB | |
669 | +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
670 | +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
671 | +#endif | |
672 | + | |
673 | +/* | |
674 | + * Environment Configuration | |
675 | + */ | |
676 | +#define CONFIG_ROOTPATH "/opt/nfsroot" | |
677 | +#define CONFIG_BOOTFILE "uImage" | |
678 | +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ | |
679 | + | |
680 | +/* default location for tftp and bootm */ | |
681 | +#define CONFIG_LOADADDR 1000000 | |
682 | +#define CONFIG_BAUDRATE 115200 | |
683 | +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
684 | +#define __USB_PHY_TYPE utmi | |
685 | + | |
686 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
687 | + "hwconfig=fsl_ddr:" \ | |
688 | + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
689 | + "bank_intlv=auto;" \ | |
690 | + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
691 | + "netdev=eth0\0" \ | |
692 | + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
693 | + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
694 | + "tftpflash=tftpboot $loadaddr $uboot && " \ | |
695 | + "protect off $ubootaddr +$filesize && " \ | |
696 | + "erase $ubootaddr +$filesize && " \ | |
697 | + "cp.b $loadaddr $ubootaddr $filesize && " \ | |
698 | + "protect on $ubootaddr +$filesize && " \ | |
699 | + "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
700 | + "consoledev=ttyS0\0" \ | |
701 | + "ramdiskaddr=2000000\0" \ | |
702 | + "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ | |
703 | + "fdtaddr=c00000\0" \ | |
704 | + "fdtfile=t2080rdb/t2080rdb.dtb\0" \ | |
705 | + "bdev=sda3\0" \ | |
706 | + "c=ffe\0" | |
707 | + | |
708 | +/* | |
709 | + * For emulation this causes u-boot to jump to the start of the | |
710 | + * proof point app code automatically | |
711 | + */ | |
712 | +#define CONFIG_PROOF_POINTS \ | |
713 | + "setenv bootargs root=/dev/$bdev rw " \ | |
714 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
715 | + "cpu 1 release 0x29000000 - - -;" \ | |
716 | + "cpu 2 release 0x29000000 - - -;" \ | |
717 | + "cpu 3 release 0x29000000 - - -;" \ | |
718 | + "cpu 4 release 0x29000000 - - -;" \ | |
719 | + "cpu 5 release 0x29000000 - - -;" \ | |
720 | + "cpu 6 release 0x29000000 - - -;" \ | |
721 | + "cpu 7 release 0x29000000 - - -;" \ | |
722 | + "go 0x29000000" | |
723 | + | |
724 | +#define CONFIG_HVBOOT \ | |
725 | + "setenv bootargs config-addr=0x60000000; " \ | |
726 | + "bootm 0x01000000 - 0x00f00000" | |
727 | + | |
728 | +#define CONFIG_ALU \ | |
729 | + "setenv bootargs root=/dev/$bdev rw " \ | |
730 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
731 | + "cpu 1 release 0x01000000 - - -;" \ | |
732 | + "cpu 2 release 0x01000000 - - -;" \ | |
733 | + "cpu 3 release 0x01000000 - - -;" \ | |
734 | + "cpu 4 release 0x01000000 - - -;" \ | |
735 | + "cpu 5 release 0x01000000 - - -;" \ | |
736 | + "cpu 6 release 0x01000000 - - -;" \ | |
737 | + "cpu 7 release 0x01000000 - - -;" \ | |
738 | + "go 0x01000000" | |
739 | + | |
740 | +#define CONFIG_LINUX \ | |
741 | + "setenv bootargs root=/dev/ram rw " \ | |
742 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
743 | + "setenv ramdiskaddr 0x02000000;" \ | |
744 | + "setenv fdtaddr 0x00c00000;" \ | |
745 | + "setenv loadaddr 0x1000000;" \ | |
746 | + "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
747 | + | |
748 | +#define CONFIG_HDBOOT \ | |
749 | + "setenv bootargs root=/dev/$bdev rw " \ | |
750 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
751 | + "tftp $loadaddr $bootfile;" \ | |
752 | + "tftp $fdtaddr $fdtfile;" \ | |
753 | + "bootm $loadaddr - $fdtaddr" | |
754 | + | |
755 | +#define CONFIG_NFSBOOTCOMMAND \ | |
756 | + "setenv bootargs root=/dev/nfs rw " \ | |
757 | + "nfsroot=$serverip:$rootpath " \ | |
758 | + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
759 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
760 | + "tftp $loadaddr $bootfile;" \ | |
761 | + "tftp $fdtaddr $fdtfile;" \ | |
762 | + "bootm $loadaddr - $fdtaddr" | |
763 | + | |
764 | +#define CONFIG_RAMBOOTCOMMAND \ | |
765 | + "setenv bootargs root=/dev/ram rw " \ | |
766 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
767 | + "tftp $ramdiskaddr $ramdiskfile;" \ | |
768 | + "tftp $loadaddr $bootfile;" \ | |
769 | + "tftp $fdtaddr $fdtfile;" \ | |
770 | + "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
771 | + | |
772 | +#define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
773 | + | |
774 | +#ifdef CONFIG_SECURE_BOOT | |
775 | +#include <asm/fsl_secure_boot.h> | |
776 | +#undef CONFIG_CMD_USB | |
777 | +#endif | |
778 | + | |
779 | +#endif /* __T2080RDB_H */ |