Eric Lee / smarc-uboot

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Commit 8da35245abc60fa4828bff63858fb501690b0fd1

Authored by Bin Meng
Committed by Joe Hershberger
1 parent 0a60a81ba3
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

linux/mii.h: Sync with Linux kernel v4.17 

This syncs U-Boot's include/linux/mii.h with Linux kernel v4.17
include/uapi/linux/mii.h.

While we are here, this also fixes some style issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 1 changed file with 69 additions and 57 deletions Side-by-side Diff

  1 +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1 2 /*
2 3 * linux/mii.h: definitions for MII-compatible transceivers
3 4 * Originally drivers/net/sunhme.h.
4 5  
5 6  
6 7  
7 8  
8 9  
9 10  
... ... @@ -9,53 +10,55 @@
9 10 #define __LINUX_MII_H__
10 11  
11 12 /* Generic MII registers. */
  13 +#define MII_BMCR 0x00 /* Basic mode control register */
  14 +#define MII_BMSR 0x01 /* Basic mode status register */
  15 +#define MII_PHYSID1 0x02 /* PHYS ID 1 */
  16 +#define MII_PHYSID2 0x03 /* PHYS ID 2 */
  17 +#define MII_ADVERTISE 0x04 /* Advertisement control reg */
  18 +#define MII_LPA 0x05 /* Link partner ability reg */
  19 +#define MII_EXPANSION 0x06 /* Expansion register */
  20 +#define MII_CTRL1000 0x09 /* 1000BASE-T control */
  21 +#define MII_STAT1000 0x0a /* 1000BASE-T status */
  22 +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
  23 +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
  24 +#define MII_ESTATUS 0x0f /* Extended Status */
  25 +#define MII_DCOUNTER 0x12 /* Disconnect counter */
  26 +#define MII_FCSCOUNTER 0x13 /* False carrier counter */
  27 +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
  28 +#define MII_RERRCOUNTER 0x15 /* Receive error counter */
  29 +#define MII_SREVISION 0x16 /* Silicon revision */
  30 +#define MII_RESV1 0x17 /* Reserved... */
  31 +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
  32 +#define MII_PHYADDR 0x19 /* PHY address */
  33 +#define MII_RESV2 0x1a /* Reserved... */
  34 +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
  35 +#define MII_NCONFIG 0x1c /* Network interface config */
12 36  
13   -#define MII_BMCR 0x00 /* Basic mode control register */
14   -#define MII_BMSR 0x01 /* Basic mode status register */
15   -#define MII_PHYSID1 0x02 /* PHYS ID 1 */
16   -#define MII_PHYSID2 0x03 /* PHYS ID 2 */
17   -#define MII_ADVERTISE 0x04 /* Advertisement control reg */
18   -#define MII_LPA 0x05 /* Link partner ability reg */
19   -#define MII_EXPANSION 0x06 /* Expansion register */
20   -#define MII_CTRL1000 0x09 /* 1000BASE-T control */
21   -#define MII_STAT1000 0x0a /* 1000BASE-T status */
22   -#define MII_ESTATUS 0x0f /* Extended Status */
23   -#define MII_DCOUNTER 0x12 /* Disconnect counter */
24   -#define MII_FCSCOUNTER 0x13 /* False carrier counter */
25   -#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
26   -#define MII_RERRCOUNTER 0x15 /* Receive error counter */
27   -#define MII_SREVISION 0x16 /* Silicon revision */
28   -#define MII_RESV1 0x17 /* Reserved... */
29   -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
30   -#define MII_PHYADDR 0x19 /* PHY address */
31   -#define MII_RESV2 0x1a /* Reserved... */
32   -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
33   -#define MII_NCONFIG 0x1c /* Network interface config */
34   -
35 37 /* Basic mode control register. */
36   -#define BMCR_RESV 0x003f /* Unused... */
37   -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
38   -#define BMCR_CTST 0x0080 /* Collision test */
39   -#define BMCR_FULLDPLX 0x0100 /* Full duplex */
  38 +#define BMCR_RESV 0x003f /* Unused... */
  39 +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
  40 +#define BMCR_CTST 0x0080 /* Collision test */
  41 +#define BMCR_FULLDPLX 0x0100 /* Full duplex */
40 42 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
41   -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
42   -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
  43 +#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
  44 +#define BMCR_PDOWN 0x0800 /* Enable low power state */
43 45 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
44   -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
45   -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
46   -#define BMCR_RESET 0x8000 /* Reset the DP83840 */
  46 +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
  47 +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
  48 +#define BMCR_RESET 0x8000 /* Reset to default state */
  49 +#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
47 50  
48 51 /* Basic mode status register. */
49   -#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
50   -#define BMSR_JCD 0x0002 /* Jabber detected */
51   -#define BMSR_LSTATUS 0x0004 /* Link status */
  52 +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
  53 +#define BMSR_JCD 0x0002 /* Jabber detected */
  54 +#define BMSR_LSTATUS 0x0004 /* Link status */
52 55 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
53 56 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
54 57 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
55   -#define BMSR_RESV 0x00c0 /* Unused... */
56   -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
57   -#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
58   -#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
  58 +#define BMSR_RESV 0x00c0 /* Unused... */
  59 +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
  60 +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
  61 +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
59 62 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
60 63 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
61 64 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
... ... @@ -63,7 +66,7 @@
63 66 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
64 67  
65 68 /* Advertisement control register. */
66   -#define ADVERTISE_SLCT 0x001f /* Selector bits */
  69 +#define ADVERTISE_SLCT 0x001f /* Selector bits */
67 70 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
68 71 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
69 72 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
70 73  
71 74  
72 75  
73 76  
... ... @@ -72,19 +75,19 @@
72 75 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
73 76 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
74 77 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
75   -#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
  78 +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
76 79 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
77   -#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
  80 +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
78 81 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
79   -#define ADVERTISE_RESV 0x1000 /* Unused... */
  82 +#define ADVERTISE_RESV 0x1000 /* Unused... */
80 83 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
81 84 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
82   -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
  85 +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
83 86  
84   -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
85   - ADVERTISE_CSMA)
86   -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
87   - ADVERTISE_100HALF | ADVERTISE_100FULL)
  87 +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
  88 + ADVERTISE_CSMA)
  89 +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  90 + ADVERTISE_100HALF | ADVERTISE_100FULL)
88 91  
89 92 /* Link partner ability register. */
90 93 #define LPA_SLCT 0x001f /* Same as advertise selector */
91 94  
92 95  
... ... @@ -97,12 +100,12 @@
97 100 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
98 101 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
99 102 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
100   -#define LPA_PAUSE_CAP 0x0400 /* Can pause */
  103 +#define LPA_PAUSE_CAP 0x0400 /* Can pause */
101 104 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
102   -#define LPA_RESV 0x1000 /* Unused... */
  105 +#define LPA_RESV 0x1000 /* Unused... */
103 106 #define LPA_RFAULT 0x2000 /* Link partner faulted */
104 107 #define LPA_LPACK 0x4000 /* Link partner acked us */
105   -#define LPA_NPAGE 0x8000 /* Next page bit */
  108 +#define LPA_NPAGE 0x8000 /* Next page bit */
106 109  
107 110 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
108 111 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
109 112  
110 113  
111 114  
112 115  
... ... @@ -113,21 +116,23 @@
113 116 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
114 117 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
115 118 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
116   -#define EXPANSION_RESV 0xffe0 /* Unused... */
  119 +#define EXPANSION_RESV 0xffe0 /* Unused... */
117 120  
118 121 #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */
119 122 #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BX Half */
120   -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
121   -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
  123 +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
  124 +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
122 125  
123 126 /* N-way test register. */
124   -#define NWAYTEST_RESV1 0x00ff /* Unused... */
  127 +#define NWAYTEST_RESV1 0x00ff /* Unused... */
125 128 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
126   -#define NWAYTEST_RESV2 0xfe00 /* Unused... */
  129 +#define NWAYTEST_RESV2 0xfe00 /* Unused... */
127 130  
128 131 /* 1000BASE-T Control register */
129   -#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
130   -#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
  132 +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
  133 +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
  134 +#define CTL1000_AS_MASTER 0x0800
  135 +#define CTL1000_ENABLE_MASTER 0x1000
131 136  
132 137 /* 1000BASE-T Status register */
133 138 #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
... ... @@ -138,6 +143,13 @@
138 143 /* Flow control flags */
139 144 #define FLOW_CTRL_TX 0x01
140 145 #define FLOW_CTRL_RX 0x02
  146 +
  147 +/* MMD Access Control register fields */
  148 +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
  149 +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */
  150 +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
  151 +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
  152 +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
141 153  
142 154 /**
143 155 * mii_nway_result