Eric Lee / smarc-uboot

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Commit 8e904df6088d2bdbda54b1d6d996e17af6e02887

Authored by Kuldeep Singh
Committed by Priyanka Jain
1 parent 03effad96d
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

spi: Transform the FSL QuadSPI driver to use the SPI MEM API 

To support the SPI MEM API, instead of modifying the existing U-Boot
driver, this patch adds a port of the existing Linux driver.
This also has the advantage that porting changes and fixes from Linux will
be easier.
Porting of driver left most of the functions unchanged while few of the
changes are:
-Remove lock(mutexes) and irq handler as u-boot is a single core execution.
-Remove invalid masterid as it was required specially for multicore
execution in LS2088ARDB which is not the case in u-boot.
-Remove clock support as changing spi speed is not supported in uboot and
nor in linux.

Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY,
LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>

Showing 2 changed files with 608 additions and 1114 deletions Side-by-side Diff

drivers/spi/fsl_qspi.c
Diff comments   View file @ 8e904df
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1 1 // SPDX-License-Identifier: GPL-2.0+
  2 +
2 3 /*
3   - * Copyright 2013-2015 Freescale Semiconductor, Inc.
  4 + * Freescale QuadSPI driver.
4 5 *
5   - * Freescale Quad Serial Peripheral Interface (QSPI) driver
  6 + * Copyright (C) 2013 Freescale Semiconductor, Inc.
  7 + * Copyright (C) 2018 Bootlin
  8 + * Copyright (C) 2018 exceet electronics GmbH
  9 + * Copyright (C) 2018 Kontron Electronics GmbH
  10 + * Copyright 2019-2020 NXP
  11 + *
  12 + * This driver is a ported version of Linux Freescale QSPI driver taken from
  13 + * v5.5-rc1 tag having following information.
  14 + *
  15 + * Transition to SPI MEM interface:
  16 + * Authors:
  17 + * Boris Brezillon <bbrezillon@kernel.org>
  18 + * Frieder Schrempf <frieder.schrempf@kontron.de>
  19 + * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  20 + * Suresh Gupta <suresh.gupta@nxp.com>
  21 + *
  22 + * Based on the original fsl-quadspi.c spi-nor driver.
  23 + * Transition to spi-mem in spi-fsl-qspi.c
6 24 */
7 25  
8 26 #include <common.h>
9   -#include <malloc.h>
10   -#include <spi.h>
11 27 #include <asm/io.h>
12   -#include <linux/sizes.h>
13   -#include <linux/iopoll.h>
14 28 #include <dm.h>
15   -#include <errno.h>
16   -#include <watchdog.h>
17   -#include <wait_bit.h>
18   -#include "fsl_qspi.h"
  29 +#include <linux/iopoll.h>
  30 +#include <linux/sizes.h>
  31 +#include <linux/err.h>
  32 +#include <spi.h>
  33 +#include <spi-mem.h>
19 34  
20 35 DECLARE_GLOBAL_DATA_PTR;
21 36  
22   -#define OFFSET_BITS_MASK GENMASK(23, 0)
  37 +/*
  38 + * The driver only uses one single LUT entry, that is updated on
  39 + * each call of exec_op(). Index 0 is preset at boot with a basic
  40 + * read operation, so let's use the last entry (15).
  41 + */
  42 +#define SEQID_LUT 15
23 43  
24   -#define FLASH_STATUS_WEL 0x02
  44 +/* Registers used by the driver */
  45 +#define QUADSPI_MCR 0x00
  46 +#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  47 +#define QUADSPI_MCR_MDIS_MASK BIT(14)
  48 +#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  49 +#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  50 +#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  51 +#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  52 +#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  53 +#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
25 54  
26   -/* SEQID */
27   -#define SEQID_WREN 1
28   -#define SEQID_FAST_READ 2
29   -#define SEQID_RDSR 3
30   -#define SEQID_SE 4
31   -#define SEQID_CHIP_ERASE 5
32   -#define SEQID_PP 6
33   -#define SEQID_RDID 7
34   -#define SEQID_BE_4K 8
35   -#ifdef CONFIG_SPI_FLASH_BAR
36   -#define SEQID_BRRD 9
37   -#define SEQID_BRWR 10
38   -#define SEQID_RDEAR 11
39   -#define SEQID_WREAR 12
40   -#endif
41   -#define SEQID_WRAR 13
42   -#define SEQID_RDAR 14
  55 +#define QUADSPI_IPCR 0x08
  56 +#define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  57 +#define QUADSPI_FLSHCR 0x0c
  58 +#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  59 +#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  60 +#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
43 61  
44   -/* QSPI CMD */
45   -#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
46   -#define QSPI_CMD_RDSR 0x05 /* Read status register */
47   -#define QSPI_CMD_WREN 0x06 /* Write enable */
48   -#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
49   -#define QSPI_CMD_BE_4K 0x20 /* 4K erase */
50   -#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
51   -#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
52   -#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
  62 +#define QUADSPI_BUF3CR 0x1c
  63 +#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  64 +#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  65 +#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
53 66  
54   -/* Used for Micron, winbond and Macronix flashes */
55   -#define QSPI_CMD_WREAR 0xc5 /* EAR register write */
56   -#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
  67 +#define QUADSPI_BFGENCR 0x20
  68 +#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
57 69  
58   -/* Used for Spansion flashes only. */
59   -#define QSPI_CMD_BRRD 0x16 /* Bank register read */
60   -#define QSPI_CMD_BRWR 0x17 /* Bank register write */
  70 +#define QUADSPI_BUF0IND 0x30
  71 +#define QUADSPI_BUF1IND 0x34
  72 +#define QUADSPI_BUF2IND 0x38
  73 +#define QUADSPI_SFAR 0x100
61 74  
62   -/* Used for Spansion S25FS-S family flash only. */
63   -#define QSPI_CMD_RDAR 0x65 /* Read any device register */
64   -#define QSPI_CMD_WRAR 0x71 /* Write any device register */
  75 +#define QUADSPI_SMPR 0x108
  76 +#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  77 +#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  78 +#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  79 +#define QUADSPI_SMPR_HSENA_MASK BIT(0)
65 80  
66   -/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
67   -#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
68   -#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
69   -#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  81 +#define QUADSPI_RBCT 0x110
  82 +#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  83 +#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
70 84  
71   -/* fsl_qspi_platdata flags */
72   -#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  85 +#define QUADSPI_TBDR 0x154
73 86  
74   -/* default SCK frequency, unit: HZ */
75   -#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
  87 +#define QUADSPI_SR 0x15c
  88 +#define QUADSPI_SR_IP_ACC_MASK BIT(1)
  89 +#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
76 90  
77   -/* QSPI max chipselect signals number */
78   -#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
  91 +#define QUADSPI_FR 0x160
  92 +#define QUADSPI_FR_TFF_MASK BIT(0)
79 93  
80   -/* Controller needs driver to swap endian */
81   -#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  94 +#define QUADSPI_RSER 0x164
  95 +#define QUADSPI_RSER_TFIE BIT(0)
82 96  
83   -enum fsl_qspi_devtype {
84   - FSL_QUADSPI_VYBRID,
85   - FSL_QUADSPI_IMX6SX,
86   - FSL_QUADSPI_IMX6UL_7D,
87   - FSL_QUADSPI_IMX7ULP,
88   -};
  97 +#define QUADSPI_SPTRCLR 0x16c
  98 +#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  99 +#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
89 100  
90   -struct fsl_qspi_devtype_data {
91   - enum fsl_qspi_devtype devtype;
92   - u32 rxfifo;
93   - u32 txfifo;
94   - u32 ahb_buf_size;
95   - u32 driver_data;
96   -};
  101 +#define QUADSPI_SFA1AD 0x180
  102 +#define QUADSPI_SFA2AD 0x184
  103 +#define QUADSPI_SFB1AD 0x188
  104 +#define QUADSPI_SFB2AD 0x18c
  105 +#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
97 106  
98   -/**
99   - * struct fsl_qspi_platdata - platform data for Freescale QSPI
  107 +#define QUADSPI_LUTKEY 0x300
  108 +#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  109 +
  110 +#define QUADSPI_LCKCR 0x304
  111 +#define QUADSPI_LCKER_LOCK BIT(0)
  112 +#define QUADSPI_LCKER_UNLOCK BIT(1)
  113 +
  114 +#define QUADSPI_LUT_BASE 0x310
  115 +#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  116 +#define QUADSPI_LUT_REG(idx) \
  117 + (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  118 +
  119 +/* Instruction set for the LUT register */
  120 +#define LUT_STOP 0
  121 +#define LUT_CMD 1
  122 +#define LUT_ADDR 2
  123 +#define LUT_DUMMY 3
  124 +#define LUT_MODE 4
  125 +#define LUT_MODE2 5
  126 +#define LUT_MODE4 6
  127 +#define LUT_FSL_READ 7
  128 +#define LUT_FSL_WRITE 8
  129 +#define LUT_JMP_ON_CS 9
  130 +#define LUT_ADDR_DDR 10
  131 +#define LUT_MODE_DDR 11
  132 +#define LUT_MODE2_DDR 12
  133 +#define LUT_MODE4_DDR 13
  134 +#define LUT_FSL_READ_DDR 14
  135 +#define LUT_FSL_WRITE_DDR 15
  136 +#define LUT_DATA_LEARN 16
  137 +
  138 +/*
  139 + * The PAD definitions for LUT register.
100 140 *
101   - * @flags: Flags for QSPI QSPI_FLAG_...
102   - * @speed_hz: Default SCK frequency
103   - * @reg_base: Base address of QSPI registers
104   - * @amba_base: Base address of QSPI memory mapping
105   - * @amba_total_size: size of QSPI memory mapping
106   - * @flash_num: Number of active slave devices
107   - * @num_chipselect: Number of QSPI chipselect signals
  141 + * The pad stands for the number of IO lines [0:3].
  142 + * For example, the quad read needs four IO lines,
  143 + * so you should use LUT_PAD(4).
108 144 */
109   -struct fsl_qspi_platdata {
110   - u32 flags;
111   - u32 speed_hz;
112   - fdt_addr_t reg_base;
113   - fdt_addr_t amba_base;
114   - fdt_size_t amba_total_size;
115   - u32 flash_num;
116   - u32 num_chipselect;
117   -};
  145 +#define LUT_PAD(x) (fls(x) - 1)
118 146  
119   -/**
120   - * struct fsl_qspi_priv - private data for Freescale QSPI
  147 +/*
  148 + * Macro for constructing the LUT entries with the following
  149 + * register layout:
121 150 *
122   - * @flags: Flags for QSPI QSPI_FLAG_...
123   - * @bus_clk: QSPI input clk frequency
124   - * @speed_hz: Default SCK frequency
125   - * @cur_seqid: current LUT table sequence id
126   - * @sf_addr: flash access offset
127   - * @amba_base: Base address of QSPI memory mapping of every CS
128   - * @amba_total_size: size of QSPI memory mapping
129   - * @cur_amba_base: Base address of QSPI memory mapping of current CS
130   - * @flash_num: Number of active slave devices
131   - * @num_chipselect: Number of QSPI chipselect signals
132   - * @regs: Point to QSPI register structure for I/O access
  151 + * ---------------------------------------------------
  152 + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  153 + * ---------------------------------------------------
133 154 */
134   -struct fsl_qspi_priv {
135   - u32 flags;
136   - u32 bus_clk;
137   - u32 speed_hz;
138   - u32 cur_seqid;
139   - u32 sf_addr;
140   - u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
141   - u32 amba_total_size;
142   - u32 cur_amba_base;
143   - u32 flash_num;
144   - u32 num_chipselect;
145   - struct fsl_qspi_regs *regs;
146   - struct fsl_qspi_devtype_data *devtype_data;
  155 +#define LUT_DEF(idx, ins, pad, opr) \
  156 + ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  157 +
  158 +/* Controller needs driver to swap endianness */
  159 +#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  160 +
  161 +/* Controller needs 4x internal clock */
  162 +#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  163 +
  164 +/*
  165 + * TKT253890, the controller needs the driver to fill the txfifo with
  166 + * 16 bytes at least to trigger a data transfer, even though the extra
  167 + * data won't be transferred.
  168 + */
  169 +#define QUADSPI_QUIRK_TKT253890 BIT(2)
  170 +
  171 +/* TKT245618, the controller cannot wake up from wait mode */
  172 +#define QUADSPI_QUIRK_TKT245618 BIT(3)
  173 +
  174 +/*
  175 + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  176 + * internally. No need to add it when setting SFXXAD and SFAR registers
  177 + */
  178 +#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  179 +
  180 +/*
  181 + * Controller uses TDH bits in register QUADSPI_FLSHCR.
  182 + * They need to be set in accordance with the DDR/SDR mode.
  183 + */
  184 +#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  185 +
  186 +struct fsl_qspi_devtype_data {
  187 + unsigned int rxfifo;
  188 + unsigned int txfifo;
  189 + unsigned int ahb_buf_size;
  190 + unsigned int quirks;
  191 + bool little_endian;
147 192 };
148 193  
149 194 static const struct fsl_qspi_devtype_data vybrid_data = {
150   - .devtype = FSL_QUADSPI_VYBRID,
151   - .rxfifo = 128,
152   - .txfifo = 64,
153   - .ahb_buf_size = 1024,
154   - .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
  195 + .rxfifo = SZ_128,
  196 + .txfifo = SZ_64,
  197 + .ahb_buf_size = SZ_1K,
  198 + .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  199 + .little_endian = true,
155 200 };
156 201  
157 202 static const struct fsl_qspi_devtype_data imx6sx_data = {
158   - .devtype = FSL_QUADSPI_IMX6SX,
159   - .rxfifo = 128,
160   - .txfifo = 512,
161   - .ahb_buf_size = 1024,
162   - .driver_data = 0,
  203 + .rxfifo = SZ_128,
  204 + .txfifo = SZ_512,
  205 + .ahb_buf_size = SZ_1K,
  206 + .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  207 + .little_endian = true,
163 208 };
164 209  
165   -static const struct fsl_qspi_devtype_data imx6ul_7d_data = {
166   - .devtype = FSL_QUADSPI_IMX6UL_7D,
167   - .rxfifo = 128,
168   - .txfifo = 512,
169   - .ahb_buf_size = 1024,
170   - .driver_data = 0,
  210 +static const struct fsl_qspi_devtype_data imx7d_data = {
  211 + .rxfifo = SZ_128,
  212 + .txfifo = SZ_512,
  213 + .ahb_buf_size = SZ_1K,
  214 + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  215 + QUADSPI_QUIRK_USE_TDH_SETTING,
  216 + .little_endian = true,
171 217 };
172 218  
173   -static const struct fsl_qspi_devtype_data imx7ulp_data = {
174   - .devtype = FSL_QUADSPI_IMX7ULP,
175   - .rxfifo = 64,
176   - .txfifo = 64,
177   - .ahb_buf_size = 128,
178   - .driver_data = 0,
  219 +static const struct fsl_qspi_devtype_data imx6ul_data = {
  220 + .rxfifo = SZ_128,
  221 + .txfifo = SZ_512,
  222 + .ahb_buf_size = SZ_1K,
  223 + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  224 + QUADSPI_QUIRK_USE_TDH_SETTING,
  225 + .little_endian = true,
179 226 };
180 227  
181   -static u32 qspi_read32(u32 flags, u32 *addr)
  228 +static const struct fsl_qspi_devtype_data ls1021a_data = {
  229 + .rxfifo = SZ_128,
  230 + .txfifo = SZ_64,
  231 + .ahb_buf_size = SZ_1K,
  232 + .quirks = 0,
  233 + .little_endian = false,
  234 +};
  235 +
  236 +static const struct fsl_qspi_devtype_data ls1088a_data = {
  237 + .rxfifo = SZ_128,
  238 + .txfifo = SZ_128,
  239 + .ahb_buf_size = SZ_1K,
  240 + .quirks = QUADSPI_QUIRK_TKT253890,
  241 + .little_endian = true,
  242 +};
  243 +
  244 +static const struct fsl_qspi_devtype_data ls2080a_data = {
  245 + .rxfifo = SZ_128,
  246 + .txfifo = SZ_64,
  247 + .ahb_buf_size = SZ_1K,
  248 + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  249 + .little_endian = true,
  250 +};
  251 +
  252 +struct fsl_qspi {
  253 + struct udevice *dev;
  254 + void __iomem *iobase;
  255 + void __iomem *ahb_addr;
  256 + u32 memmap_phy;
  257 + const struct fsl_qspi_devtype_data *devtype_data;
  258 + int selected;
  259 +};
  260 +
  261 +static inline int needs_swap_endian(struct fsl_qspi *q)
182 262 {
183   - return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
184   - in_be32(addr) : in_le32(addr);
  263 + return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
185 264 }
186 265  
187   -static void qspi_write32(u32 flags, u32 *addr, u32 val)
  266 +static inline int needs_4x_clock(struct fsl_qspi *q)
188 267 {
189   - flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
190   - out_be32(addr, val) : out_le32(addr, val);
  268 + return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
191 269 }
192 270  
193   -static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
  271 +static inline int needs_fill_txfifo(struct fsl_qspi *q)
194 272 {
195   - u32 val;
196   - u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
197   - QSPI_SR_IP_ACC_MASK;
  273 + return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  274 +}
198 275  
199   - if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
200   - mask = (u32)cpu_to_be32(mask);
  276 +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  277 +{
  278 + return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  279 +}
201 280  
202   - return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
  281 +static inline int needs_amba_base_offset(struct fsl_qspi *q)
  282 +{
  283 + return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
203 284 }
204 285  
205   -/* QSPI support swapping the flash read/write data
206   - * in hardware for LS102xA, but not for VF610 */
207   -static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data)
  286 +static inline int needs_tdh_setting(struct fsl_qspi *q)
208 287 {
209   - if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN)
210   - return swab32(data);
211   - else
212   - return data;
  288 + return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
213 289 }
214 290  
215   -static void qspi_set_lut(struct fsl_qspi_priv *priv)
  291 +/*
  292 + * An IC bug makes it necessary to rearrange the 32-bit data.
  293 + * Later chips, such as IMX6SLX, have fixed this bug.
  294 + */
  295 +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
216 296 {
217   - struct fsl_qspi_regs *regs = priv->regs;
218   - u32 lut_base;
  297 + return needs_swap_endian(q) ? __swab32(a) : a;
  298 +}
219 299  
220   - /* Unlock the LUT */
221   - qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
222   - qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
223   -
224   - /* Write Enable */
225   - lut_base = SEQID_WREN * 4;
226   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
227   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
228   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
229   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
230   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
231   -
232   - /* Fast Read */
233   - lut_base = SEQID_FAST_READ * 4;
234   -#ifdef CONFIG_SPI_FLASH_BAR
235   - qspi_write32(priv->flags, &regs->lut[lut_base],
236   - OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
237   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
238   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
239   -#else
240   - if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
241   - qspi_write32(priv->flags, &regs->lut[lut_base],
242   - OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
243   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
244   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  300 +/*
  301 + * R/W functions for big- or little-endian registers:
  302 + * The QSPI controller's endianness is independent of
  303 + * the CPU core's endianness. So far, although the CPU
  304 + * core is little-endian the QSPI controller can use
  305 + * big-endian or little-endian.
  306 + */
  307 +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  308 +{
  309 + if (q->devtype_data->little_endian)
  310 + out_le32(addr, val);
245 311 else
246   - qspi_write32(priv->flags, &regs->lut[lut_base],
247   - OPRND0(QSPI_CMD_FAST_READ_4B) |
248   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
249   - OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
250   - INSTR1(LUT_ADDR));
251   -#endif
252   - qspi_write32(priv->flags, &regs->lut[lut_base + 1],
253   - OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
254   - OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) |
255   - INSTR1(LUT_READ));
256   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
257   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  312 + out_be32(addr, val);
  313 +}
258 314  
259   - /* Read Status */
260   - lut_base = SEQID_RDSR * 4;
261   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
262   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
263   - PAD1(LUT_PAD1) | INSTR1(LUT_READ));
264   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
265   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
266   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  315 +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  316 +{
  317 + if (q->devtype_data->little_endian)
  318 + return in_le32(addr);
267 319  
268   - /* Erase a sector */
269   - lut_base = SEQID_SE * 4;
270   -#ifdef CONFIG_SPI_FLASH_BAR
271   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
272   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
273   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
274   -#else
275   - if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
276   - qspi_write32(priv->flags, &regs->lut[lut_base],
277   - OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
278   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
279   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
280   - else
281   - qspi_write32(priv->flags, &regs->lut[lut_base],
282   - OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
283   - INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
284   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
285   -#endif
286   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
287   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
288   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  320 + return in_be32(addr);
  321 +}
289 322  
290   - /* Erase the whole chip */
291   - lut_base = SEQID_CHIP_ERASE * 4;
292   - qspi_write32(priv->flags, &regs->lut[lut_base],
293   - OPRND0(QSPI_CMD_CHIP_ERASE) |
294   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
295   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
296   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
297   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  323 +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  324 +{
  325 + switch (width) {
  326 + case 1:
  327 + case 2:
  328 + case 4:
  329 + return 0;
  330 + }
298 331  
299   - /* Page Program */
300   - lut_base = SEQID_PP * 4;
301   -#ifdef CONFIG_SPI_FLASH_BAR
302   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
303   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
304   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
305   -#else
306   - if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
307   - qspi_write32(priv->flags, &regs->lut[lut_base],
308   - OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
309   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
310   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
311   - else
312   - qspi_write32(priv->flags, &regs->lut[lut_base],
313   - OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
314   - INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
315   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
316   -#endif
317   - /* Use IDATSZ in IPCR to determine the size and here set 0. */
318   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
319   - PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
320   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
321   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  332 + return -ENOTSUPP;
  333 +}
322 334  
323   - /* READ ID */
324   - lut_base = SEQID_RDID * 4;
325   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
326   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
327   - PAD1(LUT_PAD1) | INSTR1(LUT_READ));
328   - qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
329   - qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
330   - qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
  335 +static bool fsl_qspi_supports_op(struct spi_slave *slave,
  336 + const struct spi_mem_op *op)
  337 +{
  338 + struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  339 + int ret;
331 340  
332   - /* SUB SECTOR 4K ERASE */
333   - lut_base = SEQID_BE_4K * 4;
334   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
335   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
336   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
  341 + ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
337 342  
338   -#ifdef CONFIG_SPI_FLASH_BAR
339   - /*
340   - * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
341   - * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
342   - * initialization.
343   - */
344   - lut_base = SEQID_BRRD * 4;
345   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
346   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
347   - PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  343 + if (op->addr.nbytes)
  344 + ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
348 345  
349   - lut_base = SEQID_BRWR * 4;
350   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
351   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
352   - PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
  346 + if (op->dummy.nbytes)
  347 + ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
353 348  
354   - lut_base = SEQID_RDEAR * 4;
355   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
356   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
357   - PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  349 + if (op->data.nbytes)
  350 + ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
358 351  
359   - lut_base = SEQID_WREAR * 4;
360   - qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
361   - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
362   - PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
363   -#endif
  352 + if (ret)
  353 + return false;
364 354  
365 355 /*
366   - * Read any device register.
367   - * Used for Spansion S25FS-S family flash only.
  356 + * The number of instructions needed for the op, needs
  357 + * to fit into a single LUT entry.
368 358 */
369   - lut_base = SEQID_RDAR * 4;
370   - qspi_write32(priv->flags, &regs->lut[lut_base],
371   - OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
372   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
373   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
374   - qspi_write32(priv->flags, &regs->lut[lut_base + 1],
375   - OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
376   - OPRND1(1) | PAD1(LUT_PAD1) |
377   - INSTR1(LUT_READ));
  359 + if (op->addr.nbytes +
  360 + (op->dummy.nbytes ? 1 : 0) +
  361 + (op->data.nbytes ? 1 : 0) > 6)
  362 + return false;
378 363  
379   - /*
380   - * Write any device register.
381   - * Used for Spansion S25FS-S family flash only.
382   - */
383   - lut_base = SEQID_WRAR * 4;
384   - qspi_write32(priv->flags, &regs->lut[lut_base],
385   - OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
386   - INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
387   - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
388   - qspi_write32(priv->flags, &regs->lut[lut_base + 1],
389   - OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
  364 + /* Max 64 dummy clock cycles supported */
  365 + if (op->dummy.nbytes &&
  366 + (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  367 + return false;
390 368  
391   - /* Lock the LUT */
392   - qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
393   - qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
  369 + /* Max data length, check controller limits and alignment */
  370 + if (op->data.dir == SPI_MEM_DATA_IN &&
  371 + (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  372 + (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  373 + !IS_ALIGNED(op->data.nbytes, 8))))
  374 + return false;
  375 +
  376 + if (op->data.dir == SPI_MEM_DATA_OUT &&
  377 + op->data.nbytes > q->devtype_data->txfifo)
  378 + return false;
  379 +
  380 + return true;
394 381 }
395 382  
396   -#if defined(CONFIG_SYS_FSL_QSPI_AHB)
397   -/*
398   - * If we have changed the content of the flash by writing or erasing,
399   - * we need to invalidate the AHB buffer. If we do not do so, we may read out
400   - * the wrong data. The spec tells us reset the AHB domain and Serial Flash
401   - * domain at the same time.
402   - */
403   -static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
  383 +static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  384 + const struct spi_mem_op *op)
404 385 {
405   - struct fsl_qspi_regs *regs = priv->regs;
406   - u32 reg;
  386 + void __iomem *base = q->iobase;
  387 + u32 lutval[4] = {};
  388 + int lutidx = 1, i;
407 389  
408   - reg = qspi_read32(priv->flags, &regs->mcr);
409   - reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
410   - qspi_write32(priv->flags, &regs->mcr, reg);
  390 + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  391 + op->cmd.opcode);
411 392  
412 393 /*
413   - * The minimum delay : 1 AHB + 2 SFCK clocks.
414   - * Delay 1 us is enough.
  394 + * For some unknown reason, using LUT_ADDR doesn't work in some
  395 + * cases (at least with only one byte long addresses), so
  396 + * let's use LUT_MODE to write the address bytes one by one
415 397 */
416   - udelay(1);
  398 + for (i = 0; i < op->addr.nbytes; i++) {
  399 + u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
417 400  
418   - reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
419   - qspi_write32(priv->flags, &regs->mcr, reg);
420   -}
  401 + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  402 + LUT_PAD(op->addr.buswidth),
  403 + addrbyte);
  404 + lutidx++;
  405 + }
421 406  
422   -/* Read out the data from the AHB buffer. */
423   -static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
424   -{
425   - struct fsl_qspi_regs *regs = priv->regs;
426   - u32 mcr_reg;
427   - void *rx_addr;
  407 + if (op->dummy.nbytes) {
  408 + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  409 + LUT_PAD(op->dummy.buswidth),
  410 + op->dummy.nbytes * 8 /
  411 + op->dummy.buswidth);
  412 + lutidx++;
  413 + }
428 414  
429   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
  415 + if (op->data.nbytes) {
  416 + lutval[lutidx / 2] |= LUT_DEF(lutidx,
  417 + op->data.dir == SPI_MEM_DATA_IN ?
  418 + LUT_FSL_READ : LUT_FSL_WRITE,
  419 + LUT_PAD(op->data.buswidth),
  420 + 0);
  421 + lutidx++;
  422 + }
430 423  
431   - qspi_write32(priv->flags, &regs->mcr,
432   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
433   - mcr_reg);
  424 + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
434 425  
435   - rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
436   - /* Read out the data directly from the AHB buffer. */
437   - memcpy(rxbuf, rx_addr, len);
  426 + /* unlock LUT */
  427 + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  428 + qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
438 429  
439   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
440   -}
  430 + dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  431 + op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
441 432  
442   -static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
443   -{
444   - u32 reg, reg2;
445   - struct fsl_qspi_regs *regs = priv->regs;
  433 + /* fill LUT */
  434 + for (i = 0; i < ARRAY_SIZE(lutval); i++)
  435 + qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
446 436  
447   - reg = qspi_read32(priv->flags, &regs->mcr);
448   - /* Disable the module */
449   - qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
450   -
451   - /* Set the Sampling Register for DDR */
452   - reg2 = qspi_read32(priv->flags, &regs->smpr);
453   - reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
454   - reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
455   - qspi_write32(priv->flags, &regs->smpr, reg2);
456   -
457   - /* Enable the module again (enable the DDR too) */
458   - reg |= QSPI_MCR_DDR_EN_MASK;
459   - /* Enable bit 29 for imx6sx */
460   - reg |= BIT(29);
461   - qspi_write32(priv->flags, &regs->mcr, reg);
462   -
463   - /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
464   - * These two bits are reserved on other platforms
465   - */
466   - reg = qspi_read32(priv->flags, &regs->flshcr);
467   - reg &= ~(BIT(17));
468   - reg |= BIT(16);
469   - qspi_write32(priv->flags, &regs->flshcr, reg);
  437 + /* lock LUT */
  438 + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  439 + qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
470 440 }
471 441  
472 442 /*
473   - * There are two different ways to read out the data from the flash:
474   - * the "IP Command Read" and the "AHB Command Read".
475   - *
476   - * The IC guy suggests we use the "AHB Command Read" which is faster
477   - * then the "IP Command Read". (What's more is that there is a bug in
478   - * the "IP Command Read" in the Vybrid.)
479   - *
480   - * After we set up the registers for the "AHB Command Read", we can use
481   - * the memcpy to read the data directly. A "missed" access to the buffer
482   - * causes the controller to clear the buffer, and use the sequence pointed
483   - * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
  443 + * If we have changed the content of the flash by writing or erasing, or if we
  444 + * read from flash with a different offset into the page buffer, we need to
  445 + * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  446 + * data. The spec tells us reset the AHB domain and Serial Flash domain at
  447 + * the same time.
484 448 */
485   -static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
  449 +static void fsl_qspi_invalidate(struct fsl_qspi *q)
486 450 {
487   - struct fsl_qspi_regs *regs = priv->regs;
  451 + u32 reg;
488 452  
489   - /* AHB configuration for access buffer 0/1/2 .*/
490   - qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
491   - qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
492   - qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
493   - qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
494   - ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT));
  453 + reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  454 + reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  455 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
495 456  
496   - /* We only use the buffer3 */
497   - qspi_write32(priv->flags, &regs->buf0ind, 0);
498   - qspi_write32(priv->flags, &regs->buf1ind, 0);
499   - qspi_write32(priv->flags, &regs->buf2ind, 0);
500   -
501 457 /*
502   - * Set the default lut sequence for AHB Read.
503   - * Parallel mode is disabled.
  458 + * The minimum delay : 1 AHB + 2 SFCK clocks.
  459 + * Delay 1 us is enough.
504 460 */
505   - qspi_write32(priv->flags, &regs->bfgencr,
506   - SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
  461 + udelay(1);
507 462  
508   - /*Enable DDR Mode*/
509   - qspi_enable_ddr_mode(priv);
  463 + reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  464 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
510 465 }
511   -#endif
512 466  
513   -#ifdef CONFIG_SPI_FLASH_BAR
514   -/* Bank register read/write, EAR register read/write */
515   -static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
  467 +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
516 468 {
517   - struct fsl_qspi_regs *regs = priv->regs;
518   - u32 reg, mcr_reg, data, seqid;
  469 + struct dm_spi_slave_platdata *plat =
  470 + dev_get_parent_platdata(slave->dev);
519 471  
520   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
521   - qspi_write32(priv->flags, &regs->mcr,
522   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
523   - mcr_reg);
524   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
  472 + if (q->selected == plat->cs)
  473 + return;
525 474  
526   - qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
  475 + q->selected = plat->cs;
  476 + fsl_qspi_invalidate(q);
  477 +}
527 478  
528   - if (priv->cur_seqid == QSPI_CMD_BRRD)
529   - seqid = SEQID_BRRD;
530   - else
531   - seqid = SEQID_RDEAR;
  479 +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  480 +{
  481 + memcpy_fromio(op->data.buf.in,
  482 + q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
  483 + op->data.nbytes);
  484 +}
532 485  
533   - qspi_write32(priv->flags, &regs->ipcr,
534   - (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
  486 +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  487 + const struct spi_mem_op *op)
  488 +{
  489 + void __iomem *base = q->iobase;
  490 + int i;
  491 + u32 val;
535 492  
536   - /* Wait previous command complete */
537   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
538   - ;
  493 + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  494 + memcpy(&val, op->data.buf.out + i, 4);
  495 + val = fsl_qspi_endian_xchg(q, val);
  496 + qspi_writel(q, val, base + QUADSPI_TBDR);
  497 + }
539 498  
540   - while (1) {
541   - WATCHDOG_RESET();
542   -
543   - reg = qspi_read32(priv->flags, &regs->rbsr);
544   - if (reg & QSPI_RBSR_RDBFL_MASK) {
545   - data = qspi_read32(priv->flags, &regs->rbdr[0]);
546   - data = qspi_endian_xchg(priv, data);
547   - memcpy(rxbuf, &data, len);
548   - qspi_write32(priv->flags, &regs->mcr,
549   - qspi_read32(priv->flags, &regs->mcr) |
550   - QSPI_MCR_CLR_RXF_MASK);
551   - break;
552   - }
  499 + if (i < op->data.nbytes) {
  500 + memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  501 + val = fsl_qspi_endian_xchg(q, val);
  502 + qspi_writel(q, val, base + QUADSPI_TBDR);
553 503 }
554 504  
555   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
  505 + if (needs_fill_txfifo(q)) {
  506 + for (i = op->data.nbytes; i < 16; i += 4)
  507 + qspi_writel(q, 0, base + QUADSPI_TBDR);
  508 + }
556 509 }
557   -#endif
558 510  
559   -static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
  511 +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  512 + const struct spi_mem_op *op)
560 513 {
561   - struct fsl_qspi_regs *regs = priv->regs;
562   - u32 mcr_reg, rbsr_reg, data, size;
  514 + void __iomem *base = q->iobase;
563 515 int i;
  516 + u8 *buf = op->data.buf.in;
  517 + u32 val;
564 518  
565   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
566   - qspi_write32(priv->flags, &regs->mcr,
567   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
568   - mcr_reg);
569   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
570   -
571   - qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
572   -
573   - qspi_write32(priv->flags, &regs->ipcr,
574   - (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
575   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
576   - ;
577   -
578   - i = 0;
579   - while ((priv->devtype_data->rxfifo >= len) && (len > 0)) {
580   - WATCHDOG_RESET();
581   -
582   - rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
583   - if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
584   - data = qspi_read32(priv->flags, &regs->rbdr[i]);
585   - data = qspi_endian_xchg(priv, data);
586   - size = (len < 4) ? len : 4;
587   - memcpy(rxbuf, &data, size);
588   - len -= size;
589   - rxbuf++;
590   - i++;
591   - }
  519 + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  520 + val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  521 + val = fsl_qspi_endian_xchg(q, val);
  522 + memcpy(buf + i, &val, 4);
592 523 }
593 524  
594   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
  525 + if (i < op->data.nbytes) {
  526 + val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  527 + val = fsl_qspi_endian_xchg(q, val);
  528 + memcpy(buf + i, &val, op->data.nbytes - i);
  529 + }
595 530 }
596 531  
597   -/* If not use AHB read, read data from ip interface */
598   -static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
  532 +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  533 + u32 mask, u32 delay_us, u32 timeout_us)
599 534 {
600   - struct fsl_qspi_regs *regs = priv->regs;
601   - u32 mcr_reg, data;
602   - int i, size;
603   - u32 to_or_from;
604   - u32 seqid;
  535 + u32 reg;
605 536  
606   - if (priv->cur_seqid == QSPI_CMD_RDAR)
607   - seqid = SEQID_RDAR;
608   - else
609   - seqid = SEQID_FAST_READ;
  537 + if (!q->devtype_data->little_endian)
  538 + mask = (u32)cpu_to_be32(mask);
610 539  
611   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
612   - qspi_write32(priv->flags, &regs->mcr,
613   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
614   - mcr_reg);
615   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
616   -
617   - to_or_from = priv->sf_addr + priv->cur_amba_base;
618   -
619   - while (len > 0) {
620   - WATCHDOG_RESET();
621   -
622   - qspi_write32(priv->flags, &regs->sfar, to_or_from);
623   -
624   - size = (len > priv->devtype_data->rxfifo) ?
625   - priv->devtype_data->rxfifo : len;
626   -
627   - qspi_write32(priv->flags, &regs->ipcr,
628   - (seqid << QSPI_IPCR_SEQID_SHIFT) |
629   - size);
630   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
631   - ;
632   -
633   - to_or_from += size;
634   - len -= size;
635   -
636   - i = 0;
637   - while ((priv->devtype_data->rxfifo >= size) && (size > 0)) {
638   - data = qspi_read32(priv->flags, &regs->rbdr[i]);
639   - data = qspi_endian_xchg(priv, data);
640   - if (size < 4)
641   - memcpy(rxbuf, &data, size);
642   - else
643   - memcpy(rxbuf, &data, 4);
644   - rxbuf++;
645   - size -= 4;
646   - i++;
647   - }
648   - qspi_write32(priv->flags, &regs->mcr,
649   - qspi_read32(priv->flags, &regs->mcr) |
650   - QSPI_MCR_CLR_RXF_MASK);
651   - }
652   -
653   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
  540 + return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
654 541 }
655 542  
656   -static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
  543 +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
657 544 {
658   - struct fsl_qspi_regs *regs = priv->regs;
659   - u32 mcr_reg, data, reg, status_reg, seqid;
660   - int i, size, tx_size;
661   - u32 to_or_from = 0;
  545 + void __iomem *base = q->iobase;
  546 + int err = 0;
662 547  
663   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
664   - qspi_write32(priv->flags, &regs->mcr,
665   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
666   - mcr_reg);
667   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
668   -
669   - status_reg = 0;
670   - while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
671   - WATCHDOG_RESET();
672   -
673   - qspi_write32(priv->flags, &regs->ipcr,
674   - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
675   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
676   - ;
677   -
678   - qspi_write32(priv->flags, &regs->ipcr,
679   - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
680   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
681   - ;
682   -
683   - reg = qspi_read32(priv->flags, &regs->rbsr);
684   - if (reg & QSPI_RBSR_RDBFL_MASK) {
685   - status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
686   - status_reg = qspi_endian_xchg(priv, status_reg);
687   - }
688   - qspi_write32(priv->flags, &regs->mcr,
689   - qspi_read32(priv->flags, &regs->mcr) |
690   - QSPI_MCR_CLR_RXF_MASK);
691   - }
692   -
693   - /* Default is page programming */
694   - seqid = SEQID_PP;
695   - if (priv->cur_seqid == QSPI_CMD_WRAR)
696   - seqid = SEQID_WRAR;
697   -#ifdef CONFIG_SPI_FLASH_BAR
698   - if (priv->cur_seqid == QSPI_CMD_BRWR)
699   - seqid = SEQID_BRWR;
700   - else if (priv->cur_seqid == QSPI_CMD_WREAR)
701   - seqid = SEQID_WREAR;
702   -#endif
703   -
704   - to_or_from = priv->sf_addr + priv->cur_amba_base;
705   -
706   - qspi_write32(priv->flags, &regs->sfar, to_or_from);
707   -
708   - tx_size = (len > priv->devtype_data->txfifo) ?
709   - priv->devtype_data->txfifo : len;
710   -
711   - size = tx_size / 16;
712 548 /*
713   - * There must be atleast 128bit data
714   - * available in TX FIFO for any pop operation
  549 + * Always start the sequence at the same index since we update
  550 + * the LUT at each exec_op() call. And also specify the DATA
  551 + * length, since it's has not been specified in the LUT.
715 552 */
716   - if (tx_size % 16)
717   - size++;
718   - for (i = 0; i < size * 4; i++) {
719   - memcpy(&data, txbuf, 4);
720   - data = qspi_endian_xchg(priv, data);
721   - qspi_write32(priv->flags, &regs->tbdr, data);
722   - txbuf += 4;
723   - }
  553 + qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  554 + base + QUADSPI_IPCR);
724 555  
725   - qspi_write32(priv->flags, &regs->ipcr,
726   - (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
727   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
728   - ;
  556 + /* wait for the controller being ready */
  557 + err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  558 + (QUADSPI_SR_IP_ACC_MASK |
  559 + QUADSPI_SR_AHB_ACC_MASK),
  560 + 10, 1000);
729 561  
730   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
731   -}
  562 + if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  563 + fsl_qspi_read_rxfifo(q, op);
732 564  
733   -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
734   -{
735   - struct fsl_qspi_regs *regs = priv->regs;
736   - u32 mcr_reg, reg, data;
737   -
738   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
739   - qspi_write32(priv->flags, &regs->mcr,
740   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
741   - mcr_reg);
742   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
743   -
744   - qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
745   -
746   - qspi_write32(priv->flags, &regs->ipcr,
747   - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
748   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
749   - ;
750   -
751   - while (1) {
752   - WATCHDOG_RESET();
753   -
754   - reg = qspi_read32(priv->flags, &regs->rbsr);
755   - if (reg & QSPI_RBSR_RDBFL_MASK) {
756   - data = qspi_read32(priv->flags, &regs->rbdr[0]);
757   - data = qspi_endian_xchg(priv, data);
758   - memcpy(rxbuf, &data, len);
759   - qspi_write32(priv->flags, &regs->mcr,
760   - qspi_read32(priv->flags, &regs->mcr) |
761   - QSPI_MCR_CLR_RXF_MASK);
762   - break;
763   - }
764   - }
765   -
766   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
  565 + return err;
767 566 }
768 567  
769   -static void qspi_op_erase(struct fsl_qspi_priv *priv)
  568 +static int fsl_qspi_exec_op(struct spi_slave *slave,
  569 + const struct spi_mem_op *op)
770 570 {
771   - struct fsl_qspi_regs *regs = priv->regs;
772   - u32 mcr_reg;
773   - u32 to_or_from = 0;
  571 + struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  572 + void __iomem *base = q->iobase;
  573 + u32 addr_offset = 0;
  574 + int err = 0;
774 575  
775   - mcr_reg = qspi_read32(priv->flags, &regs->mcr);
776   - qspi_write32(priv->flags, &regs->mcr,
777   - QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
778   - mcr_reg);
779   - qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
  576 + /* wait for the controller being ready */
  577 + fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  578 + QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
780 579  
781   - to_or_from = priv->sf_addr + priv->cur_amba_base;
782   - qspi_write32(priv->flags, &regs->sfar, to_or_from);
  580 + fsl_qspi_select_mem(q, slave);
783 581  
784   - qspi_write32(priv->flags, &regs->ipcr,
785   - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
786   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
787   - ;
  582 + if (needs_amba_base_offset(q))
  583 + addr_offset = q->memmap_phy;
788 584  
789   - if (priv->cur_seqid == QSPI_CMD_SE) {
790   - qspi_write32(priv->flags, &regs->ipcr,
791   - (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
792   - } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
793   - qspi_write32(priv->flags, &regs->ipcr,
794   - (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
795   - }
796   - while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
797   - ;
  585 + qspi_writel(q,
  586 + q->selected * q->devtype_data->ahb_buf_size + addr_offset,
  587 + base + QUADSPI_SFAR);
798 588  
799   - qspi_write32(priv->flags, &regs->mcr, mcr_reg);
800   -}
  589 + qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  590 + QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  591 + base + QUADSPI_MCR);
801 592  
802   -int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
803   - const void *dout, void *din, unsigned long flags)
804   -{
805   - u32 bytes = DIV_ROUND_UP(bitlen, 8);
806   - static u32 wr_sfaddr;
807   - u32 txbuf;
  593 + qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  594 + base + QUADSPI_SPTRCLR);
808 595  
809   - WATCHDOG_RESET();
  596 + fsl_qspi_prepare_lut(q, op);
810 597  
811   - if (dout) {
812   - if (flags & SPI_XFER_BEGIN) {
813   - priv->cur_seqid = *(u8 *)dout;
814   - memcpy(&txbuf, dout, 4);
815   - }
  598 + /*
  599 + * If we have large chunks of data, we read them through the AHB bus
  600 + * by accessing the mapped memory. In all other cases we use
  601 + * IP commands to access the flash.
  602 + */
  603 + if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  604 + op->data.dir == SPI_MEM_DATA_IN) {
  605 + fsl_qspi_read_ahb(q, op);
  606 + } else {
  607 + qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  608 + QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
816 609  
817   - if (flags == SPI_XFER_END) {
818   - priv->sf_addr = wr_sfaddr;
819   - qspi_op_write(priv, (u8 *)dout, bytes);
820   - return 0;
821   - }
  610 + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  611 + fsl_qspi_fill_txfifo(q, op);
822 612  
823   - if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
824   - priv->cur_seqid == QSPI_CMD_RDAR) {
825   - priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
826   - } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
827   - (priv->cur_seqid == QSPI_CMD_BE_4K)) {
828   - priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
829   - qspi_op_erase(priv);
830   - } else if (priv->cur_seqid == QSPI_CMD_PP ||
831   - priv->cur_seqid == QSPI_CMD_WRAR) {
832   - wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
833   - } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
834   - (priv->cur_seqid == QSPI_CMD_WREAR)) {
835   -#ifdef CONFIG_SPI_FLASH_BAR
836   - wr_sfaddr = 0;
837   -#endif
838   - }
  613 + err = fsl_qspi_do_op(q, op);
839 614 }
840 615  
841   - if (din) {
842   - if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
843   -#ifdef CONFIG_SYS_FSL_QSPI_AHB
844   - qspi_ahb_read(priv, din, bytes);
845   -#else
846   - qspi_op_read(priv, din, bytes);
847   -#endif
848   - } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
849   - qspi_op_read(priv, din, bytes);
850   - } else if (priv->cur_seqid == QSPI_CMD_RDID)
851   - qspi_op_rdid(priv, din, bytes);
852   - else if (priv->cur_seqid == QSPI_CMD_RDSR)
853   - qspi_op_rdsr(priv, din, bytes);
854   -#ifdef CONFIG_SPI_FLASH_BAR
855   - else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
856   - (priv->cur_seqid == QSPI_CMD_RDEAR)) {
857   - priv->sf_addr = 0;
858   - qspi_op_rdbank(priv, din, bytes);
859   - }
860   -#endif
861   - }
  616 + /* Invalidate the data in the AHB buffer. */
  617 + fsl_qspi_invalidate(q);
862 618  
863   -#ifdef CONFIG_SYS_FSL_QSPI_AHB
864   - if ((priv->cur_seqid == QSPI_CMD_SE) ||
865   - (priv->cur_seqid == QSPI_CMD_PP) ||
866   - (priv->cur_seqid == QSPI_CMD_BE_4K) ||
867   - (priv->cur_seqid == QSPI_CMD_WREAR) ||
868   - (priv->cur_seqid == QSPI_CMD_BRWR))
869   - qspi_ahb_invalid(priv);
870   -#endif
871   -
872   - return 0;
  619 + return err;
873 620 }
874 621  
875   -void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
  622 +static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  623 + struct spi_mem_op *op)
876 624 {
877   - u32 mcr_val;
  625 + struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
878 626  
879   - mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
880   - if (disable)
881   - mcr_val |= QSPI_MCR_MDIS_MASK;
882   - else
883   - mcr_val &= ~QSPI_MCR_MDIS_MASK;
884   - qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
885   -}
  627 + if (op->data.dir == SPI_MEM_DATA_OUT) {
  628 + if (op->data.nbytes > q->devtype_data->txfifo)
  629 + op->data.nbytes = q->devtype_data->txfifo;
  630 + } else {
  631 + if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  632 + op->data.nbytes = q->devtype_data->ahb_buf_size;
  633 + else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  634 + op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  635 + }
886 636  
887   -void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
888   -{
889   - u32 smpr_val;
890   -
891   - smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
892   - smpr_val &= ~clear_bits;
893   - smpr_val |= set_bits;
894   - qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
895   -}
896   -
897   -static int fsl_qspi_child_pre_probe(struct udevice *dev)
898   -{
899   - struct spi_slave *slave = dev_get_parent_priv(dev);
900   - struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev));
901   -
902   - slave->max_write_size = priv->devtype_data->txfifo;
903   -
904 637 return 0;
905 638 }
906 639  
907   -static int fsl_qspi_probe(struct udevice *bus)
  640 +static int fsl_qspi_default_setup(struct fsl_qspi *q)
908 641 {
909   - u32 amba_size_per_chip;
910   - struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
911   - struct fsl_qspi_priv *priv = dev_get_priv(bus);
912   - struct dm_spi_bus *dm_spi_bus;
913   - int i, ret;
  642 + void __iomem *base = q->iobase;
  643 + u32 reg, addr_offset = 0;
914 644  
915   - dm_spi_bus = bus->uclass_priv;
  645 + /* Reset the module */
  646 + qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  647 + base + QUADSPI_MCR);
  648 + udelay(1);
916 649  
917   - dm_spi_bus->max_hz = plat->speed_hz;
  650 + /* Disable the module */
  651 + qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  652 + base + QUADSPI_MCR);
918 653  
919   - priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
920   - priv->flags = plat->flags;
921   -
922   - priv->speed_hz = plat->speed_hz;
923 654 /*
924   - * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
925   - * AMBA memory zone should be located on the 0~4GB space
926   - * even on a 64bits cpu.
  655 + * Previous boot stages (BootROM, bootloader) might have used DDR
  656 + * mode and did not clear the TDH bits. As we currently use SDR mode
  657 + * only, clear the TDH bits if necessary.
927 658 */
928   - priv->amba_base[0] = (u32)plat->amba_base;
929   - priv->amba_total_size = (u32)plat->amba_total_size;
930   - priv->flash_num = plat->flash_num;
931   - priv->num_chipselect = plat->num_chipselect;
  659 + if (needs_tdh_setting(q))
  660 + qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  661 + ~QUADSPI_FLSHCR_TDH_MASK,
  662 + base + QUADSPI_FLSHCR);
932 663  
933   - priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus);
934   - if (!priv->devtype_data) {
935   - printf("ERROR : No devtype_data found\n");
936   - return -ENODEV;
937   - }
  664 + reg = qspi_readl(q, base + QUADSPI_SMPR);
  665 + qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  666 + | QUADSPI_SMPR_FSPHS_MASK
  667 + | QUADSPI_SMPR_HSENA_MASK
  668 + | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
938 669  
939   - debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n",
940   - priv->devtype_data->devtype,
941   - priv->devtype_data->txfifo,
942   - priv->devtype_data->rxfifo,
943   - priv->devtype_data->ahb_buf_size,
944   - priv->devtype_data->driver_data);
  670 + /* We only use the buffer3 for AHB read */
  671 + qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  672 + qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  673 + qspi_writel(q, 0, base + QUADSPI_BUF2IND);
945 674  
946   - /* make sure controller is not busy anywhere */
947   - ret = is_controller_busy(priv);
  675 + qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  676 + q->iobase + QUADSPI_BFGENCR);
  677 + qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  678 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  679 + QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  680 + base + QUADSPI_BUF3CR);
948 681  
949   - if (ret) {
950   - debug("ERROR : The controller is busy\n");
951   - return ret;
952   - }
  682 + if (needs_amba_base_offset(q))
  683 + addr_offset = q->memmap_phy;
953 684  
954   - qspi_write32(priv->flags, &priv->regs->mcr,
955   - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
956   - QSPI_MCR_END_CFD_LE);
957   -
958   - qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
959   - QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
960   -
961 685 /*
962   - * Assign AMBA memory zone for every chipselect
963   - * QuadSPI has two channels, every channel has two chipselects.
964   - * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
965   - * into two parts and assign to every channel. This indicate that every
966   - * channel only has one valid chipselect.
967   - * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
968   - * into four parts and assign to every chipselect.
969   - * Every channel will has two valid chipselects.
  686 + * In HW there can be a maximum of four chips on two buses with
  687 + * two chip selects on each bus. We use four chip selects in SW
  688 + * to differentiate between the four chips.
  689 + * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  690 + * SFB2AD accordingly.
970 691 */
971   - amba_size_per_chip = priv->amba_total_size >>
972   - (priv->num_chipselect >> 1);
973   - for (i = 1 ; i < priv->num_chipselect ; i++)
974   - priv->amba_base[i] =
975   - amba_size_per_chip + priv->amba_base[i - 1];
  692 + qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
  693 + base + QUADSPI_SFA1AD);
  694 + qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
  695 + base + QUADSPI_SFA2AD);
  696 + qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
  697 + base + QUADSPI_SFB1AD);
  698 + qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
  699 + base + QUADSPI_SFB2AD);
976 700  
977   - /*
978   - * Any read access to non-implemented addresses will provide
979   - * undefined results.
980   - *
981   - * In case single die flash devices, TOP_ADDR_MEMA2 and
982   - * TOP_ADDR_MEMB2 should be initialized/programmed to
983   - * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
984   - * setting the size of these devices to 0. This would ensure
985   - * that the complete memory map is assigned to only one flash device.
986   - */
987   - qspi_write32(priv->flags, &priv->regs->sfa1ad,
988   - priv->amba_base[0] + amba_size_per_chip);
989   - switch (priv->num_chipselect) {
990   - case 1:
991   - break;
992   - case 2:
993   - qspi_write32(priv->flags, &priv->regs->sfa2ad,
994   - priv->amba_base[1]);
995   - qspi_write32(priv->flags, &priv->regs->sfb1ad,
996   - priv->amba_base[1] + amba_size_per_chip);
997   - qspi_write32(priv->flags, &priv->regs->sfb2ad,
998   - priv->amba_base[1] + amba_size_per_chip);
999   - break;
1000   - case 4:
1001   - qspi_write32(priv->flags, &priv->regs->sfa2ad,
1002   - priv->amba_base[2]);
1003   - qspi_write32(priv->flags, &priv->regs->sfb1ad,
1004   - priv->amba_base[3]);
1005   - qspi_write32(priv->flags, &priv->regs->sfb2ad,
1006   - priv->amba_base[3] + amba_size_per_chip);
1007   - break;
1008   - default:
1009   - debug("Error: Unsupported chipselect number %u!\n",
1010   - priv->num_chipselect);
1011   - qspi_module_disable(priv, 1);
1012   - return -EINVAL;
1013   - }
  701 + q->selected = -1;
1014 702  
1015   - qspi_set_lut(priv);
1016   -
1017   -#ifdef CONFIG_SYS_FSL_QSPI_AHB
1018   - qspi_init_ahb_read(priv);
1019   -#endif
1020   -
1021   - qspi_module_disable(priv, 0);
1022   -
  703 + /* Enable the module */
  704 + qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  705 + base + QUADSPI_MCR);
1023 706 return 0;
1024 707 }
1025 708  
1026   -static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
  709 +static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  710 + .adjust_op_size = fsl_qspi_adjust_op_size,
  711 + .supports_op = fsl_qspi_supports_op,
  712 + .exec_op = fsl_qspi_exec_op,
  713 +};
  714 +
  715 +static int fsl_qspi_probe(struct udevice *bus)
1027 716 {
1028   - struct fdt_resource res_regs, res_mem;
1029   - struct fsl_qspi_platdata *plat = bus->platdata;
  717 + struct dm_spi_bus *dm_bus = bus->uclass_priv;
  718 + struct fsl_qspi *q = dev_get_priv(bus);
1030 719 const void *blob = gd->fdt_blob;
1031 720 int node = dev_of_offset(bus);
1032   - int ret, flash_num = 0, subnode;
  721 + struct fdt_resource res;
  722 + int ret;
1033 723  
1034   - if (fdtdec_get_bool(blob, node, "big-endian"))
1035   - plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
  724 + q->dev = bus;
  725 + q->devtype_data = (struct fsl_qspi_devtype_data *)
  726 + dev_get_driver_data(bus);
1036 727  
1037   - ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1038   - "QuadSPI", &res_regs);
  728 + /* find the resources */
  729 + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  730 + &res);
1039 731 if (ret) {
1040   - debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
  732 + dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
1041 733 return -ENOMEM;
1042 734 }
  735 +
  736 + q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  737 +
1043 738 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1044   - "QuadSPI-memory", &res_mem);
  739 + "QuadSPI-memory", &res);
1045 740 if (ret) {
1046   - debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
  741 + dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
1047 742 return -ENOMEM;
1048 743 }
1049 744  
1050   - /* Count flash numbers */
1051   - fdt_for_each_subnode(subnode, blob, node)
1052   - ++flash_num;
  745 + q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  746 + q->memmap_phy = res.start;
1053 747  
1054   - if (flash_num == 0) {
1055   - debug("Error: Missing flashes!\n");
1056   - return -ENODEV;
1057   - }
  748 + dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  749 + 66000000);
1058 750  
1059   - plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1060   - FSL_QSPI_DEFAULT_SCK_FREQ);
1061   - plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1062   - FSL_QSPI_MAX_CHIPSELECT_NUM);
  751 + fsl_qspi_default_setup(q);
1063 752  
1064   - plat->reg_base = res_regs.start;
1065   - plat->amba_base = res_mem.start;
1066   - plat->amba_total_size = res_mem.end - res_mem.start + 1;
1067   - plat->flash_num = flash_num;
1068   -
1069   - debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1070   - __func__,
1071   - (u64)plat->reg_base,
1072   - (u64)plat->amba_base,
1073   - (u64)plat->amba_total_size,
1074   - plat->speed_hz,
1075   - plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1076   - );
1077   -
1078 753 return 0;
1079 754 }
1080 755  
1081 756 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1082   - const void *dout, void *din, unsigned long flags)
  757 + const void *dout, void *din, unsigned long flags)
1083 758 {
1084   - struct fsl_qspi_priv *priv;
1085   - struct udevice *bus;
1086   -
1087   - bus = dev->parent;
1088   - priv = dev_get_priv(bus);
1089   -
1090   - return qspi_xfer(priv, bitlen, dout, din, flags);
  759 + return 0;
1091 760 }
1092 761  
1093 762 static int fsl_qspi_claim_bus(struct udevice *dev)
1094 763 {
1095   - struct fsl_qspi_priv *priv;
1096   - struct udevice *bus;
1097   - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1098   - int ret;
1099   -
1100   - bus = dev->parent;
1101   - priv = dev_get_priv(bus);
1102   -
1103   - /* make sure controller is not busy anywhere */
1104   - ret = is_controller_busy(priv);
1105   -
1106   - if (ret) {
1107   - debug("ERROR : The controller is busy\n");
1108   - return ret;
1109   - }
1110   -
1111   - priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1112   -
1113   - qspi_module_disable(priv, 0);
1114   -
1115 764 return 0;
1116 765 }
1117 766  
1118 767 static int fsl_qspi_release_bus(struct udevice *dev)
1119 768 {
1120   - struct fsl_qspi_priv *priv;
1121   - struct udevice *bus;
1122   -
1123   - bus = dev->parent;
1124   - priv = dev_get_priv(bus);
1125   -
1126   - qspi_module_disable(priv, 1);
1127   -
1128 769 return 0;
1129 770 }
1130 771  
1131 772 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1132 773 {
1133   - /* Nothing to do */
1134 774 return 0;
1135 775 }
1136 776  
1137 777 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1138 778 {
1139   - /* Nothing to do */
1140 779 return 0;
1141 780 }
1142 781  
1143 782  
... ... @@ -1146,14 +785,17 @@
1146 785 .xfer = fsl_qspi_xfer,
1147 786 .set_speed = fsl_qspi_set_speed,
1148 787 .set_mode = fsl_qspi_set_mode,
  788 + .mem_ops = &fsl_qspi_mem_ops,
1149 789 };
1150 790  
1151 791 static const struct udevice_id fsl_qspi_ids[] = {
1152   - { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data },
1153   - { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
1154   - { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
1155   - { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
1156   - { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data },
  792 + { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  793 + { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  794 + { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  795 + { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  796 + { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  797 + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
  798 + { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
1157 799 { }
1158 800 };
1159 801  
1160 802  
... ... @@ -1162,10 +804,7 @@
1162 804 .id = UCLASS_SPI,
1163 805 .of_match = fsl_qspi_ids,
1164 806 .ops = &fsl_qspi_ops,
1165   - .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1166   - .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1167   - .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
  807 + .priv_auto_alloc_size = sizeof(struct fsl_qspi),
1168 808 .probe = fsl_qspi_probe,
1169   - .child_pre_probe = fsl_qspi_child_pre_probe,
1170 809 };
drivers/spi/fsl_qspi.h
View file @ 8e904df
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -/*
3   - * Copyright 2013-2014 Freescale Semiconductor, Inc.
4   - *
5   - * Register definitions for Freescale QSPI
6   - */
7   -
8   -#ifndef _FSL_QSPI_H_
9   -#define _FSL_QSPI_H_
10   -
11   -struct fsl_qspi_regs {
12   - u32 mcr;
13   - u32 rsvd0[1];
14   - u32 ipcr;
15   - u32 flshcr;
16   - u32 buf0cr;
17   - u32 buf1cr;
18   - u32 buf2cr;
19   - u32 buf3cr;
20   - u32 bfgencr;
21   - u32 soccr;
22   - u32 rsvd1[2];
23   - u32 buf0ind;
24   - u32 buf1ind;
25   - u32 buf2ind;
26   - u32 rsvd2[49];
27   - u32 sfar;
28   - u32 rsvd3[1];
29   - u32 smpr;
30   - u32 rbsr;
31   - u32 rbct;
32   - u32 rsvd4[15];
33   - u32 tbsr;
34   - u32 tbdr;
35   - u32 rsvd5[1];
36   - u32 sr;
37   - u32 fr;
38   - u32 rser;
39   - u32 spndst;
40   - u32 sptrclr;
41   - u32 rsvd6[4];
42   - u32 sfa1ad;
43   - u32 sfa2ad;
44   - u32 sfb1ad;
45   - u32 sfb2ad;
46   - u32 rsvd7[28];
47   - u32 rbdr[32];
48   - u32 rsvd8[32];
49   - u32 lutkey;
50   - u32 lckcr;
51   - u32 rsvd9[2];
52   - u32 lut[64];
53   -};
54   -
55   -#define QSPI_IPCR_SEQID_SHIFT 24
56   -#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
57   -
58   -#define QSPI_MCR_END_CFD_SHIFT 2
59   -#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
60   -#ifdef CONFIG_SYS_FSL_QSPI_AHB
61   -/* AHB needs 64bit operation */
62   -#define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT)
63   -#else
64   -#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
65   -#endif
66   -#define QSPI_MCR_DDR_EN_SHIFT 7
67   -#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
68   -#define QSPI_MCR_CLR_RXF_SHIFT 10
69   -#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
70   -#define QSPI_MCR_CLR_TXF_SHIFT 11
71   -#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
72   -#define QSPI_MCR_MDIS_SHIFT 14
73   -#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
74   -#define QSPI_MCR_RESERVED_SHIFT 16
75   -#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
76   -#define QSPI_MCR_SWRSTHD_SHIFT 1
77   -#define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT)
78   -#define QSPI_MCR_SWRSTSD_SHIFT 0
79   -#define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT)
80   -
81   -#define QSPI_SMPR_HSENA_SHIFT 0
82   -#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
83   -#define QSPI_SMPR_FSPHS_SHIFT 5
84   -#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
85   -#define QSPI_SMPR_FSDLY_SHIFT 6
86   -#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
87   -#define QSPI_SMPR_DDRSMP_SHIFT 16
88   -#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
89   -
90   -#define QSPI_BUFXCR_INVALID_MSTRID 0xe
91   -#define QSPI_BUF3CR_ALLMST_SHIFT 31
92   -#define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT)
93   -#define QSPI_BUF3CR_ADATSZ_SHIFT 8
94   -#define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
95   -
96   -#define QSPI_BFGENCR_SEQID_SHIFT 12
97   -#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
98   -#define QSPI_BFGENCR_PAR_EN_SHIFT 16
99   -#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
100   -
101   -#define QSPI_RBSR_RDBFL_SHIFT 8
102   -#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
103   -
104   -#define QSPI_RBCT_RXBRD_SHIFT 8
105   -#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
106   -
107   -#define QSPI_SR_AHB_ACC_SHIFT 2
108   -#define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT)
109   -#define QSPI_SR_IP_ACC_SHIFT 1
110   -#define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT)
111   -#define QSPI_SR_BUSY_SHIFT 0
112   -#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
113   -
114   -#define QSPI_LCKCR_LOCK 0x1
115   -#define QSPI_LCKCR_UNLOCK 0x2
116   -
117   -#define LUT_KEY_VALUE 0x5af05af0
118   -
119   -#define OPRND0_SHIFT 0
120   -#define OPRND0(x) ((x) << OPRND0_SHIFT)
121   -#define PAD0_SHIFT 8
122   -#define PAD0(x) ((x) << PAD0_SHIFT)
123   -#define INSTR0_SHIFT 10
124   -#define INSTR0(x) ((x) << INSTR0_SHIFT)
125   -#define OPRND1_SHIFT 16
126   -#define OPRND1(x) ((x) << OPRND1_SHIFT)
127   -#define PAD1_SHIFT 24
128   -#define PAD1(x) ((x) << PAD1_SHIFT)
129   -#define INSTR1_SHIFT 26
130   -#define INSTR1(x) ((x) << INSTR1_SHIFT)
131   -
132   -#define LUT_CMD 1
133   -#define LUT_ADDR 2
134   -#define LUT_DUMMY 3
135   -#define LUT_READ 7
136   -#define LUT_WRITE 8
137   -
138   -#define LUT_PAD1 0
139   -#define LUT_PAD2 1
140   -#define LUT_PAD4 2
141   -
142   -#define ADDR24BIT 0x18
143   -#define ADDR32BIT 0x20
144   -
145   -#endif /* _FSL_QSPI_H_ */