Eric Lee / smarc-uboot

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Commit 8ef07571a0300e6ae84931c63d5eb3b2310c8aba

Authored by Simon Glass
1 parent c03c951b06
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: Add chromebook_link board 

This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 18 changed files with 438 additions and 0 deletions Side-by-side Diff

... ... @@ -12,10 +12,33 @@
12 12  
13 13 config TARGET_COREBOOT
14 14 bool "Support coreboot"
  15 + help
  16 + This target is used for running U-Boot on top of Coreboot. In
  17 + this case Coreboot does the early inititalisation, and U-Boot
  18 + takes over once the RAM, video and CPU are fully running.
  19 + U-Boot is loaded as a fallback payload from Coreboot, in
  20 + Coreboot terminology. This method was used for the Chromebook
  21 + Pixel when launched.
15 22  
  23 +config TARGET_CHROMEBOOK_LINK
  24 + bool "Support Chromebook link"
  25 + help
  26 + This is the Chromebook Pixel released in 2013. It uses an Intel
  27 + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
  28 + SDRAM. It has a Panther Point platform controller hub, PCIe
  29 + WiFi and Bluetooth. It also includes a 720p webcam, USB SD
  30 + reader, microphone and speakers, display port and 32GB SATA
  31 + solid state drive. There is a Chrome OS EC connected on LPC,
  32 + and it provides a 2560x1700 high resolution touch-enabled LCD
  33 + display.
  34 +
16 35 endchoice
17 36  
  37 +source "arch/x86/cpu/ivybridge/Kconfig"
  38 +
18 39 source "board/chromebook-x86/coreboot/Kconfig"
  40 +
  41 +source "board/google/chromebook_link/Kconfig"
19 42  
20 43 endmenu
arch/x86/cpu/coreboot/coreboot.c
Diff comments   View file @ 8ef0757
... ... @@ -13,6 +13,7 @@
13 13 #include <ns16550.h>
14 14 #include <asm/msr.h>
15 15 #include <asm/cache.h>
  16 +#include <asm/cpu.h>
16 17 #include <asm/io.h>
17 18 #include <asm/arch-coreboot/tables.h>
18 19 #include <asm/arch-coreboot/sysinfo.h>
arch/x86/cpu/ivybridge/Kconfig
Diff comments   View file @ 8ef0757
  1 +#
  2 +# From Coreboot src/northbridge/intel/sandybridge/Kconfig
  3 +#
  4 +# Copyright (C) 2010 Google Inc.
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0
  7 +
  8 +
  9 +config NORTHBRIDGE_INTEL_SANDYBRIDGE
  10 + bool
  11 + select CACHE_MRC_BIN
  12 + select CPU_INTEL_MODEL_206AX
  13 +
  14 +config NORTHBRIDGE_INTEL_IVYBRIDGE
  15 + bool
  16 + select CACHE_MRC_BIN
  17 + select CPU_INTEL_MODEL_306AX
  18 +
  19 +if NORTHBRIDGE_INTEL_SANDYBRIDGE
  20 +
  21 +config VGA_BIOS_ID
  22 + string
  23 + default "8086,0106"
  24 +
  25 +config CACHE_MRC_SIZE_KB
  26 + int
  27 + default 256
  28 +
  29 +config MRC_CACHE_BASE
  30 + hex
  31 + default 0xff800000
  32 +
  33 +config MRC_CACHE_LOCATION
  34 + hex
  35 + depends on !CHROMEOS
  36 + default 0x1ec000
  37 +
  38 +config MRC_CACHE_SIZE
  39 + hex
  40 + depends on !CHROMEOS
  41 + default 0x10000
  42 +
  43 +config DCACHE_RAM_BASE
  44 + hex
  45 + default 0xff7f0000
  46 +
  47 +config DCACHE_RAM_SIZE
  48 + hex
  49 + default 0x10000
  50 +
  51 +endif
  52 +
  53 +if NORTHBRIDGE_INTEL_IVYBRIDGE
  54 +
  55 +config VGA_BIOS_ID
  56 + string
  57 + default "8086,0166"
  58 +
  59 +config EXTERNAL_MRC_BLOB
  60 + bool
  61 + default n
  62 +
  63 +config CACHE_MRC_SIZE_KB
  64 + int
  65 + default 512
  66 +
  67 +config MRC_CACHE_BASE
  68 + hex
  69 + default 0xff800000
  70 +
  71 +config MRC_CACHE_LOCATION
  72 + hex
  73 + depends on !CHROMEOS
  74 + default 0x370000
  75 +
  76 +config MRC_CACHE_SIZE
  77 + hex
  78 + depends on !CHROMEOS
  79 + default 0x10000
  80 +
  81 +config DCACHE_RAM_BASE
  82 + hex
  83 + default 0xff7e0000
  84 +
  85 +config DCACHE_RAM_SIZE
  86 + hex
  87 + default 0x20000
  88 +
  89 +endif
  90 +
  91 +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
  92 +
  93 +config HAVE_MRC
  94 + bool "Add a System Agent binary"
  95 + help
  96 + Select this option to add a System Agent binary to
  97 + the resulting U-Boot image. MRC stands for Memory Reference Code.
  98 + It is a binary blob which U-Boot uses to set up SDRAM.
  99 +
  100 + Note: Without this binary U-Boot will not be able to set up its
  101 + SDRAM so will not boot.
  102 +
  103 +config DCACHE_RAM_MRC_VAR_SIZE
  104 + hex
  105 + default 0x4000
  106 + help
  107 + This is the amount of CAR (Cache as RAM) reserved for use by the
  108 + memory reference code. This should be set to 16KB (0x4000 hex)
  109 + so that MRC has enough space to run.
  110 +
  111 +config MRC_FILE
  112 + string "Intel System Agent path and filename"
  113 + depends on HAVE_MRC
  114 + default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
  115 + default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
  116 + help
  117 + The path and filename of the file to use as System Agent
  118 + binary.
  119 +
  120 +config CPU_SPECIFIC_OPTIONS
  121 + def_bool y
  122 + select SMM_TSEG
  123 + select ARCH_BOOTBLOCK_X86_32
  124 + select ARCH_ROMSTAGE_X86_32
  125 + select ARCH_RAMSTAGE_X86_32
  126 + select SMP
  127 + select SSE2
  128 + select UDELAY_LAPIC
  129 + select CPU_MICROCODE_IN_CBFS
  130 + select TSC_SYNC_MFENCE
  131 + select HAVE_INTEL_ME
  132 +
  133 +config SMM_TSEG_SIZE
  134 + hex
  135 + default 0x800000
  136 +
  137 +config ENABLE_VMX
  138 + bool "Enable VMX for virtualization"
  139 + default n
  140 + help
  141 + Virtual Machine Extensions are provided in many x86 CPUs. These
  142 + provide various facilities for allowing a host OS to provide an
  143 + environment where potentially several guest OSes have only
  144 + limited access to the underlying hardware. This is achieved
  145 + without resorting to software trapping and/or instruction set
  146 + emulation (which would be very slow).
  147 +
  148 + Intel's implementation of this is called VT-x. This option enables
  149 + VT-x this so that the OS that is booted by U-Boot can make use of
  150 + these facilities. If this option is not enabled, then the host OS
  151 + will be unable to support virtualisation, or it will run very
  152 + slowly.
  153 +
  154 +endif
  155 +
  156 +config CPU_INTEL_SOCKET_RPGA989
  157 + bool
  158 +
  159 +if CPU_INTEL_SOCKET_RPGA989
  160 +
  161 +config SOCKET_SPECIFIC_OPTIONS # dummy
  162 + def_bool y
  163 + select MMX
  164 + select SSE
  165 + select CACHE_AS_RAM
  166 +
  167 +config CACHE_MRC_BIN
  168 + bool
  169 + default n
  170 +
  171 +endif
arch/x86/cpu/ivybridge/Makefile
Diff comments   View file @ 8ef0757
  1 +#
  2 +# Copyright (c) 2014 Google, Inc
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += car.o
  8 +obj-y += cpu.o
  9 +obj-y += sdram.o
arch/x86/cpu/ivybridge/car.S
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2014 Google, Inc
  3 + *
  4 + * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
  5 + *
  6 + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
  7 + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
  8 + * Copyright (C) 2007-2008 coresystems GmbH
  9 + * Copyright (C) 2012 Kyรถsti Mรคlkki <kyosti.malkki@gmail.com>
  10 + *
  11 + * SPDX-License-Identifier: GPL-2.0
  12 + */
  13 +
  14 +#include <common.h>
  15 +
  16 + /* Note: ebp must not be touched in this code */
  17 +.globl car_init
  18 +car_init:
  19 + /* TODO: Add cache-as-RAM init here */
  20 + jmp car_init_ret
arch/x86/cpu/ivybridge/cpu.c
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2014 Google, Inc
  3 + * (C) Copyright 2008
  4 + * Graeme Russ, graeme.russ@gmail.com.
  5 + *
  6 + * Some portions from coreboot src/mainboard/google/link/romstage.c
  7 + * Copyright (C) 2007-2010 coresystems GmbH
  8 + * Copyright (C) 2011 Google Inc.
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <asm/cpu.h>
  15 +#include <asm/processor.h>
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +int arch_cpu_init(void)
  20 +{
  21 + int ret;
  22 +
  23 + timer_set_base(rdtsc());
  24 +
  25 + ret = x86_cpu_init_f();
  26 + if (ret)
  27 + return ret;
  28 +
  29 + return 0;
  30 +}
  31 +
  32 +int print_cpuinfo(void)
  33 +{
  34 + char processor_name[CPU_MAX_NAME_LEN];
  35 + const char *name;
  36 +
  37 + /* Print processor name */
  38 + name = cpu_get_name(processor_name);
  39 + printf("CPU: %s\n", name);
  40 +
  41 + return 0;
  42 +}
arch/x86/cpu/ivybridge/sdram.c
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2011 The Chromium OS Authors.
  3 + * (C) Copyright 2010,2011
  4 + * Graeme Russ, <graeme.russ@gmail.com>
  5 + *
  6 + * Portions from Coreboot mainboard/google/link/romstage.c
  7 + * Copyright (C) 2007-2010 coresystems GmbH
  8 + * Copyright (C) 2011 Google Inc.
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0
  11 + */
  12 +
  13 +#include <common.h>
  14 +
  15 +int dram_init(void)
  16 +{
  17 + /* TODO: Set up DRAM */
  18 +
  19 + return 0;
  20 +}
arch/x86/dts/Makefile
Diff comments   View file @ 8ef0757
1 1 dtb-y += link.dtb \
  2 + chromebook_link.dtb \
2 3 alex.dtb
3 4  
4 5 targets += $(dtb-y)
arch/x86/dts/chromebook_link.dts
Diff comments   View file @ 8ef0757
  1 +link.dts
arch/x86/include/asm/arch-ivybridge/gpio.h
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2014, Google Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _X86_ARCH_GPIO_H_
  8 +#define _X86_ARCH_GPIO_H_
  9 +
  10 +#endif /* _X86_ARCH_GPIO_H_ */
board/google/chromebook_link/Kconfig
Diff comments   View file @ 8ef0757
  1 +if TARGET_CHROMEBOOK_LINK
  2 +
  3 +config SYS_BOARD
  4 + default "chromebook_link"
  5 +
  6 +config SYS_VENDOR
  7 + default "google"
  8 +
  9 +config SYS_SOC
  10 + default "ivybridge"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "chromebook_link"
  14 +
  15 +endif
board/google/chromebook_link/MAINTAINERS
Diff comments   View file @ 8ef0757
  1 +CHROMEBOOK LINK BOARD
  2 +M: Simon Glass <sjg@chromium.org>
  3 +S: Maintained
  4 +F: board/google/chromebook_link/
  5 +F: include/configs/chromebook_link.h
  6 +F: configs/chromebook_link_defconfig
board/google/chromebook_link/Makefile
Diff comments   View file @ 8ef0757
  1 +#
  2 +# Copyright (c) 2011 The Chromium OS Authors.
  3 +# (C) Copyright 2008
  4 +# Graeme Russ, graeme.russ@gmail.com.
  5 +#
  6 +# (C) Copyright 2006
  7 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8 +#
  9 +# (C) Copyright 2002
  10 +# Daniel Engstrรถm, Omicron Ceti AB, daniel@omicron.se.
  11 +#
  12 +# SPDX-License-Identifier: GPL-2.0+
  13 +#
  14 +
  15 +obj-y += link.o
board/google/chromebook_link/link.c
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (C) 2014 Google, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +
  9 +int arch_early_init_r(void)
  10 +{
  11 + return 0;
  12 +}
  13 +
  14 +int board_early_init_r(void)
  15 +{
  16 + return 0;
  17 +}
board/google/common/Makefile
Diff comments   View file @ 8ef0757
  1 +#
  2 +# Copyright (c) 2014 Google, Inc
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += early_init.o
board/google/common/early_init.S
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2014 Google, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +.globl early_board_init
  8 +early_board_init:
  9 + /* No 32-bit board specific initialisation */
  10 + jmp early_board_init_ret
configs/chromebook_link_defconfig
Diff comments   View file @ 8ef0757
  1 +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
  2 +CONFIG_X86=y
  3 +CONFIG_TARGET_CHROMEBOOK_LINK=y
  4 +CONFIG_OF_CONTROL=y
  5 +CONFIG_OF_SEPARATE=y
  6 +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
  7 +CONFIG_HAVE_MRC=y
  8 +CONFIG_SMM_TSEG_SIZE=0x800000
  9 +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
  10 +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
include/configs/chromebook_link.h
Diff comments   View file @ 8ef0757
  1 +/*
  2 + * Copyright (c) 2011 The Chromium OS Authors.
  3 + * (C) Copyright 2008
  4 + * Graeme Russ, graeme.russ@gmail.com.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/*
  10 + * board/config.h - configuration options, board specific
  11 + */
  12 +
  13 +#ifndef __CONFIG_H
  14 +#define __CONFIG_H
  15 +
  16 +#include <configs/x86-common.h>
  17 +
  18 +#define CONFIG_SYS_CAR_ADDR 0xff7e0000
  19 +#define CONFIG_SYS_CAR_SIZE (128 * 1024)
  20 +#define CONFIG_SYS_MONITOR_LEN (1 << 20)
  21 +#define CONFIG_BOARD_EARLY_INIT_R
  22 +
  23 +#define CONFIG_NR_DRAM_BANKS 8
  24 +
  25 +#define CONFIG_COREBOOT_SERIAL
  26 +
  27 +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
  28 + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
  29 + {PCI_VENDOR_ID_INTEL, \
  30 + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
  31 + {PCI_VENDOR_ID_INTEL, \
  32 + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
  33 + {PCI_VENDOR_ID_INTEL, \
  34 + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  35 +
  36 +/*
  37 + * These common x86 features are not yet supported, but are added in
  38 + * follow-on patches in this series. Add undefs here to avoid every patch
  39 + * having to put things back into x86-common.h
  40 + */
  41 +#undef CONFIG_INTEL_ICH6_GPIO
  42 +#undef CONFIG_DM_GPIO
  43 +#undef CONFIG_CMD_GPIO
  44 +#undef CONFIG_VIDEO
  45 +#undef CONFIG_CFB_CONSOLE
  46 +#undef CONFIG_SYS_EARLY_PCI_INIT
  47 +#undef CONFIG_PCI
  48 +#undef CONFIG_ICH_SPI
  49 +#undef CONFIG_SPI
  50 +#undef CONFIG_CMD_SPI
  51 +#undef CONFIG_CMD_SF
  52 +#undef CONFIG_USB_EHCI
  53 +#undef CONFIG_CMD_USB
  54 +#undef CONFIG_CMD_SCSI
  55 +
  56 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
  57 + "stdout=vga,serial\0" \
  58 + "stderr=vga,serial\0"
  59 +
  60 +#endif /* __CONFIG_H */