Eric Lee / smarc-uboot

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Commit 8f5a1be80b978df72bd739123b0f7667b49599b2

Authored by BJ DevOps Team
2 parents 7353572ff5 254a7e3ff9
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04 

* origin/ls_v2020.04:
  armv8: ls1028a: fix stream id allocation
  configs: ls1088aqds: add COMMON_ENV to fix distroboot
  board: fsl: ls2088ardb: Program GIC LPI configuration table

Showing 3 changed files Inline Diff

arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
Diff comments   View file @ 8f5a1be
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2015-2020 NXP 3 * Copyright 2015-2021 NXP
4 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2014 Freescale Semiconductor, Inc.
5 * 5 *
6 */ 6 */
7 #ifndef __FSL_STREAM_ID_H 7 #ifndef __FSL_STREAM_ID_H
8 #define __FSL_STREAM_ID_H 8 #define __FSL_STREAM_ID_H
9 9
10 /* 10 /*
11 * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) 11 * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
12 * devices are not hardwired and are programmed by sw. There are a limited 12 * devices are not hardwired and are programmed by sw. There are a limited
13 * number of stream IDs available, and the partitioning of them is scenario 13 * number of stream IDs available, and the partitioning of them is scenario
14 * dependent. This header defines the partitioning between legacy, 14 * dependent. This header defines the partitioning between legacy,
15 * PCI, and DPAA2 devices. 15 * PCI, and DPAA2 devices.
16 * 16 *
17 * This partitioning can be customized in this file depending 17 * This partitioning can be customized in this file depending
18 * on the specific hardware config: 18 * on the specific hardware config:
19 * 19 *
20 * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) 20 * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
21 * -all legacy devices get a unique stream ID assigned and programmed in 21 * -all legacy devices get a unique stream ID assigned and programmed in
22 * their AMQR registers by u-boot 22 * their AMQR registers by u-boot
23 * 23 *
24 * -PCIe 24 * -PCIe
25 * -there is a range of stream IDs set aside for PCI in this 25 * -there is a range of stream IDs set aside for PCI in this
26 * file. U-boot will scan the PCI bus and for each device discovered: 26 * file. U-boot will scan the PCI bus and for each device discovered:
27 * -allocate a streamID 27 * -allocate a streamID
28 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' 28 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
29 * -set a msi-map entry in the PEXn controller node in the 29 * -set a msi-map entry in the PEXn controller node in the
30 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt 30 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
31 * for more info on the msi-map definition) 31 * for more info on the msi-map definition)
32 * -set a iommu-map entry in the PEXn controller node in the 32 * -set a iommu-map entry in the PEXn controller node in the
33 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt 33 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
34 * for more info on the iommu-map definition) 34 * for more info on the iommu-map definition)
35 * 35 *
36 * -DPAA2 36 * -DPAA2
37 * -u-boot will allocate a range of stream IDs to be used by the Management 37 * -u-boot will allocate a range of stream IDs to be used by the Management
38 * Complex for containers and will set these values in the MC DPC image. 38 * Complex for containers and will set these values in the MC DPC image.
39 * -u-boot will fixup the iommu-map property in the fsl-mc node in the 39 * -u-boot will fixup the iommu-map property in the fsl-mc node in the
40 * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt 40 * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
41 * for more info on the msi-map definition) 41 * for more info on the msi-map definition)
42 * -the MC is responsible for allocating and setting up 'isolation context 42 * -the MC is responsible for allocating and setting up 'isolation context
43 * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. 43 * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
44 * 44 *
45 * - ECAM (integrated PCI) 45 * - ECAM (integrated PCI)
46 * - U-Boot applies the value here to HW and does DT fix-up for both 46 * - U-Boot applies the value here to HW and does DT fix-up for both
47 * 'iommu-map' and 'msi-map' 47 * 'iommu-map' and 'msi-map'
48 * 48 *
49 * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for 49 * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
50 * each of the different bus masters. The relationship between 50 * each of the different bus masters. The relationship between
51 * the AMQ registers and stream IDs is defined in the table below: 51 * the AMQ registers and stream IDs is defined in the table below:
52 * AMQ bit streamID bit 52 * AMQ bit streamID bit
53 * --------------------------- 53 * ---------------------------
54 * PL[18] 9 // privilege bit 54 * PL[18] 9 // privilege bit
55 * BMT[17] 8 // bypass translation 55 * BMT[17] 8 // bypass translation
56 * VA[16] 7 // reserved 56 * VA[16] 7 // reserved
57 * [15] - // unused 57 * [15] - // unused
58 * ICID[14:7] - // unused 58 * ICID[14:7] - // unused
59 * ICID[6:0] 6-0 // isolation context id 59 * ICID[6:0] 6-0 // isolation context id
60 * ---------------------------- 60 * ----------------------------
61 * 61 *
62 */ 62 */
63 63
64 #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ 64 #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
65 #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ 65 #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
66 66
67 #define FSL_INVALID_STREAM_ID 0 67 #define FSL_INVALID_STREAM_ID 0
68 68
69 #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) 69 #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
70 70
71 /* legacy devices */ 71 /* legacy devices */
72 #define FSL_USB1_STREAM_ID 1 72 #define FSL_USB1_STREAM_ID 1
73 #define FSL_USB2_STREAM_ID 2 73 #define FSL_USB2_STREAM_ID 2
74 #define FSL_SDMMC_STREAM_ID 3 74 #define FSL_SDMMC_STREAM_ID 3
75 #define FSL_SATA1_STREAM_ID 4 75 #define FSL_SATA1_STREAM_ID 4
76 76
77 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ 77 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
78 defined(CONFIG_ARCH_LX2162A) 78 defined(CONFIG_ARCH_LX2162A)
79 #define FSL_SATA2_STREAM_ID 5 79 #define FSL_SATA2_STREAM_ID 5
80 #endif 80 #endif
81 81
82 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ 82 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
83 defined(CONFIG_ARCH_LX2162A) 83 defined(CONFIG_ARCH_LX2162A)
84 #define FSL_DMA_STREAM_ID 6 84 #define FSL_DMA_STREAM_ID 6
85 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) 85 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
86 #define FSL_DMA_STREAM_ID 5 86 #define FSL_DMA_STREAM_ID 5
87 #endif 87 #endif
88 88
89 /* PCI - programmed in PEXn_LUT */ 89 /* PCI - programmed in PEXn_LUT */
90 #define FSL_PEX_STREAM_ID_START 7 90 #define FSL_PEX_STREAM_ID_START 7
91 91
92 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) 92 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
93 #define FSL_PEX_STREAM_ID_END 22 93 #define FSL_PEX_STREAM_ID_END 22
94 #elif defined(CONFIG_ARCH_LS1088A) 94 #elif defined(CONFIG_ARCH_LS1088A)
95 #define FSL_PEX_STREAM_ID_END 18 95 #define FSL_PEX_STREAM_ID_END 18
96 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 96 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
97 #define FSL_PEX_STREAM_ID_END (0x100) 97 #define FSL_PEX_STREAM_ID_END (0x100)
98 #endif 98 #endif
99 99
100 100
101 /* DPAA2 - set in MC DPC and alloced by MC */ 101 /* DPAA2 - set in MC DPC and alloced by MC */
102 #define FSL_DPAA2_STREAM_ID_START 23 102 #define FSL_DPAA2_STREAM_ID_START 23
103 #define FSL_DPAA2_STREAM_ID_END 63 103 #define FSL_DPAA2_STREAM_ID_END 63
104 104
105 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ 105 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */
106 #define FSL_ECAM_STREAM_ID_START 32 106 #define FSL_ECAM_STREAM_ID_START 41
107 #define FSL_ECAM_STREAM_ID_END 63 107 #define FSL_ECAM_STREAM_ID_END 63
108 108
109 #define FSL_SEC_STREAM_ID 64 109 #define FSL_SEC_STREAM_ID 64
110 #define FSL_SEC_JR1_STREAM_ID 65 110 #define FSL_SEC_JR1_STREAM_ID 65
111 #define FSL_SEC_JR2_STREAM_ID 66 111 #define FSL_SEC_JR2_STREAM_ID 66
112 #define FSL_SEC_JR3_STREAM_ID 67 112 #define FSL_SEC_JR3_STREAM_ID 67
113 #define FSL_SEC_JR4_STREAM_ID 68 113 #define FSL_SEC_JR4_STREAM_ID 68
114 114
115 #define FSL_SDMMC2_STREAM_ID 69 115 #define FSL_SDMMC2_STREAM_ID 69
116 116
117 /* 117 /*
118 * Erratum A-050382 workaround 118 * Erratum A-050382 workaround
119 * 119 *
120 * Description: 120 * Description:
121 * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not 121 * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
122 * correctly forwarded to the SMMU. 122 * correctly forwarded to the SMMU.
123 * Workaround: 123 * Workaround:
124 * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. 124 * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
125 */ 125 */
126 #ifdef CONFIG_SYS_FSL_ERRATUM_A050382 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A050382
127 #define FSL_EDMA_STREAM_ID 40 127 #define FSL_EDMA_STREAM_ID 40
128 #else 128 #else
129 #define FSL_EDMA_STREAM_ID 70 129 #define FSL_EDMA_STREAM_ID 70
130 #endif 130 #endif
131 131
132 #define FSL_GPU_STREAM_ID 71 132 #define FSL_GPU_STREAM_ID 71
133 #define FSL_DISPLAY_STREAM_ID 72 133 #define FSL_DISPLAY_STREAM_ID 72
134 #define FSL_SATA3_STREAM_ID 73 134 #define FSL_SATA3_STREAM_ID 73
135 #define FSL_SATA4_STREAM_ID 74 135 #define FSL_SATA4_STREAM_ID 74
136 136
137 #endif 137 #endif
138 138
board/freescale/ls2080ardb/ls2080ardb.c
Diff comments   View file @ 8f5a1be
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2015 Freescale Semiconductor 3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2017 NXP 4 * Copyright 2017-2020 NXP
5 */ 5 */
6 #include <common.h> 6 #include <common.h>
7 #include <env.h> 7 #include <env.h>
8 #include <malloc.h> 8 #include <malloc.h>
9 #include <errno.h> 9 #include <errno.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <fsl_ifc.h> 11 #include <fsl_ifc.h>
12 #include <fsl_ddr.h> 12 #include <fsl_ddr.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <hwconfig.h> 14 #include <hwconfig.h>
15 #include <fdt_support.h> 15 #include <fdt_support.h>
16 #include <linux/libfdt.h> 16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h> 17 #include <fsl-mc/fsl_mc.h>
18 #include <env_internal.h> 18 #include <env_internal.h>
19 #include <efi_loader.h> 19 #include <efi_loader.h>
20 #include <i2c.h> 20 #include <i2c.h>
21 #include <asm/arch/mmu.h> 21 #include <asm/arch/mmu.h>
22 #include <asm/arch/soc.h> 22 #include <asm/arch/soc.h>
23 #include <asm/arch/ppa.h> 23 #include <asm/arch/ppa.h>
24 #include <fsl_sec.h> 24 #include <fsl_sec.h>
25 #include <asm/arch-fsl-layerscape/fsl_icid.h> 25 #include <asm/arch-fsl-layerscape/fsl_icid.h>
26 #include <asm/gic-v3.h>
27 #include <cpu_func.h>
26 28
29 #define GIC_LPI_SIZE 0x200000
27 #ifdef CONFIG_FSL_QIXIS 30 #ifdef CONFIG_FSL_QIXIS
28 #include "../common/qixis.h" 31 #include "../common/qixis.h"
29 #include "ls2080ardb_qixis.h" 32 #include "ls2080ardb_qixis.h"
30 #endif 33 #endif
31 #include "../common/vid.h" 34 #include "../common/vid.h"
32 35
33 #define PIN_MUX_SEL_SDHC 0x00 36 #define PIN_MUX_SEL_SDHC 0x00
34 #define PIN_MUX_SEL_DSPI 0x0a 37 #define PIN_MUX_SEL_DSPI 0x0a
35 38
36 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 39 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
37 DECLARE_GLOBAL_DATA_PTR; 40 DECLARE_GLOBAL_DATA_PTR;
38 41
39 enum { 42 enum {
40 MUX_TYPE_SDHC, 43 MUX_TYPE_SDHC,
41 MUX_TYPE_DSPI, 44 MUX_TYPE_DSPI,
42 }; 45 };
43 46
44 unsigned long long get_qixis_addr(void) 47 unsigned long long get_qixis_addr(void)
45 { 48 {
46 unsigned long long addr; 49 unsigned long long addr;
47 50
48 if (gd->flags & GD_FLG_RELOC) 51 if (gd->flags & GD_FLG_RELOC)
49 addr = QIXIS_BASE_PHYS; 52 addr = QIXIS_BASE_PHYS;
50 else 53 else
51 addr = QIXIS_BASE_PHYS_EARLY; 54 addr = QIXIS_BASE_PHYS_EARLY;
52 55
53 /* 56 /*
54 * IFC address under 256MB is mapped to 0x30000000, any address above 57 * IFC address under 256MB is mapped to 0x30000000, any address above
55 * is mapped to 0x5_10000000 up to 4GB. 58 * is mapped to 0x5_10000000 up to 4GB.
56 */ 59 */
57 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 60 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
58 61
59 return addr; 62 return addr;
60 } 63 }
61 64
62 int checkboard(void) 65 int checkboard(void)
63 { 66 {
64 #ifdef CONFIG_FSL_QIXIS 67 #ifdef CONFIG_FSL_QIXIS
65 u8 sw; 68 u8 sw;
66 #endif 69 #endif
67 char buf[15]; 70 char buf[15];
68 71
69 cpu_name(buf); 72 cpu_name(buf);
70 printf("Board: %s-RDB, ", buf); 73 printf("Board: %s-RDB, ", buf);
71 74
72 #ifdef CONFIG_TARGET_LS2081ARDB 75 #ifdef CONFIG_TARGET_LS2081ARDB
73 #ifdef CONFIG_FSL_QIXIS 76 #ifdef CONFIG_FSL_QIXIS
74 sw = QIXIS_READ(arch); 77 sw = QIXIS_READ(arch);
75 printf("Board version: %c, ", (sw & 0xf) + 'A'); 78 printf("Board version: %c, ", (sw & 0xf) + 'A');
76 79
77 sw = QIXIS_READ(brdcfg[0]); 80 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK; 81 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
79 switch (sw) { 82 switch (sw) {
80 case 0: 83 case 0:
81 puts("boot from QSPI DEV#0\n"); 84 puts("boot from QSPI DEV#0\n");
82 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); 85 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
83 break; 86 break;
84 case 1: 87 case 1:
85 puts("boot from QSPI DEV#1\n"); 88 puts("boot from QSPI DEV#1\n");
86 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); 89 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
87 break; 90 break;
88 case 2: 91 case 2:
89 puts("boot from QSPI EMU\n"); 92 puts("boot from QSPI EMU\n");
90 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); 93 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
91 break; 94 break;
92 case 3: 95 case 3:
93 puts("boot from QSPI EMU\n"); 96 puts("boot from QSPI EMU\n");
94 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); 97 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
95 break; 98 break;
96 case 4: 99 case 4:
97 puts("boot from QSPI DEV#0\n"); 100 puts("boot from QSPI DEV#0\n");
98 puts("QSPI_CSA_1 mapped to QSPI EMU\n"); 101 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
99 break; 102 break;
100 default: 103 default:
101 printf("invalid setting of SW%u\n", sw); 104 printf("invalid setting of SW%u\n", sw);
102 break; 105 break;
103 } 106 }
104 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 107 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
105 #endif 108 #endif
106 puts("SERDES1 Reference : "); 109 puts("SERDES1 Reference : ");
107 printf("Clock1 = 100MHz "); 110 printf("Clock1 = 100MHz ");
108 printf("Clock2 = 161.13MHz"); 111 printf("Clock2 = 161.13MHz");
109 #else 112 #else
110 #ifdef CONFIG_FSL_QIXIS 113 #ifdef CONFIG_FSL_QIXIS
111 sw = QIXIS_READ(arch); 114 sw = QIXIS_READ(arch);
112 printf("Board Arch: V%d, ", sw >> 4); 115 printf("Board Arch: V%d, ", sw >> 4);
113 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 116 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
114 117
115 sw = QIXIS_READ(brdcfg[0]); 118 sw = QIXIS_READ(brdcfg[0]);
116 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 119 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
117 120
118 if (sw < 0x8) 121 if (sw < 0x8)
119 printf("vBank: %d\n", sw); 122 printf("vBank: %d\n", sw);
120 else if (sw == 0x9) 123 else if (sw == 0x9)
121 puts("NAND\n"); 124 puts("NAND\n");
122 else 125 else
123 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 126 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
124 127
125 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 128 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
126 #endif 129 #endif
127 puts("SERDES1 Reference : "); 130 puts("SERDES1 Reference : ");
128 printf("Clock1 = 156.25MHz "); 131 printf("Clock1 = 156.25MHz ");
129 printf("Clock2 = 156.25MHz"); 132 printf("Clock2 = 156.25MHz");
130 #endif 133 #endif
131 134
132 puts("\nSERDES2 Reference : "); 135 puts("\nSERDES2 Reference : ");
133 printf("Clock1 = 100MHz "); 136 printf("Clock1 = 100MHz ");
134 printf("Clock2 = 100MHz\n"); 137 printf("Clock2 = 100MHz\n");
135 138
136 return 0; 139 return 0;
137 } 140 }
138 141
139 unsigned long get_board_sys_clk(void) 142 unsigned long get_board_sys_clk(void)
140 { 143 {
141 #ifdef CONFIG_FSL_QIXIS 144 #ifdef CONFIG_FSL_QIXIS
142 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 145 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
143 146
144 switch (sysclk_conf & 0x0F) { 147 switch (sysclk_conf & 0x0F) {
145 case QIXIS_SYSCLK_83: 148 case QIXIS_SYSCLK_83:
146 return 83333333; 149 return 83333333;
147 case QIXIS_SYSCLK_100: 150 case QIXIS_SYSCLK_100:
148 return 100000000; 151 return 100000000;
149 case QIXIS_SYSCLK_125: 152 case QIXIS_SYSCLK_125:
150 return 125000000; 153 return 125000000;
151 case QIXIS_SYSCLK_133: 154 case QIXIS_SYSCLK_133:
152 return 133333333; 155 return 133333333;
153 case QIXIS_SYSCLK_150: 156 case QIXIS_SYSCLK_150:
154 return 150000000; 157 return 150000000;
155 case QIXIS_SYSCLK_160: 158 case QIXIS_SYSCLK_160:
156 return 160000000; 159 return 160000000;
157 case QIXIS_SYSCLK_166: 160 case QIXIS_SYSCLK_166:
158 return 166666666; 161 return 166666666;
159 } 162 }
160 #endif 163 #endif
161 return 100000000; 164 return 100000000;
162 } 165 }
163 166
164 int select_i2c_ch_pca9547(u8 ch) 167 int select_i2c_ch_pca9547(u8 ch)
165 { 168 {
166 int ret; 169 int ret;
167 170
168 #ifndef CONFIG_DM_I2C 171 #ifndef CONFIG_DM_I2C
169 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 172 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
170 #else 173 #else
171 struct udevice *dev; 174 struct udevice *dev;
172 175
173 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); 176 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
174 if (!ret) 177 if (!ret)
175 ret = dm_i2c_write(dev, 0, &ch, 1); 178 ret = dm_i2c_write(dev, 0, &ch, 1);
176 #endif 179 #endif
177 180
178 if (ret) { 181 if (ret) {
179 puts("PCA: failed to select proper channel\n"); 182 puts("PCA: failed to select proper channel\n");
180 return ret; 183 return ret;
181 } 184 }
182 185
183 return 0; 186 return 0;
184 } 187 }
185 188
186 int i2c_multiplexer_select_vid_channel(u8 channel) 189 int i2c_multiplexer_select_vid_channel(u8 channel)
187 { 190 {
188 return select_i2c_ch_pca9547(channel); 191 return select_i2c_ch_pca9547(channel);
189 } 192 }
190 193
191 int config_board_mux(int ctrl_type) 194 int config_board_mux(int ctrl_type)
192 { 195 {
193 #ifdef CONFIG_FSL_QIXIS 196 #ifdef CONFIG_FSL_QIXIS
194 u8 reg5; 197 u8 reg5;
195 198
196 reg5 = QIXIS_READ(brdcfg[5]); 199 reg5 = QIXIS_READ(brdcfg[5]);
197 200
198 switch (ctrl_type) { 201 switch (ctrl_type) {
199 case MUX_TYPE_SDHC: 202 case MUX_TYPE_SDHC:
200 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 203 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
201 break; 204 break;
202 case MUX_TYPE_DSPI: 205 case MUX_TYPE_DSPI:
203 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 206 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
204 break; 207 break;
205 default: 208 default:
206 printf("Wrong mux interface type\n"); 209 printf("Wrong mux interface type\n");
207 return -1; 210 return -1;
208 } 211 }
209 212
210 QIXIS_WRITE(brdcfg[5], reg5); 213 QIXIS_WRITE(brdcfg[5], reg5);
211 #endif 214 #endif
212 return 0; 215 return 0;
213 } 216 }
214 217
215 int board_init(void) 218 int board_init(void)
216 { 219 {
217 #ifdef CONFIG_FSL_MC_ENET 220 #ifdef CONFIG_FSL_MC_ENET
218 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 221 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
219 #endif 222 #endif
220 223
221 init_final_memctl_regs(); 224 init_final_memctl_regs();
222 225
223 #ifdef CONFIG_ENV_IS_NOWHERE 226 #ifdef CONFIG_ENV_IS_NOWHERE
224 gd->env_addr = (ulong)&default_environment[0]; 227 gd->env_addr = (ulong)&default_environment[0];
225 #endif 228 #endif
226 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 229 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
227 230
228 #ifdef CONFIG_FSL_QIXIS 231 #ifdef CONFIG_FSL_QIXIS
229 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 232 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
230 #endif 233 #endif
231 234
232 #ifdef CONFIG_FSL_CAAM 235 #ifdef CONFIG_FSL_CAAM
233 sec_init(); 236 sec_init();
234 #endif 237 #endif
235 #ifdef CONFIG_FSL_LS_PPA 238 #ifdef CONFIG_FSL_LS_PPA
236 ppa_init(); 239 ppa_init();
237 #endif 240 #endif
238 241
239 #ifdef CONFIG_FSL_MC_ENET 242 #ifdef CONFIG_FSL_MC_ENET
240 /* invert AQR405 IRQ pins polarity */ 243 /* invert AQR405 IRQ pins polarity */
241 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 244 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
242 #endif 245 #endif
243 #ifdef CONFIG_FSL_CAAM 246 #ifdef CONFIG_FSL_CAAM
244 sec_init(); 247 sec_init();
245 #endif 248 #endif
246 249
247 return 0; 250 return 0;
248 } 251 }
249 252
250 int board_early_init_f(void) 253 int board_early_init_f(void)
251 { 254 {
252 #ifdef CONFIG_SYS_I2C_EARLY_INIT 255 #ifdef CONFIG_SYS_I2C_EARLY_INIT
253 i2c_early_init_f(); 256 i2c_early_init_f();
254 #endif 257 #endif
255 fsl_lsch3_early_init_f(); 258 fsl_lsch3_early_init_f();
256 return 0; 259 return 0;
257 } 260 }
258 261
259 int misc_init_r(void) 262 int misc_init_r(void)
260 { 263 {
261 char *env_hwconfig; 264 char *env_hwconfig;
262 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 265 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
263 u32 val; 266 u32 val;
264 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 267 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
265 u32 svr = gur_in32(&gur->svr); 268 u32 svr = gur_in32(&gur->svr);
266 269
267 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 270 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
268 271
269 env_hwconfig = env_get("hwconfig"); 272 env_hwconfig = env_get("hwconfig");
270 273
271 if (hwconfig_f("dspi", env_hwconfig) && 274 if (hwconfig_f("dspi", env_hwconfig) &&
272 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 275 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
273 config_board_mux(MUX_TYPE_DSPI); 276 config_board_mux(MUX_TYPE_DSPI);
274 else 277 else
275 config_board_mux(MUX_TYPE_SDHC); 278 config_board_mux(MUX_TYPE_SDHC);
276 279
277 /* 280 /*
278 * LS2081ARDB RevF board has smart voltage translator 281 * LS2081ARDB RevF board has smart voltage translator
279 * which needs to be programmed to enable high speed SD interface 282 * which needs to be programmed to enable high speed SD interface
280 * by setting GPIO4_10 output to zero 283 * by setting GPIO4_10 output to zero
281 */ 284 */
282 #ifdef CONFIG_TARGET_LS2081ARDB 285 #ifdef CONFIG_TARGET_LS2081ARDB
283 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | 286 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
284 in_le32(GPIO4_GPDIR_ADDR))); 287 in_le32(GPIO4_GPDIR_ADDR)));
285 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & 288 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
286 in_le32(GPIO4_GPDAT_ADDR))); 289 in_le32(GPIO4_GPDAT_ADDR)));
287 #endif 290 #endif
288 if (hwconfig("sdhc")) 291 if (hwconfig("sdhc"))
289 config_board_mux(MUX_TYPE_SDHC); 292 config_board_mux(MUX_TYPE_SDHC);
290 293
291 if (adjust_vdd(0)) 294 if (adjust_vdd(0))
292 printf("Warning: Adjusting core voltage failed.\n"); 295 printf("Warning: Adjusting core voltage failed.\n");
293 /* 296 /*
294 * Default value of board env is based on filename which is 297 * Default value of board env is based on filename which is
295 * ls2080ardb. Modify board env for other supported SoCs 298 * ls2080ardb. Modify board env for other supported SoCs
296 */ 299 */
297 if ((SVR_SOC_VER(svr) == SVR_LS2088A) || 300 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
298 (SVR_SOC_VER(svr) == SVR_LS2048A)) 301 (SVR_SOC_VER(svr) == SVR_LS2048A))
299 env_set("board", "ls2088ardb"); 302 env_set("board", "ls2088ardb");
300 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) || 303 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
301 (SVR_SOC_VER(svr) == SVR_LS2041A)) 304 (SVR_SOC_VER(svr) == SVR_LS2041A))
302 env_set("board", "ls2081ardb"); 305 env_set("board", "ls2081ardb");
303 306
304 return 0; 307 return 0;
305 } 308 }
306 309
307 void detail_board_ddr_info(void) 310 void detail_board_ddr_info(void)
308 { 311 {
309 puts("\nDDR "); 312 puts("\nDDR ");
310 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 313 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
311 print_ddr_info(0); 314 print_ddr_info(0);
312 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 315 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
313 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 316 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
314 puts("\nDP-DDR "); 317 puts("\nDP-DDR ");
315 print_size(gd->bd->bi_dram[2].size, ""); 318 print_size(gd->bd->bi_dram[2].size, "");
316 print_ddr_info(CONFIG_DP_DDR_CTRL); 319 print_ddr_info(CONFIG_DP_DDR_CTRL);
317 } 320 }
318 #endif 321 #endif
319 } 322 }
320 323
321 #ifdef CONFIG_FSL_MC_ENET 324 #ifdef CONFIG_FSL_MC_ENET
322 void fdt_fixup_board_enet(void *fdt) 325 void fdt_fixup_board_enet(void *fdt)
323 { 326 {
324 int offset; 327 int offset;
325 328
326 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 329 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
327 330
328 if (offset < 0) 331 if (offset < 0)
329 offset = fdt_path_offset(fdt, "/fsl-mc"); 332 offset = fdt_path_offset(fdt, "/fsl-mc");
330 333
331 if (offset < 0) { 334 if (offset < 0) {
332 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 335 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
333 __func__, offset); 336 __func__, offset);
334 return; 337 return;
335 } 338 }
336 339
337 if (get_mc_boot_status() == 0 && 340 if (get_mc_boot_status() == 0 &&
338 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) 341 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
339 fdt_status_okay(fdt, offset); 342 fdt_status_okay(fdt, offset);
340 else 343 else
341 fdt_status_fail(fdt, offset); 344 fdt_status_fail(fdt, offset);
342 } 345 }
343 346
344 void board_quiesce_devices(void) 347 void board_quiesce_devices(void)
345 { 348 {
346 fsl_mc_ldpaa_exit(gd->bd); 349 fsl_mc_ldpaa_exit(gd->bd);
347 } 350 }
348 #endif 351 #endif
349 352
353 #ifdef CONFIG_GIC_V3_ITS
354 void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
355 {
356 u32 phandle;
357 int err;
358 struct fdt_memory gic_lpi;
359
360 gic_lpi.start = gic_lpi_base;
361 gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
362 err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
363 if (err < 0)
364 debug("failed to add reserved memory: %d\n", err);
365 }
366 #endif
367
350 #ifdef CONFIG_OF_BOARD_SETUP 368 #ifdef CONFIG_OF_BOARD_SETUP
351 void fsl_fdt_fixup_flash(void *fdt) 369 void fsl_fdt_fixup_flash(void *fdt)
352 { 370 {
353 int offset; 371 int offset;
354 #ifdef CONFIG_TFABOOT 372 #ifdef CONFIG_TFABOOT
355 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 373 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
356 u32 val; 374 u32 val;
357 #endif 375 #endif
358 376
359 /* 377 /*
360 * IFC and QSPI are muxed on board. 378 * IFC and QSPI are muxed on board.
361 * So disable IFC node in dts if QSPI is enabled or 379 * So disable IFC node in dts if QSPI is enabled or
362 * disable QSPI node in dts in case QSPI is not enabled. 380 * disable QSPI node in dts in case QSPI is not enabled.
363 */ 381 */
364 #ifdef CONFIG_TFABOOT 382 #ifdef CONFIG_TFABOOT
365 enum boot_src src = get_boot_src(); 383 enum boot_src src = get_boot_src();
366 bool disable_ifc = false; 384 bool disable_ifc = false;
367 385
368 switch (src) { 386 switch (src) {
369 case BOOT_SOURCE_IFC_NOR: 387 case BOOT_SOURCE_IFC_NOR:
370 disable_ifc = false; 388 disable_ifc = false;
371 break; 389 break;
372 case BOOT_SOURCE_QSPI_NOR: 390 case BOOT_SOURCE_QSPI_NOR:
373 disable_ifc = true; 391 disable_ifc = true;
374 break; 392 break;
375 default: 393 default:
376 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); 394 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
377 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) 395 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
378 disable_ifc = true; 396 disable_ifc = true;
379 break; 397 break;
380 } 398 }
381 399
382 if (disable_ifc) { 400 if (disable_ifc) {
383 offset = fdt_path_offset(fdt, "/soc/ifc"); 401 offset = fdt_path_offset(fdt, "/soc/ifc");
384 402
385 if (offset < 0) 403 if (offset < 0)
386 offset = fdt_path_offset(fdt, "/ifc"); 404 offset = fdt_path_offset(fdt, "/ifc");
387 } else { 405 } else {
388 offset = fdt_path_offset(fdt, "/soc/quadspi"); 406 offset = fdt_path_offset(fdt, "/soc/quadspi");
389 407
390 if (offset < 0) 408 if (offset < 0)
391 offset = fdt_path_offset(fdt, "/quadspi"); 409 offset = fdt_path_offset(fdt, "/quadspi");
392 } 410 }
393 411
394 #else 412 #else
395 #ifdef CONFIG_FSL_QSPI 413 #ifdef CONFIG_FSL_QSPI
396 offset = fdt_path_offset(fdt, "/soc/ifc"); 414 offset = fdt_path_offset(fdt, "/soc/ifc");
397 415
398 if (offset < 0) 416 if (offset < 0)
399 offset = fdt_path_offset(fdt, "/ifc"); 417 offset = fdt_path_offset(fdt, "/ifc");
400 #else 418 #else
401 offset = fdt_path_offset(fdt, "/soc/quadspi"); 419 offset = fdt_path_offset(fdt, "/soc/quadspi");
402 420
403 if (offset < 0) 421 if (offset < 0)
404 offset = fdt_path_offset(fdt, "/quadspi"); 422 offset = fdt_path_offset(fdt, "/quadspi");
405 #endif 423 #endif
406 #endif 424 #endif
407 425
408 if (offset < 0) 426 if (offset < 0)
409 return; 427 return;
410 428
411 fdt_status_disabled(fdt, offset); 429 fdt_status_disabled(fdt, offset);
412 } 430 }
413 431
414 int ft_board_setup(void *blob, bd_t *bd) 432 int ft_board_setup(void *blob, bd_t *bd)
415 { 433 {
416 int i; 434 int i;
417 u16 mc_memory_bank = 0; 435 u16 mc_memory_bank = 0;
418 436
419 u64 *base; 437 u64 *base;
420 u64 *size; 438 u64 *size;
421 u64 mc_memory_base = 0; 439 u64 mc_memory_base = 0;
422 u64 mc_memory_size = 0; 440 u64 mc_memory_size = 0;
423 u16 total_memory_banks; 441 u16 total_memory_banks;
442 u64 gic_lpi_base;
424 443
425 ft_cpu_setup(blob, bd); 444 ft_cpu_setup(blob, bd);
426 445
427 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); 446 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
428 447
429 if (mc_memory_base != 0) 448 if (mc_memory_base != 0)
430 mc_memory_bank++; 449 mc_memory_bank++;
431 450
432 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; 451 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
433 452
434 base = calloc(total_memory_banks, sizeof(u64)); 453 base = calloc(total_memory_banks, sizeof(u64));
435 size = calloc(total_memory_banks, sizeof(u64)); 454 size = calloc(total_memory_banks, sizeof(u64));
436 455
437 /* fixup DT for the two GPP DDR banks */ 456 /* fixup DT for the two GPP DDR banks */
438 base[0] = gd->bd->bi_dram[0].start; 457 base[0] = gd->bd->bi_dram[0].start;
439 size[0] = gd->bd->bi_dram[0].size; 458 size[0] = gd->bd->bi_dram[0].size;
440 base[1] = gd->bd->bi_dram[1].start; 459 base[1] = gd->bd->bi_dram[1].start;
441 size[1] = gd->bd->bi_dram[1].size; 460 size[1] = gd->bd->bi_dram[1].size;
461
462 #ifdef CONFIG_GIC_V3_ITS
463 gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
464 gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
465 fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
466 #endif
442 467
443 #ifdef CONFIG_RESV_RAM 468 #ifdef CONFIG_RESV_RAM
444 /* reduce size if reserved memory is within this bank */ 469 /* reduce size if reserved memory is within this bank */
445 if (gd->arch.resv_ram >= base[0] && 470 if (gd->arch.resv_ram >= base[0] &&
446 gd->arch.resv_ram < base[0] + size[0]) 471 gd->arch.resv_ram < base[0] + size[0])
447 size[0] = gd->arch.resv_ram - base[0]; 472 size[0] = gd->arch.resv_ram - base[0];
448 else if (gd->arch.resv_ram >= base[1] && 473 else if (gd->arch.resv_ram >= base[1] &&
449 gd->arch.resv_ram < base[1] + size[1]) 474 gd->arch.resv_ram < base[1] + size[1])
450 size[1] = gd->arch.resv_ram - base[1]; 475 size[1] = gd->arch.resv_ram - base[1];
451 #endif 476 #endif
452 477
453 if (mc_memory_base != 0) { 478 if (mc_memory_base != 0) {
454 for (i = 0; i <= total_memory_banks; i++) { 479 for (i = 0; i <= total_memory_banks; i++) {
455 if (base[i] == 0 && size[i] == 0) { 480 if (base[i] == 0 && size[i] == 0) {
456 base[i] = mc_memory_base; 481 base[i] = mc_memory_base;
457 size[i] = mc_memory_size; 482 size[i] = mc_memory_size;
458 break; 483 break;
459 } 484 }
460 } 485 }
461 } 486 }
462 487
463 fdt_fixup_memory_banks(blob, base, size, total_memory_banks); 488 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
464 489
465 fdt_fsl_mc_fixup_iommu_map_entry(blob); 490 fdt_fsl_mc_fixup_iommu_map_entry(blob);
466 491
467 fsl_fdt_fixup_dr_usb(blob, bd); 492 fsl_fdt_fixup_dr_usb(blob, bd);
468 493
469 fsl_fdt_fixup_flash(blob); 494 fsl_fdt_fixup_flash(blob);
470 495
471 #ifdef CONFIG_FSL_MC_ENET 496 #ifdef CONFIG_FSL_MC_ENET
472 fdt_fixup_board_enet(blob); 497 fdt_fixup_board_enet(blob);
473 #endif 498 #endif
474 499
475 fdt_fixup_icid(blob); 500 fdt_fixup_icid(blob);
476 501
477 return 0; 502 return 0;
478 } 503 }
479 #endif 504 #endif
480 505
481 void qixis_dump_switch(void) 506 void qixis_dump_switch(void)
482 { 507 {
483 #ifdef CONFIG_FSL_QIXIS 508 #ifdef CONFIG_FSL_QIXIS
484 int i, nr_of_cfgsw; 509 int i, nr_of_cfgsw;
485 510
486 QIXIS_WRITE(cms[0], 0x00); 511 QIXIS_WRITE(cms[0], 0x00);
487 nr_of_cfgsw = QIXIS_READ(cms[1]); 512 nr_of_cfgsw = QIXIS_READ(cms[1]);
488 513
489 puts("DIP switch settings dump:\n"); 514 puts("DIP switch settings dump:\n");
490 for (i = 1; i <= nr_of_cfgsw; i++) { 515 for (i = 1; i <= nr_of_cfgsw; i++) {
491 QIXIS_WRITE(cms[0], i); 516 QIXIS_WRITE(cms[0], i);
492 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 517 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
493 } 518 }
494 #endif 519 #endif
495 } 520 }
496 521
497 /* 522 /*
498 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 523 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
499 * Both slots has 0x54, resulting 2nd slot unusable. 524 * Both slots has 0x54, resulting 2nd slot unusable.
500 */ 525 */
501 void update_spd_address(unsigned int ctrl_num, 526 void update_spd_address(unsigned int ctrl_num,
502 unsigned int slot, 527 unsigned int slot,
503 unsigned int *addr) 528 unsigned int *addr)
504 { 529 {
505 #ifndef CONFIG_TARGET_LS2081ARDB 530 #ifndef CONFIG_TARGET_LS2081ARDB
506 #ifdef CONFIG_FSL_QIXIS 531 #ifdef CONFIG_FSL_QIXIS
507 u8 sw; 532 u8 sw;
508 533
509 sw = QIXIS_READ(arch); 534 sw = QIXIS_READ(arch);
510 if ((sw & 0xf) < 0x3) { 535 if ((sw & 0xf) < 0x3) {
511 if (ctrl_num == 1 && slot == 0) 536 if (ctrl_num == 1 && slot == 0)
512 *addr = SPD_EEPROM_ADDRESS4; 537 *addr = SPD_EEPROM_ADDRESS4;
513 else if (ctrl_num == 1 && slot == 1) 538 else if (ctrl_num == 1 && slot == 1)
514 *addr = SPD_EEPROM_ADDRESS3; 539 *addr = SPD_EEPROM_ADDRESS3;
515 } 540 }
516 #endif 541 #endif
517 #endif 542 #endif
518 } 543 }
519 544
include/configs/ls1088aqds.h
Diff comments   View file @ 8f5a1be
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2017, 2020 NXP 3 * Copyright 2017, 2020 NXP
4 */ 4 */
5 5
6 #ifndef __LS1088A_QDS_H 6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H 7 #define __LS1088A_QDS_H
8 8
9 #include "ls1088a_common.h" 9 #include "ls1088a_common.h"
10 10
11 11
12 #ifndef __ASSEMBLY__ 12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void); 14 unsigned long get_board_ddr_clk(void);
15 #endif 15 #endif
16 16
17 #ifdef CONFIG_TFABOOT 17 #ifdef CONFIG_TFABOOT
18 #define CONFIG_SYS_MMC_ENV_DEV 0 18 #define CONFIG_SYS_MMC_ENV_DEV 0
19 19
20 #define CONFIG_MISC_INIT_R 20 #define CONFIG_MISC_INIT_R
21 #else 21 #else
22 #if defined(CONFIG_QSPI_BOOT) 22 #if defined(CONFIG_QSPI_BOOT)
23 #elif defined(CONFIG_SD_BOOT) 23 #elif defined(CONFIG_SD_BOOT)
24 #define CONFIG_SYS_MMC_ENV_DEV 0 24 #define CONFIG_SYS_MMC_ENV_DEV 0
25 #endif 25 #endif
26 #endif 26 #endif
27 27
28 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 28 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
29 #define CONFIG_QIXIS_I2C_ACCESS 29 #define CONFIG_QIXIS_I2C_ACCESS
30 #define SYS_NO_FLASH 30 #define SYS_NO_FLASH
31 31
32 #undef CONFIG_CMD_IMLS 32 #undef CONFIG_CMD_IMLS
33 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_SYS_CLK_FREQ 100000000
34 #define CONFIG_DDR_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000
35 #else 35 #else
36 #define CONFIG_QIXIS_I2C_ACCESS 36 #define CONFIG_QIXIS_I2C_ACCESS
37 #ifndef CONFIG_DM_I2C 37 #ifndef CONFIG_DM_I2C
38 #define CONFIG_SYS_I2C_EARLY_INIT 38 #define CONFIG_SYS_I2C_EARLY_INIT
39 #endif 39 #endif
40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
42 #endif 42 #endif
43 43
44 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 44 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
45 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
46 46
47 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 47 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
48 48
49 #define CONFIG_DDR_SPD 49 #define CONFIG_DDR_SPD
50 #define CONFIG_DDR_ECC 50 #define CONFIG_DDR_ECC
51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 52 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
53 #define SPD_EEPROM_ADDRESS 0x51 53 #define SPD_EEPROM_ADDRESS 0x51
54 #define CONFIG_SYS_SPD_BUS_NUM 0 54 #define CONFIG_SYS_SPD_BUS_NUM 0
55 55
56 56
57 /* 57 /*
58 * IFC Definitions 58 * IFC Definitions
59 */ 59 */
60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
61 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 61 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
62 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 62 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
63 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 63 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
64 64
65 #define CONFIG_SYS_NOR0_CSPR \ 65 #define CONFIG_SYS_NOR0_CSPR \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
67 CSPR_PORT_SIZE_16 | \ 67 CSPR_PORT_SIZE_16 | \
68 CSPR_MSEL_NOR | \ 68 CSPR_MSEL_NOR | \
69 CSPR_V) 69 CSPR_V)
70 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 70 #define CONFIG_SYS_NOR0_CSPR_EARLY \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
72 CSPR_PORT_SIZE_16 | \ 72 CSPR_PORT_SIZE_16 | \
73 CSPR_MSEL_NOR | \ 73 CSPR_MSEL_NOR | \
74 CSPR_V) 74 CSPR_V)
75 #define CONFIG_SYS_NOR1_CSPR \ 75 #define CONFIG_SYS_NOR1_CSPR \
76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
77 CSPR_PORT_SIZE_16 | \ 77 CSPR_PORT_SIZE_16 | \
78 CSPR_MSEL_NOR | \ 78 CSPR_MSEL_NOR | \
79 CSPR_V) 79 CSPR_V)
80 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 80 #define CONFIG_SYS_NOR1_CSPR_EARLY \
81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
82 CSPR_PORT_SIZE_16 | \ 82 CSPR_PORT_SIZE_16 | \
83 CSPR_MSEL_NOR | \ 83 CSPR_MSEL_NOR | \
84 CSPR_V) 84 CSPR_V)
85 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 85 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
86 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 86 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
87 FTIM0_NOR_TEADC(0x5) | \ 87 FTIM0_NOR_TEADC(0x5) | \
88 FTIM0_NOR_TAVDS(0x6) | \ 88 FTIM0_NOR_TAVDS(0x6) | \
89 FTIM0_NOR_TEAHC(0x5)) 89 FTIM0_NOR_TEAHC(0x5))
90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
91 FTIM1_NOR_TRAD_NOR(0x1a) | \ 91 FTIM1_NOR_TRAD_NOR(0x1a) | \
92 FTIM1_NOR_TSEQRAD_NOR(0x13)) 92 FTIM1_NOR_TSEQRAD_NOR(0x13))
93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
94 FTIM2_NOR_TCH(0x8) | \ 94 FTIM2_NOR_TCH(0x8) | \
95 FTIM2_NOR_TWPH(0xe) | \ 95 FTIM2_NOR_TWPH(0xe) | \
96 FTIM2_NOR_TWP(0x1c)) 96 FTIM2_NOR_TWP(0x1c))
97 #define CONFIG_SYS_NOR_FTIM3 0x04000000 97 #define CONFIG_SYS_NOR_FTIM3 0x04000000
98 #define CONFIG_SYS_IFC_CCR 0x01000000 98 #define CONFIG_SYS_IFC_CCR 0x01000000
99 99
100 #ifndef SYS_NO_FLASH 100 #ifndef SYS_NO_FLASH
101 #define CONFIG_SYS_FLASH_QUIET_TEST 101 #define CONFIG_SYS_FLASH_QUIET_TEST
102 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 102 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
103 103
104 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 104 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
105 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 105 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
108 108
109 #define CONFIG_SYS_FLASH_EMPTY_INFO 109 #define CONFIG_SYS_FLASH_EMPTY_INFO
110 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 110 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
111 CONFIG_SYS_FLASH_BASE + 0x40000000} 111 CONFIG_SYS_FLASH_BASE + 0x40000000}
112 #endif 112 #endif
113 #endif 113 #endif
114 114
115 #define CONFIG_NAND_FSL_IFC 115 #define CONFIG_NAND_FSL_IFC
116 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 116 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
117 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 117 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
118 118
119 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 119 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
120 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 120 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
121 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 121 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
122 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 122 | CSPR_MSEL_NAND /* MSEL = NAND */ \
123 | CSPR_V) 123 | CSPR_V)
124 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 124 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
125 125
126 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 126 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
129 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 129 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
131 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 131 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
132 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 132 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
133 133
134 #define CONFIG_SYS_NAND_ONFI_DETECTION 134 #define CONFIG_SYS_NAND_ONFI_DETECTION
135 135
136 /* ONFI NAND Flash mode0 Timing Params */ 136 /* ONFI NAND Flash mode0 Timing Params */
137 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 137 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
138 FTIM0_NAND_TWP(0x18) | \ 138 FTIM0_NAND_TWP(0x18) | \
139 FTIM0_NAND_TWCHT(0x07) | \ 139 FTIM0_NAND_TWCHT(0x07) | \
140 FTIM0_NAND_TWH(0x0a)) 140 FTIM0_NAND_TWH(0x0a))
141 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 141 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
142 FTIM1_NAND_TWBE(0x39) | \ 142 FTIM1_NAND_TWBE(0x39) | \
143 FTIM1_NAND_TRR(0x0e) | \ 143 FTIM1_NAND_TRR(0x0e) | \
144 FTIM1_NAND_TRP(0x18)) 144 FTIM1_NAND_TRP(0x18))
145 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 145 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
146 FTIM2_NAND_TREH(0x0a) | \ 146 FTIM2_NAND_TREH(0x0a) | \
147 FTIM2_NAND_TWHRE(0x1e)) 147 FTIM2_NAND_TWHRE(0x1e))
148 #define CONFIG_SYS_NAND_FTIM3 0x0 148 #define CONFIG_SYS_NAND_FTIM3 0x0
149 149
150 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 150 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1
152 #define CONFIG_MTD_NAND_VERIFY_WRITE 152 #define CONFIG_MTD_NAND_VERIFY_WRITE
153 #define CONFIG_CMD_NAND 153 #define CONFIG_CMD_NAND
154 154
155 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 155 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
156 156
157 #define CONFIG_FSL_QIXIS 157 #define CONFIG_FSL_QIXIS
158 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 158 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
159 #define QIXIS_LBMAP_SWITCH 6 159 #define QIXIS_LBMAP_SWITCH 6
160 #define QIXIS_QMAP_MASK 0xe0 160 #define QIXIS_QMAP_MASK 0xe0
161 #define QIXIS_QMAP_SHIFT 5 161 #define QIXIS_QMAP_SHIFT 5
162 #define QIXIS_LBMAP_MASK 0x0f 162 #define QIXIS_LBMAP_MASK 0x0f
163 #define QIXIS_LBMAP_SHIFT 0 163 #define QIXIS_LBMAP_SHIFT 0
164 #define QIXIS_LBMAP_DFLTBANK 0x0e 164 #define QIXIS_LBMAP_DFLTBANK 0x0e
165 #define QIXIS_LBMAP_ALTBANK 0x2e 165 #define QIXIS_LBMAP_ALTBANK 0x2e
166 #define QIXIS_LBMAP_SD 0x00 166 #define QIXIS_LBMAP_SD 0x00
167 #define QIXIS_LBMAP_EMMC 0x00 167 #define QIXIS_LBMAP_EMMC 0x00
168 #define QIXIS_LBMAP_IFC 0x00 168 #define QIXIS_LBMAP_IFC 0x00
169 #define QIXIS_LBMAP_SD_QSPI 0x0e 169 #define QIXIS_LBMAP_SD_QSPI 0x0e
170 #define QIXIS_LBMAP_QSPI 0x0e 170 #define QIXIS_LBMAP_QSPI 0x0e
171 #define QIXIS_RCW_SRC_IFC 0x25 171 #define QIXIS_RCW_SRC_IFC 0x25
172 #define QIXIS_RCW_SRC_SD 0x40 172 #define QIXIS_RCW_SRC_SD 0x40
173 #define QIXIS_RCW_SRC_EMMC 0x41 173 #define QIXIS_RCW_SRC_EMMC 0x41
174 #define QIXIS_RCW_SRC_QSPI 0x62 174 #define QIXIS_RCW_SRC_QSPI 0x62
175 #define QIXIS_RST_CTL_RESET 0x41 175 #define QIXIS_RST_CTL_RESET 0x41
176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179 #define QIXIS_RST_FORCE_MEM 0x01 179 #define QIXIS_RST_FORCE_MEM 0x01
180 #define QIXIS_STAT_PRES1 0xb 180 #define QIXIS_STAT_PRES1 0xb
181 #define QIXIS_SDID_MASK 0x07 181 #define QIXIS_SDID_MASK 0x07
182 #define QIXIS_ESDHC_NO_ADAPTER 0x7 182 #define QIXIS_ESDHC_NO_ADAPTER 0x7
183 183
184 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 184 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
185 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 185 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
186 | CSPR_PORT_SIZE_8 \ 186 | CSPR_PORT_SIZE_8 \
187 | CSPR_MSEL_GPCM \ 187 | CSPR_MSEL_GPCM \
188 | CSPR_V) 188 | CSPR_V)
189 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 189 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 \ 190 | CSPR_PORT_SIZE_8 \
191 | CSPR_MSEL_GPCM \ 191 | CSPR_MSEL_GPCM \
192 | CSPR_V) 192 | CSPR_V)
193 193
194 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 194 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
196 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 196 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
197 #else 197 #else
198 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 198 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
199 #endif 199 #endif
200 /* QIXIS Timing parameters*/ 200 /* QIXIS Timing parameters*/
201 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 201 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
202 FTIM0_GPCM_TEADC(0x0e) | \ 202 FTIM0_GPCM_TEADC(0x0e) | \
203 FTIM0_GPCM_TEAHC(0x0e)) 203 FTIM0_GPCM_TEAHC(0x0e))
204 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 204 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
205 FTIM1_GPCM_TRAD(0x3f)) 205 FTIM1_GPCM_TRAD(0x3f))
206 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 206 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
207 FTIM2_GPCM_TCH(0xf) | \ 207 FTIM2_GPCM_TCH(0xf) | \
208 FTIM2_GPCM_TWP(0x3E)) 208 FTIM2_GPCM_TWP(0x3E))
209 #define SYS_FPGA_CS_FTIM3 0x0 209 #define SYS_FPGA_CS_FTIM3 0x0
210 210
211 #ifdef CONFIG_TFABOOT 211 #ifdef CONFIG_TFABOOT
212 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 212 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
214 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 214 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
221 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 221 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
222 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 222 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
223 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 223 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
224 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 224 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
225 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 225 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
226 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 226 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
227 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 227 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
228 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 228 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
229 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 229 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
230 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 230 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
231 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 231 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
232 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 232 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
233 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 233 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
234 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 234 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
235 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 235 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
236 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 236 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
237 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 237 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
238 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 238 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
239 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 239 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
240 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 240 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
241 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 241 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
242 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 242 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
243 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 243 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
244 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 244 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
245 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 245 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
246 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 246 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
247 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 247 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
248 #else 248 #else
249 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 249 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
250 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 250 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
251 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 251 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
252 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 252 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
253 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 253 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
254 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 254 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
255 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 255 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
256 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 256 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
257 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 257 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
258 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 258 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
259 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 259 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
260 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 260 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
261 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 261 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
262 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 262 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
263 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 263 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
264 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 264 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
265 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 265 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
266 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 266 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
267 #else 267 #else
268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
270 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 270 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
279 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 279 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
281 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 281 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 282 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 283 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 284 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 285 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 286 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
287 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 287 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
288 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 288 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
289 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 289 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
290 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 290 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
291 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 291 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
292 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 292 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
293 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 293 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
294 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 294 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
295 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 295 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
296 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 296 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
297 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 297 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
298 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 298 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
299 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 299 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
300 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 300 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
301 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 301 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
302 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 302 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
303 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 303 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
304 #endif 304 #endif
305 #endif 305 #endif
306 306
307 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 307 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
308 308
309 /* 309 /*
310 * I2C bus multiplexer 310 * I2C bus multiplexer
311 */ 311 */
312 #define I2C_MUX_PCA_ADDR_PRI 0x77 312 #define I2C_MUX_PCA_ADDR_PRI 0x77
313 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 313 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
314 #define I2C_RETIMER_ADDR 0x18 314 #define I2C_RETIMER_ADDR 0x18
315 #define I2C_RETIMER_ADDR2 0x19 315 #define I2C_RETIMER_ADDR2 0x19
316 #define I2C_MUX_CH_DEFAULT 0x8 316 #define I2C_MUX_CH_DEFAULT 0x8
317 #define I2C_MUX_CH5 0xD 317 #define I2C_MUX_CH5 0xD
318 318
319 #define I2C_MUX_CH_VOL_MONITOR 0xA 319 #define I2C_MUX_CH_VOL_MONITOR 0xA
320 320
321 /* Voltage monitor on channel 2*/ 321 /* Voltage monitor on channel 2*/
322 #define I2C_VOL_MONITOR_ADDR 0x63 322 #define I2C_VOL_MONITOR_ADDR 0x63
323 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 323 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
324 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 324 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
325 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 325 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
326 #define I2C_SVDD_MONITOR_ADDR 0x4F 326 #define I2C_SVDD_MONITOR_ADDR 0x4F
327 327
328 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 328 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
329 #define CONFIG_VID 329 #define CONFIG_VID
330 330
331 /* The lowest and highest voltage allowed for LS1088AQDS */ 331 /* The lowest and highest voltage allowed for LS1088AQDS */
332 #define VDD_MV_MIN 819 332 #define VDD_MV_MIN 819
333 #define VDD_MV_MAX 1212 333 #define VDD_MV_MAX 1212
334 334
335 #define CONFIG_VOL_MONITOR_LTC3882_SET 335 #define CONFIG_VOL_MONITOR_LTC3882_SET
336 #define CONFIG_VOL_MONITOR_LTC3882_READ 336 #define CONFIG_VOL_MONITOR_LTC3882_READ
337 337
338 /* PM Bus commands code for LTC3882*/ 338 /* PM Bus commands code for LTC3882*/
339 #define PMBUS_CMD_PAGE 0x0 339 #define PMBUS_CMD_PAGE 0x0
340 #define PMBUS_CMD_READ_VOUT 0x8B 340 #define PMBUS_CMD_READ_VOUT 0x8B
341 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 341 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
342 #define PMBUS_CMD_VOUT_COMMAND 0x21 342 #define PMBUS_CMD_VOUT_COMMAND 0x21
343 343
344 #define PWM_CHANNEL0 0x0 344 #define PWM_CHANNEL0 0x0
345 345
346 /* 346 /*
347 * RTC configuration 347 * RTC configuration
348 */ 348 */
349 #define RTC 349 #define RTC
350 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 350 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
351 351
352 /* EEPROM */ 352 /* EEPROM */
353 #define CONFIG_ID_EEPROM 353 #define CONFIG_ID_EEPROM
354 #define CONFIG_SYS_I2C_EEPROM_NXID 354 #define CONFIG_SYS_I2C_EEPROM_NXID
355 #define CONFIG_SYS_EEPROM_BUS_NUM 0 355 #define CONFIG_SYS_EEPROM_BUS_NUM 0
356 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 356 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
359 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 359 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
360 360
361 #ifdef CONFIG_FSL_DSPI 361 #ifdef CONFIG_FSL_DSPI
362 #define CONFIG_SPI_FLASH_STMICRO 362 #define CONFIG_SPI_FLASH_STMICRO
363 #define CONFIG_SPI_FLASH_SST 363 #define CONFIG_SPI_FLASH_SST
364 #define CONFIG_SPI_FLASH_EON 364 #define CONFIG_SPI_FLASH_EON
365 #if !defined(CONFIG_TFABOOT) && \ 365 #if !defined(CONFIG_TFABOOT) && \
366 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 366 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
367 #endif 367 #endif
368 #endif 368 #endif
369 369
370 #define CONFIG_CMD_MEMINFO 370 #define CONFIG_CMD_MEMINFO
371 #define CONFIG_SYS_MEMTEST_START 0x80000000 371 #define CONFIG_SYS_MEMTEST_START 0x80000000
372 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 372 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
373 373
374 #ifdef CONFIG_SPL_BUILD 374 #ifdef CONFIG_SPL_BUILD
375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
376 #else 376 #else
377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
378 #endif 378 #endif
379 379
380 #define CONFIG_FSL_MEMAC 380 #define CONFIG_FSL_MEMAC
381 381
382 /* MMC */ 382 /* MMC */
383 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 383 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
384 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 384 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
385 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 385 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
386 386
387 #define COMMON_ENV \
388 "kernelheader_addr_r=0x80200000\0" \
389 "fdtheader_addr_r=0x80100000\0" \
390 "kernel_addr_r=0x81000000\0" \
391 "fdt_addr_r=0x90000000\0" \
392 "load_addr=0xa0000000\0"
393
387 /* Initial environment variables */ 394 /* Initial environment variables */
388 #ifdef CONFIG_NXP_ESBC 395 #ifdef CONFIG_NXP_ESBC
389 #undef CONFIG_EXTRA_ENV_SETTINGS 396 #undef CONFIG_EXTRA_ENV_SETTINGS
390 #define CONFIG_EXTRA_ENV_SETTINGS \ 397 #define CONFIG_EXTRA_ENV_SETTINGS \
398 COMMON_ENV \
391 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 399 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
392 "loadaddr=0x90100000\0" \ 400 "loadaddr=0x90100000\0" \
393 "kernel_addr=0x100000\0" \ 401 "kernel_addr=0x100000\0" \
394 "ramdisk_addr=0x800000\0" \ 402 "ramdisk_addr=0x800000\0" \
395 "ramdisk_size=0x2000000\0" \ 403 "ramdisk_size=0x2000000\0" \
396 "fdt_high=0xa0000000\0" \ 404 "fdt_high=0xa0000000\0" \
397 "initrd_high=0xffffffffffffffff\0" \ 405 "initrd_high=0xffffffffffffffff\0" \
398 "kernel_start=0x1000000\0" \ 406 "kernel_start=0x1000000\0" \
399 "kernel_load=0xa0000000\0" \ 407 "kernel_load=0xa0000000\0" \
400 "kernel_size=0x2800000\0" \ 408 "kernel_size=0x2800000\0" \
401 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 409 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
402 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ 410 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
403 "sf read 0xa0e00000 0xe00000 0x100000;" \ 411 "sf read 0xa0e00000 0xe00000 0x100000;" \
404 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ 412 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
405 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 413 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
406 "mcmemsize=0x70000000 \0" 414 "mcmemsize=0x70000000 \0"
407 #else /* if !(CONFIG_NXP_ESBC) */ 415 #else /* if !(CONFIG_NXP_ESBC) */
408 #ifdef CONFIG_TFABOOT 416 #ifdef CONFIG_TFABOOT
409 #define QSPI_MC_INIT_CMD \ 417 #define QSPI_MC_INIT_CMD \
410 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 418 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
411 "sf read 0x80100000 0xE00000 0x100000;" \ 419 "sf read 0x80100000 0xE00000 0x100000;" \
412 "fsl_mc start mc 0x80000000 0x80100000\0" 420 "fsl_mc start mc 0x80000000 0x80100000\0"
413 #define SD_MC_INIT_CMD \ 421 #define SD_MC_INIT_CMD \
414 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 422 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
415 "mmc read 0x80100000 0x7000 0x800;" \ 423 "mmc read 0x80100000 0x7000 0x800;" \
416 "fsl_mc start mc 0x80000000 0x80100000\0" 424 "fsl_mc start mc 0x80000000 0x80100000\0"
417 #define IFC_MC_INIT_CMD \ 425 #define IFC_MC_INIT_CMD \
418 "fsl_mc start mc 0x580A00000 0x580E00000\0" 426 "fsl_mc start mc 0x580A00000 0x580E00000\0"
419 427
420 #undef CONFIG_EXTRA_ENV_SETTINGS 428 #undef CONFIG_EXTRA_ENV_SETTINGS
421 #define CONFIG_EXTRA_ENV_SETTINGS \ 429 #define CONFIG_EXTRA_ENV_SETTINGS \
430 COMMON_ENV \
422 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 431 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
423 "loadaddr=0x90100000\0" \ 432 "loadaddr=0x90100000\0" \
424 "kernel_addr=0x100000\0" \ 433 "kernel_addr=0x100000\0" \
425 "kernel_addr_sd=0x800\0" \ 434 "kernel_addr_sd=0x800\0" \
426 "ramdisk_addr=0x800000\0" \ 435 "ramdisk_addr=0x800000\0" \
427 "ramdisk_size=0x2000000\0" \ 436 "ramdisk_size=0x2000000\0" \
428 "fdt_high=0xa0000000\0" \ 437 "fdt_high=0xa0000000\0" \
429 "initrd_high=0xffffffffffffffff\0" \ 438 "initrd_high=0xffffffffffffffff\0" \
430 "kernel_start=0x1000000\0" \ 439 "kernel_start=0x1000000\0" \
431 "kernel_start_sd=0x8000\0" \ 440 "kernel_start_sd=0x8000\0" \
432 "kernel_load=0xa0000000\0" \ 441 "kernel_load=0xa0000000\0" \
433 "kernel_size=0x2800000\0" \ 442 "kernel_size=0x2800000\0" \
434 "kernel_size_sd=0x14000\0" \ 443 "kernel_size_sd=0x14000\0" \
435 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 444 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
436 "sf read 0x80100000 0xE00000 0x100000;" \ 445 "sf read 0x80100000 0xE00000 0x100000;" \
437 "fsl_mc start mc 0x80000000 0x80100000\0" \ 446 "fsl_mc start mc 0x80000000 0x80100000\0" \
438 "mcmemsize=0x70000000 \0" \ 447 "mcmemsize=0x70000000 \0" \
439 "BOARD=ls1088aqds\0" \ 448 "BOARD=ls1088aqds\0" \
440 "scriptaddr=0x80000000\0" \ 449 "scriptaddr=0x80000000\0" \
441 "scripthdraddr=0x80080000\0" \ 450 "scripthdraddr=0x80080000\0" \
442 BOOTENV \ 451 BOOTENV \
443 "boot_scripts=ls1088aqds_boot.scr\0" \ 452 "boot_scripts=ls1088aqds_boot.scr\0" \
444 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ 453 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
445 "scan_dev_for_boot_part=" \ 454 "scan_dev_for_boot_part=" \
446 "part list ${devtype} ${devnum} devplist; " \ 455 "part list ${devtype} ${devnum} devplist; " \
447 "env exists devplist || setenv devplist 1; " \ 456 "env exists devplist || setenv devplist 1; " \
448 "for distro_bootpart in ${devplist}; do " \ 457 "for distro_bootpart in ${devplist}; do " \
449 "if fstype ${devtype} " \ 458 "if fstype ${devtype} " \
450 "${devnum}:${distro_bootpart} " \ 459 "${devnum}:${distro_bootpart} " \
451 "bootfstype; then " \ 460 "bootfstype; then " \
452 "run scan_dev_for_boot; " \ 461 "run scan_dev_for_boot; " \
453 "fi; " \ 462 "fi; " \
454 "done\0" \ 463 "done\0" \
455 "boot_a_script=" \ 464 "boot_a_script=" \
456 "load ${devtype} ${devnum}:${distro_bootpart} " \ 465 "load ${devtype} ${devnum}:${distro_bootpart} " \
457 "${scriptaddr} ${prefix}${script}; " \ 466 "${scriptaddr} ${prefix}${script}; " \
458 "env exists secureboot && load ${devtype} " \ 467 "env exists secureboot && load ${devtype} " \
459 "${devnum}:${distro_bootpart} " \ 468 "${devnum}:${distro_bootpart} " \
460 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ 469 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
461 "env exists secureboot " \ 470 "env exists secureboot " \
462 "&& esbc_validate ${scripthdraddr};" \ 471 "&& esbc_validate ${scripthdraddr};" \
463 "source ${scriptaddr}\0" \ 472 "source ${scriptaddr}\0" \
464 "qspi_bootcmd=echo Trying load from qspi..; " \ 473 "qspi_bootcmd=echo Trying load from qspi..; " \
465 "sf probe 0:0; " \ 474 "sf probe 0:0; " \
466 "sf read 0x80001000 0xd00000 0x100000; " \ 475 "sf read 0x80001000 0xd00000 0x100000; " \
467 "fsl_mc lazyapply dpl 0x80001000 && " \ 476 "fsl_mc lazyapply dpl 0x80001000 && " \
468 "sf read $kernel_load $kernel_start " \ 477 "sf read $kernel_load $kernel_start " \
469 "$kernel_size && bootm $kernel_load#$BOARD\0" \ 478 "$kernel_size && bootm $kernel_load#$BOARD\0" \
470 "sd_bootcmd=echo Trying load from sd card..; " \ 479 "sd_bootcmd=echo Trying load from sd card..; " \
471 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ 480 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
472 "fsl_mc lazyapply dpl 0x80001000 && " \ 481 "fsl_mc lazyapply dpl 0x80001000 && " \
473 "mmc read $kernel_load $kernel_start_sd " \ 482 "mmc read $kernel_load $kernel_start_sd " \
474 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ 483 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
475 "nor_bootcmd=echo Trying load from nor..; " \ 484 "nor_bootcmd=echo Trying load from nor..; " \
476 "fsl_mc lazyapply dpl 0x580d00000 && " \ 485 "fsl_mc lazyapply dpl 0x580d00000 && " \
477 "cp.b $kernel_start $kernel_load " \ 486 "cp.b $kernel_start $kernel_load " \
478 "$kernel_size && bootm $kernel_load#$BOARD\0" 487 "$kernel_size && bootm $kernel_load#$BOARD\0"
479 #else 488 #else
480 #if defined(CONFIG_QSPI_BOOT) 489 #if defined(CONFIG_QSPI_BOOT)
481 #undef CONFIG_EXTRA_ENV_SETTINGS 490 #undef CONFIG_EXTRA_ENV_SETTINGS
482 #define CONFIG_EXTRA_ENV_SETTINGS \ 491 #define CONFIG_EXTRA_ENV_SETTINGS \
492 COMMON_ENV \
483 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 493 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
484 "loadaddr=0x90100000\0" \ 494 "loadaddr=0x90100000\0" \
485 "kernel_addr=0x100000\0" \ 495 "kernel_addr=0x100000\0" \
486 "ramdisk_addr=0x800000\0" \ 496 "ramdisk_addr=0x800000\0" \
487 "ramdisk_size=0x2000000\0" \ 497 "ramdisk_size=0x2000000\0" \
488 "fdt_high=0xa0000000\0" \ 498 "fdt_high=0xa0000000\0" \
489 "initrd_high=0xffffffffffffffff\0" \ 499 "initrd_high=0xffffffffffffffff\0" \
490 "kernel_start=0x1000000\0" \ 500 "kernel_start=0x1000000\0" \
491 "kernel_load=0xa0000000\0" \ 501 "kernel_load=0xa0000000\0" \
492 "kernel_size=0x2800000\0" \ 502 "kernel_size=0x2800000\0" \
493 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 503 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
494 "sf read 0x80100000 0xE00000 0x100000;" \ 504 "sf read 0x80100000 0xE00000 0x100000;" \
495 "fsl_mc start mc 0x80000000 0x80100000\0" \ 505 "fsl_mc start mc 0x80000000 0x80100000\0" \
496 "mcmemsize=0x70000000 \0" 506 "mcmemsize=0x70000000 \0"
497 #elif defined(CONFIG_SD_BOOT) 507 #elif defined(CONFIG_SD_BOOT)
498 #undef CONFIG_EXTRA_ENV_SETTINGS 508 #undef CONFIG_EXTRA_ENV_SETTINGS
499 #define CONFIG_EXTRA_ENV_SETTINGS \ 509 #define CONFIG_EXTRA_ENV_SETTINGS \
510 COMMON_ENV \
500 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 511 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
501 "loadaddr=0x90100000\0" \ 512 "loadaddr=0x90100000\0" \
502 "kernel_addr=0x800\0" \ 513 "kernel_addr=0x800\0" \
503 "ramdisk_addr=0x800000\0" \ 514 "ramdisk_addr=0x800000\0" \
504 "ramdisk_size=0x2000000\0" \ 515 "ramdisk_size=0x2000000\0" \
505 "fdt_high=0xa0000000\0" \ 516 "fdt_high=0xa0000000\0" \
506 "initrd_high=0xffffffffffffffff\0" \ 517 "initrd_high=0xffffffffffffffff\0" \
507 "kernel_start=0x8000\0" \ 518 "kernel_start=0x8000\0" \
508 "kernel_load=0xa0000000\0" \ 519 "kernel_load=0xa0000000\0" \
509 "kernel_size=0x14000\0" \ 520 "kernel_size=0x14000\0" \
510 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 521 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
511 "mmc read 0x80100000 0x7000 0x800;" \ 522 "mmc read 0x80100000 0x7000 0x800;" \
512 "fsl_mc start mc 0x80000000 0x80100000\0" \ 523 "fsl_mc start mc 0x80000000 0x80100000\0" \
513 "mcmemsize=0x70000000 \0" 524 "mcmemsize=0x70000000 \0"
514 #else /* NOR BOOT */ 525 #else /* NOR BOOT */
515 #undef CONFIG_EXTRA_ENV_SETTINGS 526 #undef CONFIG_EXTRA_ENV_SETTINGS
516 #define CONFIG_EXTRA_ENV_SETTINGS \ 527 #define CONFIG_EXTRA_ENV_SETTINGS \
528 COMMON_ENV \
517 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 529 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
518 "loadaddr=0x90100000\0" \ 530 "loadaddr=0x90100000\0" \
519 "kernel_addr=0x100000\0" \ 531 "kernel_addr=0x100000\0" \
520 "ramdisk_addr=0x800000\0" \ 532 "ramdisk_addr=0x800000\0" \
521 "ramdisk_size=0x2000000\0" \ 533 "ramdisk_size=0x2000000\0" \
522 "fdt_high=0xa0000000\0" \ 534 "fdt_high=0xa0000000\0" \
523 "initrd_high=0xffffffffffffffff\0" \ 535 "initrd_high=0xffffffffffffffff\0" \
524 "kernel_start=0x1000000\0" \ 536 "kernel_start=0x1000000\0" \
525 "kernel_load=0xa0000000\0" \ 537 "kernel_load=0xa0000000\0" \
526 "kernel_size=0x2800000\0" \ 538 "kernel_size=0x2800000\0" \
527 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 539 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
528 "mcmemsize=0x70000000 \0" 540 "mcmemsize=0x70000000 \0"
529 #endif 541 #endif
530 #endif /* CONFIG_TFABOOT */ 542 #endif /* CONFIG_TFABOOT */
531 #endif /* CONFIG_NXP_ESBC */ 543 #endif /* CONFIG_NXP_ESBC */
532 544
533 #ifdef CONFIG_TFABOOT 545 #ifdef CONFIG_TFABOOT
534 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 546 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
535 "env exists secureboot && esbc_halt;;" 547 "env exists secureboot && esbc_halt;;"
536 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 548 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
537 "env exists secureboot && esbc_halt;;" 549 "env exists secureboot && esbc_halt;;"
538 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 550 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
539 "env exists secureboot && esbc_halt;;" 551 "env exists secureboot && esbc_halt;;"
540 #endif 552 #endif
541 553
542 #ifdef CONFIG_FSL_MC_ENET 554 #ifdef CONFIG_FSL_MC_ENET
543 #define CONFIG_FSL_MEMAC 555 #define CONFIG_FSL_MEMAC
544 #define RGMII_PHY1_ADDR 0x1 556 #define RGMII_PHY1_ADDR 0x1
545 #define RGMII_PHY2_ADDR 0x2 557 #define RGMII_PHY2_ADDR 0x2
546 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 558 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
547 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 559 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
548 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 560 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
549 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 561 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
550 562
551 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 563 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
552 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 564 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
553 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 565 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
554 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 566 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
555 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 567 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
556 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 568 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
557 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 569 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
558 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 570 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
559 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 571 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
560 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 572 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
561 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 573 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
562 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 574 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
563 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 575 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
564 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 576 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
565 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 577 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
566 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 578 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
567 579
568 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 580 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
569 581
570 #endif 582 #endif
571 583
572 #define BOOT_TARGET_DEVICES(func) \ 584 #define BOOT_TARGET_DEVICES(func) \
573 func(USB, usb, 0) \ 585 func(USB, usb, 0) \
574 func(MMC, mmc, 0) \ 586 func(MMC, mmc, 0) \
575 func(SCSI, scsi, 0) \ 587 func(SCSI, scsi, 0) \
576 func(DHCP, dhcp, na) 588 func(DHCP, dhcp, na)
577 #include <config_distro_bootcmd.h> 589 #include <config_distro_bootcmd.h>
578 590
579 #include <asm/fsl_secure_boot.h> 591 #include <asm/fsl_secure_boot.h>
580 592
581 #endif /* __LS1088A_QDS_H */ 593 #endif /* __LS1088A_QDS_H */
582 594