Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04

* origin/ls_v2020.04: armv8: ls1028a: fix stream id allocation configs: ls1088aqds: add COMMON_ENV to fix distroboot board: fsl: ls2088ardb: Program GIC LPI configuration table

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04
* origin/ls_v2020.04: armv8: ls1028a: fix stream id allocation configs: ls1088aqds: add COMMON_ENV to fix distroboot board: fsl: ls2088ardb: Program GIC LPI configuration table
BJ DevOps Team
2 parents 7353572ff5 254a7e3ff9
Showing 3 changed files Side-by-side Diff
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
board/freescale/ls2080ardb/ls2080ardb.c
include/configs/ls1088aqds.h
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015-2020 NXP
+ * Copyright 2015-2021 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  */
@@ -103,7 +103,7 @@
 #define FSL_DPAA2_STREAM_ID_END		63
  
 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */
-#define FSL_ECAM_STREAM_ID_START	32
+#define FSL_ECAM_STREAM_ID_START	41
 #define FSL_ECAM_STREAM_ID_END		63
  
 #define FSL_SEC_STREAM_ID		64
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
  */
 #include <common.h>
 #include <env.h>
  
@@ -23,7 +23,10 @@
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
+#include <cpu_func.h>
  
+#define GIC_LPI_SIZE                             0x200000
 #ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
@@ -347,6 +350,21 @@
 }
 #endif
  
+#ifdef CONFIG_GIC_V3_ITS
+void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
+{
+	u32 phandle;
+	int err;
+	struct fdt_memory gic_lpi;
+
+	gic_lpi.start = gic_lpi_base;
+	gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
+	err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
+	if (err < 0)
+		debug("failed to add reserved memory: %d\n", err);
+}
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 void fsl_fdt_fixup_flash(void *fdt)
 {
@@ -421,6 +439,7 @@
 	u64 mc_memory_base = 0;
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
+	u64 gic_lpi_base;
  
 	ft_cpu_setup(blob, bd);
  
@@ -439,6 +458,12 @@
 	size[0] = gd->bd->bi_dram[0].size;
 	base[1] = gd->bd->bi_dram[1].start;
 	size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_GIC_V3_ITS
+	gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
+	gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
+#endif
  
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
@@ -384,10 +384,18 @@
 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  
+#define COMMON_ENV \
+	"kernelheader_addr_r=0x80200000\0"	\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"
+
 /* Initial environment variables */
 #ifdef CONFIG_NXP_ESBC
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	COMMON_ENV				\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x90100000\0"			\
 	"kernel_addr=0x100000\0"		\
@@ -419,6 +427,7 @@
  
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	COMMON_ENV				\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x90100000\0"			\
 	"kernel_addr=0x100000\0"		\
@@ -480,6 +489,7 @@
 #if defined(CONFIG_QSPI_BOOT)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	COMMON_ENV				\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x90100000\0"			\
 	"kernel_addr=0x100000\0"		\
@@ -497,6 +507,7 @@
 #elif defined(CONFIG_SD_BOOT)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS               \
+	COMMON_ENV				\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 	"loadaddr=0x90100000\0"                 \
 	"kernel_addr=0x800\0"                \
@@ -514,6 +525,7 @@
 #else	/* NOR BOOT */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	COMMON_ENV				\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x90100000\0"			\
 	"kernel_addr=0x100000\0"		\
1	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	2	/*
3		- * Copyright 2015-2020 NXP
	3	+ * Copyright 2015-2021 NXP
4	4	* Copyright 2014 Freescale Semiconductor, Inc.
5	5	*
6	6	*/
...	...	@@ -103,7 +103,7 @@
103	103	#define FSL_DPAA2_STREAM_ID_END 63
104	104
105	105	/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */
106		-#define FSL_ECAM_STREAM_ID_START 32
	106	+#define FSL_ECAM_STREAM_ID_START 41
107	107	#define FSL_ECAM_STREAM_ID_END 63
108	108
109	109	#define FSL_SEC_STREAM_ID 64
1	1	// SPDX-License-Identifier: GPL-2.0+
2	2	/*
3	3	* Copyright 2015 Freescale Semiconductor
4		- * Copyright 2017 NXP
	4	+ * Copyright 2017-2020 NXP
5	5	*/
6	6	#include <common.h>
7	7	#include <env.h>
8	8
...	...	@@ -23,7 +23,10 @@
23	23	#include <asm/arch/ppa.h>
24	24	#include <fsl_sec.h>
25	25	#include <asm/arch-fsl-layerscape/fsl_icid.h>
	26	+#include <asm/gic-v3.h>
	27	+#include <cpu_func.h>
26	28
	29	+#define GIC_LPI_SIZE 0x200000
27	30	#ifdef CONFIG_FSL_QIXIS
28	31	#include "../common/qixis.h"
29	32	#include "ls2080ardb_qixis.h"
...	...	@@ -347,6 +350,21 @@
347	350	}
348	351	#endif
349	352
	353	+#ifdef CONFIG_GIC_V3_ITS
	354	+void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
	355	+{
	356	+ u32 phandle;
	357	+ int err;
	358	+ struct fdt_memory gic_lpi;
	359	+
	360	+ gic_lpi.start = gic_lpi_base;
	361	+ gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
	362	+ err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
	363	+ if (err < 0)
	364	+ debug("failed to add reserved memory: %d\n", err);
	365	+}
	366	+#endif
	367	+
350	368	#ifdef CONFIG_OF_BOARD_SETUP
351	369	void fsl_fdt_fixup_flash(void *fdt)
352	370	{
...	...	@@ -421,6 +439,7 @@
421	439	u64 mc_memory_base = 0;
422	440	u64 mc_memory_size = 0;
423	441	u16 total_memory_banks;
	442	+ u64 gic_lpi_base;
424	443
425	444	ft_cpu_setup(blob, bd);
426	445
...	...	@@ -439,6 +458,12 @@
439	458	size[0] = gd->bd->bi_dram[0].size;
440	459	base[1] = gd->bd->bi_dram[1].start;
441	460	size[1] = gd->bd->bi_dram[1].size;
	461	+
	462	+#ifdef CONFIG_GIC_V3_ITS
	463	+ gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
	464	+ gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
	465	+ fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
	466	+#endif
442	467
443	468	#ifdef CONFIG_RESV_RAM
444	469	/* reduce size if reserved memory is within this bank */
...	...	@@ -384,10 +384,18 @@
384	384	#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
385	385	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
386	386
	387	+#define COMMON_ENV \
	388	+ "kernelheader_addr_r=0x80200000\0" \
	389	+ "fdtheader_addr_r=0x80100000\0" \
	390	+ "kernel_addr_r=0x81000000\0" \
	391	+ "fdt_addr_r=0x90000000\0" \
	392	+ "load_addr=0xa0000000\0"
	393	+
387	394	/* Initial environment variables */
388	395	#ifdef CONFIG_NXP_ESBC
389	396	#undef CONFIG_EXTRA_ENV_SETTINGS
390	397	#define CONFIG_EXTRA_ENV_SETTINGS \
	398	+ COMMON_ENV \
391	399	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
392	400	"loadaddr=0x90100000\0" \
393	401	"kernel_addr=0x100000\0" \
...	...	@@ -419,6 +427,7 @@
419	427
420	428	#undef CONFIG_EXTRA_ENV_SETTINGS
421	429	#define CONFIG_EXTRA_ENV_SETTINGS \
	430	+ COMMON_ENV \
422	431	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
423	432	"loadaddr=0x90100000\0" \
424	433	"kernel_addr=0x100000\0" \
...	...	@@ -480,6 +489,7 @@
480	489	#if defined(CONFIG_QSPI_BOOT)
481	490	#undef CONFIG_EXTRA_ENV_SETTINGS
482	491	#define CONFIG_EXTRA_ENV_SETTINGS \
	492	+ COMMON_ENV \
483	493	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
484	494	"loadaddr=0x90100000\0" \
485	495	"kernel_addr=0x100000\0" \
...	...	@@ -497,6 +507,7 @@
497	507	#elif defined(CONFIG_SD_BOOT)
498	508	#undef CONFIG_EXTRA_ENV_SETTINGS
499	509	#define CONFIG_EXTRA_ENV_SETTINGS \
	510	+ COMMON_ENV \
500	511	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
501	512	"loadaddr=0x90100000\0" \
502	513	"kernel_addr=0x800\0" \
...	...	@@ -514,6 +525,7 @@
514	525	#else /* NOR BOOT */
515	526	#undef CONFIG_EXTRA_ENV_SETTINGS
516	527	#define CONFIG_EXTRA_ENV_SETTINGS \
	528	+ COMMON_ENV \
517	529	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
518	530	"loadaddr=0x90100000\0" \
519	531	"kernel_addr=0x100000\0" \