Eric Lee / smarc-uboot

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Commit 8f86a3636ef88427f880610638e80991adc41896

Authored by Wolfgang Denk
2 parents 1ea0823786 18af1c5f0f
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 48 changed files Side-by-side Diff

... ... @@ -374,6 +374,7 @@
374 374 MPC8560ADS \
375 375 MPC8568MDS \
376 376 MPC8572DS \
  377 + MPC8572DS_36BIT \
377 378 PM854 \
378 379 PM856 \
379 380 sbc8540 \
... ... @@ -2416,8 +2416,14 @@
2416 2416 MPC8568MDS_config: unconfig
2417 2417 @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
2418 2418  
  2419 +MPC8572DS_36BIT_config \
2419 2420 MPC8572DS_config: unconfig
2420   - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
  2421 + @mkdir -p $(obj)include
  2422 + @if [ "$(findstring _36BIT_,$@)" ] ; then \
  2423 + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
  2424 + $(XECHO) "... enabling 36-bit physical addressing." ; \
  2425 + fi
  2426 + @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
2421 2427  
2422 2428 PM854_config: unconfig
2423 2429 @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
board/freescale/mpc8536ds/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -79,5 +79,11 @@
79 79 * - number of DIMMs installed
80 80 */
81 81 popts->half_strength_driver_enable = 0;
  82 +
  83 + /*
  84 + * For wake up arp feature, we need enable auto self refresh
  85 + */
  86 + popts->auto_self_refresh_en = 1;
  87 + popts->sr_it = 0x6;
82 88 }
board/freescale/mpc8536ds/law.c
Diff comments   View file @ 8f86a36
... ... @@ -30,14 +30,14 @@
30 30 struct law_entry law_table[] = {
31 31 SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
32 32 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
33   - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
  33 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
34 34 SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
35 35 SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
36 36 SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
37 37 SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
38 38 SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
39 39 SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
40   - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
  40 + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
41 41 SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
42 42 };
43 43  
board/freescale/mpc8536ds/mpc8536ds.c
Diff comments   View file @ 8f86a36
... ... @@ -192,14 +192,14 @@
192 192  
193 193 /* outbound memory */
194 194 pci_set_region(r++,
195   - CONFIG_SYS_PCIE3_MEM_BASE,
  195 + CONFIG_SYS_PCIE3_MEM_BUS,
196 196 CONFIG_SYS_PCIE3_MEM_PHYS,
197 197 CONFIG_SYS_PCIE3_MEM_SIZE,
198 198 PCI_REGION_MEM);
199 199  
200 200 /* outbound io */
201 201 pci_set_region(r++,
202   - CONFIG_SYS_PCIE3_IO_BASE,
  202 + CONFIG_SYS_PCIE3_IO_BUS,
203 203 CONFIG_SYS_PCIE3_IO_PHYS,
204 204 CONFIG_SYS_PCIE3_IO_SIZE,
205 205 PCI_REGION_IO);
206 206  
207 207  
208 208  
... ... @@ -247,22 +247,22 @@
247 247  
248 248 /* outbound memory */
249 249 pci_set_region(r++,
250   - CONFIG_SYS_PCIE1_MEM_BASE,
  250 + CONFIG_SYS_PCIE1_MEM_BUS,
251 251 CONFIG_SYS_PCIE1_MEM_PHYS,
252 252 CONFIG_SYS_PCIE1_MEM_SIZE,
253 253 PCI_REGION_MEM);
254 254  
255 255 /* outbound io */
256 256 pci_set_region(r++,
257   - CONFIG_SYS_PCIE1_IO_BASE,
  257 + CONFIG_SYS_PCIE1_IO_BUS,
258 258 CONFIG_SYS_PCIE1_IO_PHYS,
259 259 CONFIG_SYS_PCIE1_IO_SIZE,
260 260 PCI_REGION_IO);
261 261  
262   -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
  262 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
263 263 /* outbound memory */
264 264 pci_set_region(r++,
265   - CONFIG_SYS_PCIE1_MEM_BASE2,
  265 + CONFIG_SYS_PCIE1_MEM_BUS2,
266 266 CONFIG_SYS_PCIE1_MEM_PHYS2,
267 267 CONFIG_SYS_PCIE1_MEM_SIZE2,
268 268 PCI_REGION_MEM);
269 269  
270 270  
271 271  
... ... @@ -310,22 +310,22 @@
310 310  
311 311 /* outbound memory */
312 312 pci_set_region(r++,
313   - CONFIG_SYS_PCIE2_MEM_BASE,
  313 + CONFIG_SYS_PCIE2_MEM_BUS,
314 314 CONFIG_SYS_PCIE2_MEM_PHYS,
315 315 CONFIG_SYS_PCIE2_MEM_SIZE,
316 316 PCI_REGION_MEM);
317 317  
318 318 /* outbound io */
319 319 pci_set_region(r++,
320   - CONFIG_SYS_PCIE2_IO_BASE,
  320 + CONFIG_SYS_PCIE2_IO_BUS,
321 321 CONFIG_SYS_PCIE2_IO_PHYS,
322 322 CONFIG_SYS_PCIE2_IO_SIZE,
323 323 PCI_REGION_IO);
324 324  
325   -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
  325 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
326 326 /* outbound memory */
327 327 pci_set_region(r++,
328   - CONFIG_SYS_PCIE2_MEM_BASE2,
  328 + CONFIG_SYS_PCIE2_MEM_BUS2,
329 329 CONFIG_SYS_PCIE2_MEM_PHYS2,
330 330 CONFIG_SYS_PCIE2_MEM_SIZE2,
331 331 PCI_REGION_MEM);
332 332  
333 333  
334 334  
... ... @@ -378,22 +378,22 @@
378 378  
379 379 /* outbound memory */
380 380 pci_set_region(r++,
381   - CONFIG_SYS_PCI1_MEM_BASE,
  381 + CONFIG_SYS_PCI1_MEM_BUS,
382 382 CONFIG_SYS_PCI1_MEM_PHYS,
383 383 CONFIG_SYS_PCI1_MEM_SIZE,
384 384 PCI_REGION_MEM);
385 385  
386 386 /* outbound io */
387 387 pci_set_region(r++,
388   - CONFIG_SYS_PCI1_IO_BASE,
  388 + CONFIG_SYS_PCI1_IO_BUS,
389 389 CONFIG_SYS_PCI1_IO_PHYS,
390 390 CONFIG_SYS_PCI1_IO_SIZE,
391 391 PCI_REGION_IO);
392 392  
393   -#ifdef CONFIG_SYS_PCI1_MEM_BASE2
  393 +#ifdef CONFIG_SYS_PCI1_MEM_BUS2
394 394 /* outbound memory */
395 395 pci_set_region(r++,
396   - CONFIG_SYS_PCI1_MEM_BASE2,
  396 + CONFIG_SYS_PCI1_MEM_BUS2,
397 397 CONFIG_SYS_PCI1_MEM_PHYS2,
398 398 CONFIG_SYS_PCI1_MEM_SIZE2,
399 399 PCI_REGION_MEM);
... ... @@ -433,7 +433,7 @@
433 433 /* invalidate existing TLB entry for flash + promjet */
434 434 disable_tlb(flash_esel);
435 435  
436   - set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
  436 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
437 437 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
438 438 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
439 439  
board/freescale/mpc8536ds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -41,7 +41,7 @@
41 41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 42 0, 0, BOOKE_PAGESZ_4K, 0),
43 43  
44   - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
  44 + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
45 45 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
46 46 0, 0, BOOKE_PAGESZ_4K, 0),
47 47  
48 48  
49 49  
... ... @@ -53,17 +53,17 @@
53 53  
54 54 /* W**G* - Flash/promjet, localbus */
55 55 /* This will be changed to *I*G* after relocation to RAM. */
56   - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  56 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
57 57 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
58 58 0, 1, BOOKE_PAGESZ_256M, 1),
59 59  
60 60 /* *I*G* - PCI */
61   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  61 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
62 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 63 0, 2, BOOKE_PAGESZ_1G, 1),
64 64  
65 65 /* *I*G* - PCI I/O */
66   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
  66 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
67 67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 68 0, 3, BOOKE_PAGESZ_256K, 1),
69 69  
board/freescale/mpc8540ads/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -65,6 +65,9 @@
65 65 */
66 66 popts->write_data_delay = 3;
67 67  
  68 + /* 2T timing enable */
  69 + popts->twoT_en = 1;
  70 +
68 71 /*
69 72 * Factors to consider for half-strength driver enable:
70 73 * - number of DIMMs installed
board/freescale/mpc8540ads/law.c
Diff comments   View file @ 8f86a36
... ... @@ -52,7 +52,7 @@
52 52 /* This is not so much the SDRAM map as it is the whole localbus map. */
53 53 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
54 54 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
55   - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
  55 + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
56 56 };
57 57  
58 58 int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/mpc8540ads/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 * TLB 1: 256M Non-cacheable, guarded
55 55 * 0x80000000 256M PCI1 MEM First half
56 56 */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
58 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 59 0, 1, BOOKE_PAGESZ_256M, 1),
60 60  
... ... @@ -62,7 +62,7 @@
62 62 * TLB 2: 256M Non-cacheable, guarded
63 63 * 0x90000000 256M PCI1 MEM Second half
64 64 */
65   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
66 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 67 0, 2, BOOKE_PAGESZ_256M, 1),
68 68  
... ... @@ -70,7 +70,7 @@
70 70 * TLB 3: 256M Non-cacheable, guarded
71 71 * 0xc0000000 256M Rapid IO MEM First half
72 72 */
73   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
74 74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 75 0, 3, BOOKE_PAGESZ_256M, 1),
76 76  
... ... @@ -78,7 +78,7 @@
78 78 * TLB 4: 256M Non-cacheable, guarded
79 79 * 0xd0000000 256M Rapid IO MEM Second half
80 80 */
81   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
82 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 83 0, 4, BOOKE_PAGESZ_256M, 1),
84 84  
board/freescale/mpc8541cds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 * TLB 1: 256M Non-cacheable, guarded
55 55 * 0x80000000 256M PCI1 MEM First half
56 56 */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
58 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 59 0, 1, BOOKE_PAGESZ_256M, 1),
60 60  
... ... @@ -62,7 +62,7 @@
62 62 * TLB 2: 256M Non-cacheable, guarded
63 63 * 0x90000000 256M PCI1 MEM Second half
64 64 */
65   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
66 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 67 0, 2, BOOKE_PAGESZ_256M, 1),
68 68  
... ... @@ -70,7 +70,7 @@
70 70 * TLB 3: 256M Non-cacheable, guarded
71 71 * 0xa0000000 256M PCI2 MEM First half
72 72 */
73   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
74 74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 75 0, 3, BOOKE_PAGESZ_256M, 1),
76 76  
... ... @@ -78,7 +78,7 @@
78 78 * TLB 4: 256M Non-cacheable, guarded
79 79 * 0xb0000000 256M PCI2 MEM Second half
80 80 */
81   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
82 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 83 0, 4, BOOKE_PAGESZ_256M, 1),
84 84  
board/freescale/mpc8544ds/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -75,6 +75,9 @@
75 75 */
76 76 popts->write_data_delay = 3;
77 77  
  78 + /* 2T timing enable */
  79 + popts->twoT_en = 1;
  80 +
78 81 /*
79 82 * Factors to consider for half-strength driver enable:
80 83 * - number of DIMMs installed
board/freescale/mpc8544ds/mpc8544ds.c
Diff comments   View file @ 8f86a36
... ... @@ -139,22 +139,22 @@
139 139  
140 140 /* outbound memory */
141 141 pci_set_region(r++,
142   - CONFIG_SYS_PCIE3_MEM_BASE,
  142 + CONFIG_SYS_PCIE3_MEM_BUS,
143 143 CONFIG_SYS_PCIE3_MEM_PHYS,
144 144 CONFIG_SYS_PCIE3_MEM_SIZE,
145 145 PCI_REGION_MEM);
146 146  
147 147 /* outbound io */
148 148 pci_set_region(r++,
149   - CONFIG_SYS_PCIE3_IO_BASE,
  149 + CONFIG_SYS_PCIE3_IO_BUS,
150 150 CONFIG_SYS_PCIE3_IO_PHYS,
151 151 CONFIG_SYS_PCIE3_IO_SIZE,
152 152 PCI_REGION_IO);
153 153  
154   -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
  154 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
155 155 /* outbound memory */
156 156 pci_set_region(r++,
157   - CONFIG_SYS_PCIE3_MEM_BASE2,
  157 + CONFIG_SYS_PCIE3_MEM_BUS2,
158 158 CONFIG_SYS_PCIE3_MEM_PHYS2,
159 159 CONFIG_SYS_PCIE3_MEM_SIZE2,
160 160 PCI_REGION_MEM);
... ... @@ -173,7 +173,7 @@
173 173 * Activate ULI1575 legacy chip by performing a fake
174 174 * memory access. Needed to make ULI RTC work.
175 175 */
176   - in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
  176 + in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
177 177 } else {
178 178 printf (" PCIE3: disabled\n");
179 179 }
180 180  
181 181  
182 182  
... ... @@ -206,22 +206,22 @@
206 206  
207 207 /* outbound memory */
208 208 pci_set_region(r++,
209   - CONFIG_SYS_PCIE1_MEM_BASE,
  209 + CONFIG_SYS_PCIE1_MEM_BUS,
210 210 CONFIG_SYS_PCIE1_MEM_PHYS,
211 211 CONFIG_SYS_PCIE1_MEM_SIZE,
212 212 PCI_REGION_MEM);
213 213  
214 214 /* outbound io */
215 215 pci_set_region(r++,
216   - CONFIG_SYS_PCIE1_IO_BASE,
  216 + CONFIG_SYS_PCIE1_IO_BUS,
217 217 CONFIG_SYS_PCIE1_IO_PHYS,
218 218 CONFIG_SYS_PCIE1_IO_SIZE,
219 219 PCI_REGION_IO);
220 220  
221   -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
  221 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
222 222 /* outbound memory */
223 223 pci_set_region(r++,
224   - CONFIG_SYS_PCIE1_MEM_BASE2,
  224 + CONFIG_SYS_PCIE1_MEM_BUS2,
225 225 CONFIG_SYS_PCIE1_MEM_PHYS2,
226 226 CONFIG_SYS_PCIE1_MEM_SIZE2,
227 227 PCI_REGION_MEM);
228 228  
229 229  
230 230  
... ... @@ -269,22 +269,22 @@
269 269  
270 270 /* outbound memory */
271 271 pci_set_region(r++,
272   - CONFIG_SYS_PCIE2_MEM_BASE,
  272 + CONFIG_SYS_PCIE2_MEM_BUS,
273 273 CONFIG_SYS_PCIE2_MEM_PHYS,
274 274 CONFIG_SYS_PCIE2_MEM_SIZE,
275 275 PCI_REGION_MEM);
276 276  
277 277 /* outbound io */
278 278 pci_set_region(r++,
279   - CONFIG_SYS_PCIE2_IO_BASE,
  279 + CONFIG_SYS_PCIE2_IO_BUS,
280 280 CONFIG_SYS_PCIE2_IO_PHYS,
281 281 CONFIG_SYS_PCIE2_IO_SIZE,
282 282 PCI_REGION_IO);
283 283  
284   -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
  284 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
285 285 /* outbound memory */
286 286 pci_set_region(r++,
287   - CONFIG_SYS_PCIE2_MEM_BASE2,
  287 + CONFIG_SYS_PCIE2_MEM_BUS2,
288 288 CONFIG_SYS_PCIE2_MEM_PHYS2,
289 289 CONFIG_SYS_PCIE2_MEM_SIZE2,
290 290 PCI_REGION_MEM);
291 291  
292 292  
293 293  
... ... @@ -337,22 +337,22 @@
337 337  
338 338 /* outbound memory */
339 339 pci_set_region(r++,
340   - CONFIG_SYS_PCI1_MEM_BASE,
  340 + CONFIG_SYS_PCI1_MEM_BUS,
341 341 CONFIG_SYS_PCI1_MEM_PHYS,
342 342 CONFIG_SYS_PCI1_MEM_SIZE,
343 343 PCI_REGION_MEM);
344 344  
345 345 /* outbound io */
346 346 pci_set_region(r++,
347   - CONFIG_SYS_PCI1_IO_BASE,
  347 + CONFIG_SYS_PCI1_IO_BUS,
348 348 CONFIG_SYS_PCI1_IO_PHYS,
349 349 CONFIG_SYS_PCI1_IO_SIZE,
350 350 PCI_REGION_IO);
351 351  
352   -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
  352 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
353 353 /* outbound memory */
354 354 pci_set_region(r++,
355   - CONFIG_SYS_PCIE3_MEM_BASE2,
  355 + CONFIG_SYS_PCIE3_MEM_BUS2,
356 356 CONFIG_SYS_PCIE3_MEM_PHYS2,
357 357 CONFIG_SYS_PCIE3_MEM_SIZE2,
358 358 PCI_REGION_MEM);
board/freescale/mpc8544ds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -52,21 +52,21 @@
52 52 * TLB 1: 1G Non-cacheable, guarded
53 53 * 0x80000000 1G PCIE 8,9,a,b
54 54 */
55   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
  55 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
56 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 57 0, 1, BOOKE_PAGESZ_1G, 1),
58 58  
59 59 /*
60 60 * TLB 2: 256M Non-cacheable, guarded
61 61 */
62   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
  62 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
63 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 64 0, 2, BOOKE_PAGESZ_256M, 1),
65 65  
66 66 /*
67 67 * TLB 3: 256M Non-cacheable, guarded
68 68 */
69   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
  69 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
70 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 71 0, 3, BOOKE_PAGESZ_256M, 1),
72 72  
board/freescale/mpc8548cds/mpc8548cds.c
Diff comments   View file @ 8f86a36
... ... @@ -306,14 +306,14 @@
306 306  
307 307 /* outbound memory */
308 308 pci_set_region(r++,
309   - CONFIG_SYS_PCI1_MEM_BASE,
  309 + CONFIG_SYS_PCI1_MEM_BUS,
310 310 CONFIG_SYS_PCI1_MEM_PHYS,
311 311 CONFIG_SYS_PCI1_MEM_SIZE,
312 312 PCI_REGION_MEM);
313 313  
314 314 /* outbound io */
315 315 pci_set_region(r++,
316   - CONFIG_SYS_PCI1_IO_BASE,
  316 + CONFIG_SYS_PCI1_IO_BUS,
317 317 CONFIG_SYS_PCI1_IO_PHYS,
318 318 CONFIG_SYS_PCI1_IO_SIZE,
319 319 PCI_REGION_IO);
320 320  
... ... @@ -390,14 +390,14 @@
390 390  
391 391 /* outbound memory */
392 392 pci_set_region(r++,
393   - CONFIG_SYS_PCIE1_MEM_BASE,
  393 + CONFIG_SYS_PCIE1_MEM_BUS,
394 394 CONFIG_SYS_PCIE1_MEM_PHYS,
395 395 CONFIG_SYS_PCIE1_MEM_SIZE,
396 396 PCI_REGION_MEM);
397 397  
398 398 /* outbound io */
399 399 pci_set_region(r++,
400   - CONFIG_SYS_PCIE1_IO_BASE,
  400 + CONFIG_SYS_PCIE1_IO_BUS,
401 401 CONFIG_SYS_PCIE1_IO_PHYS,
402 402 CONFIG_SYS_PCIE1_IO_SIZE,
403 403 PCI_REGION_IO);
board/freescale/mpc8548cds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 * TLB 1: 1G Non-cacheable, guarded
55 55 * 0x80000000 1G PCI1/PCIE 8,9,a,b
56 56 */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
58 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 59 0, 1, BOOKE_PAGESZ_1G, 1),
60 60  
61 61  
... ... @@ -62,14 +62,14 @@
62 62 /*
63 63 * TLB 2: 256M Non-cacheable, guarded
64 64 */
65   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
66 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 67 0, 2, BOOKE_PAGESZ_256M, 1),
68 68  
69 69 /*
70 70 * TLB 3: 256M Non-cacheable, guarded
71 71 */
72   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
  72 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
73 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 74 0, 3, BOOKE_PAGESZ_256M, 1),
75 75 #endif
board/freescale/mpc8555cds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 * TLB 1: 256M Non-cacheable, guarded
55 55 * 0x80000000 256M PCI1 MEM First half
56 56 */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
58 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 59 0, 1, BOOKE_PAGESZ_256M, 1),
60 60  
... ... @@ -62,7 +62,7 @@
62 62 * TLB 2: 256M Non-cacheable, guarded
63 63 * 0x90000000 256M PCI1 MEM Second half
64 64 */
65   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
66 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 67 0, 2, BOOKE_PAGESZ_256M, 1),
68 68  
... ... @@ -70,7 +70,7 @@
70 70 * TLB 3: 256M Non-cacheable, guarded
71 71 * 0xa0000000 256M PCI2 MEM First half
72 72 */
73   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
74 74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 75 0, 3, BOOKE_PAGESZ_256M, 1),
76 76  
... ... @@ -78,7 +78,7 @@
78 78 * TLB 4: 256M Non-cacheable, guarded
79 79 * 0xb0000000 256M PCI2 MEM Second half
80 80 */
81   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
82 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 83 0, 4, BOOKE_PAGESZ_256M, 1),
84 84  
board/freescale/mpc8560ads/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -65,6 +65,9 @@
65 65 */
66 66 popts->write_data_delay = 3;
67 67  
  68 + /* 2T timing enable */
  69 + popts->twoT_en = 1;
  70 +
68 71 /*
69 72 * Factors to consider for half-strength driver enable:
70 73 * - number of DIMMs installed
board/freescale/mpc8560ads/law.c
Diff comments   View file @ 8f86a36
... ... @@ -52,7 +52,7 @@
52 52 /* This is not so much the SDRAM map as it is the whole localbus map. */
53 53 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
54 54 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
55   - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
  55 + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
56 56 };
57 57  
58 58 int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/mpc8560ads/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 * TLB 1: 256M Non-cacheable, guarded
55 55 * 0x80000000 256M PCI1 MEM First half
56 56 */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
58 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 59 0, 1, BOOKE_PAGESZ_256M, 1),
60 60  
... ... @@ -62,7 +62,7 @@
62 62 * TLB 2: 256M Non-cacheable, guarded
63 63 * 0x90000000 256M PCI1 MEM Second half
64 64 */
65   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
66 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 67 0, 2, BOOKE_PAGESZ_256M, 1),
68 68  
... ... @@ -70,7 +70,7 @@
70 70 * TLB 3: 256M Non-cacheable, guarded
71 71 * 0xc0000000 256M Rapid IO MEM First half
72 72 */
73   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
74 74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 75 0, 3, BOOKE_PAGESZ_256M, 1),
76 76  
... ... @@ -78,7 +78,7 @@
78 78 * TLB 4: 256M Non-cacheable, guarded
79 79 * 0xd0000000 256M Rapid IO MEM Second half
80 80 */
81   - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
82 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 83 0, 4, BOOKE_PAGESZ_256M, 1),
84 84  
board/freescale/mpc8568mds/law.c
Diff comments   View file @ 8f86a36
... ... @@ -54,7 +54,7 @@
54 54 SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
55 55 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
56 56 SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
57   - SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
  57 + SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
58 58 /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
59 59 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
60 60 };
board/freescale/mpc8568mds/mpc8568mds.c
Diff comments   View file @ 8f86a36
... ... @@ -397,14 +397,14 @@
397 397  
398 398 /* outbound memory */
399 399 pci_set_region(r++,
400   - CONFIG_SYS_PCI1_MEM_BASE,
  400 + CONFIG_SYS_PCI1_MEM_BUS,
401 401 CONFIG_SYS_PCI1_MEM_PHYS,
402 402 CONFIG_SYS_PCI1_MEM_SIZE,
403 403 PCI_REGION_MEM);
404 404  
405 405 /* outbound io */
406 406 pci_set_region(r++,
407   - CONFIG_SYS_PCI1_IO_BASE,
  407 + CONFIG_SYS_PCI1_IO_BUS,
408 408 CONFIG_SYS_PCI1_IO_PHYS,
409 409 CONFIG_SYS_PCI1_IO_SIZE,
410 410 PCI_REGION_IO);
411 411  
... ... @@ -450,14 +450,14 @@
450 450  
451 451 /* outbound memory */
452 452 pci_set_region(r++,
453   - CONFIG_SYS_PCIE1_MEM_BASE,
  453 + CONFIG_SYS_PCIE1_MEM_BUS,
454 454 CONFIG_SYS_PCIE1_MEM_PHYS,
455 455 CONFIG_SYS_PCIE1_MEM_SIZE,
456 456 PCI_REGION_MEM);
457 457  
458 458 /* outbound io */
459 459 pci_set_region(r++,
460   - CONFIG_SYS_PCIE1_IO_BASE,
  460 + CONFIG_SYS_PCIE1_IO_BUS,
461 461 CONFIG_SYS_PCIE1_IO_PHYS,
462 462 CONFIG_SYS_PCIE1_IO_SIZE,
463 463 PCI_REGION_IO);
board/freescale/mpc8568mds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -64,7 +64,7 @@
64 64 * 0x80000000 512M PCI1 MEM
65 65 * 0xa0000000 512M PCIe MEM
66 66 */
67   - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  67 + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
68 68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 69 0, 2, BOOKE_PAGESZ_1G, 1),
70 70  
board/freescale/mpc8572ds/law.c
Diff comments   View file @ 8f86a36
... ... @@ -28,14 +28,14 @@
28 28 #include <asm/mmu.h>
29 29  
30 30 struct law_entry law_table[] = {
31   - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
  31 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
32 32 SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
33 33 SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
34 34 SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
35 35 SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
36 36 SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
37 37 SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
38   - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
  38 + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
39 39 SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
40 40 };
41 41  
board/freescale/mpc8572ds/mpc8572ds.c
Diff comments   View file @ 8f86a36
... ... @@ -185,14 +185,14 @@
185 185  
186 186 /* outbound memory */
187 187 pci_set_region(r++,
188   - CONFIG_SYS_PCIE3_MEM_BASE,
  188 + CONFIG_SYS_PCIE3_MEM_BUS,
189 189 CONFIG_SYS_PCIE3_MEM_PHYS,
190 190 CONFIG_SYS_PCIE3_MEM_SIZE,
191 191 PCI_REGION_MEM);
192 192  
193 193 /* outbound io */
194 194 pci_set_region(r++,
195   - CONFIG_SYS_PCIE3_IO_BASE,
  195 + CONFIG_SYS_PCIE3_IO_BUS,
196 196 CONFIG_SYS_PCIE3_IO_PHYS,
197 197 CONFIG_SYS_PCIE3_IO_SIZE,
198 198 PCI_REGION_IO);
... ... @@ -215,7 +215,7 @@
215 215  
216 216 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
217 217 PCI_BASE_ADDRESS_1, &temp32);
218   - if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
  218 + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
219 219 debug(" uli1572 read to %x\n", temp32);
220 220 in_be32((unsigned *)temp32);
221 221 }
222 222  
... ... @@ -252,14 +252,14 @@
252 252  
253 253 /* outbound memory */
254 254 pci_set_region(r++,
255   - CONFIG_SYS_PCIE2_MEM_BASE,
  255 + CONFIG_SYS_PCIE2_MEM_BUS,
256 256 CONFIG_SYS_PCIE2_MEM_PHYS,
257 257 CONFIG_SYS_PCIE2_MEM_SIZE,
258 258 PCI_REGION_MEM);
259 259  
260 260 /* outbound io */
261 261 pci_set_region(r++,
262   - CONFIG_SYS_PCIE2_IO_BASE,
  262 + CONFIG_SYS_PCIE2_IO_BUS,
263 263 CONFIG_SYS_PCIE2_IO_PHYS,
264 264 CONFIG_SYS_PCIE2_IO_SIZE,
265 265 PCI_REGION_IO);
266 266  
... ... @@ -307,14 +307,14 @@
307 307  
308 308 /* outbound memory */
309 309 pci_set_region(r++,
310   - CONFIG_SYS_PCIE1_MEM_BASE,
  310 + CONFIG_SYS_PCIE1_MEM_BUS,
311 311 CONFIG_SYS_PCIE1_MEM_PHYS,
312 312 CONFIG_SYS_PCIE1_MEM_SIZE,
313 313 PCI_REGION_MEM);
314 314  
315 315 /* outbound io */
316 316 pci_set_region(r++,
317   - CONFIG_SYS_PCIE1_IO_BASE,
  317 + CONFIG_SYS_PCIE1_IO_BUS,
318 318 CONFIG_SYS_PCIE1_IO_PHYS,
319 319 CONFIG_SYS_PCIE1_IO_SIZE,
320 320 PCI_REGION_IO);
... ... @@ -358,7 +358,7 @@
358 358 /* invalidate existing TLB entry for flash + promjet */
359 359 disable_tlb(flash_esel);
360 360  
361   - set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
  361 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
362 362 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
363 363 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
364 364  
board/freescale/mpc8572ds/tlb.c
Diff comments   View file @ 8f86a36
... ... @@ -54,26 +54,26 @@
54 54  
55 55 /* W**G* - Flash/promjet, localbus */
56 56 /* This will be changed to *I*G* after relocation to RAM. */
57   - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  57 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
58 58 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
59 59 0, 2, BOOKE_PAGESZ_256M, 1),
60 60  
61 61 /* *I*G* - PCI */
62   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
  62 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
63 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 64 0, 3, BOOKE_PAGESZ_1G, 1),
65 65  
66 66 /* *I*G* - PCI */
67   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  67 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
68 68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 69 0, 4, BOOKE_PAGESZ_256M, 1),
70 70  
71   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  71 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
72 72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 73 0, 5, BOOKE_PAGESZ_256M, 1),
74 74  
75 75 /* *I*G* - PCI I/O */
76   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
  76 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
77 77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
78 78 0, 6, BOOKE_PAGESZ_256K, 1),
79 79  
... ... @@ -82,7 +82,7 @@
82 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 83 0, 7, BOOKE_PAGESZ_1M, 1),
84 84  
85   - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
  85 + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
86 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 87 0, 8, BOOKE_PAGESZ_4K, 1),
88 88 };
board/freescale/mpc8610hpcd/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -74,6 +74,9 @@
74 74 */
75 75 popts->write_data_delay = 3;
76 76  
  77 + /* 2T timing enable */
  78 + popts->twoT_en = 1;
  79 +
77 80 /*
78 81 * Factors to consider for half-strength driver enable:
79 82 * - number of DIMMs installed
board/freescale/mpc8641hpcn/ddr.c
Diff comments   View file @ 8f86a36
... ... @@ -162,5 +162,7 @@
162 162 }
163 163 }
164 164  
  165 + /* 2T timing enable */
  166 + popts->twoT_en = 1;
165 167 }
... ... @@ -65,6 +65,9 @@
65 65 */
66 66 popts->write_data_delay = 3;
67 67  
  68 + /* 2T timing enable */
  69 + popts->twoT_en = 1;
  70 +
68 71 /*
69 72 * Factors to consider for half-strength driver enable:
70 73 * - number of DIMMs installed
... ... @@ -65,6 +65,9 @@
65 65 */
66 66 popts->write_data_delay = 3;
67 67  
  68 + /* 2T timing enable */
  69 + popts->twoT_en = 1;
  70 +
68 71 /*
69 72 * Factors to consider for half-strength driver enable:
70 73 * - number of DIMMs installed
... ... @@ -90,6 +90,7 @@
90 90 #else
91 91 u32 ddr_ratio = 0;
92 92 #endif
  93 + int i;
93 94  
94 95 svr = get_svr();
95 96 ver = SVR_SOC_VER(svr);
... ... @@ -141,8 +142,10 @@
141 142  
142 143 get_sys_info(&sysinfo);
143 144  
144   - puts("Clock Configuration:\n");
145   - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
  145 + puts("Clock Configuration:\n ");
  146 + for (i = 0; i < CONFIG_NUM_CPUS; i++)
  147 + printf("CPU%d:%-4s MHz, ",
  148 + i,strmhz(buf1, sysinfo.freqProcessor[i]));
146 149 printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
147 150  
148 151 switch (ddr_ratio) {
... ... @@ -213,6 +213,10 @@
213 213  
214 214 void ft_cpu_setup(void *blob, bd_t *bd)
215 215 {
  216 + int off;
  217 + int val;
  218 + sys_info_t sysinfo;
  219 +
216 220 /* delete crypto node if not on an E-processor */
217 221 if (!IS_E_PROCESSOR(get_svr()))
218 222 fdt_fixup_crypto_node(blob, 0);
... ... @@ -228,8 +232,15 @@
228 232 "timebase-frequency", bd->bi_busfreq / 8, 1);
229 233 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
230 234 "bus-frequency", bd->bi_busfreq, 1);
231   - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
232   - "clock-frequency", bd->bi_intfreq, 1);
  235 + get_sys_info(&sysinfo);
  236 + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  237 + while (off != -FDT_ERR_NOTFOUND) {
  238 + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  239 + val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
  240 + fdt_setprop(blob, off, "clock-frequency", &val, 4);
  241 + off = fdt_node_offset_by_prop_value(blob, off, "device_type",
  242 + "cpu", 4);
  243 + }
233 244 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
234 245 "bus-frequency", bd->bi_busfreq, 1);
235 246  
... ... @@ -31,6 +31,22 @@
31 31  
32 32 #if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
33 33  
  34 +#ifndef CONFIG_SYS_PCI1_MEM_BUS
  35 +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
  36 +#endif
  37 +
  38 +#ifndef CONFIG_SYS_PCI1_IO_BUS
  39 +#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
  40 +#endif
  41 +
  42 +#ifndef CONFIG_SYS_PCI2_MEM_BUS
  43 +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
  44 +#endif
  45 +
  46 +#ifndef CONFIG_SYS_PCI2_IO_BUS
  47 +#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
  48 +#endif
  49 +
34 50 static struct pci_controller *pci_hose;
35 51  
36 52 void
37 53  
... ... @@ -80,14 +96,14 @@
80 96 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
81 97 }
82 98  
83   - pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
  99 + pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
84 100 pcix->potear1 = 0x00000000;
85 101 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
86 102 pcix->powbear1 = 0x00000000;
87 103 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
88 104 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
89 105  
90   - pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
  106 + pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
91 107 pcix->potear2 = 0x00000000;
92 108 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
93 109 pcix->powbear2 = 0x00000000;
94 110  
... ... @@ -105,13 +121,13 @@
105 121 pcix->piwar3 = 0;
106 122  
107 123 pci_set_region(hose->regions + 0,
108   - CONFIG_SYS_PCI1_MEM_BASE,
  124 + CONFIG_SYS_PCI1_MEM_BUS,
109 125 CONFIG_SYS_PCI1_MEM_PHYS,
110 126 CONFIG_SYS_PCI1_MEM_SIZE,
111 127 PCI_REGION_MEM);
112 128  
113 129 pci_set_region(hose->regions + 1,
114   - CONFIG_SYS_PCI1_IO_BASE,
  130 + CONFIG_SYS_PCI1_IO_BUS,
115 131 CONFIG_SYS_PCI1_IO_PHYS,
116 132 CONFIG_SYS_PCI1_IO_SIZE,
117 133 PCI_REGION_IO);
118 134  
... ... @@ -165,14 +181,14 @@
165 181 */
166 182 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
167 183  
168   - pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
  184 + pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
169 185 pcix2->potear1 = 0x00000000;
170 186 pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
171 187 pcix2->powbear1 = 0x00000000;
172 188 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
173 189 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
174 190  
175   - pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
  191 + pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
176 192 pcix2->potear2 = 0x00000000;
177 193 pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
178 194 pcix2->powbear2 = 0x00000000;
179 195  
... ... @@ -190,13 +206,13 @@
190 206 pcix2->piwar3 = 0;
191 207  
192 208 pci_set_region(hose->regions + 0,
193   - CONFIG_SYS_PCI2_MEM_BASE,
  209 + CONFIG_SYS_PCI2_MEM_BUS,
194 210 CONFIG_SYS_PCI2_MEM_PHYS,
195 211 CONFIG_SYS_PCI2_MEM_SIZE,
196 212 PCI_REGION_MEM);
197 213  
198 214 pci_set_region(hose->regions + 1,
199   - CONFIG_SYS_PCI2_IO_BASE,
  215 + CONFIG_SYS_PCI2_IO_BUS,
200 216 CONFIG_SYS_PCI2_IO_PHYS,
201 217 CONFIG_SYS_PCI2_IO_SIZE,
202 218 PCI_REGION_IO);
... ... @@ -39,17 +39,19 @@
39 39 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 40 uint plat_ratio,e500_ratio,half_freqSystemBus;
41 41 uint lcrr_div;
  42 + int i;
42 43  
43 44 plat_ratio = (gur->porpllsr) & 0x0000003e;
44 45 plat_ratio >>= 1;
45 46 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
46   - e500_ratio = (gur->porpllsr) & 0x003f0000;
47   - e500_ratio >>= 16;
48 47  
49 48 /* Divide before multiply to avoid integer
50 49 * overflow for processor speeds above 2GHz */
51 50 half_freqSystemBus = sysInfo->freqSystemBus/2;
52   - sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
  51 + for (i = 0; i < CONFIG_NUM_CPUS; i++) {
  52 + e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
  53 + sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
  54 + }
53 55  
54 56 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
55 57 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
... ... @@ -105,7 +107,7 @@
105 107 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
106 108 #endif
107 109 get_sys_info (&sys_info);
108   - gd->cpu_clk = sys_info.freqProcessor;
  110 + gd->cpu_clk = sys_info.freqProcessor[0];
109 111 gd->bus_clk = sys_info.freqSystemBus;
110 112 gd->mem_clk = sys_info.freqDDRBus;
111 113 gd->lbc_clk = sys_info.freqLocalBus;
cpu/mpc8xxx/ddr/ctrl_regs.c
Diff comments   View file @ 8f86a36
... ... @@ -167,7 +167,7 @@
167 167 | ((trrt_mclk & 0x3) << 26) /* RRT */
168 168 | ((twwt_mclk & 0x3) << 24) /* WWT */
169 169 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
170   - | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */
  170 + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
171 171 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
172 172 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
173 173 );
174 174  
... ... @@ -185,10 +185,14 @@
185 185 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
186 186 unsigned int cntl_adj = 0; /* Control Adjust */
187 187  
  188 + /* If the tRAS > 19 MCLK, we use the ext mode */
  189 + if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
  190 + ext_acttopre = 1;
  191 +
188 192 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
189 193 ddr->timing_cfg_3 = (0
190 194 | ((ext_acttopre & 0x1) << 24)
191   - | ((ext_refrec & 0x7) << 16)
  195 + | ((ext_refrec & 0xF) << 16)
192 196 | ((ext_caslat & 0x1) << 12)
193 197 | ((cntl_adj & 0x7) << 0)
194 198 );
195 199  
196 200  
... ... @@ -251,12 +255,12 @@
251 255 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
252 256  
253 257 ddr->timing_cfg_1 = (0
254   - | ((pretoact_mclk & 0x07) << 28)
  258 + | ((pretoact_mclk & 0x0F) << 28)
255 259 | ((acttopre_mclk & 0x0F) << 24)
256   - | ((acttorw_mclk & 0x7) << 20)
  260 + | ((acttorw_mclk & 0xF) << 20)
257 261 | ((caslat_ctrl & 0xF) << 16)
258 262 | ((refrec_ctrl & 0xF) << 12)
259   - | ((wrrec_mclk & 0x07) << 8)
  263 + | ((wrrec_mclk & 0x0F) << 8)
260 264 | ((acttoact_mclk & 0x07) << 4)
261 265 | ((wrtord_mclk & 0x07) << 0)
262 266 );
263 267  
264 268  
... ... @@ -309,13 +313,13 @@
309 313 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
310 314  
311 315 ddr->timing_cfg_2 = (0
312   - | ((add_lat_mclk & 0x7) << 28)
  316 + | ((add_lat_mclk & 0xf) << 28)
313 317 | ((cpo & 0x1f) << 23)
314   - | ((wr_lat & 0x7) << 19)
  318 + | ((wr_lat & 0xf) << 19)
315 319 | ((rd_to_pre & 0x7) << 13)
316 320 | ((wr_data_delay & 0x7) << 10)
317 321 | ((cke_pls & 0x7) << 6)
318   - | ((four_act & 0x1f) << 0)
  322 + | ((four_act & 0x3f) << 0)
319 323 );
320 324 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
321 325 }
... ... @@ -332,7 +336,7 @@
332 336 unsigned int sdram_type; /* Type of SDRAM */
333 337 unsigned int dyn_pwr; /* Dynamic power management mode */
334 338 unsigned int dbw; /* DRAM dta bus width */
335   - unsigned int eight_be; /* 8-beat burst enable */
  339 + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
336 340 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
337 341 unsigned int threeT_en; /* Enable 3T timing */
338 342 unsigned int twoT_en; /* Enable 2T timing */
... ... @@ -359,7 +363,9 @@
359 363  
360 364 dyn_pwr = popts->dynamic_power;
361 365 dbw = popts->data_bus_width;
362   - eight_be = 0; /* always 0 for DDR2 */
  366 + /* DDR3 must use 8-beat bursts when using 32-bit bus mode */
  367 + if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1))
  368 + eight_be = 1;
363 369 threeT_en = popts->threeT_en;
364 370 twoT_en = popts->twoT_en;
365 371 ba_intlv_ctl = popts->ba_intlv_ctl;
... ... @@ -691,10 +697,10 @@
691 697 unsigned int wodt_off = 0; /* Write to ODT off */
692 698  
693 699 ddr->timing_cfg_5 = (0
694   - | ((rodt_on & 0xf) << 24)
695   - | ((rodt_off & 0xf) << 20)
696   - | ((wodt_on & 0xf) << 12)
697   - | ((wodt_off & 0xf) << 8)
  700 + | ((rodt_on & 0x1f) << 24)
  701 + | ((rodt_off & 0x7) << 20)
  702 + | ((wodt_on & 0x1f) << 12)
  703 + | ((wodt_off & 0x7) << 8)
698 704 );
699 705 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
700 706 }
701 707  
702 708  
... ... @@ -744,15 +750,14 @@
744 750 | ((wrlvl_dqsen & 0x7) << 16)
745 751 | ((wrlvl_smpl & 0xf) << 12)
746 752 | ((wrlvl_wlr & 0x7) << 8)
747   - | ((wrlvl_start & 0xF) << 0)
  753 + | ((wrlvl_start & 0x1F) << 0)
748 754 );
749 755 }
750 756  
751 757 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
752   -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
  758 +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
753 759 {
754   - unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
755   -
  760 + /* Self Refresh Idle Threshold */
756 761 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
757 762 }
758 763  
... ... @@ -855,6 +860,7 @@
855 860 unsigned int i;
856 861 unsigned int cas_latency;
857 862 unsigned int additive_latency;
  863 + unsigned int sr_it;
858 864  
859 865 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
860 866  
... ... @@ -876,6 +882,10 @@
876 882 ? popts->additive_latency_override_value
877 883 : common_dimm->additive_latency;
878 884  
  885 + sr_it = (popts->auto_self_refresh_en)
  886 + ? popts->sr_it
  887 + : 0;
  888 +
879 889 /* Chip Select Memory Bounds (CSn_BNDS) */
880 890 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
881 891 phys_size_t sa = 0;
... ... @@ -1036,7 +1046,7 @@
1036 1046 set_ddr_wrlvl_cntl(ddr);
1037 1047  
1038 1048 set_ddr_pd_cntl(ddr);
1039   - set_ddr_sr_cntr(ddr);
  1049 + set_ddr_sr_cntr(ddr, sr_it);
1040 1050  
1041 1051 set_ddr_sdram_rcw_1(ddr);
1042 1052 set_ddr_sdram_rcw_2(ddr);
cpu/mpc8xxx/ddr/options.c
Diff comments   View file @ 8f86a36
... ... @@ -142,7 +142,7 @@
142 142 * - number of components, number of active ranks
143 143 * - how much time you want to spend playing around
144 144 */
145   - popts->twoT_en = 1;
  145 + popts->twoT_en = 0;
146 146 popts->threeT_en = 0;
147 147  
148 148 /*
doc/README.mpc8572ds
Diff comments   View file @ 8f86a36
  1 +Overview
  2 +--------
  3 +MPC8572DS is a high-performance computing, evaluation and development platform
  4 +supporting the mpc8572 PowerTM processor.
  5 +
  6 +Building U-boot
  7 +-----------
  8 + make MPC8572DS_config
  9 + make
  10 +
  11 +Flash Banks
  12 +-----------
  13 +MPC8572DS board has two flash banks. They are both present on boot, but their
  14 +locations can be swapped using the dip-switch SW9[1:2].
  15 +
  16 +Booting is always from the boot bank at 0xec00_0000.
  17 +
  18 +
  19 +Memory Map
  20 +----------
  21 +
  22 +0xe800_0000 - 0xebff_ffff Alernate bank 64MB
  23 +0xec00_0000 - 0xefff_ffff Boot bank 64MB
  24 +
  25 +0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
  26 +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
  27 +
  28 +
  29 +Flashing Images
  30 +---------------
  31 +
  32 +To place a new u-boot image in the alternate flash bank and then reset with that
  33 + new image temporarily, use this:
  34 +
  35 + tftp 1000000 u-boot.bin
  36 + erase ebf80000 ebffffff
  37 + cp.b 1000000 ebf80000 80000
  38 + pixis_reset altbank
  39 +
  40 +
  41 +To program the image in the boot flash bank:
  42 +
  43 + tftp 1000000 u-boot.bin
  44 + protect off all
  45 + erase eff80000 ffffffff
  46 + cp.b 1000000 eff80000 80000
  47 +
  48 +
  49 +The pixis_reset command
  50 +-----------------------
  51 +The command - "pixis_reset", is introduced to reset mpc8572ds board
  52 +using the FPGA sequencer. When the board restarts, it has the option
  53 +of using either the current or alternate flash bank as the boot
  54 +image, with or without the watchdog timer enabled, and finally with
  55 +or without frequency changes.
  56 +
  57 +Usage is;
  58 +
  59 + pixis_reset
  60 + pixis_reset altbank
  61 + pixis_reset altbank wd
  62 + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
  63 + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
  64 +
  65 +Examples:
  66 +
  67 + /* reset to current bank, like "reset" command */
  68 + pixis_reset
  69 +
  70 + /* reset board but use the to alternate flash bank */
  71 + pixis_reset altbank
  72 +
  73 +
  74 +Using the Device Tree Source File
  75 +---------------------------------
  76 +To create the DTB (Device Tree Binary) image file,
  77 +use a command similar to this:
  78 +
  79 + dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
  80 +
  81 +Likely, that .dts file will come from here;
  82 +
  83 + linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
  84 +
  85 +
  86 +Booting Linux
  87 +-------------
  88 +
  89 +Place a linux uImage in the TFTP disk area.
  90 +
  91 + tftp 1000000 uImage.8572
  92 + tftp c00000 mpc8572ds.dtb
  93 + bootm 1000000 - c00000
  94 +
  95 +
  96 +Implementing AMP(Asymmetric MultiProcessing)
  97 +-------------
  98 +1. Build kernel image for core0:
  99 +
  100 + a. $ make 85xx/mpc8572_ds_defconfig
  101 +
  102 + b. $ make menuconfig
  103 + - un-select "Processor support"->"Symetric multi-processing support"
  104 +
  105 + c. $ make uImage
  106 +
  107 + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
  108 +
  109 +2. Build kernel image for core1:
  110 +
  111 + a. $ make 85xx/mpc8572_ds_defconfig
  112 +
  113 + b. $ make menuconfig
  114 + - Un-select "Processor support"->"Symetric multi-processing support"
  115 + - Select "Advanced setup" -> " Prompt for advanced kernel
  116 + configuration options"
  117 + - Select "Set physical address where the kernel is loaded" and
  118 + set it to 0x20000000, asssuming core1 will start from 512MB.
  119 + - Select "Set custom page offset address"
  120 + - Select "Set custom kernel base address"
  121 + - Select "Set maximum low memory"
  122 + - "Exit" and save the selection.
  123 +
  124 + c. $ make uImage
  125 +
  126 + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
  127 +
  128 +3. Create dtb for core0:
  129 +
  130 + $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
  131 +
  132 +4. Create dtb for core1:
  133 +
  134 + $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
  135 +
  136 +5. Bring up two cores separately:
  137 +
  138 + a. Power on the board, under u-boot prompt:
  139 + => setenv <serverip>
  140 + => setenv <ipaddr>
  141 + => setenv bootargs root=/dev/ram rw console=ttyS0,115200
  142 + b. Bring up core1's kernel first:
  143 + => setenv bootm_low 0x20000000
  144 + => setenv bootm_size 0x10000000
  145 + => tftp 21000000 8572/uImage.core1
  146 + => tftp 22000000 8572/ramdiskfile
  147 + => tftp 20c00000 8572/mpc8572ds_core1.dtb
  148 + => interrupts off
  149 + => bootm start 21000000 22000000 20c00000
  150 + => bootm loados
  151 + => bootm ramdisk
  152 + => bootm fdt
  153 + => fdt boardsetup
  154 + => fdt chosen $initrd_start $initrd_end
  155 + => bootm prep
  156 + => cpu 1 release $bootm_low - $fdtaddr -
  157 + c. Bring up core0's kernel(on the same u-boot console):
  158 + => setenv bootm_low 0
  159 + => setenv bootm_size 0x20000000
  160 + => tftp 1000000 8572/uImage.core0
  161 + => tftp 2000000 8572/ramdiskfile
  162 + => tftp c00000 8572/mpc8572ds_core0.dtb
  163 + => bootm 1000000 2000000 c00000
  164 +
  165 +Please note only core0 will run u-boot, core1 starts kernel directly after
  166 +"cpu release" command is issued.
include/asm-ppc/fsl_ddr_sdram.h
Diff comments   View file @ 8f86a36
... ... @@ -34,7 +34,10 @@
34 34 #elif defined(CONFIG_FSL_DDR3)
35 35 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
36 36 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
  37 +#ifndef CONFIG_FSL_SDRAM_TYPE
  38 +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
37 39 #endif
  40 +#endif /* #if defined(CONFIG_FSL_DDR1) */
38 41  
39 42 /* define bank(chip select) interleaving mode */
40 43 #define FSL_DDR_CS0_CS1 0x40
... ... @@ -143,6 +146,10 @@
143 146 unsigned int bstopre;
144 147 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
145 148 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
  149 +
  150 + /* Automatic self refresh */
  151 + unsigned int auto_self_refresh_en;
  152 + unsigned int sr_it;
146 153 } memctl_options_t;
147 154  
148 155 extern phys_size_t fsl_ddr_sdram(void);
include/asm-ppc/fsl_lbc.h
Diff comments   View file @ 8f86a36
... ... @@ -28,6 +28,8 @@
28 28  
29 29 #define BR_BA 0xFFFF8000
30 30 #define BR_BA_SHIFT 15
  31 +#define BR_XBA 0x00006000
  32 +#define BR_XBA_SHIFT 13
31 33 #define BR_PS 0x00001800
32 34 #define BR_PS_SHIFT 11
33 35 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
... ... @@ -70,7 +72,7 @@
70 72 #endif
71 73  
72 74 /* Convert an address into the right format for the BR registers */
73   -#ifdef CONFIG_PHYS_64BIT
  75 +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
74 76 #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
75 77 ((x & 0x300000000ULL) >> 19)))
76 78 #else
... ... @@ -90,6 +92,8 @@
90 92  
91 93 #define OR_GPCM_AM 0xFFFF8000
92 94 #define OR_GPCM_AM_SHIFT 15
  95 +#define OR_GPCM_XAM 0x00006000
  96 +#define OR_GPCM_XAM_SHIFT 13
93 97 #define OR_GPCM_BCTLD 0x00001000
94 98 #define OR_GPCM_BCTLD_SHIFT 12
95 99 #define OR_GPCM_CSNT 0x00000800
... ... @@ -132,6 +136,8 @@
132 136  
133 137 #define OR_FCM_AM 0xFFFF8000
134 138 #define OR_FCM_AM_SHIFT 15
  139 +#define OR_FCM_XAM 0x00006000
  140 +#define OR_FCM_XAM_SHIFT 13
135 141 #define OR_FCM_BCTLD 0x00001000
136 142 #define OR_FCM_BCTLD_SHIFT 12
137 143 #define OR_FCM_PGS 0x00000400
include/configs/MPC8536DS.h
Diff comments   View file @ 8f86a36
... ... @@ -34,6 +34,7 @@
34 34 #define CONFIG_MPC8536 1
35 35 #define CONFIG_MPC8536DS 1
36 36  
  37 +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
37 38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
38 39 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
39 40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40 41  
41 42  
... ... @@ -166,12 +167,13 @@
166 167 * Local Bus Definitions
167 168 */
168 169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  170 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169 171  
170   -#define CONFIG_SYS_BR0_PRELIM 0xe8001001
171   -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
  172 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
  173 +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
172 174  
173   -#define CONFIG_SYS_BR1_PRELIM 0xe0001001
174   -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  175 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  176 +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
175 177  
176 178 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
177 179 #define CONFIG_SYS_FLASH_QUIET_TEST
178 180  
... ... @@ -194,8 +196,9 @@
194 196  
195 197 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
196 198 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  199 +#define PIXIS_BASE_PHYS PIXIS_BASE
197 200  
198   -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
  201 +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
199 202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
200 203  
201 204 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
... ... @@ -254,7 +257,7 @@
254 257 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
255 258  
256 259 /* NAND flash config */
257   -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  260 +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
258 261 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
259 262 | BR_PS_8 /* Port Size = 8 bit */ \
260 263 | BR_MS_FCM /* MSEL = FCM */ \
261 264  
262 265  
... ... @@ -271,20 +274,20 @@
271 274 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
272 275 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
273 276  
274   -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
  277 +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
275 278 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
276 279 | BR_PS_8 /* Port Size = 8 bit */ \
277 280 | BR_MS_FCM /* MSEL = FCM */ \
278 281 | BR_V) /* valid */
279 282 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
280   -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
  283 +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
281 284 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
282 285 | BR_PS_8 /* Port Size = 8 bit */ \
283 286 | BR_MS_FCM /* MSEL = FCM */ \
284 287 | BR_V) /* valid */
285 288 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
286 289  
287   -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
  290 +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
288 291 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
289 292 | BR_PS_8 /* Port Size = 8 bit */ \
290 293 | BR_MS_FCM /* MSEL = FCM */ \
291 294  
292 295  
293 296  
294 297  
295 298  
296 299  
297 300  
... ... @@ -355,34 +358,42 @@
355 358 * Memory space is mapped 1-1, but I/O space must start from 0.
356 359 */
357 360  
358   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
359   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  361 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  362 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  363 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
360 364 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
361   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  365 +#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
  366 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
362 367 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
363 368 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
364 369  
365 370 /* controller 1, Slot 1, tgtid 1, Base address a000 */
366   -#define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000
367   -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  371 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  372 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  373 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
368 374 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
369   -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  375 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
  376 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
370 377 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
371 378 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
372 379  
373 380 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
374   -#define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000
375   -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
  381 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
  382 +#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
  383 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
376 384 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
377   -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  385 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
  386 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
378 387 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
379 388 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
380 389  
381 390 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
382   -#define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000
383   -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
  391 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  392 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  393 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
384 394 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
385   -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
  395 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
  396 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
386 397 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
387 398 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
388 399  
389 400  
... ... @@ -392,10 +403,10 @@
392 403 #define CONFIG_PCI_PNP /* do pci plug-and-play */
393 404  
394 405 /*PCIE video card used*/
395   -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS
  406 +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
396 407  
397 408 /*PCI video card used*/
398   -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
  409 +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
399 410  
400 411 /* video */
401 412 #define CONFIG_VIDEO
... ... @@ -408,7 +419,7 @@
408 419 #define CONFIG_ATI_RADEON_FB
409 420 #define CONFIG_VIDEO_LOGO
410 421 /*#define CONFIG_CONSOLE_CURSOR*/
411   -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS
  422 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
412 423 #endif
413 424  
414 425 #undef CONFIG_EEPRO100
... ... @@ -422,8 +433,8 @@
422 433 #endif
423 434  
424 435 #ifndef CONFIG_PCI_PNP
425   - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
426   - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
  436 + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  437 + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
427 438 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
428 439 #endif
429 440  
include/configs/MPC8540ADS.h
Diff comments   View file @ 8f86a36
... ... @@ -308,18 +308,21 @@
308 308 #define CONFIG_SYS_I2C_OFFSET 0x3000
309 309  
310 310 /* RapidIO MMU */
311   -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
312   -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
  311 +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  312 +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  313 +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
313 314 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
314 315  
315 316 /*
316 317 * General PCI
317 318 * Memory space is mapped 1-1, but I/O space must start from 0.
318 319 */
319   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
320   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  320 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  321 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  322 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
321 323 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
322   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  324 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  325 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
323 326 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
324 327 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
325 328  
include/configs/MPC8541CDS.h
Diff comments   View file @ 8f86a36
... ... @@ -341,17 +341,21 @@
341 341 * General PCI
342 342 * Memory space is mapped 1-1, but I/O space must start from 0.
343 343 */
344   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
345   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  344 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  345 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  346 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
346 347 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
347   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  348 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  349 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
348 350 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
349 351 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
350 352  
351   -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
352   -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  353 +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  354 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  355 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
353 356 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
354   -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  357 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  358 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
355 359 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
356 360 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
357 361  
include/configs/MPC8544DS.h
Diff comments   View file @ 8f86a36
... ... @@ -263,50 +263,61 @@
263 263 * General PCI
264 264 * Memory space is mapped 1-1, but I/O space must start from 0.
265 265 */
  266 +#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
266 267 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
  268 +#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
267 269 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
268 270  
269   -#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
270   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  271 +#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
  272 +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
  273 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
271 274 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
272   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  275 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  276 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
273 277 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
274 278 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
275 279  
276 280 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
277   -#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
278   -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
  281 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
  282 +#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
  283 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
279 284 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
280   -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  285 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
  286 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
281 287 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
282 288 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
283 289  
284 290 /* controller 1, Slot 2,tgtid 2, Base address a000 */
285   -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
286   -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  291 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  292 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  293 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
287 294 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
288   -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  295 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
  296 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
289 297 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
290 298 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
291 299  
292 300 /* controller 3, direct to uli, tgtid 3, Base address b000 */
293   -#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000
294   -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
  301 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  302 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
  303 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
295 304 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
296   -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
  305 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
  306 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
297 307 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
298 308 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
299   -#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000
300   -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2
  309 +#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
  310 +#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
  311 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
301 312 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
302 313  
303 314 #if defined(CONFIG_PCI)
304 315  
305 316 /*PCIE video card used*/
306   -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS
  317 +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
307 318  
308 319 /*PCI video card used*/
309   -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
  320 +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
310 321  
311 322 /* video */
312 323 #define CONFIG_VIDEO
... ... @@ -336,8 +347,8 @@
336 347 #endif
337 348  
338 349 #ifndef CONFIG_PCI_PNP
339   - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
340   - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
  350 + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  351 + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
341 352 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
342 353 #endif
343 354  
include/configs/MPC8548CDS.h
Diff comments   View file @ 8f86a36
... ... @@ -365,29 +365,36 @@
365 365 * General PCI
366 366 * Memory space is mapped 1-1, but I/O space must start from 0.
367 367 */
  368 +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
368 369 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
369 370  
370   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
371   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  371 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  372 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  373 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
372 374 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
373   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  375 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  376 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
374 377 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
375 378 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
376 379  
377 380 #ifdef CONFIG_PCI2
378   -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
379   -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  381 +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  382 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  383 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
380 384 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
381   -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  385 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
  386 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
382 387 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
383 388 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
384 389 #endif
385 390  
386 391 #ifdef CONFIG_PCIE1
387   -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
388   -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  392 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  393 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  394 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
389 395 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
390   -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  396 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
  397 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
391 398 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
392 399 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
393 400 #endif
... ... @@ -396,7 +403,8 @@
396 403 /*
397 404 * RapidIO MMU
398 405 */
399   -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
  406 +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
  407 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
400 408 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
401 409 #endif
402 410  
include/configs/MPC8555CDS.h
Diff comments   View file @ 8f86a36
... ... @@ -339,17 +339,21 @@
339 339 * General PCI
340 340 * Addresses are mapped 1-1.
341 341 */
342   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
343   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  342 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  343 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  344 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
344 345 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
345   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  346 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  347 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
346 348 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
347 349 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
348 350  
349   -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
350   -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  351 +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  352 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  353 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
351 354 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
352   -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  355 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  356 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
353 357 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
354 358 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
355 359  
include/configs/MPC8560ADS.h
Diff comments   View file @ 8f86a36
... ... @@ -300,18 +300,21 @@
300 300 #define CONFIG_SYS_I2C_OFFSET 0x3000
301 301  
302 302 /* RapidIO MMU */
303   -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
304   -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
  303 +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  304 +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  305 +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
305 306 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
306 307  
307 308 /*
308 309 * General PCI
309 310 * Memory space is mapped 1-1, but I/O space must start from 0.
310 311 */
311   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
312   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  312 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  313 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  314 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
313 315 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
314   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  316 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  317 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
315 318 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
316 319 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
317 320  
include/configs/MPC8568MDS.h
Diff comments   View file @ 8f86a36
... ... @@ -322,21 +322,27 @@
322 322 * General PCI
323 323 * Memory Addresses are mapped 1-1. I/O is mapped from 0
324 324 */
325   -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
326   -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  325 +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  326 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  327 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
327 328 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
328   -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  329 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  330 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
329 331 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
330 332 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
331 333  
332   -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
333   -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  334 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  335 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  336 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
334 337 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
335   -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  338 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  339 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
336 340 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
337 341 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
338 342  
339   -#define CONFIG_SYS_SRIO_MEM_BASE 0xc0000000
  343 +#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
  344 +#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
  345 +#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
340 346  
341 347 #ifdef CONFIG_QE
342 348 /*
include/configs/MPC8572DS.h
Diff comments   View file @ 8f86a36
... ... @@ -36,6 +36,7 @@
36 36 #define CONFIG_MP 1 /* support multiple processors */
37 37 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
38 38  
  39 +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
39 40 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
40 41 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
41 42 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
... ... @@ -74,6 +75,11 @@
74 75  
75 76 #define CONFIG_ENABLE_36BIT_PHYS 1
76 77  
  78 +#ifdef CONFIG_PHYS_64BIT
  79 +#define CONFIG_ADDR_MAP 1
  80 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  81 +#endif
  82 +
77 83 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
78 84 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
79 85 #define CONFIG_PANIC_HANG /* do not reset board on panic */
80 86  
... ... @@ -84,7 +90,11 @@
84 90 */
85 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 92 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  93 +#ifdef CONFIG_PHYS_64BIT
  94 +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
  95 +#else
87 96 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  97 +#endif
88 98 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
89 99  
90 100 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
91 101  
92 102  
93 103  
... ... @@ -169,14 +179,19 @@
169 179 * Local Bus Definitions
170 180 */
171 181 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  182 +#ifdef CONFIG_PHYS_64BIT
  183 +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  184 +#else
  185 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  186 +#endif
172 187  
173   -#define CONFIG_SYS_BR0_PRELIM 0xe8001001
174   -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
  188 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
  189 +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
175 190  
176   -#define CONFIG_SYS_BR1_PRELIM 0xe0001001
177   -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  191 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  192 +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
178 193  
179   -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
  194 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
180 195 #define CONFIG_SYS_FLASH_QUIET_TEST
181 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
182 197  
183 198  
... ... @@ -197,8 +212,13 @@
197 212  
198 213 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
199 214 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  215 +#ifdef CONFIG_PHYS_64BIT
  216 +#define PIXIS_BASE_PHYS 0xfffdf0000ull
  217 +#else
  218 +#define PIXIS_BASE_PHYS PIXIS_BASE
  219 +#endif
200 220  
201   -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
  221 +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
202 222 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
203 223  
204 224 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
205 225  
... ... @@ -261,7 +281,11 @@
261 281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
262 282  
263 283 #define CONFIG_SYS_NAND_BASE 0xffa00000
  284 +#ifdef CONFIG_PHYS_64BIT
  285 +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  286 +#else
264 287 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  288 +#endif
265 289 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
266 290 CONFIG_SYS_NAND_BASE + 0x40000, \
267 291 CONFIG_SYS_NAND_BASE + 0x80000,\
... ... @@ -273,7 +297,7 @@
273 297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
274 298  
275 299 /* NAND flash config */
276   -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  300 +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
277 301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
278 302 | BR_PS_8 /* Port Size = 8 bit */ \
279 303 | BR_MS_FCM /* MSEL = FCM */ \
280 304  
281 305  
... ... @@ -290,20 +314,20 @@
290 314 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
291 315 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
292 316  
293   -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
  317 +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
294 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
295 319 | BR_PS_8 /* Port Size = 8 bit */ \
296 320 | BR_MS_FCM /* MSEL = FCM */ \
297 321 | BR_V) /* valid */
298 322 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
299   -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
  323 +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
300 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
301 325 | BR_PS_8 /* Port Size = 8 bit */ \
302 326 | BR_MS_FCM /* MSEL = FCM */ \
303 327 | BR_V) /* valid */
304 328 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
305 329  
306   -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
  330 +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
307 331 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
308 332 | BR_PS_8 /* Port Size = 8 bit */ \
309 333 | BR_MS_FCM /* MSEL = FCM */ \
310 334  
311 335  
312 336  
313 337  
314 338  
315 339  
316 340  
317 341  
318 342  
... ... @@ -378,33 +402,63 @@
378 402 */
379 403  
380 404 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
381   -#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
382   -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
  405 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  406 +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  407 +#ifdef CONFIG_PHYS_64BIT
  408 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  409 +#else
  410 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  411 +#endif
383 412 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
384   -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
  413 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  414 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  415 +#ifdef CONFIG_PHYS_64BIT
  416 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  417 +#else
385 418 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  419 +#endif
386 420 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
387 421  
388 422 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
389   -#define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000
390   -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
  423 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  424 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  425 +#ifdef CONFIG_PHYS_64BIT
  426 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  427 +#else
  428 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  429 +#endif
391 430 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
392   -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  431 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  432 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  433 +#ifdef CONFIG_PHYS_64BIT
  434 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  435 +#else
393 436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  437 +#endif
394 438 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
395 439  
396 440 /* controller 1, Slot 1, tgtid 1, Base address a000 */
397   -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
398   -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  441 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  442 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  443 +#ifdef CONFIG_PHYS_64BIT
  444 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  445 +#else
  446 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  447 +#endif
399 448 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
400   -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  449 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  450 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  451 +#ifdef CONFIG_PHYS_64BIT
  452 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  453 +#else
401 454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  455 +#endif
402 456 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
403 457  
404 458 #if defined(CONFIG_PCI)
405 459  
406 460 /*PCIE video card used*/
407   -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS
  461 +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
408 462  
409 463 /* video */
410 464 #define CONFIG_VIDEO
... ... @@ -434,8 +488,8 @@
434 488 #endif
435 489  
436 490 #ifndef CONFIG_PCI_PNP
437   - #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE
438   - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE
  491 + #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
  492 + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
439 493 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
440 494 #endif
441 495  
... ... @@ -8,9 +8,13 @@
8 8  
9 9 #ifndef __ASSEMBLY__
10 10  
  11 +#ifndef CONFIG_NUM_CPUS
  12 +#define CONFIG_NUM_CPUS 1
  13 +#endif
  14 +
11 15 typedef struct
12 16 {
13   - unsigned long freqProcessor;
  17 + unsigned long freqProcessor[CONFIG_NUM_CPUS];
14 18 unsigned long freqSystemBus;
15 19 unsigned long freqDDRBus;
16 20 unsigned long freqLocalBus;