Commit 901f6950a482d11849b7c748eaef7bda010e91dc

Authored by Patrick Delaunay
Committed by Marek Vasut
1 parent e1904abc1b

phy: usbphyc: increase PLL wait timeout

wait 200us to solve USB init issue on device mode
(ums and stm32prog commands)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Showing 1 changed file with 4 additions and 6 deletions Side-by-side Diff

drivers/phy/phy-stm32-usbphyc.c
... ... @@ -37,7 +37,8 @@
37 37  
38 38 #define MAX_PHYS 2
39 39  
40   -#define PLL_LOCK_TIME_US 100
  40 +/* max 100 us for PLL lock and 100 us for PHY init */
  41 +#define PLL_INIT_TIME_US 200
41 42 #define PLL_PWR_DOWN_TIME_US 5
42 43 #define PLL_FVCO 2880 /* in MHz */
43 44 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
... ... @@ -177,11 +178,8 @@
177 178  
178 179 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
179 180  
180   - /*
181   - * We must wait PLL_LOCK_TIME_US before checking that PLLEN
182   - * bit is still set
183   - */
184   - udelay(PLL_LOCK_TIME_US);
  181 + /* We must wait PLL_INIT_TIME_US before using PHY */
  182 + udelay(PLL_INIT_TIME_US);
185 183  
186 184 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
187 185 return -EIO;