update/fix PDNB3 board

Signed-off-by: Michael Schwingen <michael@schwingen.org>

update/fix PDNB3 board
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Michael Schwingen · Albert ARIBAUD
1 parent 973af335e6
Showing 2 changed files with 7 additions and 5 deletions Side-by-side Diff
board/prodrive/pdnb3/config.mk
include/configs/pdnb3.h
-#
-CONFIG_SYS_TEXT_BASE = 0x01f00000
@@ -50,9 +50,6 @@
 /*
  * Misc configuration options
  */
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
-
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
  
@@ -117,6 +114,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
  
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
  
+#define CONFIG_SYS_TEXT_BASE	       0x50000000
 #define CONFIG_SYS_FLASH_BASE          0x50000000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
@@ -344,6 +343,11 @@
  * Cache Configuration
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR        \
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  
 #endif  /* __CONFIG_H */
...	...	@@ -50,9 +50,6 @@
50	50	/*
51	51	* Misc configuration options
52	52	*/
53		-#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
54		-#define CONFIG_TIMER_IRQ
55		-
56	53	#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
57	54	#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
58	55
...	...	@@ -117,6 +114,7 @@
117	114	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
118	115	#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
119	116
	117	+#define CONFIG_IXP425_TIMER_CLK 66666666
120	118	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
121	119	/* valid baudrates */
122	120	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
...	...	@@ -188,6 +186,7 @@
188	186	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
189	187	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
190	188
	189	+#define CONFIG_SYS_TEXT_BASE 0x50000000
191	190	#define CONFIG_SYS_FLASH_BASE 0x50000000
192	191	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
193	192	#if defined(CONFIG_SCPU)
...	...	@@ -344,6 +343,11 @@
344	343	* Cache Configuration
345	344	*/
346	345	#define CONFIG_SYS_CACHELINE_SIZE 32
	346	+
	347	+/* additions for new relocation code, must be added to all boards */
	348	+#define CONFIG_SYS_SDRAM_BASE 0x00000000
	349	+#define CONFIG_SYS_INIT_SP_ADDR \
	350	+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
347	351
348	352	#endif /* __CONFIG_H */