Eric Lee / smarc-uboot

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Commit 9055f66c2dfb637d0f30372a7e79cca854e45bae

Authored by Stefan Roese
1 parent 1affd4d4a3
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Fix GPIO handling in lwmon5 and lcd4_lwmon5 BSP 

LCD4 needs a slightly different GPIO configuration than the
original LWMON5 variant. GPIO49 needs to be configured to a
default output value of 0 (permanent voltage supply).

Additionally lcd4 also needs to enable the LSB transmitter.

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 2 changed files with 12 additions and 1 deletions Side-by-side Diff

board/lwmon5/lwmon5.c
Diff comments   View file @ 9055f66
... ... @@ -527,6 +527,9 @@
527 527 */
528 528 board_early_init_f();
529 529  
  530 + /* enable the LSB transmitter */
  531 + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
  532 +
530 533 /*
531 534 * Clear resets
532 535 */
include/configs/lwmon5.h
Diff comments   View file @ 9055f66
... ... @@ -565,6 +565,7 @@
565 565 #define CONFIG_SYS_GPIO_PHY1_RST 12
566 566 #define CONFIG_SYS_GPIO_FLASH_WP 14
567 567 #define CONFIG_SYS_GPIO_PHY0_RST 22
  568 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
568 569 #define CONFIG_SYS_GPIO_DSPIC_READY 51
569 570 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
570 571 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
... ... @@ -577,6 +578,13 @@
577 578 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
578 579 #define CONFIG_SYS_GPIO_WATCHDOG 63
579 580  
  581 +/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
  582 +#ifdef CONFIG_LCD4_LWMON5
  583 +#define GPIO49_VAL 0
  584 +#else
  585 +#define GPIO49_VAL 1
  586 +#endif
  587 +
580 588 /*
581 589 * PPC440 GPIO Configuration
582 590 */
... ... @@ -635,7 +643,7 @@
635 643 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
636 644 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
637 645 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
638   -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
  646 +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
639 647 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
640 648 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
641 649 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \