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Commit 9067b30008e4c09fb6287d306caf2a6bed08370f

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent f7e1af8690
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc8260: remove atc board support 

These boards are still non-generic boards.

drivers/rtc/ds12887.c should also be removed because it can not
be built without CONFIG_ATC.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>

Showing 13 changed files with 1 additions and 2388 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8260/Kconfig
Diff comments   View file @ 9067b30
... ... @@ -7,15 +7,11 @@
7 7 choice
8 8 prompt "Target select"
9 9  
10   -config TARGET_ATC
11   - bool "Support atc"
12   -
13 10 config TARGET_KM82XX
14 11 bool "Support km82xx"
15 12  
16 13 endchoice
17 14  
18   -source "board/atc/Kconfig"
19 15 source "board/keymile/km82xx/Kconfig"
20 16  
21 17 endmenu
board/atc/Kconfig
View file @ 9067b30
1   -if TARGET_ATC
2   -
3   -config SYS_BOARD
4   - default "atc"
5   -
6   -config SYS_CONFIG_NAME
7   - default "atc"
8   -
9   -endif
board/atc/MAINTAINERS
View file @ 9067b30
1   -ATC BOARD
2   -M: Wolfgang Denk <wd@denx.de>
3   -S: Maintained
4   -F: board/atc/
5   -F: include/configs/atc.h
6   -F: configs/atc_defconfig
board/atc/Makefile
View file @ 9067b30
1   -#
2   -# (C) Copyright 2001-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = atc.o flash.o ti113x.o
board/atc/atc.c
View file @ 9067b30
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <ioports.h>
10   -#include <mpc8260.h>
11   -#include <pci.h>
12   -
13   -/*
14   - * I/O Port configuration table
15   - *
16   - * if conf is 1, then that port pin will be configured at boot time
17   - * according to the five values podr/pdir/ppar/psor/pdat for that entry
18   - */
19   -
20   -const iop_conf_t iop_conf_tab[4][32] = {
21   -
22   - /* Port A configuration */
23   - { /* conf ppar psor pdir podr pdat */
24   - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
25   - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
26   - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
27   - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
28   - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
29   - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
30   - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
31   - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
32   - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
33   - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
34   - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
35   - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
36   - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
37   - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
38   - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
39   - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
40   - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
41   - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
42   - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
43   - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
44   - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
45   - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
46   -#if 1
47   - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
48   - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
49   -#else
50   - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
51   - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
52   -#endif
53   - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
54   - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
55   - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
56   - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
57   - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
58   - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
59   - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
60   - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
61   - },
62   -
63   - /* Port B configuration */
64   - { /* conf ppar psor pdir podr pdat */
65   - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66   - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67   - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68   - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69   - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70   - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71   - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72   - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73   - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74   - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75   - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76   - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77   - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78   - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
79   - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
80   - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
81   - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
82   - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
83   - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
84   - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
85   - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
86   - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
87   - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
88   - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
89   - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
90   - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
91   - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
92   - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
93   - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
94   - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
95   - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
96   - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
97   - },
98   -
99   - /* Port C */
100   - { /* conf ppar psor pdir podr pdat */
101   - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
102   - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
103   - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
104   - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
105   - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
106   - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
107   - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
108   - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
109   - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
110   - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
111   - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
112   - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
113   - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
114   - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
115   - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
116   - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
117   -#if 0
118   - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
119   -#else
120   - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */
121   -#endif
122   - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
123   - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
124   - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
125   - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
126   - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
127   - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
128   - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
129   - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
130   - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
131   - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
132   - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
133   - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
134   - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
135   - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
136   - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
137   - },
138   -
139   - /* Port D */
140   - { /* conf ppar psor pdir podr pdat */
141   - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
142   - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
143   - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
144   - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
145   - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
146   - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
147   - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
148   - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
149   - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
150   - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
151   - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
152   - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
153   - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
154   - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
155   - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
156   - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
157   -#if defined(CONFIG_SYS_I2C_SOFT)
158   - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
159   - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
160   -#else
161   -#if defined(CONFIG_HARD_I2C)
162   - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
163   - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
164   -#else /* normal I/O port pins */
165   - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
166   - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
167   -#endif
168   -#endif
169   - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
170   - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
171   - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
172   - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
173   - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
174   - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
175   - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
176   - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
177   - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
178   -#if 0
179   - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
180   -#else
181   - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */
182   -#endif
183   - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
184   - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
185   - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
186   - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
187   - }
188   -};
189   -
190   -/*
191   - * UPMB initialization table
192   - */
193   -#define _NOT_USED_ 0xFFFFFFFF
194   -
195   -static const uint rtc_table[] =
196   -{
197   - /*
198   - * Single Read. (Offset 0 in UPMA RAM)
199   - */
200   - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
201   - 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
202   - /*
203   - * Burst Read. (Offset 8 in UPMA RAM)
204   - */
205   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
206   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
207   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
208   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
209   - /*
210   - * Single Write. (Offset 18 in UPMA RAM)
211   - */
212   - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
213   - 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
214   - /*
215   - * Burst Write. (Offset 20 in UPMA RAM)
216   - */
217   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
218   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
219   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
220   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
221   - /*
222   - * Refresh (Offset 30 in UPMA RAM)
223   - */
224   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
225   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
226   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
227   - /*
228   - * Exception. (Offset 3c in UPMA RAM)
229   - */
230   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
231   -};
232   -
233   -/* ------------------------------------------------------------------------- */
234   -
235   -/* Check Board Identity:
236   - */
237   -int checkboard (void)
238   -{
239   - printf ("Board: ATC\n");
240   - return 0;
241   -}
242   -
243   -/* ------------------------------------------------------------------------- */
244   -
245   -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
246   - *
247   - * This routine performs standard 8260 initialization sequence
248   - * and calculates the available memory size. It may be called
249   - * several times to try different SDRAM configurations on both
250   - * 60x and local buses.
251   - */
252   -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
253   - ulong orx, volatile uchar * base)
254   -{
255   - volatile uchar c = 0xff;
256   - volatile uint *sdmr_ptr;
257   - volatile uint *orx_ptr;
258   - ulong maxsize, size;
259   - int i;
260   -
261   - /* We must be able to test a location outsize the maximum legal size
262   - * to find out THAT we are outside; but this address still has to be
263   - * mapped by the controller. That means, that the initial mapping has
264   - * to be (at least) twice as large as the maximum expected size.
265   - */
266   - maxsize = (1 + (~orx | 0x7fff)) / 2;
267   -
268   - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
269   - * we are configuring CS1 if base != 0
270   - */
271   - sdmr_ptr = &memctl->memc_psdmr;
272   - orx_ptr = &memctl->memc_or2;
273   -
274   - *orx_ptr = orx;
275   -
276   - /*
277   - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
278   - *
279   - * "At system reset, initialization software must set up the
280   - * programmable parameters in the memory controller banks registers
281   - * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
282   - * system software should execute the following initialization sequence
283   - * for each SDRAM device.
284   - *
285   - * 1. Issue a PRECHARGE-ALL-BANKS command
286   - * 2. Issue eight CBR REFRESH commands
287   - * 3. Issue a MODE-SET command to initialize the mode register
288   - *
289   - * The initial commands are executed by setting P/LSDMR[OP] and
290   - * accessing the SDRAM with a single-byte transaction."
291   - *
292   - * The appropriate BRx/ORx registers have already been set when we
293   - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
294   - */
295   -
296   - *sdmr_ptr = sdmr | PSDMR_OP_PREA;
297   - *base = c;
298   -
299   - *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
300   - for (i = 0; i < 8; i++)
301   - *base = c;
302   -
303   - *sdmr_ptr = sdmr | PSDMR_OP_MRW;
304   - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
305   -
306   - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
307   - *base = c;
308   -
309   - size = get_ram_size((long *)base, maxsize);
310   -
311   - *orx_ptr = orx | ~(size - 1);
312   -
313   - return (size);
314   -}
315   -
316   -int misc_init_r(void)
317   -{
318   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
319   - volatile memctl8260_t *memctl = &immap->im_memctl;
320   -
321   - upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
322   - memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
323   -
324   - return (0);
325   -}
326   -
327   -phys_size_t initdram (int board_type)
328   -{
329   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
330   - volatile memctl8260_t *memctl = &immap->im_memctl;
331   -
332   -#ifndef CONFIG_SYS_RAMBOOT
333   - ulong size8, size9;
334   -#endif
335   - long psize;
336   -
337   - psize = 8 * 1024 * 1024;
338   -
339   - memctl->memc_mptpr = CONFIG_SYS_MPTPR;
340   - memctl->memc_psrt = CONFIG_SYS_PSRT;
341   -
342   -#ifndef CONFIG_SYS_RAMBOOT
343   - /* 60x SDRAM setup:
344   - */
345   - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
346   - (uchar *) CONFIG_SYS_SDRAM_BASE);
347   - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
348   - (uchar *) CONFIG_SYS_SDRAM_BASE);
349   -
350   - if (size8 < size9) {
351   - psize = size9;
352   - printf ("(60x:9COL) ");
353   - } else {
354   - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
355   - (uchar *) CONFIG_SYS_SDRAM_BASE);
356   - printf ("(60x:8COL) ");
357   - }
358   -
359   -#endif /* CONFIG_SYS_RAMBOOT */
360   -
361   - icache_enable ();
362   -
363   - return (psize);
364   -}
365   -
366   -#if defined(CONFIG_CMD_DOC)
367   -void doc_init (void)
368   -{
369   - doc_probe (CONFIG_SYS_DOC_BASE);
370   -}
371   -#endif
372   -
373   -#ifdef CONFIG_PCI
374   -struct pci_controller hose;
375   -
376   -extern void pci_mpc8250_init(struct pci_controller *);
377   -
378   -void pci_init_board(void)
379   -{
380   - pci_mpc8250_init(&hose);
381   -}
382   -#endif
board/atc/flash.c
View file @ 9067b30
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -
10   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
11   -
12   -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
13   - * has nothing to do with the flash chip being 8-bit or 16-bit.
14   - */
15   -#ifdef CONFIG_FLASH_16BIT
16   -typedef unsigned short FLASH_PORT_WIDTH;
17   -typedef volatile unsigned short FLASH_PORT_WIDTHV;
18   -#define FLASH_ID_MASK 0xFFFF
19   -#else
20   -typedef unsigned long FLASH_PORT_WIDTH;
21   -typedef volatile unsigned long FLASH_PORT_WIDTHV;
22   -#define FLASH_ID_MASK 0xFFFFFFFF
23   -#endif
24   -
25   -#define FPW FLASH_PORT_WIDTH
26   -#define FPWV FLASH_PORT_WIDTHV
27   -
28   -#define ORMASK(size) ((-size) & OR_AM_MSK)
29   -
30   -#define FLASH_CYCLE1 0x0555
31   -#define FLASH_CYCLE2 0x02aa
32   -
33   -/*-----------------------------------------------------------------------
34   - * Functions
35   - */
36   -static ulong flash_get_size(FPWV *addr, flash_info_t *info);
37   -static void flash_reset(flash_info_t *info);
38   -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
39   -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
40   -static void flash_get_offsets(ulong base, flash_info_t *info);
41   -static flash_info_t *flash_get_info(ulong base);
42   -
43   -/*-----------------------------------------------------------------------
44   - * flash_init()
45   - *
46   - * sets up flash_info and returns size of FLASH (bytes)
47   - */
48   -unsigned long flash_init (void)
49   -{
50   - unsigned long size = 0;
51   - int i;
52   -
53   - /* Init: no FLASHes known */
54   - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
55   -#if 0
56   - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
57   -#else
58   - ulong flashbase = CONFIG_SYS_FLASH_BASE;
59   -#endif
60   -
61   - memset(&flash_info[i], 0, sizeof(flash_info_t));
62   -
63   - flash_info[i].size =
64   - flash_get_size((FPW *)flashbase, &flash_info[i]);
65   -
66   - if (flash_info[i].flash_id == FLASH_UNKNOWN) {
67   - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
68   - i, flash_info[i].size);
69   - }
70   -
71   - size += flash_info[i].size;
72   - }
73   -
74   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
75   - /* monitor protection ON by default */
76   - flash_protect(FLAG_PROTECT_SET,
77   - CONFIG_SYS_MONITOR_BASE,
78   - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
79   - flash_get_info(CONFIG_SYS_MONITOR_BASE));
80   -#endif
81   -
82   -#ifdef CONFIG_ENV_IS_IN_FLASH
83   - /* ENV protection ON by default */
84   - flash_protect(FLAG_PROTECT_SET,
85   - CONFIG_ENV_ADDR,
86   - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
87   - flash_get_info(CONFIG_ENV_ADDR));
88   -#endif
89   -
90   -
91   - return size ? size : 1;
92   -}
93   -
94   -/*-----------------------------------------------------------------------
95   - */
96   -static void flash_reset(flash_info_t *info)
97   -{
98   - FPWV *base = (FPWV *)(info->start[0]);
99   -
100   - /* Put FLASH back in read mode */
101   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
102   - *base = (FPW)0x00FF00FF; /* Intel Read Mode */
103   - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
104   - *base = (FPW)0x00F000F0; /* AMD Read Mode */
105   -}
106   -
107   -/*-----------------------------------------------------------------------
108   - */
109   -static void flash_get_offsets (ulong base, flash_info_t *info)
110   -{
111   - int i;
112   -
113   - /* set up sector start address table */
114   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
115   - && (info->flash_id & FLASH_BTYPE)) {
116   - int bootsect_size; /* number of bytes/boot sector */
117   - int sect_size; /* number of bytes/regular sector */
118   -
119   - bootsect_size = 0x00002000 * (sizeof(FPW)/2);
120   - sect_size = 0x00010000 * (sizeof(FPW)/2);
121   -
122   - /* set sector offsets for bottom boot block type */
123   - for (i = 0; i < 8; ++i) {
124   - info->start[i] = base + (i * bootsect_size);
125   - }
126   - for (i = 8; i < info->sector_count; i++) {
127   - info->start[i] = base + ((i - 7) * sect_size);
128   - }
129   - }
130   - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
131   - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
132   -
133   - int sect_size; /* number of bytes/sector */
134   -
135   - sect_size = 0x00010000 * (sizeof(FPW)/2);
136   -
137   - /* set up sector start address table (uniform sector type) */
138   - for( i = 0; i < info->sector_count; i++ )
139   - info->start[i] = base + (i * sect_size);
140   - }
141   -}
142   -
143   -/*-----------------------------------------------------------------------
144   - */
145   -
146   -static flash_info_t *flash_get_info(ulong base)
147   -{
148   - int i;
149   - flash_info_t * info;
150   -
151   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
152   - info = & flash_info[i];
153   - if (info->start[0] <= base && base < info->start[0] + info->size)
154   - break;
155   - }
156   -
157   - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
158   -}
159   -
160   -/*-----------------------------------------------------------------------
161   - */
162   -
163   -void flash_print_info (flash_info_t *info)
164   -{
165   - int i;
166   - uchar *boottype;
167   - uchar *bootletter;
168   - char *fmt;
169   - uchar botbootletter[] = "B";
170   - uchar topbootletter[] = "T";
171   - uchar botboottype[] = "bottom boot sector";
172   - uchar topboottype[] = "top boot sector";
173   -
174   - if (info->flash_id == FLASH_UNKNOWN) {
175   - printf ("missing or unknown FLASH type\n");
176   - return;
177   - }
178   -
179   - switch (info->flash_id & FLASH_VENDMASK) {
180   - case FLASH_MAN_AMD: printf ("AMD "); break;
181   - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
182   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
183   - case FLASH_MAN_SST: printf ("SST "); break;
184   - case FLASH_MAN_STM: printf ("STM "); break;
185   - case FLASH_MAN_INTEL: printf ("INTEL "); break;
186   - default: printf ("Unknown Vendor "); break;
187   - }
188   -
189   - /* check for top or bottom boot, if it applies */
190   - if (info->flash_id & FLASH_BTYPE) {
191   - boottype = botboottype;
192   - bootletter = botbootletter;
193   - }
194   - else {
195   - boottype = topboottype;
196   - bootletter = topbootletter;
197   - }
198   -
199   - switch (info->flash_id & FLASH_TYPEMASK) {
200   - case FLASH_AM640U:
201   - fmt = "29LV641D (64 Mbit, uniform sectors)\n";
202   - break;
203   - case FLASH_28F800C3B:
204   - case FLASH_28F800C3T:
205   - fmt = "28F800C3%s (8 Mbit, %s)\n";
206   - break;
207   - case FLASH_INTEL800B:
208   - case FLASH_INTEL800T:
209   - fmt = "28F800B3%s (8 Mbit, %s)\n";
210   - break;
211   - case FLASH_28F160C3B:
212   - case FLASH_28F160C3T:
213   - fmt = "28F160C3%s (16 Mbit, %s)\n";
214   - break;
215   - case FLASH_INTEL160B:
216   - case FLASH_INTEL160T:
217   - fmt = "28F160B3%s (16 Mbit, %s)\n";
218   - break;
219   - case FLASH_28F320C3B:
220   - case FLASH_28F320C3T:
221   - fmt = "28F320C3%s (32 Mbit, %s)\n";
222   - break;
223   - case FLASH_INTEL320B:
224   - case FLASH_INTEL320T:
225   - fmt = "28F320B3%s (32 Mbit, %s)\n";
226   - break;
227   - case FLASH_28F640C3B:
228   - case FLASH_28F640C3T:
229   - fmt = "28F640C3%s (64 Mbit, %s)\n";
230   - break;
231   - case FLASH_INTEL640B:
232   - case FLASH_INTEL640T:
233   - fmt = "28F640B3%s (64 Mbit, %s)\n";
234   - break;
235   - default:
236   - fmt = "Unknown Chip Type\n";
237   - break;
238   - }
239   -
240   - printf (fmt, bootletter, boottype);
241   -
242   - printf (" Size: %ld MB in %d Sectors\n",
243   - info->size >> 20,
244   - info->sector_count);
245   -
246   - printf (" Sector Start Addresses:");
247   -
248   - for (i=0; i<info->sector_count; ++i) {
249   - if ((i % 5) == 0) {
250   - printf ("\n ");
251   - }
252   -
253   - printf (" %08lX%s", info->start[i],
254   - info->protect[i] ? " (RO)" : " ");
255   - }
256   -
257   - printf ("\n");
258   -}
259   -
260   -/*-----------------------------------------------------------------------
261   - */
262   -
263   -/*
264   - * The following code cannot be run from FLASH!
265   - */
266   -
267   -ulong flash_get_size (FPWV *addr, flash_info_t *info)
268   -{
269   - /* Write auto select command: read Manufacturer ID */
270   -
271   - /* Write auto select command sequence and test FLASH answer */
272   - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
273   - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
274   - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
275   -
276   - /* The manufacturer codes are only 1 byte, so just use 1 byte.
277   - * This works for any bus width and any FLASH device width.
278   - */
279   - udelay(100);
280   - switch (addr[0] & 0xff) {
281   -
282   - case (uchar)AMD_MANUFACT:
283   - info->flash_id = FLASH_MAN_AMD;
284   - break;
285   -
286   - case (uchar)INTEL_MANUFACT:
287   - info->flash_id = FLASH_MAN_INTEL;
288   - break;
289   -
290   - default:
291   - info->flash_id = FLASH_UNKNOWN;
292   - info->sector_count = 0;
293   - info->size = 0;
294   - break;
295   - }
296   -
297   - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
298   - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
299   -
300   - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
301   - info->flash_id += FLASH_AM640U;
302   - info->sector_count = 128;
303   - info->size = 0x00800000 * (sizeof(FPW)/2);
304   - break; /* => 8 or 16 MB */
305   -
306   - case (FPW)INTEL_ID_28F800C3B:
307   - info->flash_id += FLASH_28F800C3B;
308   - info->sector_count = 23;
309   - info->size = 0x00100000 * (sizeof(FPW)/2);
310   - break; /* => 1 or 2 MB */
311   -
312   - case (FPW)INTEL_ID_28F800B3B:
313   - info->flash_id += FLASH_INTEL800B;
314   - info->sector_count = 23;
315   - info->size = 0x00100000 * (sizeof(FPW)/2);
316   - break; /* => 1 or 2 MB */
317   -
318   - case (FPW)INTEL_ID_28F160C3B:
319   - info->flash_id += FLASH_28F160C3B;
320   - info->sector_count = 39;
321   - info->size = 0x00200000 * (sizeof(FPW)/2);
322   - break; /* => 2 or 4 MB */
323   -
324   - case (FPW)INTEL_ID_28F160B3B:
325   - info->flash_id += FLASH_INTEL160B;
326   - info->sector_count = 39;
327   - info->size = 0x00200000 * (sizeof(FPW)/2);
328   - break; /* => 2 or 4 MB */
329   -
330   - case (FPW)INTEL_ID_28F320C3B:
331   - info->flash_id += FLASH_28F320C3B;
332   - info->sector_count = 71;
333   - info->size = 0x00400000 * (sizeof(FPW)/2);
334   - break; /* => 4 or 8 MB */
335   -
336   - case (FPW)INTEL_ID_28F320B3B:
337   - info->flash_id += FLASH_INTEL320B;
338   - info->sector_count = 71;
339   - info->size = 0x00400000 * (sizeof(FPW)/2);
340   - break; /* => 4 or 8 MB */
341   -
342   - case (FPW)INTEL_ID_28F640C3B:
343   - info->flash_id += FLASH_28F640C3B;
344   - info->sector_count = 135;
345   - info->size = 0x00800000 * (sizeof(FPW)/2);
346   - break; /* => 8 or 16 MB */
347   -
348   - case (FPW)INTEL_ID_28F640B3B:
349   - info->flash_id += FLASH_INTEL640B;
350   - info->sector_count = 135;
351   - info->size = 0x00800000 * (sizeof(FPW)/2);
352   - break; /* => 8 or 16 MB */
353   -
354   - default:
355   - info->flash_id = FLASH_UNKNOWN;
356   - info->sector_count = 0;
357   - info->size = 0;
358   - return (0); /* => no or unknown flash */
359   - }
360   -
361   - flash_get_offsets((ulong)addr, info);
362   -
363   - /* Put FLASH back in read mode */
364   - flash_reset(info);
365   -
366   - return (info->size);
367   -}
368   -
369   -/*-----------------------------------------------------------------------
370   - */
371   -
372   -int flash_erase (flash_info_t *info, int s_first, int s_last)
373   -{
374   - FPWV *addr;
375   - int flag, prot, sect;
376   - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
377   - ulong start, now, last;
378   - int rcode = 0;
379   -
380   - if ((s_first < 0) || (s_first > s_last)) {
381   - if (info->flash_id == FLASH_UNKNOWN) {
382   - printf ("- missing\n");
383   - } else {
384   - printf ("- no sectors to erase\n");
385   - }
386   - return 1;
387   - }
388   -
389   - switch (info->flash_id & FLASH_TYPEMASK) {
390   - case FLASH_INTEL800B:
391   - case FLASH_INTEL160B:
392   - case FLASH_INTEL320B:
393   - case FLASH_INTEL640B:
394   - case FLASH_28F800C3B:
395   - case FLASH_28F160C3B:
396   - case FLASH_28F320C3B:
397   - case FLASH_28F640C3B:
398   - case FLASH_AM640U:
399   - break;
400   - case FLASH_UNKNOWN:
401   - default:
402   - printf ("Can't erase unknown flash type %08lx - aborted\n",
403   - info->flash_id);
404   - return 1;
405   - }
406   -
407   - prot = 0;
408   - for (sect=s_first; sect<=s_last; ++sect) {
409   - if (info->protect[sect]) {
410   - prot++;
411   - }
412   - }
413   -
414   - if (prot) {
415   - printf ("- Warning: %d protected sectors will not be erased!\n",
416   - prot);
417   - } else {
418   - printf ("\n");
419   - }
420   -
421   - last = get_timer(0);
422   -
423   - /* Start erase on unprotected sectors */
424   - for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
425   -
426   - if (info->protect[sect] != 0) /* protected, skip it */
427   - continue;
428   -
429   - /* Disable interrupts which might cause a timeout here */
430   - flag = disable_interrupts();
431   -
432   - addr = (FPWV *)(info->start[sect]);
433   - if (intel) {
434   - *addr = (FPW)0x00500050; /* clear status register */
435   - *addr = (FPW)0x00200020; /* erase setup */
436   - *addr = (FPW)0x00D000D0; /* erase confirm */
437   - }
438   - else {
439   - /* must be AMD style if not Intel */
440   - FPWV *base; /* first address in bank */
441   -
442   - base = (FPWV *)(info->start[0]);
443   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
444   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
445   - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
446   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
447   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
448   - *addr = (FPW)0x00300030; /* erase sector */
449   - }
450   -
451   - /* re-enable interrupts if necessary */
452   - if (flag)
453   - enable_interrupts();
454   -
455   - start = get_timer(0);
456   -
457   - /* wait at least 50us for AMD, 80us for Intel.
458   - * Let's wait 1 ms.
459   - */
460   - udelay (1000);
461   -
462   - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
463   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
464   - printf ("Timeout\n");
465   -
466   - if (intel) {
467   - /* suspend erase */
468   - *addr = (FPW)0x00B000B0;
469   - }
470   -
471   - flash_reset(info); /* reset to read mode */
472   - rcode = 1; /* failed */
473   - break;
474   - }
475   -
476   - /* show that we're waiting */
477   - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
478   - putc ('.');
479   - last = get_timer(0);
480   - }
481   - }
482   -
483   - /* show that we're waiting */
484   - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
485   - putc ('.');
486   - last = get_timer(0);
487   - }
488   -
489   - flash_reset(info); /* reset to read mode */
490   - }
491   -
492   - printf (" done\n");
493   - return rcode;
494   -}
495   -
496   -/*-----------------------------------------------------------------------
497   - * Copy memory to flash, returns:
498   - * 0 - OK
499   - * 1 - write timeout
500   - * 2 - Flash not erased
501   - */
502   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
503   -{
504   - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
505   - int bytes; /* number of bytes to program in current word */
506   - int left; /* number of bytes left to program */
507   - int i, res;
508   -
509   - for (left = cnt, res = 0;
510   - left > 0 && res == 0;
511   - addr += sizeof(data), left -= sizeof(data) - bytes) {
512   -
513   - bytes = addr & (sizeof(data) - 1);
514   - addr &= ~(sizeof(data) - 1);
515   -
516   - /* combine source and destination data so can program
517   - * an entire word of 16 or 32 bits
518   - */
519   - for (i = 0; i < sizeof(data); i++) {
520   - data <<= 8;
521   - if (i < bytes || i - bytes >= left )
522   - data += *((uchar *)addr + i);
523   - else
524   - data += *src++;
525   - }
526   -
527   - /* write one word to the flash */
528   - switch (info->flash_id & FLASH_VENDMASK) {
529   - case FLASH_MAN_AMD:
530   - res = write_word_amd(info, (FPWV *)addr, data);
531   - break;
532   - case FLASH_MAN_INTEL:
533   - res = write_word_intel(info, (FPWV *)addr, data);
534   - break;
535   - default:
536   - /* unknown flash type, error! */
537   - printf ("missing or unknown FLASH type\n");
538   - res = 1; /* not really a timeout, but gives error */
539   - break;
540   - }
541   - }
542   -
543   - return (res);
544   -}
545   -
546   -/*-----------------------------------------------------------------------
547   - * Write a word to Flash for AMD FLASH
548   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
549   - * (not an individual chip) is.
550   - *
551   - * returns:
552   - * 0 - OK
553   - * 1 - write timeout
554   - * 2 - Flash not erased
555   - */
556   -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
557   -{
558   - ulong start;
559   - int flag;
560   - int res = 0; /* result, assume success */
561   - FPWV *base; /* first address in flash bank */
562   -
563   - /* Check if Flash is (sufficiently) erased */
564   - if ((*dest & data) != data) {
565   - return (2);
566   - }
567   -
568   -
569   - base = (FPWV *)(info->start[0]);
570   -
571   - /* Disable interrupts which might cause a timeout here */
572   - flag = disable_interrupts();
573   -
574   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
575   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
576   - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
577   -
578   - *dest = data; /* start programming the data */
579   -
580   - /* re-enable interrupts if necessary */
581   - if (flag)
582   - enable_interrupts();
583   -
584   - start = get_timer (0);
585   -
586   - /* data polling for D7 */
587   - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
588   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
589   - *dest = (FPW)0x00F000F0; /* reset bank */
590   - res = 1;
591   - }
592   - }
593   -
594   - return (res);
595   -}
596   -
597   -/*-----------------------------------------------------------------------
598   - * Write a word to Flash for Intel FLASH
599   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
600   - * (not an individual chip) is.
601   - *
602   - * returns:
603   - * 0 - OK
604   - * 1 - write timeout
605   - * 2 - Flash not erased
606   - */
607   -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
608   -{
609   - ulong start;
610   - int flag;
611   - int res = 0; /* result, assume success */
612   -
613   - /* Check if Flash is (sufficiently) erased */
614   - if ((*dest & data) != data) {
615   - return (2);
616   - }
617   -
618   - /* Disable interrupts which might cause a timeout here */
619   - flag = disable_interrupts();
620   -
621   - *dest = (FPW)0x00500050; /* clear status register */
622   - *dest = (FPW)0x00FF00FF; /* make sure in read mode */
623   - *dest = (FPW)0x00400040; /* program setup */
624   -
625   - *dest = data; /* start programming the data */
626   -
627   - /* re-enable interrupts if necessary */
628   - if (flag)
629   - enable_interrupts();
630   -
631   - start = get_timer (0);
632   -
633   - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
634   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
635   - *dest = (FPW)0x00B000B0; /* Suspend program */
636   - res = 1;
637   - }
638   - }
639   -
640   - if (res == 0 && (*dest & (FPW)0x00100010))
641   - res = 1; /* write failed, time out error is close enough */
642   -
643   - *dest = (FPW)0x00500050; /* clear status register */
644   - *dest = (FPW)0x00FF00FF; /* make sure in read mode */
645   -
646   - return (res);
647   -}
board/atc/ti113x.c
View file @ 9067b30
1   -/*
2   - * (C) Copyright 2003-2005
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - ********************************************************************
7   - *
8   - * Lots of code copied from:
9   - *
10   - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
11   - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
12   - * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
13   - */
14   -
15   -#include <common.h>
16   -
17   -#ifdef CONFIG_I82365
18   -
19   -#include <command.h>
20   -#include <pci.h>
21   -#include <pcmcia.h>
22   -#include <asm/io.h>
23   -
24   -#include <pcmcia/ss.h>
25   -#include <pcmcia/i82365.h>
26   -#include <pcmcia/yenta.h>
27   -#include <pcmcia/ti113x.h>
28   -
29   -static struct pci_device_id supported[] = {
30   - {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
31   - {0, 0}
32   -};
33   -
34   -#define CYCLE_TIME 120
35   -
36   -#ifdef DEBUG
37   -static void i82365_dump_regions (pci_dev_t dev);
38   -#endif
39   -
40   -typedef struct socket_info_t {
41   - pci_dev_t dev;
42   - u_short bcr;
43   - u_char pci_lat, cb_lat, sub_bus, cache;
44   - u_int cb_phys;
45   -
46   - socket_cap_t cap;
47   - u_short type;
48   - u_int flags;
49   - ti113x_state_t state;
50   -} socket_info_t;
51   -
52   -static socket_info_t socket;
53   -static socket_state_t state;
54   -static struct pccard_mem_map mem;
55   -static struct pccard_io_map io;
56   -
57   -/*====================================================================*/
58   -
59   -/* Some PCI shortcuts */
60   -
61   -static int pci_readb (socket_info_t * s, int r, u_char * v)
62   -{
63   - return pci_read_config_byte (s->dev, r, v);
64   -}
65   -static int pci_writeb (socket_info_t * s, int r, u_char v)
66   -{
67   - return pci_write_config_byte (s->dev, r, v);
68   -}
69   -static int pci_readw (socket_info_t * s, int r, u_short * v)
70   -{
71   - return pci_read_config_word (s->dev, r, v);
72   -}
73   -static int pci_writew (socket_info_t * s, int r, u_short v)
74   -{
75   - return pci_write_config_word (s->dev, r, v);
76   -}
77   -static int pci_readl (socket_info_t * s, int r, u_int * v)
78   -{
79   - return pci_read_config_dword (s->dev, r, v);
80   -}
81   -static int pci_writel (socket_info_t * s, int r, u_int v)
82   -{
83   - return pci_write_config_dword (s->dev, r, v);
84   -}
85   -
86   -/*====================================================================*/
87   -
88   -#define cb_readb(s, r) readb((s)->cb_phys + (r))
89   -#define cb_readl(s, r) readl((s)->cb_phys + (r))
90   -#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
91   -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
92   -
93   -static u_char i365_get (socket_info_t * s, u_short reg)
94   -{
95   - return cb_readb (s, 0x0800 + reg);
96   -}
97   -
98   -static void i365_set (socket_info_t * s, u_short reg, u_char data)
99   -{
100   - cb_writeb (s, 0x0800 + reg, data);
101   -}
102   -
103   -static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
104   -{
105   - i365_set (s, reg, i365_get (s, reg) | mask);
106   -}
107   -
108   -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
109   -{
110   - i365_set (s, reg, i365_get (s, reg) & ~mask);
111   -}
112   -
113   -#if 0 /* not used */
114   -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
115   -{
116   - u_char d = i365_get (s, reg);
117   -
118   - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
119   -}
120   -
121   -static u_short i365_get_pair (socket_info_t * s, u_short reg)
122   -{
123   - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
124   -}
125   -#endif /* not used */
126   -
127   -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
128   -{
129   - i365_set (s, reg, data & 0xff);
130   - i365_set (s, reg + 1, data >> 8);
131   -}
132   -
133   -/*======================================================================
134   -
135   - Code to save and restore global state information for TI 1130 and
136   - TI 1131 controllers, and to set and report global configuration
137   - options.
138   -
139   -======================================================================*/
140   -
141   -static void ti113x_get_state (socket_info_t * s)
142   -{
143   - ti113x_state_t *p = &s->state;
144   -
145   - pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
146   - pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
147   - pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
148   - pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
149   - pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
150   -}
151   -
152   -static void ti113x_set_state (socket_info_t * s)
153   -{
154   - ti113x_state_t *p = &s->state;
155   -
156   - pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
157   - pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
158   - pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
159   - pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
160   - pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
161   - pci_writel (s, TI12XX_IRQMUX, p->irqmux);
162   - i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
163   - i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
164   -}
165   -
166   -static u_int ti113x_set_opts (socket_info_t * s)
167   -{
168   - ti113x_state_t *p = &s->state;
169   - u_int mask = 0xffff;
170   -
171   - p->cardctl &= ~TI113X_CCR_ZVENABLE;
172   - p->cardctl |= TI113X_CCR_SPKROUTEN;
173   -
174   - return mask;
175   -}
176   -
177   -/*======================================================================
178   -
179   - Routines to handle common CardBus options
180   -
181   -======================================================================*/
182   -
183   -/* Default settings for PCI command configuration register */
184   -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
185   - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
186   -
187   -static void cb_get_state (socket_info_t * s)
188   -{
189   - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
190   - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
191   - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
192   - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
193   - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
194   - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
195   -}
196   -
197   -static void cb_set_state (socket_info_t * s)
198   -{
199   - pci_writel (s, CB_LEGACY_MODE_BASE, 0);
200   - pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
201   - pci_writew (s, PCI_COMMAND, CMD_DFLT);
202   - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
203   - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
204   - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
205   - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
206   - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
207   - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
208   -}
209   -
210   -static void cb_set_opts (socket_info_t * s)
211   -{
212   - if (s->cache == 0)
213   - s->cache = 8;
214   - if (s->pci_lat == 0)
215   - s->pci_lat = 0xa8;
216   - if (s->cb_lat == 0)
217   - s->cb_lat = 0xb0;
218   -}
219   -
220   -/*======================================================================
221   -
222   - Power control for Cardbus controllers: used both for 16-bit and
223   - Cardbus cards.
224   -
225   -======================================================================*/
226   -
227   -static int cb_set_power (socket_info_t * s, socket_state_t * state)
228   -{
229   - u_int reg = 0;
230   -
231   - /* restart card voltage detection if it seems appropriate */
232   - if ((state->Vcc == 0) && (state->Vpp == 0) &&
233   - !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
234   - cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
235   - switch (state->Vcc) {
236   - case 0:
237   - reg = 0;
238   - break;
239   - case 33:
240   - reg = CB_SC_VCC_3V;
241   - break;
242   - case 50:
243   - reg = CB_SC_VCC_5V;
244   - break;
245   - default:
246   - return -1;
247   - }
248   - switch (state->Vpp) {
249   - case 0:
250   - break;
251   - case 33:
252   - reg |= CB_SC_VPP_3V;
253   - break;
254   - case 50:
255   - reg |= CB_SC_VPP_5V;
256   - break;
257   - case 120:
258   - reg |= CB_SC_VPP_12V;
259   - break;
260   - default:
261   - return -1;
262   - }
263   - if (reg != cb_readl (s, CB_SOCKET_CONTROL))
264   - cb_writel (s, CB_SOCKET_CONTROL, reg);
265   -
266   - return 0;
267   -}
268   -
269   -/*======================================================================
270   -
271   - Generic routines to get and set controller options
272   -
273   -======================================================================*/
274   -
275   -static void get_bridge_state (socket_info_t * s)
276   -{
277   - ti113x_get_state (s);
278   - cb_get_state (s);
279   -}
280   -
281   -static void set_bridge_state (socket_info_t * s)
282   -{
283   - cb_set_state (s);
284   - i365_set (s, I365_GBLCTL, 0x00);
285   - i365_set (s, I365_GENCTL, 0x00);
286   - ti113x_set_state (s);
287   -}
288   -
289   -static void set_bridge_opts (socket_info_t * s)
290   -{
291   - ti113x_set_opts (s);
292   - cb_set_opts (s);
293   -}
294   -
295   -/*====================================================================*/
296   -#define PD67_EXT_INDEX 0x2e /* Extension index */
297   -#define PD67_EXT_DATA 0x2f /* Extension data */
298   -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
299   -
300   -#define pd67_ext_get(s, r) \
301   - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
302   -
303   -static int i365_get_status (socket_info_t * s, u_int * value)
304   -{
305   - u_int status;
306   -
307   - status = i365_get (s, I365_IDENT);
308   - status = i365_get (s, I365_STATUS);
309   - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
310   - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
311   - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
312   - } else {
313   - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
314   - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
315   - }
316   - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
317   - *value |= (status & I365_CS_READY) ? SS_READY : 0;
318   - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
319   -
320   - status = cb_readl (s, CB_SOCKET_STATE);
321   - *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
322   - *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
323   - *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
324   - *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
325   - /* For now, ignore cards with unsupported voltage keys */
326   - if (*value & SS_XVCARD)
327   - *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
328   -
329   - return 0;
330   -} /* i365_get_status */
331   -
332   -static int i365_set_socket (socket_info_t * s, socket_state_t * state)
333   -{
334   - u_char reg;
335   -
336   - set_bridge_state (s);
337   -
338   - /* IO card, RESET flag */
339   - reg = 0;
340   - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
341   - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
342   - i365_set (s, I365_INTCTL, reg);
343   -
344   - reg = I365_PWR_NORESET;
345   - if (state->flags & SS_PWR_AUTO)
346   - reg |= I365_PWR_AUTO;
347   - if (state->flags & SS_OUTPUT_ENA)
348   - reg |= I365_PWR_OUT;
349   -
350   - cb_set_power (s, state);
351   - reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
352   -
353   - if (reg != i365_get (s, I365_POWER))
354   - i365_set (s, I365_POWER, reg);
355   -
356   - return 0;
357   -} /* i365_set_socket */
358   -
359   -/*====================================================================*/
360   -
361   -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
362   -{
363   - u_short base, i;
364   - u_char map;
365   -
366   - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
367   - mem->map, mem->flags, mem->speed,
368   - mem->sys_start, mem->sys_stop, mem->card_start);
369   -
370   - map = mem->map;
371   - if ((map > 4) ||
372   - (mem->card_start > 0x3ffffff) ||
373   - (mem->sys_start > mem->sys_stop) ||
374   - (mem->speed > 1000)) {
375   - return -1;
376   - }
377   -
378   - /* Turn off the window before changing anything */
379   - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
380   - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
381   -
382   - /* Take care of high byte, for PCI controllers */
383   - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
384   -
385   - base = I365_MEM (map);
386   - i = (mem->sys_start >> 12) & 0x0fff;
387   - if (mem->flags & MAP_16BIT)
388   - i |= I365_MEM_16BIT;
389   - if (mem->flags & MAP_0WS)
390   - i |= I365_MEM_0WS;
391   - i365_set_pair (s, base + I365_W_START, i);
392   -
393   - i = (mem->sys_stop >> 12) & 0x0fff;
394   - switch (mem->speed / CYCLE_TIME) {
395   - case 0:
396   - break;
397   - case 1:
398   - i |= I365_MEM_WS0;
399   - break;
400   - case 2:
401   - i |= I365_MEM_WS1;
402   - break;
403   - default:
404   - i |= I365_MEM_WS1 | I365_MEM_WS0;
405   - break;
406   - }
407   - i365_set_pair (s, base + I365_W_STOP, i);
408   -
409   - i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
410   - if (mem->flags & MAP_WRPROT)
411   - i |= I365_MEM_WRPROT;
412   - if (mem->flags & MAP_ATTRIB)
413   - i |= I365_MEM_REG;
414   - i365_set_pair (s, base + I365_W_OFF, i);
415   -
416   - /* Turn on the window if necessary */
417   - if (mem->flags & MAP_ACTIVE)
418   - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
419   - return 0;
420   -} /* i365_set_mem_map */
421   -
422   -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
423   -{
424   - u_char map, ioctl;
425   -
426   - map = io->map;
427   - /* comment out: comparison is always false due to limited range of data type */
428   - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
429   - (io->stop < io->start))
430   - return -1;
431   - /* Turn off the window before changing anything */
432   - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
433   - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
434   - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
435   - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
436   - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
437   - if (io->speed)
438   - ioctl |= I365_IOCTL_WAIT (map);
439   - if (io->flags & MAP_0WS)
440   - ioctl |= I365_IOCTL_0WS (map);
441   - if (io->flags & MAP_16BIT)
442   - ioctl |= I365_IOCTL_16BIT (map);
443   - if (io->flags & MAP_AUTOSZ)
444   - ioctl |= I365_IOCTL_IOCS16 (map);
445   - i365_set (s, I365_IOCTL, ioctl);
446   - /* Turn on the window if necessary */
447   - if (io->flags & MAP_ACTIVE)
448   - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
449   - return 0;
450   -} /* i365_set_io_map */
451   -
452   -/*====================================================================*/
453   -
454   -static int i82365_init (void)
455   -{
456   - u_int val;
457   - int i;
458   -
459   - if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
460   - /* Controller not found */
461   - return 1;
462   - }
463   - debug ("i82365 Device Found!\n");
464   -
465   - pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
466   - socket.cb_phys &= ~0xf;
467   -
468   - get_bridge_state (&socket);
469   - set_bridge_opts (&socket);
470   -
471   - i = i365_get_status (&socket, &val);
472   -
473   - if (val & SS_DETECT) {
474   - if (val & SS_3VCARD) {
475   - state.Vcc = state.Vpp = 33;
476   - puts (" 3.3V card found: ");
477   - } else if (!(val & SS_XVCARD)) {
478   - state.Vcc = state.Vpp = 50;
479   - puts (" 5.0V card found: ");
480   - } else {
481   - puts ("i82365: unsupported voltage key\n");
482   - state.Vcc = state.Vpp = 0;
483   - }
484   - } else {
485   - /* No card inserted */
486   - puts ("No card\n");
487   - return 1;
488   - }
489   -
490   - state.flags = SS_IOCARD | SS_OUTPUT_ENA;
491   - state.csc_mask = 0;
492   - state.io_irq = 0;
493   -
494   - i365_set_socket (&socket, &state);
495   -
496   - for (i = 500; i; i--) {
497   - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
498   - break;
499   - udelay (1000);
500   - }
501   -
502   - if (i == 0) {
503   - /* PC Card not ready for data transfer */
504   - puts ("i82365 PC Card not ready for data transfer\n");
505   - return 1;
506   - }
507   - debug (" PC Card ready for data transfer: ");
508   -
509   - mem.map = 0;
510   - mem.flags = MAP_ATTRIB | MAP_ACTIVE;
511   - mem.speed = 300;
512   - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
513   - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
514   - mem.card_start = 0;
515   - i365_set_mem_map (&socket, &mem);
516   -
517   - io.map = 0;
518   - io.flags = MAP_AUTOSZ | MAP_ACTIVE;
519   - io.speed = 0;
520   - io.start = 0x0100;
521   - io.stop = 0x010F;
522   - i365_set_io_map (&socket, &io);
523   -
524   -#ifdef DEBUG
525   - i82365_dump_regions (socket.dev);
526   -#endif
527   -
528   - return 0;
529   -}
530   -
531   -static void i82365_exit (void)
532   -{
533   - io.map = 0;
534   - io.flags = 0;
535   - io.speed = 0;
536   - io.start = 0;
537   - io.stop = 0x1;
538   -
539   - i365_set_io_map (&socket, &io);
540   -
541   - mem.map = 0;
542   - mem.flags = 0;
543   - mem.speed = 0;
544   - mem.sys_start = 0;
545   - mem.sys_stop = 0x1000;
546   - mem.card_start = 0;
547   -
548   - i365_set_mem_map (&socket, &mem);
549   -
550   - socket.state.sysctl &= 0xFFFF00FF;
551   -
552   - state.Vcc = state.Vpp = 0;
553   -
554   - i365_set_socket (&socket, &state);
555   -}
556   -
557   -int pcmcia_on (void)
558   -{
559   - u_int rc;
560   -
561   - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
562   -
563   - rc = i82365_init();
564   - if (rc)
565   - goto exit;
566   -
567   - rc = check_ide_device(0);
568   - if (rc == 0)
569   - goto exit;
570   -
571   - i82365_exit();
572   -
573   -exit:
574   - return rc;
575   -}
576   -
577   -#if defined(CONFIG_CMD_PCMCIA)
578   -int pcmcia_off (void)
579   -{
580   - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
581   -
582   - i82365_exit();
583   -
584   - return 0;
585   -}
586   -#endif
587   -
588   -/*======================================================================
589   -
590   - Debug stuff
591   -
592   -======================================================================*/
593   -
594   -#ifdef DEBUG
595   -static void i82365_dump_regions (pci_dev_t dev)
596   -{
597   - u_int tmp[2];
598   - u_int *mem = (void *) socket.cb_phys;
599   - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
600   - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
601   -
602   - pci_read_config_dword (dev, 0x00, tmp + 0);
603   - pci_read_config_dword (dev, 0x80, tmp + 1);
604   -
605   - printf ("PCI CONF: %08X ... %08X\n",
606   - tmp[0], tmp[1]);
607   - printf ("PCI MEM: ... %08X ... %08X\n",
608   - mem[0x8 / 4], mem[0x800 / 4]);
609   - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
610   - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
611   - cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
612   - printf ("CIS CONF: %02X %02X %02X ...\n",
613   - cis[0x200], cis[0x202], cis[0x204]);
614   - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
615   - ide[0], ide[1], ide[2], ide[3],
616   - ide[4], ide[5], ide[6], ide[7]);
617   -}
618   -#endif /* DEBUG */
619   -
620   -#endif /* CONFIG_I82365 */
configs/atc_defconfig
View file @ 9067b30
1   -CONFIG_PPC=y
2   -CONFIG_MPC8260=y
3   -CONFIG_TARGET_ATC=y
doc/README.scrapyard
Diff comments   View file @ 9067b30
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +atc powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
15 16 CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
16 17 CPU87 powerpc mpc8260 - -
17 18 ep82xxm powerpc mpc8260 - -
drivers/rtc/Makefile
Diff comments   View file @ 9067b30
... ... @@ -11,7 +11,6 @@
11 11 obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
12 12 obj-y += date.o
13 13 obj-$(CONFIG_RTC_DAVINCI) += davinci.o
14   -obj-$(CONFIG_RTC_DS12887) += ds12887.o
15 14 obj-$(CONFIG_RTC_DS1302) += ds1302.o
16 15 obj-$(CONFIG_RTC_DS1306) += ds1306.o
17 16 obj-$(CONFIG_RTC_DS1307) += ds1307.o
drivers/rtc/ds12887.c
View file @ 9067b30
1   -/*
2   - * (C) Copyright 2003
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -/*
8   - * Date & Time support for the DS12887 RTC
9   - */
10   -
11   -#undef RTC_DEBUG
12   -
13   -#include <common.h>
14   -#include <command.h>
15   -#include <config.h>
16   -#include <rtc.h>
17   -
18   -#if defined(CONFIG_CMD_DATE)
19   -
20   -#define RTC_SECONDS 0x00
21   -#define RTC_SECONDS_ALARM 0x01
22   -#define RTC_MINUTES 0x02
23   -#define RTC_MINUTES_ALARM 0x03
24   -#define RTC_HOURS 0x04
25   -#define RTC_HOURS_ALARM 0x05
26   -#define RTC_DAY_OF_WEEK 0x06
27   -#define RTC_DATE_OF_MONTH 0x07
28   -#define RTC_MONTH 0x08
29   -#define RTC_YEAR 0x09
30   -#define RTC_CONTROL_A 0x0A
31   -#define RTC_CONTROL_B 0x0B
32   -#define RTC_CONTROL_C 0x0C
33   -#define RTC_CONTROL_D 0x0D
34   -
35   -#define RTC_CA_UIP 0x80
36   -#define RTC_CB_DM 0x04
37   -#define RTC_CB_24_12 0x02
38   -#define RTC_CB_SET 0x80
39   -
40   -#if defined(CONFIG_ATC)
41   -
42   -static uchar rtc_read (uchar reg)
43   -{
44   - uchar val;
45   -
46   - *(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
47   - __asm__ __volatile__ ("sync");
48   -
49   - val = *(volatile unsigned char*)(RTC_PORT_DATA);
50   - return (val);
51   -}
52   -
53   -static void rtc_write (uchar reg, uchar val)
54   -{
55   - *(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
56   - __asm__ __volatile__ ("sync");
57   -
58   - *(volatile unsigned char*)(RTC_PORT_DATA) = val;
59   - __asm__ __volatile__ ("sync");
60   -}
61   -
62   -#else
63   -# error Board specific rtc access functions should be supplied
64   -#endif
65   -
66   -int rtc_get (struct rtc_time *tmp)
67   -{
68   - uchar sec, min, hour, mday, wday, mon, year;
69   -
70   - /* check if rtc is available for access */
71   - while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP)
72   - ;
73   -
74   - sec = rtc_read(RTC_SECONDS);
75   - min = rtc_read(RTC_MINUTES);
76   - hour = rtc_read(RTC_HOURS);
77   - mday = rtc_read(RTC_DATE_OF_MONTH);
78   - wday = rtc_read(RTC_DAY_OF_WEEK);
79   - mon = rtc_read(RTC_MONTH);
80   - year = rtc_read(RTC_YEAR);
81   -
82   -#ifdef RTC_DEBUG
83   - printf( "Get RTC year: %d; mon: %d; mday: %d; wday: %d; "
84   - "hr: %d; min: %d; sec: %d\n",
85   - year, mon, mday, wday, hour, min, sec );
86   -
87   - printf ( "Alarms: hour: %02x min: %02x sec: %02x\n",
88   - rtc_read (RTC_HOURS_ALARM),
89   - rtc_read (RTC_MINUTES_ALARM),
90   - rtc_read (RTC_SECONDS_ALARM) );
91   -#endif
92   -
93   - if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
94   - { /* Information is in BCD format */
95   -printf(" Get: Convert BSD to BIN\n");
96   - tmp->tm_sec = bcd2bin (sec & 0x7F);
97   - tmp->tm_min = bcd2bin (min & 0x7F);
98   - tmp->tm_hour = bcd2bin (hour & 0x3F);
99   - tmp->tm_mday = bcd2bin (mday & 0x3F);
100   - tmp->tm_mon = bcd2bin (mon & 0x1F);
101   - tmp->tm_year = bcd2bin (year);
102   - tmp->tm_wday = bcd2bin (wday & 0x07);
103   - }
104   -else
105   - {
106   - tmp->tm_sec = sec & 0x7F;
107   - tmp->tm_min = min & 0x7F;
108   - tmp->tm_hour = hour & 0x3F;
109   - tmp->tm_mday = mday & 0x3F;
110   - tmp->tm_mon = mon & 0x1F;
111   - tmp->tm_year = year;
112   - tmp->tm_wday = wday & 0x07;
113   - }
114   -
115   -
116   - if(tmp->tm_year<70)
117   - tmp->tm_year+=2000;
118   - else
119   - tmp->tm_year+=1900;
120   -
121   - tmp->tm_yday = 0;
122   - tmp->tm_isdst= 0;
123   -#ifdef RTC_DEBUG
124   - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
125   - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
126   - tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
127   -#endif
128   -
129   - return 0;
130   -}
131   -
132   -int rtc_set (struct rtc_time *tmp)
133   -{
134   - uchar save_ctrl_b;
135   - uchar sec, min, hour, mday, wday, mon, year;
136   -
137   -#ifdef RTC_DEBUG
138   - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
139   - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
140   - tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
141   -#endif
142   -
143   - if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
144   - { /* Information is in BCD format */
145   - year = bin2bcd(tmp->tm_year % 100);
146   - mon = bin2bcd(tmp->tm_mon);
147   - wday = bin2bcd(tmp->tm_wday);
148   - mday = bin2bcd(tmp->tm_mday);
149   - hour = bin2bcd(tmp->tm_hour);
150   - min = bin2bcd(tmp->tm_min);
151   - sec = bin2bcd(tmp->tm_sec);
152   - }
153   - else
154   - {
155   - year = tmp->tm_year % 100;
156   - mon = tmp->tm_mon;
157   - wday = tmp->tm_wday;
158   - mday = tmp->tm_mday;
159   - hour = tmp->tm_hour;
160   - min = tmp->tm_min;
161   - sec = tmp->tm_sec;
162   - }
163   -
164   - /* disables the RTC to update the regs */
165   - save_ctrl_b = rtc_read(RTC_CONTROL_B);
166   - save_ctrl_b |= RTC_CB_SET;
167   - rtc_write(RTC_CONTROL_B, save_ctrl_b);
168   -
169   - rtc_write (RTC_YEAR, year);
170   - rtc_write (RTC_MONTH, mon);
171   - rtc_write (RTC_DAY_OF_WEEK, wday);
172   - rtc_write (RTC_DATE_OF_MONTH, mday);
173   - rtc_write (RTC_HOURS, hour);
174   - rtc_write (RTC_MINUTES, min);
175   - rtc_write (RTC_SECONDS, sec);
176   -
177   - /* enables the RTC to update the regs */
178   - save_ctrl_b &= ~RTC_CB_SET;
179   - rtc_write(RTC_CONTROL_B, save_ctrl_b);
180   -
181   - return 0;
182   -}
183   -
184   -void rtc_reset (void)
185   -{
186   - struct rtc_time tmp;
187   - uchar ctrl_rg;
188   -
189   - ctrl_rg = RTC_CB_SET;
190   - rtc_write(RTC_CONTROL_B,ctrl_rg);
191   -
192   - tmp.tm_year = 1970 % 100;
193   - tmp.tm_mon = 1;
194   - tmp.tm_mday= 1;
195   - tmp.tm_hour = 0;
196   - tmp.tm_min = 0;
197   - tmp.tm_sec = 0;
198   -
199   -#ifdef RTC_DEBUG
200   - printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
201   - tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
202   - tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
203   -#endif
204   -
205   - ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM;
206   - rtc_write(RTC_CONTROL_B,ctrl_rg);
207   - rtc_set(&tmp);
208   -
209   - rtc_write(RTC_HOURS_ALARM, 0),
210   - rtc_write(RTC_MINUTES_ALARM, 0),
211   - rtc_write(RTC_SECONDS_ALARM, 0);
212   -
213   - ctrl_rg = RTC_CB_24_12 | RTC_CB_DM;
214   - rtc_write(RTC_CONTROL_B,ctrl_rg);
215   -}
216   -
217   -#endif
include/configs/atc.h
View file @ 9067b30
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_ATC 1 /* ...on a ATC board */
21   -#define CONFIG_CPM2 1 /* Has a CPM2 */
22   -
23   -#define CONFIG_SYS_TEXT_BASE 0xFF000000
24   -
25   -/*
26   - * select serial console configuration
27   - *
28   - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
29   - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
30   - * for SCC).
31   - *
32   - * if CONFIG_CONS_NONE is defined, then the serial console routines must
33   - * defined elsewhere (for example, on the cogent platform, there are serial
34   - * ports on the motherboard which are used for the serial console - see
35   - * cogent/cma101/serial.[ch]).
36   - */
37   -#define CONFIG_CONS_ON_SMC /* define if console on SMC */
38   -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
39   -#undef CONFIG_CONS_NONE /* define if console on something else*/
40   -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
41   -
42   -#define CONFIG_BAUDRATE 115200
43   -
44   -/*
45   - * select ethernet configuration
46   - *
47   - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
48   - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
49   - * for FCC)
50   - *
51   - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
52   - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
53   - */
54   -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
55   -#undef CONFIG_ETHER_NONE /* define if ether on something else */
56   -#define CONFIG_ETHER_ON_FCC
57   -
58   -#define CONFIG_ETHER_ON_FCC2
59   -
60   -/*
61   - * - Rx-CLK is CLK13
62   - * - Tx-CLK is CLK14
63   - * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
64   - * - Enable Full Duplex in FSMR
65   - */
66   -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
67   -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
68   -# define CONFIG_SYS_CPMFCR_RAMTYPE 0
69   -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
70   -
71   -#define CONFIG_ETHER_ON_FCC3
72   -
73   -/*
74   - * - Rx-CLK is CLK15
75   - * - Tx-CLK is CLK16
76   - * - RAM for BD/Buffers is on the local Bus (see 28-13)
77   - * - Enable Half Duplex in FSMR
78   - */
79   -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
80   -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
81   -
82   -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
83   -#define CONFIG_8260_CLKIN 64000000 /* in Hz */
84   -
85   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
86   -
87   -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
88   -
89   -#define CONFIG_PREBOOT \
90   - "echo;" \
91   - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
92   - "echo"
93   -
94   -#undef CONFIG_BOOTARGS
95   -#define CONFIG_BOOTCOMMAND \
96   - "bootp;" \
97   - "setenv bootargs root=/dev/nfs rw " \
98   - "nfsroot=${serverip}:${rootpath} " \
99   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
100   - "bootm"
101   -
102   -/*-----------------------------------------------------------------------
103   - * Miscellaneous configuration options
104   - */
105   -
106   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
107   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
108   -
109   -
110   -/*
111   - * BOOTP options
112   - */
113   -#define CONFIG_BOOTP_SUBNETMASK
114   -#define CONFIG_BOOTP_GATEWAY
115   -#define CONFIG_BOOTP_HOSTNAME
116   -#define CONFIG_BOOTP_BOOTPATH
117   -#define CONFIG_BOOTP_BOOTFILESIZE
118   -
119   -
120   -/*
121   - * Command line configuration.
122   - */
123   -#include <config_cmd_default.h>
124   -
125   -#define CONFIG_CMD_EEPROM
126   -#define CONFIG_CMD_PCI
127   -#define CONFIG_CMD_PCMCIA
128   -#define CONFIG_CMD_DATE
129   -#define CONFIG_CMD_IDE
130   -
131   -
132   -#define CONFIG_DOS_PARTITION
133   -
134   -/*
135   - * Miscellaneous configurable options
136   - */
137   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
138   -#if defined(CONFIG_CMD_KGDB)
139   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
140   -#else
141   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
142   -#endif
143   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
146   -
147   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
148   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
149   -
150   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
151   -
152   -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
153   -
154   -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
155   -
156   -#define CONFIG_SYS_ALLOC_DPRAM
157   -
158   -#undef CONFIG_WATCHDOG /* watchdog disabled */
159   -
160   -#define CONFIG_SPI
161   -
162   -#define CONFIG_RTC_DS12887
163   -
164   -#define RTC_BASE_ADDR 0xF5000000
165   -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
166   -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
167   -
168   -#define CONFIG_MISC_INIT_R
169   -
170   -/*
171   - * For booting Linux, the board info and command line data
172   - * have to be in the first 8 MB of memory, since this is
173   - * the maximum mapped by the Linux kernel during initialization.
174   - */
175   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
176   -
177   -/*-----------------------------------------------------------------------
178   - * Flash configuration
179   - */
180   -
181   -#define CONFIG_SYS_FLASH_BASE 0xFF000000
182   -#define CONFIG_SYS_FLASH_SIZE 0x00800000
183   -
184   -/*-----------------------------------------------------------------------
185   - * FLASH organization
186   - */
187   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
188   -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
189   -
190   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
191   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
192   -
193   -#define CONFIG_FLASH_16BIT
194   -
195   -/*-----------------------------------------------------------------------
196   - * Hard Reset Configuration Words
197   - *
198   - * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
199   - * defines for the various registers affected by the HRCW e.g. changing
200   - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
201   - */
202   -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
203   - HRCW_BPS10 |\
204   - HRCW_APPC10)
205   -
206   -/* no slaves so just fill with zeros */
207   -#define CONFIG_SYS_HRCW_SLAVE1 0
208   -#define CONFIG_SYS_HRCW_SLAVE2 0
209   -#define CONFIG_SYS_HRCW_SLAVE3 0
210   -#define CONFIG_SYS_HRCW_SLAVE4 0
211   -#define CONFIG_SYS_HRCW_SLAVE5 0
212   -#define CONFIG_SYS_HRCW_SLAVE6 0
213   -#define CONFIG_SYS_HRCW_SLAVE7 0
214   -
215   -/*-----------------------------------------------------------------------
216   - * Internal Memory Mapped Register
217   - */
218   -#define CONFIG_SYS_IMMR 0xF0000000
219   -
220   -/*-----------------------------------------------------------------------
221   - * Definitions for initial stack pointer and data area (in DPRAM)
222   - */
223   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
224   -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
225   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
227   -
228   -/*-----------------------------------------------------------------------
229   - * Start addresses for the final memory configuration
230   - * (Set up by the startup code)
231   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
232   - *
233   - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
234   - */
235   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
236   -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
237   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
238   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
239   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
240   -
241   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
242   -# define CONFIG_SYS_RAMBOOT
243   -#endif
244   -
245   -#define CONFIG_PCI
246   -#define CONFIG_PCI_INDIRECT_BRIDGE
247   -#define CONFIG_PCI_PNP
248   -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
249   -
250   -#if 1
251   -/* environment is in Flash */
252   -#define CONFIG_ENV_IS_IN_FLASH 1
253   -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
254   -# define CONFIG_ENV_SIZE 0x10000
255   -# define CONFIG_ENV_SECT_SIZE 0x10000
256   -#else
257   -#define CONFIG_ENV_IS_IN_EEPROM 1
258   -#define CONFIG_ENV_OFFSET 0
259   -#define CONFIG_ENV_SIZE 2048
260   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
261   -#endif
262   -
263   -/*-----------------------------------------------------------------------
264   - * Cache Configuration
265   - */
266   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
267   -#if defined(CONFIG_CMD_KGDB)
268   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
269   -#endif
270   -
271   -/*-----------------------------------------------------------------------
272   - * HIDx - Hardware Implementation-dependent Registers 2-11
273   - *-----------------------------------------------------------------------
274   - * HID0 also contains cache control - initially enable both caches and
275   - * invalidate contents, then the final state leaves only the instruction
276   - * cache enabled. Note that Power-On and Hard reset invalidate the caches,
277   - * but Soft reset does not.
278   - *
279   - * HID1 has only read-only information - nothing to set.
280   - */
281   -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
282   - HID0_DCI|HID0_IFEM|HID0_ABE)
283   -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
284   -#define CONFIG_SYS_HID2 0
285   -
286   -/*-----------------------------------------------------------------------
287   - * RMR - Reset Mode Register 5-5
288   - *-----------------------------------------------------------------------
289   - * turn on Checkstop Reset Enable
290   - */
291   -#define CONFIG_SYS_RMR RMR_CSRE
292   -
293   -/*-----------------------------------------------------------------------
294   - * BCR - Bus Configuration 4-25
295   - *-----------------------------------------------------------------------
296   - */
297   -#define BCR_APD01 0x10000000
298   -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
299   -
300   -/*-----------------------------------------------------------------------
301   - * SIUMCR - SIU Module Configuration 4-31
302   - *-----------------------------------------------------------------------
303   - */
304   -#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
305   - SIUMCR_CS10PC00|SIUMCR_BCTLC10)
306   -
307   -/*-----------------------------------------------------------------------
308   - * SYPCR - System Protection Control 4-35
309   - * SYPCR can only be written once after reset!
310   - *-----------------------------------------------------------------------
311   - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
312   - */
313   -#if defined(CONFIG_WATCHDOG)
314   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
315   - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
316   -#else
317   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
318   - SYPCR_SWRI|SYPCR_SWP)
319   -#endif /* CONFIG_WATCHDOG */
320   -
321   -/*-----------------------------------------------------------------------
322   - * TMCNTSC - Time Counter Status and Control 4-40
323   - *-----------------------------------------------------------------------
324   - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
325   - * and enable Time Counter
326   - */
327   -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
328   -
329   -/*-----------------------------------------------------------------------
330   - * PISCR - Periodic Interrupt Status and Control 4-42
331   - *-----------------------------------------------------------------------
332   - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
333   - * Periodic timer
334   - */
335   -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
336   -
337   -/*-----------------------------------------------------------------------
338   - * SCCR - System Clock Control 9-8
339   - *-----------------------------------------------------------------------
340   - * Ensure DFBRG is Divide by 16
341   - */
342   -#define CONFIG_SYS_SCCR SCCR_DFBRG01
343   -
344   -/*-----------------------------------------------------------------------
345   - * RCCR - RISC Controller Configuration 13-7
346   - *-----------------------------------------------------------------------
347   - */
348   -#define CONFIG_SYS_RCCR 0
349   -
350   -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
351   -/*-----------------------------------------------------------------------
352   - * MPTPR - Memory Refresh Timer Prescaler Register 10-18
353   - *-----------------------------------------------------------------------
354   - */
355   -#define CONFIG_SYS_MPTPR 0x1F00
356   -
357   -/*-----------------------------------------------------------------------
358   - * PSRT - Refresh Timer Register 10-16
359   - *-----------------------------------------------------------------------
360   - */
361   -#define CONFIG_SYS_PSRT 0x0f
362   -
363   -/*-----------------------------------------------------------------------
364   - * PSRT - SDRAM Mode Register 10-10
365   - *-----------------------------------------------------------------------
366   - */
367   -
368   - /* SDRAM initialization values for 8-column chips
369   - */
370   -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
371   - ORxS_BPD_4 |\
372   - ORxS_ROWST_PBI1_A7 |\
373   - ORxS_NUMR_12)
374   -
375   -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
376   - PSDMR_SDAM_A15_IS_A5 |\
377   - PSDMR_BSMA_A15_A17 |\
378   - PSDMR_SDA10_PBI1_A7 |\
379   - PSDMR_RFRC_7_CLK |\
380   - PSDMR_PRETOACT_3W |\
381   - PSDMR_ACTTORW_2W |\
382   - PSDMR_LDOTOPRE_1C |\
383   - PSDMR_WRC_1C |\
384   - PSDMR_CL_2)
385   -
386   - /* SDRAM initialization values for 9-column chips
387   - */
388   -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
389   - ORxS_BPD_4 |\
390   - ORxS_ROWST_PBI1_A6 |\
391   - ORxS_NUMR_12)
392   -
393   -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
394   - PSDMR_SDAM_A16_IS_A5 |\
395   - PSDMR_BSMA_A15_A17 |\
396   - PSDMR_SDA10_PBI1_A6 |\
397   - PSDMR_RFRC_7_CLK |\
398   - PSDMR_PRETOACT_3W |\
399   - PSDMR_ACTTORW_2W |\
400   - PSDMR_LDOTOPRE_1C |\
401   - PSDMR_WRC_1C |\
402   - PSDMR_CL_2)
403   -
404   -/*
405   - * Init Memory Controller:
406   - *
407   - * Bank Bus Machine PortSz Device
408   - * ---- --- ------- ------ ------
409   - * 0 60x GPCM 8 bit Boot ROM
410   - * 1 60x GPCM 64 bit FLASH
411   - * 2 60x SDRAM 64 bit SDRAM
412   - *
413   - */
414   -
415   -#define CONFIG_SYS_MRS_OFFS 0x00000000
416   -
417   -/* Bank 0 - FLASH
418   - */
419   -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
420   - BRx_PS_16 |\
421   - BRx_MS_GPCM_P |\
422   - BRx_V)
423   -
424   -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
425   - ORxG_CSNT |\
426   - ORxG_ACS_DIV1 |\
427   - ORxG_SCY_3_CLK |\
428   - ORxU_EHTR_8IDLE)
429   -
430   -
431   -/* Bank 2 - 60x bus SDRAM
432   - */
433   -#ifndef CONFIG_SYS_RAMBOOT
434   -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
435   - BRx_PS_64 |\
436   - BRx_MS_SDRAM_P |\
437   - BRx_V)
438   -
439   -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
440   -
441   -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
442   -#endif /* CONFIG_SYS_RAMBOOT */
443   -
444   -#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
445   - BRx_PS_8 |\
446   - BRx_MS_UPMA |\
447   - BRx_V)
448   -
449   -#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
450   -
451   -/*-----------------------------------------------------------------------
452   - * PCMCIA stuff
453   - *-----------------------------------------------------------------------
454   - *
455   - */
456   -#define CONFIG_I82365
457   -
458   -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
459   -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
460   -
461   -/*-----------------------------------------------------------------------
462   - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
463   - *-----------------------------------------------------------------------
464   - */
465   -
466   -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
467   -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
468   -
469   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
470   -#undef CONFIG_IDE_LED /* LED for ide not supported */
471   -#undef CONFIG_IDE_RESET /* reset for ide not supported */
472   -
473   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
474   -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
475   -
476   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
477   -
478   -#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
479   -
480   -/* Offset for data I/O */
481   -#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
482   -
483   -/* Offset for normal register accesses */
484   -#define CONFIG_SYS_ATA_REG_OFFSET 0x100
485   -
486   -/* Offset for alternate registers */
487   -#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
488   -
489   -#endif /* __CONFIG_H */
... ... @@ -23,8 +23,6 @@
23 23  
24 24 #if defined(CONFIG_TQM8xxL)
25 25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26   -#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
27   -# define CONFIG_PCMCIA_SLOT_A
28 26 #else
29 27 # error "PCMCIA Slot not configured"
30 28 #endif