Eric Lee / smarc-uboot

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Commit 90a2f7171182f3b96c28b2dcff67b02a3164cdb1

Authored by Vikas Manocha
Committed by Jagan Teki
1 parent c0535c0ef0
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

spi: cadence_qspi: get sram size from device tree 

sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>

Showing 5 changed files with 5 additions and 5 deletions Side-by-side Diff

arch/arm/dts/socfpga.dtsi
Diff comments   View file @ 90a2f71
... ... @@ -639,6 +639,7 @@
639 639 ext-decoder = <0>; /* external decoder */
640 640 num-cs = <4>;
641 641 fifo-depth = <128>;
  642 + sram-size = <128>;
642 643 bus-num = <2>;
643 644 status = "disabled";
644 645 };
arch/arm/dts/stv0991.dts
Diff comments   View file @ 90a2f71
... ... @@ -35,6 +35,7 @@
35 35 ext-decoder = <0>; /* external decoder */
36 36 num-cs = <4>;
37 37 fifo-depth = <256>;
  38 + sram-size = <256>;
38 39 bus-num = <0>;
39 40 status = "okay";
40 41  
drivers/spi/cadence_qspi.c
Diff comments   View file @ 90a2f71
... ... @@ -309,6 +309,7 @@
309 309 plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
310 310 plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
311 311 plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
  312 + plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
312 313  
313 314 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
314 315 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
drivers/spi/cadence_qspi.h
Diff comments   View file @ 90a2f71
... ... @@ -25,6 +25,7 @@
25 25 u32 tsd2d_ns;
26 26 u32 tchsh_ns;
27 27 u32 tslch_ns;
  28 + u32 sram_size;
28 29 };
29 30  
30 31 struct cadence_spi_priv {
drivers/spi/cadence_qspi_apb.c
Diff comments   View file @ 90a2f71
... ... @@ -36,9 +36,6 @@
36 36  
37 37 #define CQSPI_FIFO_WIDTH (4)
38 38  
39   -/* Controller sram size in word */
40   -#define CQSPI_REG_SRAM_SIZE_WORD (128)
41   -#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)
42 39 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
43 40  
44 41 /* Transfer mode */
... ... @@ -536,8 +533,7 @@
536 533 writel(0, plat->regbase + CQSPI_REG_REMAP);
537 534  
538 535 /* Indirect mode configurations */
539   - writel(CQSPI_REG_SRAM_PARTITION_RD,
540   - plat->regbase + CQSPI_REG_SRAMPARTITION);
  536 + writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
541 537  
542 538 /* Disable all interrupts */
543 539 writel(0, plat->regbase + CQSPI_REG_IRQMASK);