x86: chromebook_link: dts: Add PCH and LPC devices

The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>

x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass
1 parent a274e9cac5
Showing 5 changed files with 55 additions and 34 deletions Side-by-side Diff
arch/x86/cpu/ivybridge/cpu.c
arch/x86/cpu/ivybridge/lpc.c
arch/x86/dts/chromebook_link.dts
include/fdtdec.h
lib/fdtdec.c
@@ -142,7 +142,7 @@
 	/* TODO(sjg@chromium.org): Get rid of gd->hose */
 	gd->hose = hose;
  
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
 	if (node < 0)
 		return -ENOENT;
 	ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
@@ -510,7 +510,7 @@
 	pci_write_bar32(hose, dev, 3, 0x800);
 	pci_write_bar32(hose, dev, 4, 0x900);
  
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
 	if (node < 0)
 		return -ENOENT;
  
@@ -568,4 +568,15 @@
 	writew(0x0010, RCB_REG(DISPBDF));
 	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
+
+static const struct udevice_id bd82x6x_lpc_ids[] = {
+	{ .compatible = "intel,bd82x6x-lpc" },
+	{ }
+};
+
+U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
+	.name		= "lpc",
+	.id		= UCLASS_LPC,
+	.of_match	= bd82x6x_lpc_ids,
+};
@@ -8,7 +8,7 @@
 	compatible = "google,link", "intel,celeron-ivybridge";
  
 	aliases {
-		spi0 = "/spi";
+		spi0 = "/pci/pch/spi";
 	};
  
 	config {
@@ -151,26 +151,6 @@
 		};
 	};
  
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#size-cells = <1>;
-			#address-cells = <1>;
-			reg = <0>;
-			compatible = "winbond,w25q64", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				/* Alignment: 4k (for updating) */
-				reg = <0x003e0000 0x00010000>;
-				type = "wiped";
-				wipe-value = [ff];
-			};
-		};
-	};
-
 	pci {
 		compatible = "intel,pci-ivybridge", "pci-x86";
 		#address-cells = <3>;
  
@@ -199,9 +179,10 @@
 			intel,pch-backlight = <0x04000000>;
 		};
  
-		lpc {
+		pch {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,bd82x6x";
+			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			gen-dec = <0x800 0xfc 0x900 0xfc>;
  
  
@@ -212,17 +193,44 @@
 						1 0 0 0 0 0 0 0>;
 			/* Enable EC SMI source */
 			intel,alt-gp-smi-enable = <0x0100>;
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+							"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+						type = "wiped";
+						wipe-value = [ff];
+					};
+				};
+			};
  
-			cros-ec@200 {
-				compatible = "google,cros-ec";
-				reg = <0x204 1 0x200 1 0x880 0x80>;
-
-				/* Describes the flash memory within the EC */
+			lpc {
+				compatible = "intel,bd82x6x-lpc";
 				#address-cells = <1>;
-				#size-cells = <1>;
-				flash@8000000 {
-					reg = <0x08000000 0x20000>;
-					erase-value = <0xff>;
+				#size-cells = <0>;
+				cros-ec@200 {
+					compatible = "google,cros-ec";
+					reg = <0x204 1 0x200 1 0x880 0x80>;
+
+					/*
+					 * Describes the flash memory within
+					 * the EC
+					 */
+					#address-cells = <1>;
+					#size-cells = <1>;
+					flash@8000000 {
+						reg = <0x08000000 0x20000>;
+						erase-value = <0xff>;
+					};
 				};
 			};
 		};
@@ -169,6 +169,7 @@
 	COMPAT_INTEL_ICH_SPI,		/* Intel ICH7/9 SPI controller */
 	COMPAT_INTEL_QRK_MRC,		/* Intel Quark MRC */
 	COMPAT_SOCIONEXT_XHCI,		/* Socionext UniPhier xHCI */
+	COMPAT_INTEL_PCH,		/* Intel PCH */
  
 	COMPAT_COUNT,
 };
@@ -67,7 +67,7 @@
 	COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(PARADE_PS8625, "parade,ps8625"),
-	COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x"),
+	COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
 	COMPAT(MEMORY_SPD, "memory-spd"),
 	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
@@ -77,6 +77,7 @@
 	COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
 	COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
 	COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
+	COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 };
  
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
...	...	@@ -142,7 +142,7 @@
142	142	/* TODO(sjg@chromium.org): Get rid of gd->hose */
143	143	gd->hose = hose;
144	144
145		- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
	145	+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
146	146	if (node < 0)
147	147	return -ENOENT;
148	148	ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
...	...	@@ -510,7 +510,7 @@
510	510	pci_write_bar32(hose, dev, 3, 0x800);
511	511	pci_write_bar32(hose, dev, 4, 0x900);
512	512
513		- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
	513	+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
514	514	if (node < 0)
515	515	return -ENOENT;
516	516
...	...	@@ -568,4 +568,15 @@
568	568	writew(0x0010, RCB_REG(DISPBDF));
569	569	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
570	570	}
	571	+
	572	+static const struct udevice_id bd82x6x_lpc_ids[] = {
	573	+ { .compatible = "intel,bd82x6x-lpc" },
	574	+ { }
	575	+};
	576	+
	577	+U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
	578	+ .name = "lpc",
	579	+ .id = UCLASS_LPC,
	580	+ .of_match = bd82x6x_lpc_ids,
	581	+};
...	...	@@ -8,7 +8,7 @@
8	8	compatible = "google,link", "intel,celeron-ivybridge";
9	9
10	10	aliases {
11		- spi0 = "/spi";
	11	+ spi0 = "/pci/pch/spi";
12	12	};
13	13
14	14	config {
...	...	@@ -151,26 +151,6 @@
151	151	};
152	152	};
153	153
154		- spi {
155		- #address-cells = <1>;
156		- #size-cells = <0>;
157		- compatible = "intel,ich-spi";
158		- spi-flash@0 {
159		- #size-cells = <1>;
160		- #address-cells = <1>;
161		- reg = <0>;
162		- compatible = "winbond,w25q64", "spi-flash";
163		- memory-map = <0xff800000 0x00800000>;
164		- rw-mrc-cache {
165		- label = "rw-mrc-cache";
166		- /* Alignment: 4k (for updating) */
167		- reg = <0x003e0000 0x00010000>;
168		- type = "wiped";
169		- wipe-value = [ff];
170		- };
171		- };
172		- };
173		-
174	154	pci {
175	155	compatible = "intel,pci-ivybridge", "pci-x86";
176	156	#address-cells = <3>;
177	157
...	...	@@ -199,9 +179,10 @@
199	179	intel,pch-backlight = <0x04000000>;
200	180	};
201	181
202		- lpc {
	182	+ pch {
203	183	reg = <0x0000f800 0 0 0 0>;
204	184	compatible = "intel,bd82x6x";
	185	+ u-boot,dm-pre-reloc;
205	186	#address-cells = <1>;
206	187	#size-cells = <1>;
207	188	gen-dec = <0x800 0xfc 0x900 0xfc>;
208	189
209	190
...	...	@@ -212,17 +193,44 @@
212	193	1 0 0 0 0 0 0 0>;
213	194	/* Enable EC SMI source */
214	195	intel,alt-gp-smi-enable = <0x0100>;
	196	+ spi {
	197	+ #address-cells = <1>;
	198	+ #size-cells = <0>;
	199	+ compatible = "intel,ich-spi";
	200	+ spi-flash@0 {
	201	+ #size-cells = <1>;
	202	+ #address-cells = <1>;
	203	+ reg = <0>;
	204	+ compatible = "winbond,w25q64",
	205	+ "spi-flash";
	206	+ memory-map = <0xff800000 0x00800000>;
	207	+ rw-mrc-cache {
	208	+ label = "rw-mrc-cache";
	209	+ reg = <0x003e0000 0x00010000>;
	210	+ type = "wiped";
	211	+ wipe-value = [ff];
	212	+ };
	213	+ };
	214	+ };
215	215
216		- cros-ec@200 {
217		- compatible = "google,cros-ec";
218		- reg = <0x204 1 0x200 1 0x880 0x80>;
219		-
220		- /* Describes the flash memory within the EC */
	216	+ lpc {
	217	+ compatible = "intel,bd82x6x-lpc";
221	218	#address-cells = <1>;
222		- #size-cells = <1>;
223		- flash@8000000 {
224		- reg = <0x08000000 0x20000>;
225		- erase-value = <0xff>;
	219	+ #size-cells = <0>;
	220	+ cros-ec@200 {
	221	+ compatible = "google,cros-ec";
	222	+ reg = <0x204 1 0x200 1 0x880 0x80>;
	223	+
	224	+ /*
	225	+ * Describes the flash memory within
	226	+ * the EC
	227	+ */
	228	+ #address-cells = <1>;
	229	+ #size-cells = <1>;
	230	+ flash@8000000 {
	231	+ reg = <0x08000000 0x20000>;
	232	+ erase-value = <0xff>;
	233	+ };
226	234	};
227	235	};
228	236	};
...	...	@@ -169,6 +169,7 @@
169	169	COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
170	170	COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
171	171	COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
	172	+ COMPAT_INTEL_PCH, /* Intel PCH */
172	173
173	174	COMPAT_COUNT,
174	175	};
...	...	@@ -67,7 +67,7 @@
67	67	COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
68	68	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
69	69	COMPAT(PARADE_PS8625, "parade,ps8625"),
70		- COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x"),
	70	+ COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"),
71	71	COMPAT(INTEL_MICROCODE, "intel,microcode"),
72	72	COMPAT(MEMORY_SPD, "memory-spd"),
73	73	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
...	...	@@ -77,6 +77,7 @@
77	77	COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
78	78	COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
79	79	COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
	80	+ COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
80	81	};
81	82
82	83	const char *fdtdec_get_compatible(enum fdt_compat_id id)