Merge branch 'master' of git://git.denx.de/u-boot-net

Tom Rini
2 parents dd9958a3f4 523bb66f5a
Showing 10 changed files Side-by-side Diff
MAINTAINERS
common/cmd_mii.c
doc/git-mailrc
drivers/net/pch_gbe.c
drivers/net/phy/micrel.c
drivers/net/phy/phy.c
drivers/net/phy/realtek.c
drivers/net/rtl8169.c
drivers/net/zynq_gem.c
include/phy.h
@@ -328,10 +328,11 @@
 F:	arch/powerpc/cpu/ppc4xx/
  
 NETWORK
-M:	Joe Hershberger <joe.hershberger@gmail.com>
+M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-net.git
 F:	drivers/net/
+F:	net/
  
 NAND FLASH
 M:	Scott Wood <scottwood@freescale.com>
@@ -249,6 +249,7 @@
 static uint last_addr_hi;
 static uint last_reg_lo;
 static uint last_reg_hi;
+static uint last_mask;
  
 static void extract_range(
 	char * input,
@@ -272,7 +273,7 @@
 	char		op[2];
 	unsigned char	addrlo, addrhi, reglo, reghi;
 	unsigned char	addr, reg;
-	unsigned short	data;
+	unsigned short	data, mask;
 	int		rcode = 0;
 	const char	*devname;
  
@@ -294,6 +295,7 @@
 	reglo  = last_reg_lo;
 	reghi  = last_reg_hi;
 	data   = last_data;
+	mask   = last_mask;
  
 	if ((flag & CMD_FLAG_REPEAT) == 0) {
 		op[0] = argv[1][0];
@@ -307,7 +309,9 @@
 		if (argc >= 4)
 			extract_range(argv[3], &reglo, &reghi);
 		if (argc >= 5)
-			data = simple_strtoul (argv[4], NULL, 16);
+			data = simple_strtoul(argv[4], NULL, 16);
+		if (argc >= 6)
+			mask = simple_strtoul(argv[5], NULL, 16);
 	}
  
 	/* use current device */
@@ -375,6 +379,28 @@
 				}
 			}
 		}
+	} else if (op[0] == 'm') {
+		for (addr = addrlo; addr <= addrhi; addr++) {
+			for (reg = reglo; reg <= reghi; reg++) {
+				unsigned short val = 0;
+				if (miiphy_read(devname, addr,
+						reg, &val)) {
+					printf("Error reading from the PHY");
+					printf(" addr=%02x", addr);
+					printf(" reg=%02x\n", reg);
+					rcode = 1;
+				} else {
+					val = (val & ~mask) | (data & mask);
+					if (miiphy_write(devname, addr,
+							 reg, val)) {
+						printf("Error writing to the PHY");
+						printf(" addr=%02x", addr);
+						printf(" reg=%02x\n", reg);
+						rcode = 1;
+					}
+				}
+			}
+		}
 	} else if (strncmp(op, "du", 2) == 0) {
 		ushort regs[6];
 		int ok = 1;
@@ -417,6 +443,7 @@
 	last_reg_lo  = reglo;
 	last_reg_hi  = reghi;
 	last_data    = data;
+	last_mask    = mask;
  
 	return rcode;
 }
  
@@ -424,14 +451,16 @@
 /***************************************************/
  
 U_BOOT_CMD(
-	mii,	5,	1,	do_mii,
+	mii, 6, 1, do_mii,
 	"MII utility commands",
-	"device                     - list available devices\n"
-	"mii device <devname>           - set current device\n"
-	"mii info   <addr>              - display MII PHY info\n"
-	"mii read   <addr> <reg>        - read  MII PHY <addr> register <reg>\n"
-	"mii write  <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
-	"mii dump   <addr> <reg>        - pretty-print <addr> <reg> (0-5 only)\n"
+	"device                            - list available devices\n"
+	"mii device <devname>                  - set current device\n"
+	"mii info   <addr>                     - display MII PHY info\n"
+	"mii read   <addr> <reg>               - read  MII PHY <addr> register <reg>\n"
+	"mii write  <addr> <reg> <data>        - write MII PHY <addr> register <reg>\n"
+	"mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
+	"                                        updating bits identified in <mask>\n"
+	"mii dump   <addr> <reg>               - pretty-print <addr> <reg> (0-5 only)\n"
 	"Addr and/or reg may be ranges, e.g. 2-7."
 );
@@ -24,7 +24,7 @@
 alias iwamatsu       Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 alias jagan          Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 alias jasonjin       Jason Jin <jason.jin@freescale.com>
-alias jhersh         Joe Hershberger <joe.hershberger@gmail.com>
+alias jhersh         Joe Hershberger <joe.hershberger@ni.com>
 alias jwrdegoede     Hans de Goede <hdegoede@redhat.com>
 alias kimphill       Kim Phillips <kim.phillips@freescale.com>
 alias luka           Luka Perkov <luka.perkov@sartura.hr>
@@ -113,6 +113,7 @@
 alias dm             uboot, sjg
 alias cfi            uboot, stroese
 alias dfu            uboot, lukma
+alias eth            uboot, jhersh
 alias kerneldoc      uboot, marex
 alias fdt            uboot, sjg
 alias i2c            uboot, hs
@@ -120,6 +121,7 @@
 alias mmc            uboot, panto
 alias nand           uboot, scottwood
 alias net            uboot, jhersh
+alias phy            uboot, jhersh
 alias spi            uboot, jagan
 alias ubi            uboot, hs
 alias usb            uboot, marex
@@ -446,7 +446,7 @@
 	dev->iobase = iobase;
 	priv->mac_regs = (struct pch_gbe_regs *)iobase;
  
-	sprintf(dev->name, "pch_gbe.%x", iobase);
+	sprintf(dev->name, "pch_gbe");
  
 	/* Read MAC address from SROM and initialize dev->enetaddr with it */
 	pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
@@ -22,6 +22,16 @@
 	.shutdown = &genphy_shutdown,
 };
  
+static struct phy_driver KSZ8081_driver = {
+	.name = "Micrel KSZ8081",
+	.uid = 0x221560,
+	.mask = 0xfffff0,
+	.features = PHY_BASIC_FEATURES,
+	.config = &genphy_config,
+	.startup = &genphy_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 /**
  * KSZ8895
  */
@@ -272,6 +282,7 @@
 int phy_micrel_init(void)
 {
 	phy_register(&KSZ804_driver);
+	phy_register(&KSZ8081_driver);
 #ifdef CONFIG_PHY_MICREL_KSZ9021
 	phy_register(&ksz9021_driver);
 #else
@@ -582,7 +582,7 @@
  * Description: Reads the ID registers of the PHY at @addr on the
  *   @bus, stores it in @phy_id and returns zero on success.
  */
-static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
 	int phy_reg;
  
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
  * author Andy Fleming
  */
 #include <config.h>
  
  
@@ -21,11 +21,27 @@
 #define MIIM_RTL8211x_PHYSTAT_SPDDONE  0x0800
 #define MIIM_RTL8211x_PHYSTAT_LINK     0x0400
  
+/* RTL8211x PHY Interrupt Enable Register */
+#define MIIM_RTL8211x_PHY_INER         0x12
+#define MIIM_RTL8211x_PHY_INTR_ENA     0x9f01
+#define MIIM_RTL8211x_PHY_INTR_DIS     0x0000
  
+/* RTL8211x PHY Interrupt Status Register */
+#define MIIM_RTL8211x_PHY_INSR         0x13
+
 /* RealTek RTL8211x */
 static int rtl8211x_config(struct phy_device *phydev)
 {
 	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+
+	/* mask interrupt at init; if the interrupt is
+	 * needed indeed, it should be explicitly enabled
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
+		  MIIM_RTL8211x_PHY_INTR_DIS);
+
+	/* read interrupt status just to clear it */
+	phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
  
 	genphy_config_aneg(phydev);
  
@@ -55,7 +55,7 @@
 #define drv_version "v1.5"
 #define drv_date "01-17-2004"
  
-static u32 ioaddr;
+static unsigned long ioaddr;
  
 /* Condensed operations for readability. */
 #define currticks()	get_timer(0)
  
@@ -92,19 +92,21 @@
 #define TX_TIMEOUT  (6*HZ)
  
 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
-#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
-#define RTL_R8(reg)		readb (ioaddr + (reg))
-#define RTL_R16(reg)		readw (ioaddr + (reg))
-#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
+#define RTL_W8(reg, val8)	writeb((val8), ioaddr + (reg))
+#define RTL_W16(reg, val16)	writew((val16), ioaddr + (reg))
+#define RTL_W32(reg, val32)	writel((val32), ioaddr + (reg))
+#define RTL_R8(reg)		readb(ioaddr + (reg))
+#define RTL_R16(reg)		readw(ioaddr + (reg))
+#define RTL_R32(reg)		readl(ioaddr + (reg))
  
 #define ETH_FRAME_LEN	MAX_ETH_FRAME_SIZE
 #define ETH_ALEN	MAC_ADDR_LEN
 #define ETH_ZLEN	60
  
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
+#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
+	(pci_addr_t)(unsigned long)a)
+#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
+	(phys_addr_t)a)
  
 enum RTL8169_registers {
 	MAC0 = 0,		/* Ethernet hardware address. */
@@ -852,7 +854,7 @@
  
 #ifdef DEBUG_RTL8169
 	/* Print out some hardware info */
-	printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
+	printf("%s: at ioaddr 0x%lx\n", dev->name, ioaddr);
 #endif
  
 	/* if TBI is not endbled */
@@ -1004,7 +1006,7 @@
 		memset(dev, 0, sizeof(*dev));
 		sprintf (dev->name, "RTL8169#%d", card_number);
  
-		dev->priv = (void *) devno;
+		dev->priv = (void *)(unsigned long)devno;
 		dev->iobase = (int)pci_mem_to_phys(devno, iobase);
  
 		dev->init = rtl_reset;
@@ -513,7 +513,8 @@
  
 	/* Align bd_space to 1MB */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
+					BD_SPACE, DCACHE_OFF);
  
 	/* Initialize the bd spaces for tx and rx bd's */
 	priv->tx_bd = (struct emac_bd *)bd_space;
@@ -254,6 +254,7 @@
 int phy_vitesse_init(void);
  
 int board_phy_config(struct phy_device *phydev);
+int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
  
 /**
  * phy_get_interface_by_name() - Look up a PHY interface name
...	...	@@ -328,10 +328,11 @@
328	328	F: arch/powerpc/cpu/ppc4xx/
329	329
330	330	NETWORK
331		-M: Joe Hershberger <joe.hershberger@gmail.com>
	331	+M: Joe Hershberger <joe.hershberger@ni.com>
332	332	S: Maintained
333	333	T: git git://git.denx.de/u-boot-net.git
334	334	F: drivers/net/
	335	+F: net/
335	336
336	337	NAND FLASH
337	338	M: Scott Wood <scottwood@freescale.com>
...	...	@@ -249,6 +249,7 @@
249	249	static uint last_addr_hi;
250	250	static uint last_reg_lo;
251	251	static uint last_reg_hi;
	252	+static uint last_mask;
252	253
253	254	static void extract_range(
254	255	char * input,
...	...	@@ -272,7 +273,7 @@
272	273	char op[2];
273	274	unsigned char addrlo, addrhi, reglo, reghi;
274	275	unsigned char addr, reg;
275		- unsigned short data;
	276	+ unsigned short data, mask;
276	277	int rcode = 0;
277	278	const char *devname;
278	279
...	...	@@ -294,6 +295,7 @@
294	295	reglo = last_reg_lo;
295	296	reghi = last_reg_hi;
296	297	data = last_data;
	298	+ mask = last_mask;
297	299
298	300	if ((flag & CMD_FLAG_REPEAT) == 0) {
299	301	op[0] = argv[1][0];
...	...	@@ -307,7 +309,9 @@
307	309	if (argc >= 4)
308	310	extract_range(argv[3], &reglo, &reghi);
309	311	if (argc >= 5)
310		- data = simple_strtoul (argv[4], NULL, 16);
	312	+ data = simple_strtoul(argv[4], NULL, 16);
	313	+ if (argc >= 6)
	314	+ mask = simple_strtoul(argv[5], NULL, 16);
311	315	}
312	316
313	317	/* use current device */
...	...	@@ -375,6 +379,28 @@
375	379	}
376	380	}
377	381	}
	382	+ } else if (op[0] == 'm') {
	383	+ for (addr = addrlo; addr <= addrhi; addr++) {
	384	+ for (reg = reglo; reg <= reghi; reg++) {
	385	+ unsigned short val = 0;
	386	+ if (miiphy_read(devname, addr,
	387	+ reg, &val)) {
	388	+ printf("Error reading from the PHY");
	389	+ printf(" addr=%02x", addr);
	390	+ printf(" reg=%02x\n", reg);
	391	+ rcode = 1;
	392	+ } else {
	393	+ val = (val & ~mask) \| (data & mask);
	394	+ if (miiphy_write(devname, addr,
	395	+ reg, val)) {
	396	+ printf("Error writing to the PHY");
	397	+ printf(" addr=%02x", addr);
	398	+ printf(" reg=%02x\n", reg);
	399	+ rcode = 1;
	400	+ }
	401	+ }
	402	+ }
	403	+ }
378	404	} else if (strncmp(op, "du", 2) == 0) {
379	405	ushort regs[6];
380	406	int ok = 1;
...	...	@@ -417,6 +443,7 @@
417	443	last_reg_lo = reglo;
418	444	last_reg_hi = reghi;
419	445	last_data = data;
	446	+ last_mask = mask;
420	447
421	448	return rcode;
422	449	}
423	450
...	...	@@ -424,14 +451,16 @@
424	451	/***************************************************/
425	452
426	453	U_BOOT_CMD(
427		- mii, 5, 1, do_mii,
	454	+ mii, 6, 1, do_mii,
428	455	"MII utility commands",
429		- "device - list available devices\n"
430		- "mii device <devname> - set current device\n"
431		- "mii info <addr> - display MII PHY info\n"
432		- "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
433		- "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
434		- "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
	456	+ "device - list available devices\n"
	457	+ "mii device <devname> - set current device\n"
	458	+ "mii info <addr> - display MII PHY info\n"
	459	+ "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
	460	+ "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
	461	+ "mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
	462	+ " updating bits identified in <mask>\n"
	463	+ "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
435	464	"Addr and/or reg may be ranges, e.g. 2-7."
436	465	);
...	...	@@ -24,7 +24,7 @@
24	24	alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
25	25	alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
26	26	alias jasonjin Jason Jin <jason.jin@freescale.com>
27		-alias jhersh Joe Hershberger <joe.hershberger@gmail.com>
	27	+alias jhersh Joe Hershberger <joe.hershberger@ni.com>
28	28	alias jwrdegoede Hans de Goede <hdegoede@redhat.com>
29	29	alias kimphill Kim Phillips <kim.phillips@freescale.com>
30	30	alias luka Luka Perkov <luka.perkov@sartura.hr>
...	...	@@ -113,6 +113,7 @@
113	113	alias dm uboot, sjg
114	114	alias cfi uboot, stroese
115	115	alias dfu uboot, lukma
	116	+alias eth uboot, jhersh
116	117	alias kerneldoc uboot, marex
117	118	alias fdt uboot, sjg
118	119	alias i2c uboot, hs
...	...	@@ -120,6 +121,7 @@
120	121	alias mmc uboot, panto
121	122	alias nand uboot, scottwood
122	123	alias net uboot, jhersh
	124	+alias phy uboot, jhersh
123	125	alias spi uboot, jagan
124	126	alias ubi uboot, hs
125	127	alias usb uboot, marex
...	...	@@ -446,7 +446,7 @@
446	446	dev->iobase = iobase;
447	447	priv->mac_regs = (struct pch_gbe_regs *)iobase;
448	448
449		- sprintf(dev->name, "pch_gbe.%x", iobase);
	449	+ sprintf(dev->name, "pch_gbe");
450	450
451	451	/* Read MAC address from SROM and initialize dev->enetaddr with it */
452	452	pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
...	...	@@ -22,6 +22,16 @@
22	22	.shutdown = &genphy_shutdown,
23	23	};
24	24
	25	+static struct phy_driver KSZ8081_driver = {
	26	+ .name = "Micrel KSZ8081",
	27	+ .uid = 0x221560,
	28	+ .mask = 0xfffff0,
	29	+ .features = PHY_BASIC_FEATURES,
	30	+ .config = &genphy_config,
	31	+ .startup = &genphy_startup,
	32	+ .shutdown = &genphy_shutdown,
	33	+};
	34	+
25	35	/**
26	36	* KSZ8895
27	37	*/
...	...	@@ -272,6 +282,7 @@
272	282	int phy_micrel_init(void)
273	283	{
274	284	phy_register(&KSZ804_driver);
	285	+ phy_register(&KSZ8081_driver);
275	286	#ifdef CONFIG_PHY_MICREL_KSZ9021
276	287	phy_register(&ksz9021_driver);
277	288	#else
...	...	@@ -582,7 +582,7 @@
582	582	* Description: Reads the ID registers of the PHY at @addr on the
583	583	* @bus, stores it in @phy_id and returns zero on success.
584	584	*/
585		-static int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id)
	585	+int __weak get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id)
586	586	{
587	587	int phy_reg;
588	588
...	...	@@ -3,7 +3,7 @@
3	3	*
4	4	* SPDX-License-Identifier: GPL-2.0+
5	5	*
6		- * Copyright 2010-2011 Freescale Semiconductor, Inc.
	6	+ * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
7	7	* author Andy Fleming
8	8	*/
9	9	#include <config.h>
10	10
11	11
...	...	@@ -21,11 +21,27 @@
21	21	#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
22	22	#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
23	23
	24	+/* RTL8211x PHY Interrupt Enable Register */
	25	+#define MIIM_RTL8211x_PHY_INER 0x12
	26	+#define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
	27	+#define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
24	28
	29	+/* RTL8211x PHY Interrupt Status Register */
	30	+#define MIIM_RTL8211x_PHY_INSR 0x13
	31	+
25	32	/* RealTek RTL8211x */
26	33	static int rtl8211x_config(struct phy_device *phydev)
27	34	{
28	35	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	36	+
	37	+ /* mask interrupt at init; if the interrupt is
	38	+ * needed indeed, it should be explicitly enabled
	39	+ */
	40	+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
	41	+ MIIM_RTL8211x_PHY_INTR_DIS);
	42	+
	43	+ /* read interrupt status just to clear it */
	44	+ phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
29	45
30	46	genphy_config_aneg(phydev);
31	47
...	...	@@ -55,7 +55,7 @@
55	55	#define drv_version "v1.5"
56	56	#define drv_date "01-17-2004"
57	57
58		-static u32 ioaddr;
	58	+static unsigned long ioaddr;
59	59
60	60	/* Condensed operations for readability. */
61	61	#define currticks() get_timer(0)
62	62
...	...	@@ -92,19 +92,21 @@
92	92	#define TX_TIMEOUT (6*HZ)
93	93
94	94	/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
95		-#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96		-#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97		-#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98		-#define RTL_R8(reg) readb (ioaddr + (reg))
99		-#define RTL_R16(reg) readw (ioaddr + (reg))
100		-#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
	95	+#define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
	96	+#define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
	97	+#define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
	98	+#define RTL_R8(reg) readb(ioaddr + (reg))
	99	+#define RTL_R16(reg) readw(ioaddr + (reg))
	100	+#define RTL_R32(reg) readl(ioaddr + (reg))
101	101
102	102	#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
103	103	#define ETH_ALEN MAC_ADDR_LEN
104	104	#define ETH_ZLEN 60
105	105
106		-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
107		-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
	106	+#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
	107	+ (pci_addr_t)(unsigned long)a)
	108	+#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
	109	+ (phys_addr_t)a)
108	110
109	111	enum RTL8169_registers {
110	112	MAC0 = 0, /* Ethernet hardware address. */
...	...	@@ -852,7 +854,7 @@
852	854
853	855	#ifdef DEBUG_RTL8169
854	856	/* Print out some hardware info */
855		- printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
	857	+ printf("%s: at ioaddr 0x%lx\n", dev->name, ioaddr);
856	858	#endif
857	859
858	860	/* if TBI is not endbled */
...	...	@@ -1004,7 +1006,7 @@
1004	1006	memset(dev, 0, sizeof(*dev));
1005	1007	sprintf (dev->name, "RTL8169#%d", card_number);
1006	1008
1007		- dev->priv = (void *) devno;
	1009	+ dev->priv = (void *)(unsigned long)devno;
1008	1010	dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1009	1011
1010	1012	dev->init = rtl_reset;
...	...	@@ -513,7 +513,8 @@
513	513
514	514	/* Align bd_space to 1MB */
515	515	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
516		- mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
	516	+ mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
	517	+ BD_SPACE, DCACHE_OFF);
517	518
518	519	/* Initialize the bd spaces for tx and rx bd's */
519	520	priv->tx_bd = (struct emac_bd *)bd_space;
...	...	@@ -254,6 +254,7 @@
254	254	int phy_vitesse_init(void);
255	255
256	256	int board_phy_config(struct phy_device *phydev);
	257	+int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
257	258
258	259	/**
259	260	* phy_get_interface_by_name() - Look up a PHY interface name