Eric Lee / smarc-uboot

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Commit 91703d0672342145da32d4e1bc1f42436dbae6cf

Authored by Bai Ping
1 parent c5dc9e64ff
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ull 

Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0
bit[6:4]) setting to 2b'110.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

Showing 2 changed files with 7 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 91703d0
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix 3 * Sascha Hauer, Pengutronix
4 * 4 *
5 * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. 5 * (C) Copyright 2009-2016 Freescale Semiconductor, Inc.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/errno.h> 11 #include <asm/errno.h>
12 #include <asm/io.h> 12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h> 14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h> 16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h> 17 #include <asm/imx-common/dma.h>
18 #include <asm/imx-common/hab.h> 18 #include <asm/imx-common/hab.h>
19 #include <stdbool.h> 19 #include <stdbool.h>
20 #include <asm/arch/mxc_hdmi.h> 20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/crm_regs.h>
22 #include <dm.h> 22 #include <dm.h>
23 #include <imx_thermal.h> 23 #include <imx_thermal.h>
24 #include <mmc.h> 24 #include <mmc.h>
25 #if defined(CONFIG_FSL_FASTBOOT) && defined(CONFIG_ANDROID_RECOVERY) 25 #if defined(CONFIG_FSL_FASTBOOT) && defined(CONFIG_ANDROID_RECOVERY)
26 #include <recovery.h> 26 #include <recovery.h>
27 #endif 27 #endif
28 28
29 29
30 enum ldo_reg { 30 enum ldo_reg {
31 LDO_ARM, 31 LDO_ARM,
32 LDO_SOC, 32 LDO_SOC,
33 LDO_PU, 33 LDO_PU,
34 }; 34 };
35 35
36 struct scu_regs { 36 struct scu_regs {
37 u32 ctrl; 37 u32 ctrl;
38 u32 config; 38 u32 config;
39 u32 status; 39 u32 status;
40 u32 invalidate; 40 u32 invalidate;
41 u32 fpga_rev; 41 u32 fpga_rev;
42 }; 42 };
43 43
44 #if defined(CONFIG_IMX_THERMAL) 44 #if defined(CONFIG_IMX_THERMAL)
45 static const struct imx_thermal_plat imx6_thermal_plat = { 45 static const struct imx_thermal_plat imx6_thermal_plat = {
46 .regs = (void *)ANATOP_BASE_ADDR, 46 .regs = (void *)ANATOP_BASE_ADDR,
47 .fuse_bank = 1, 47 .fuse_bank = 1,
48 .fuse_word = 6, 48 .fuse_word = 6,
49 }; 49 };
50 50
51 U_BOOT_DEVICE(imx6_thermal) = { 51 U_BOOT_DEVICE(imx6_thermal) = {
52 .name = "imx_thermal", 52 .name = "imx_thermal",
53 .platdata = &imx6_thermal_plat, 53 .platdata = &imx6_thermal_plat,
54 }; 54 };
55 #endif 55 #endif
56 56
57 #if defined(CONFIG_SECURE_BOOT) 57 #if defined(CONFIG_SECURE_BOOT)
58 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 58 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
59 .bank = 0, 59 .bank = 0,
60 .word = 6, 60 .word = 6,
61 }; 61 };
62 #endif 62 #endif
63 63
64 u32 get_nr_cpus(void) 64 u32 get_nr_cpus(void)
65 { 65 {
66 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 66 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
67 return readl(&scu->config) & 3; 67 return readl(&scu->config) & 3;
68 } 68 }
69 69
70 u32 get_cpu_rev(void) 70 u32 get_cpu_rev(void)
71 { 71 {
72 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 72 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
73 u32 reg = readl(&anatop->digprog_sololite); 73 u32 reg = readl(&anatop->digprog_sololite);
74 u32 type = ((reg >> 16) & 0xff); 74 u32 type = ((reg >> 16) & 0xff);
75 u32 major, cfg = 0; 75 u32 major, cfg = 0;
76 76
77 if (type != MXC_CPU_MX6SL) { 77 if (type != MXC_CPU_MX6SL) {
78 reg = readl(&anatop->digprog); 78 reg = readl(&anatop->digprog);
79 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 79 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
80 cfg = readl(&scu->config) & 3; 80 cfg = readl(&scu->config) & 3;
81 type = ((reg >> 16) & 0xff); 81 type = ((reg >> 16) & 0xff);
82 if (type == MXC_CPU_MX6DL) { 82 if (type == MXC_CPU_MX6DL) {
83 if (!cfg) 83 if (!cfg)
84 type = MXC_CPU_MX6SOLO; 84 type = MXC_CPU_MX6SOLO;
85 } 85 }
86 86
87 if (type == MXC_CPU_MX6Q) { 87 if (type == MXC_CPU_MX6Q) {
88 if (cfg == 1) 88 if (cfg == 1)
89 type = MXC_CPU_MX6D; 89 type = MXC_CPU_MX6D;
90 } 90 }
91 91
92 } 92 }
93 major = ((reg >> 8) & 0xff); 93 major = ((reg >> 8) & 0xff);
94 if ((major >= 1) && 94 if ((major >= 1) &&
95 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { 95 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
96 major--; 96 major--;
97 type = MXC_CPU_MX6QP; 97 type = MXC_CPU_MX6QP;
98 if (cfg == 1) 98 if (cfg == 1)
99 type = MXC_CPU_MX6DP; 99 type = MXC_CPU_MX6DP;
100 } 100 }
101 reg &= 0xff; /* mx6 silicon revision */ 101 reg &= 0xff; /* mx6 silicon revision */
102 return (type << 12) | (reg + (0x10 * (major + 1))); 102 return (type << 12) | (reg + (0x10 * (major + 1)));
103 } 103 }
104 104
105 /* 105 /*
106 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) 106 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
107 * defines a 2-bit SPEED_GRADING 107 * defines a 2-bit SPEED_GRADING
108 */ 108 */
109 #define OCOTP_CFG3_SPEED_SHIFT 16 109 #define OCOTP_CFG3_SPEED_SHIFT 16
110 #define OCOTP_CFG3_SPEED_800MHZ 0 110 #define OCOTP_CFG3_SPEED_800MHZ 0
111 #define OCOTP_CFG3_SPEED_850MHZ 1 111 #define OCOTP_CFG3_SPEED_850MHZ 1
112 #define OCOTP_CFG3_SPEED_1GHZ 2 112 #define OCOTP_CFG3_SPEED_1GHZ 2
113 #define OCOTP_CFG3_SPEED_1P2GHZ 3 113 #define OCOTP_CFG3_SPEED_1P2GHZ 3
114 114
115 /* 115 /*
116 * For i.MX6UL 116 * For i.MX6UL
117 */ 117 */
118 #define OCOTP_CFG3_SPEED_528MHZ 1 118 #define OCOTP_CFG3_SPEED_528MHZ 1
119 #define OCOTP_CFG3_SPEED_696MHZ 2 119 #define OCOTP_CFG3_SPEED_696MHZ 2
120 120
121 u32 get_cpu_speed_grade_hz(void) 121 u32 get_cpu_speed_grade_hz(void)
122 { 122 {
123 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 123 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
124 struct fuse_bank *bank = &ocotp->bank[0]; 124 struct fuse_bank *bank = &ocotp->bank[0];
125 struct fuse_bank0_regs *fuse = 125 struct fuse_bank0_regs *fuse =
126 (struct fuse_bank0_regs *)bank->fuse_regs; 126 (struct fuse_bank0_regs *)bank->fuse_regs;
127 uint32_t val; 127 uint32_t val;
128 128
129 val = readl(&fuse->cfg3); 129 val = readl(&fuse->cfg3);
130 val >>= OCOTP_CFG3_SPEED_SHIFT; 130 val >>= OCOTP_CFG3_SPEED_SHIFT;
131 val &= 0x3; 131 val &= 0x3;
132 132
133 if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) { 133 if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) {
134 if (val == OCOTP_CFG3_SPEED_528MHZ) 134 if (val == OCOTP_CFG3_SPEED_528MHZ)
135 return 528000000; 135 return 528000000;
136 else if (val == OCOTP_CFG3_SPEED_696MHZ) 136 else if (val == OCOTP_CFG3_SPEED_696MHZ)
137 return 69600000; 137 return 69600000;
138 else 138 else
139 return 0; 139 return 0;
140 } 140 }
141 141
142 switch (val) { 142 switch (val) {
143 /* Valid for IMX6DQ */ 143 /* Valid for IMX6DQ */
144 case OCOTP_CFG3_SPEED_1P2GHZ: 144 case OCOTP_CFG3_SPEED_1P2GHZ:
145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) || 145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
146 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 146 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
147 return 1200000000; 147 return 1200000000;
148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
149 case OCOTP_CFG3_SPEED_1GHZ: 149 case OCOTP_CFG3_SPEED_1GHZ:
150 return 996000000; 150 return 996000000;
151 /* Valid for IMX6DQ */ 151 /* Valid for IMX6DQ */
152 case OCOTP_CFG3_SPEED_850MHZ: 152 case OCOTP_CFG3_SPEED_850MHZ:
153 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) || 153 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
154 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 154 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
155 return 852000000; 155 return 852000000;
156 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 156 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
157 case OCOTP_CFG3_SPEED_800MHZ: 157 case OCOTP_CFG3_SPEED_800MHZ:
158 return 792000000; 158 return 792000000;
159 } 159 }
160 return 0; 160 return 0;
161 } 161 }
162 162
163 /* 163 /*
164 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) 164 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
165 * defines a 2-bit Temperature Grade 165 * defines a 2-bit Temperature Grade
166 * 166 *
167 * return temperature grade and min/max temperature in celcius 167 * return temperature grade and min/max temperature in celcius
168 */ 168 */
169 #define OCOTP_MEM0_TEMP_SHIFT 6 169 #define OCOTP_MEM0_TEMP_SHIFT 6
170 170
171 u32 get_cpu_temp_grade(int *minc, int *maxc) 171 u32 get_cpu_temp_grade(int *minc, int *maxc)
172 { 172 {
173 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 173 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
174 struct fuse_bank *bank = &ocotp->bank[1]; 174 struct fuse_bank *bank = &ocotp->bank[1];
175 struct fuse_bank1_regs *fuse = 175 struct fuse_bank1_regs *fuse =
176 (struct fuse_bank1_regs *)bank->fuse_regs; 176 (struct fuse_bank1_regs *)bank->fuse_regs;
177 uint32_t val; 177 uint32_t val;
178 178
179 val = readl(&fuse->mem0); 179 val = readl(&fuse->mem0);
180 val >>= OCOTP_MEM0_TEMP_SHIFT; 180 val >>= OCOTP_MEM0_TEMP_SHIFT;
181 val &= 0x3; 181 val &= 0x3;
182 182
183 if (minc && maxc) { 183 if (minc && maxc) {
184 if (val == TEMP_AUTOMOTIVE) { 184 if (val == TEMP_AUTOMOTIVE) {
185 *minc = -40; 185 *minc = -40;
186 *maxc = 125; 186 *maxc = 125;
187 } else if (val == TEMP_INDUSTRIAL) { 187 } else if (val == TEMP_INDUSTRIAL) {
188 *minc = -40; 188 *minc = -40;
189 *maxc = 105; 189 *maxc = 105;
190 } else if (val == TEMP_EXTCOMMERCIAL) { 190 } else if (val == TEMP_EXTCOMMERCIAL) {
191 *minc = -20; 191 *minc = -20;
192 *maxc = 105; 192 *maxc = 105;
193 } else { 193 } else {
194 *minc = 0; 194 *minc = 0;
195 *maxc = 95; 195 *maxc = 95;
196 } 196 }
197 } 197 }
198 return val; 198 return val;
199 } 199 }
200 200
201 #ifdef CONFIG_REVISION_TAG 201 #ifdef CONFIG_REVISION_TAG
202 u32 __weak get_board_rev(void) 202 u32 __weak get_board_rev(void)
203 { 203 {
204 u32 cpurev = get_cpu_rev(); 204 u32 cpurev = get_cpu_rev();
205 u32 type = ((cpurev >> 12) & 0xff); 205 u32 type = ((cpurev >> 12) & 0xff);
206 if (type == MXC_CPU_MX6SOLO) 206 if (type == MXC_CPU_MX6SOLO)
207 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); 207 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
208 208
209 if (type == MXC_CPU_MX6D) 209 if (type == MXC_CPU_MX6D)
210 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); 210 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
211 211
212 if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP) 212 if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP)
213 cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF); 213 cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF);
214 214
215 return cpurev; 215 return cpurev;
216 } 216 }
217 #endif 217 #endif
218 218
219 static void clear_ldo_ramp(void) 219 static void clear_ldo_ramp(void)
220 { 220 {
221 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 221 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
222 int reg; 222 int reg;
223 223
224 /* ROM may modify LDO ramp up time according to fuse setting, so in 224 /* ROM may modify LDO ramp up time according to fuse setting, so in
225 * order to be in the safe side we neeed to reset these settings to 225 * order to be in the safe side we neeed to reset these settings to
226 * match the reset value: 0'b00 226 * match the reset value: 0'b00
227 */ 227 */
228 reg = readl(&anatop->ana_misc2); 228 reg = readl(&anatop->ana_misc2);
229 reg &= ~(0x3f << 24); 229 reg &= ~(0x3f << 24);
230 writel(reg, &anatop->ana_misc2); 230 writel(reg, &anatop->ana_misc2);
231 } 231 }
232 232
233 /* 233 /*
234 * Set the PMU_REG_CORE register 234 * Set the PMU_REG_CORE register
235 * 235 *
236 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. 236 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
237 * Possible values are from 0.725V to 1.450V in steps of 237 * Possible values are from 0.725V to 1.450V in steps of
238 * 0.025V (25mV). 238 * 0.025V (25mV).
239 */ 239 */
240 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) 240 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
241 { 241 {
242 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 242 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
243 u32 val, step, old, reg = readl(&anatop->reg_core); 243 u32 val, step, old, reg = readl(&anatop->reg_core);
244 u8 shift; 244 u8 shift;
245 245
246 if (mv < 725) 246 if (mv < 725)
247 val = 0x00; /* Power gated off */ 247 val = 0x00; /* Power gated off */
248 else if (mv > 1450) 248 else if (mv > 1450)
249 val = 0x1F; /* Power FET switched full on. No regulation */ 249 val = 0x1F; /* Power FET switched full on. No regulation */
250 else 250 else
251 val = (mv - 700) / 25; 251 val = (mv - 700) / 25;
252 252
253 clear_ldo_ramp(); 253 clear_ldo_ramp();
254 254
255 switch (ldo) { 255 switch (ldo) {
256 case LDO_SOC: 256 case LDO_SOC:
257 shift = 18; 257 shift = 18;
258 break; 258 break;
259 case LDO_PU: 259 case LDO_PU:
260 shift = 9; 260 shift = 9;
261 break; 261 break;
262 case LDO_ARM: 262 case LDO_ARM:
263 shift = 0; 263 shift = 0;
264 break; 264 break;
265 default: 265 default:
266 return -EINVAL; 266 return -EINVAL;
267 } 267 }
268 268
269 old = (reg & (0x1F << shift)) >> shift; 269 old = (reg & (0x1F << shift)) >> shift;
270 step = abs(val - old); 270 step = abs(val - old);
271 if (step == 0) 271 if (step == 0)
272 return 0; 272 return 0;
273 273
274 reg = (reg & ~(0x1F << shift)) | (val << shift); 274 reg = (reg & ~(0x1F << shift)) | (val << shift);
275 writel(reg, &anatop->reg_core); 275 writel(reg, &anatop->reg_core);
276 276
277 /* 277 /*
278 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per 278 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
279 * step 279 * step
280 */ 280 */
281 udelay(3 * step); 281 udelay(3 * step);
282 282
283 return 0; 283 return 0;
284 } 284 }
285 285
286 static void set_ahb_rate(u32 val) 286 static void set_ahb_rate(u32 val)
287 { 287 {
288 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 288 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
289 u32 reg, div; 289 u32 reg, div;
290 290
291 div = get_periph_clk() / val - 1; 291 div = get_periph_clk() / val - 1;
292 reg = readl(&mxc_ccm->cbcdr); 292 reg = readl(&mxc_ccm->cbcdr);
293 293
294 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | 294 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
295 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); 295 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
296 } 296 }
297 297
298 static void clear_mmdc_ch_mask(void) 298 static void clear_mmdc_ch_mask(void)
299 { 299 {
300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
301 u32 reg; 301 u32 reg;
302 reg = readl(&mxc_ccm->ccdr); 302 reg = readl(&mxc_ccm->ccdr);
303 303
304 /* Clear MMDC channel mask */ 304 /* Clear MMDC channel mask */
305 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 305 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
306 is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL)) 306 is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL))
307 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); 307 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
308 else 308 else
309 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); 309 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
310 writel(reg, &mxc_ccm->ccdr); 310 writel(reg, &mxc_ccm->ccdr);
311 } 311 }
312 312
313 static void init_bandgap(void) 313 static void init_bandgap(void)
314 { 314 {
315 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 315 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
316 /* 316 /*
317 * Ensure the bandgap has stabilized. 317 * Ensure the bandgap has stabilized.
318 */ 318 */
319 while (!(readl(&anatop->ana_misc0) & 0x80)) 319 while (!(readl(&anatop->ana_misc0) & 0x80))
320 ; 320 ;
321 /* 321 /*
322 * For best noise performance of the analog blocks using the 322 * For best noise performance of the analog blocks using the
323 * outputs of the bandgap, the reftop_selfbiasoff bit should 323 * outputs of the bandgap, the reftop_selfbiasoff bit should
324 * be set. 324 * be set.
325 */ 325 */
326 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); 326 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
327 /*
328 * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
329 * VBGADJ bits to 2b'110 to adjust it.
330 */
331 if (is_cpu_type(MXC_CPU_MX6ULL))
332 writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
327 } 333 }
328 334
329 335
330 #ifdef CONFIG_MX6SL 336 #ifdef CONFIG_MX6SL
331 static void set_preclk_from_osc(void) 337 static void set_preclk_from_osc(void)
332 { 338 {
333 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 339 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
334 u32 reg; 340 u32 reg;
335 341
336 reg = readl(&mxc_ccm->cscmr1); 342 reg = readl(&mxc_ccm->cscmr1);
337 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; 343 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
338 writel(reg, &mxc_ccm->cscmr1); 344 writel(reg, &mxc_ccm->cscmr1);
339 } 345 }
340 #endif 346 #endif
341 347
342 #ifdef CONFIG_MX6SX 348 #ifdef CONFIG_MX6SX
343 void vadc_power_up(void) 349 void vadc_power_up(void)
344 { 350 {
345 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 351 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
346 u32 val; 352 u32 val;
347 353
348 /* csi0 */ 354 /* csi0 */
349 val = readl(&iomux->gpr[5]); 355 val = readl(&iomux->gpr[5]);
350 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 356 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
351 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; 357 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
352 writel(val, &iomux->gpr[5]); 358 writel(val, &iomux->gpr[5]);
353 359
354 /* Power on vadc analog 360 /* Power on vadc analog
355 * Power down vadc ext power */ 361 * Power down vadc ext power */
356 val = readl(GPC_BASE_ADDR + 0); 362 val = readl(GPC_BASE_ADDR + 0);
357 val &= ~0x60000; 363 val &= ~0x60000;
358 writel(val, GPC_BASE_ADDR + 0); 364 writel(val, GPC_BASE_ADDR + 0);
359 365
360 /* software reset afe */ 366 /* software reset afe */
361 val = readl(&iomux->gpr[1]); 367 val = readl(&iomux->gpr[1]);
362 writel(val | 0x80000, &iomux->gpr[1]); 368 writel(val | 0x80000, &iomux->gpr[1]);
363 369
364 udelay(10*1000); 370 udelay(10*1000);
365 371
366 /* Release reset bit */ 372 /* Release reset bit */
367 writel(val & ~0x80000, &iomux->gpr[1]); 373 writel(val & ~0x80000, &iomux->gpr[1]);
368 374
369 /* Power on vadc ext power */ 375 /* Power on vadc ext power */
370 val = readl(GPC_BASE_ADDR + 0); 376 val = readl(GPC_BASE_ADDR + 0);
371 val |= 0x40000; 377 val |= 0x40000;
372 writel(val, GPC_BASE_ADDR + 0); 378 writel(val, GPC_BASE_ADDR + 0);
373 } 379 }
374 380
375 void vadc_power_down(void) 381 void vadc_power_down(void)
376 { 382 {
377 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 383 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
378 u32 val; 384 u32 val;
379 385
380 /* Power down vadc ext power 386 /* Power down vadc ext power
381 * Power off vadc analog */ 387 * Power off vadc analog */
382 val = readl(GPC_BASE_ADDR + 0); 388 val = readl(GPC_BASE_ADDR + 0);
383 val &= ~0x40000; 389 val &= ~0x40000;
384 val |= 0x20000; 390 val |= 0x20000;
385 writel(val, GPC_BASE_ADDR + 0); 391 writel(val, GPC_BASE_ADDR + 0);
386 392
387 /* clean csi0 connect to vadc */ 393 /* clean csi0 connect to vadc */
388 val = readl(&iomux->gpr[5]); 394 val = readl(&iomux->gpr[5]);
389 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 395 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
390 writel(val, &iomux->gpr[5]); 396 writel(val, &iomux->gpr[5]);
391 } 397 }
392 398
393 void pcie_power_up(void) 399 void pcie_power_up(void)
394 { 400 {
395 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ 401 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
396 } 402 }
397 403
398 void pcie_power_off(void) 404 void pcie_power_off(void)
399 { 405 {
400 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ 406 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */
401 } 407 }
402 #endif 408 #endif
403 409
404 static void set_uart_from_osc(void) 410 static void set_uart_from_osc(void)
405 { 411 {
406 u32 reg; 412 u32 reg;
407 413
408 /* set uart clk to OSC */ 414 /* set uart clk to OSC */
409 reg = readl(CCM_BASE_ADDR + 0x24); 415 reg = readl(CCM_BASE_ADDR + 0x24);
410 reg |= MXC_CCM_CSCDR1_UART_CLK_SEL; 416 reg |= MXC_CCM_CSCDR1_UART_CLK_SEL;
411 writel(reg, CCM_BASE_ADDR + 0x24); 417 writel(reg, CCM_BASE_ADDR + 0x24);
412 } 418 }
413 419
414 static void imx_set_vddpu_power_down(void) 420 static void imx_set_vddpu_power_down(void)
415 { 421 {
416 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 422 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
417 u32 val; 423 u32 val;
418 424
419 /* need to power down xPU in GPC before turn off PU LDO */ 425 /* need to power down xPU in GPC before turn off PU LDO */
420 val = readl(GPC_BASE_ADDR + 0x260); 426 val = readl(GPC_BASE_ADDR + 0x260);
421 writel(val | 0x1, GPC_BASE_ADDR + 0x260); 427 writel(val | 0x1, GPC_BASE_ADDR + 0x260);
422 428
423 val = readl(GPC_BASE_ADDR + 0x0); 429 val = readl(GPC_BASE_ADDR + 0x0);
424 writel(val | 0x1, GPC_BASE_ADDR + 0x0); 430 writel(val | 0x1, GPC_BASE_ADDR + 0x0);
425 while (readl(GPC_BASE_ADDR + 0x0) & 0x1) 431 while (readl(GPC_BASE_ADDR + 0x0) & 0x1)
426 ; 432 ;
427 433
428 /* disable VDDPU */ 434 /* disable VDDPU */
429 val = 0x3e00; 435 val = 0x3e00;
430 writel(val, &anatop->reg_core_clr); 436 writel(val, &anatop->reg_core_clr);
431 } 437 }
432 438
433 static void imx_set_pcie_phy_power_down(void) 439 static void imx_set_pcie_phy_power_down(void)
434 { 440 {
435 u32 val; 441 u32 val;
436 442
437 if (!is_cpu_type(MXC_CPU_MX6SX)) { 443 if (!is_cpu_type(MXC_CPU_MX6SX)) {
438 val = readl(IOMUXC_BASE_ADDR + 0x4); 444 val = readl(IOMUXC_BASE_ADDR + 0x4);
439 val |= 0x1 << 18; 445 val |= 0x1 << 18;
440 writel(val, IOMUXC_BASE_ADDR + 0x4); 446 writel(val, IOMUXC_BASE_ADDR + 0x4);
441 } else { 447 } else {
442 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); 448 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30);
443 val |= 0x1 << 30; 449 val |= 0x1 << 30;
444 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); 450 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30);
445 } 451 }
446 } 452 }
447 453
448 int arch_cpu_init(void) 454 int arch_cpu_init(void)
449 { 455 {
450 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6SX) 456 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6SX)
451 && !is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) { 457 && !is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) {
452 /* 458 /*
453 * imx6sl doesn't have pcie at all. 459 * imx6sl doesn't have pcie at all.
454 * this bit is not used by imx6sx anymore 460 * this bit is not used by imx6sx anymore
455 */ 461 */
456 u32 val; 462 u32 val;
457 463
458 /* 464 /*
459 * There are about 0.02% percentage, random pcie link down 465 * There are about 0.02% percentage, random pcie link down
460 * when warm-reset is used. 466 * when warm-reset is used.
461 * clear the ref_ssp_en bit16 of gpr1 to workaround it. 467 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
462 * then warm-reset imx6q/dl/solo again. 468 * then warm-reset imx6q/dl/solo again.
463 */ 469 */
464 val = readl(IOMUXC_BASE_ADDR + 0x4); 470 val = readl(IOMUXC_BASE_ADDR + 0x4);
465 if (val & (0x1 << 16)) { 471 if (val & (0x1 << 16)) {
466 val &= ~(0x1 << 16); 472 val &= ~(0x1 << 16);
467 writel(val, IOMUXC_BASE_ADDR + 0x4); 473 writel(val, IOMUXC_BASE_ADDR + 0x4);
468 reset_cpu(0); 474 reset_cpu(0);
469 } 475 }
470 } 476 }
471 477
472 init_aips(); 478 init_aips();
473 479
474 /* Need to clear MMDC_CHx_MASK to make warm reset work. */ 480 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
475 clear_mmdc_ch_mask(); 481 clear_mmdc_ch_mask();
476 482
477 /* 483 /*
478 * Disable self-bias circuit in the analog bandap. 484 * Disable self-bias circuit in the analog bandap.
479 * The self-bias circuit is used by the bandgap during startup. 485 * The self-bias circuit is used by the bandgap during startup.
480 * This bit should be set after the bandgap has initialized. 486 * This bit should be set after the bandgap has initialized.
481 */ 487 */
482 init_bandgap(); 488 init_bandgap();
483 489
484 if (!is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) { 490 if (!is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) {
485 /* 491 /*
486 * When low freq boot is enabled, ROM will not set AHB 492 * When low freq boot is enabled, ROM will not set AHB
487 * freq, so we need to ensure AHB freq is 132MHz in such 493 * freq, so we need to ensure AHB freq is 132MHz in such
488 * scenario. 494 * scenario.
489 */ 495 */
490 if (mxc_get_clock(MXC_ARM_CLK) == 396000000) 496 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
491 set_ahb_rate(132000000); 497 set_ahb_rate(132000000);
492 } 498 }
493 499
494 if (is_cpu_type(MXC_CPU_MX6UL)) { 500 if (is_cpu_type(MXC_CPU_MX6UL)) {
495 if (is_soc_rev(CHIP_REV_1_0)) { 501 if (is_soc_rev(CHIP_REV_1_0)) {
496 /* 502 /*
497 * According to the design team's requirement on i.MX6UL, 503 * According to the design team's requirement on i.MX6UL,
498 * the PMIC_STBY_REQ PAD should be configured as open 504 * the PMIC_STBY_REQ PAD should be configured as open
499 * drain 100K (0x0000b8a0). 505 * drain 100K (0x0000b8a0).
500 */ 506 */
501 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); 507 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
502 } else { 508 } else {
503 /* 509 /*
504 * From TO1.1, SNVS adds internal pull up control for POR_B, 510 * From TO1.1, SNVS adds internal pull up control for POR_B,
505 * the register filed is GPBIT[1:0], after system boot up, 511 * the register filed is GPBIT[1:0], after system boot up,
506 * it can be set to 2b'01 to disable internal pull up. 512 * it can be set to 2b'01 to disable internal pull up.
507 * It can save about 30uA power in SNVS mode. 513 * It can save about 30uA power in SNVS mode.
508 */ 514 */
509 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & (~0x1400)) | 0x400, 515 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & (~0x1400)) | 0x400,
510 MX6UL_SNVS_LP_BASE_ADDR + 0x10); 516 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
511 } 517 }
512 } 518 }
513 519
514 if (is_cpu_type(MXC_CPU_MX6ULL)) { 520 if (is_cpu_type(MXC_CPU_MX6ULL)) {
515 /* 521 /*
516 * GPBIT[1:0] is suggested to set to 2'b11: 522 * GPBIT[1:0] is suggested to set to 2'b11:
517 * 2'b00 : always PUP100K 523 * 2'b00 : always PUP100K
518 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL 524 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
519 * 2'b10 : always disable PUP100K 525 * 2'b10 : always disable PUP100K
520 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL 526 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
521 * register offset is different from i.MX6UL, since 527 * register offset is different from i.MX6UL, since
522 * i.MX6UL is fixed by ECO. 528 * i.MX6UL is fixed by ECO.
523 */ 529 */
524 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | 530 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
525 0x3, MX6UL_SNVS_LP_BASE_ADDR); 531 0x3, MX6UL_SNVS_LP_BASE_ADDR);
526 } 532 }
527 533
528 /* Set perclk to source from OSC 24MHz */ 534 /* Set perclk to source from OSC 24MHz */
529 #if defined(CONFIG_MX6SL) 535 #if defined(CONFIG_MX6SL)
530 set_preclk_from_osc(); 536 set_preclk_from_osc();
531 #endif 537 #endif
532 538
533 if (is_cpu_type(MXC_CPU_MX6SX)) 539 if (is_cpu_type(MXC_CPU_MX6SX))
534 set_uart_from_osc(); 540 set_uart_from_osc();
535 541
536 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ 542 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
537 543
538 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL) && 544 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL) &&
539 !is_cpu_type(MXC_CPU_MX6ULL)) 545 !is_cpu_type(MXC_CPU_MX6ULL))
540 imx_set_pcie_phy_power_down(); 546 imx_set_pcie_phy_power_down();
541 547
542 if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL) && 548 if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL) &&
543 !is_cpu_type(MXC_CPU_MX6ULL)) 549 !is_cpu_type(MXC_CPU_MX6ULL))
544 imx_set_vddpu_power_down(); 550 imx_set_vddpu_power_down();
545 551
546 #ifdef CONFIG_APBH_DMA 552 #ifdef CONFIG_APBH_DMA
547 /* Start APBH DMA */ 553 /* Start APBH DMA */
548 mxs_dma_init(); 554 mxs_dma_init();
549 #endif 555 #endif
550 556
551 init_src(); 557 init_src();
552 558
553 if (is_mx6dqp()) 559 if (is_mx6dqp())
554 writel(0x80000201, 0xbb0608); 560 writel(0x80000201, 0xbb0608);
555 561
556 return 0; 562 return 0;
557 } 563 }
558 564
559 #ifdef CONFIG_ENV_IS_IN_MMC 565 #ifdef CONFIG_ENV_IS_IN_MMC
560 __weak int board_mmc_get_env_dev(int devno) 566 __weak int board_mmc_get_env_dev(int devno)
561 { 567 {
562 return CONFIG_SYS_MMC_ENV_DEV; 568 return CONFIG_SYS_MMC_ENV_DEV;
563 } 569 }
564 570
565 static int mmc_get_boot_dev(void) 571 static int mmc_get_boot_dev(void)
566 { 572 {
567 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 573 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
568 u32 soc_sbmr = readl(&src_regs->sbmr1); 574 u32 soc_sbmr = readl(&src_regs->sbmr1);
569 u32 bootsel; 575 u32 bootsel;
570 int devno; 576 int devno;
571 577
572 /* 578 /*
573 * Refer to 579 * Refer to
574 * "i.MX 6Dual/6Quad Applications Processor Reference Manual" 580 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
575 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" 581 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
576 * i.MX6SL/SX/UL has same layout. 582 * i.MX6SL/SX/UL has same layout.
577 */ 583 */
578 bootsel = (soc_sbmr & 0x000000FF) >> 6; 584 bootsel = (soc_sbmr & 0x000000FF) >> 6;
579 585
580 /* No boot from sd/mmc */ 586 /* No boot from sd/mmc */
581 if (bootsel != 1) 587 if (bootsel != 1)
582 return -1; 588 return -1;
583 589
584 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 590 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
585 devno = (soc_sbmr & 0x00001800) >> 11; 591 devno = (soc_sbmr & 0x00001800) >> 11;
586 592
587 return devno; 593 return devno;
588 } 594 }
589 595
590 int mmc_get_env_dev(void) 596 int mmc_get_env_dev(void)
591 { 597 {
592 int devno = mmc_get_boot_dev(); 598 int devno = mmc_get_boot_dev();
593 599
594 /* If not boot from sd/mmc, use default value */ 600 /* If not boot from sd/mmc, use default value */
595 if (devno < 0) 601 if (devno < 0)
596 return CONFIG_SYS_MMC_ENV_DEV; 602 return CONFIG_SYS_MMC_ENV_DEV;
597 603
598 return board_mmc_get_env_dev(devno); 604 return board_mmc_get_env_dev(devno);
599 } 605 }
600 606
601 #ifdef CONFIG_SYS_MMC_ENV_PART 607 #ifdef CONFIG_SYS_MMC_ENV_PART
602 __weak int board_mmc_get_env_part(int devno) 608 __weak int board_mmc_get_env_part(int devno)
603 { 609 {
604 return CONFIG_SYS_MMC_ENV_PART; 610 return CONFIG_SYS_MMC_ENV_PART;
605 } 611 }
606 612
607 uint mmc_get_env_part(struct mmc *mmc) 613 uint mmc_get_env_part(struct mmc *mmc)
608 { 614 {
609 int devno = mmc_get_boot_dev(); 615 int devno = mmc_get_boot_dev();
610 616
611 /* If not boot from sd/mmc, use default value */ 617 /* If not boot from sd/mmc, use default value */
612 if (devno < 0) 618 if (devno < 0)
613 return CONFIG_SYS_MMC_ENV_PART; 619 return CONFIG_SYS_MMC_ENV_PART;
614 620
615 return board_mmc_get_env_part(devno); 621 return board_mmc_get_env_part(devno);
616 } 622 }
617 #endif 623 #endif
618 #endif 624 #endif
619 625
620 int board_postclk_init(void) 626 int board_postclk_init(void)
621 { 627 {
622 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ 628 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
623 629
624 return 0; 630 return 0;
625 } 631 }
626 632
627 #ifdef CONFIG_SERIAL_TAG 633 #ifdef CONFIG_SERIAL_TAG
628 void get_board_serial(struct tag_serialnr *serialnr) 634 void get_board_serial(struct tag_serialnr *serialnr)
629 { 635 {
630 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 636 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
631 struct fuse_bank *bank = &ocotp->bank[0]; 637 struct fuse_bank *bank = &ocotp->bank[0];
632 struct fuse_bank0_regs *fuse = 638 struct fuse_bank0_regs *fuse =
633 (struct fuse_bank0_regs *)bank->fuse_regs; 639 (struct fuse_bank0_regs *)bank->fuse_regs;
634 640
635 serialnr->low = fuse->uid_low; 641 serialnr->low = fuse->uid_low;
636 serialnr->high = fuse->uid_high; 642 serialnr->high = fuse->uid_high;
637 } 643 }
638 #endif 644 #endif
639 645
640 #if defined(CONFIG_FEC_MXC) 646 #if defined(CONFIG_FEC_MXC)
641 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 647 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
642 { 648 {
643 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 649 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
644 struct fuse_bank *bank = &ocotp->bank[4]; 650 struct fuse_bank *bank = &ocotp->bank[4];
645 struct fuse_bank4_regs *fuse = 651 struct fuse_bank4_regs *fuse =
646 (struct fuse_bank4_regs *)bank->fuse_regs; 652 (struct fuse_bank4_regs *)bank->fuse_regs;
647 653
648 if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 654 if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
649 is_cpu_type(MXC_CPU_MX6ULL)) && dev_id == 1) { 655 is_cpu_type(MXC_CPU_MX6ULL)) && dev_id == 1) {
650 u32 value = readl(&fuse->mac_addr2); 656 u32 value = readl(&fuse->mac_addr2);
651 mac[0] = value >> 24 ; 657 mac[0] = value >> 24 ;
652 mac[1] = value >> 16 ; 658 mac[1] = value >> 16 ;
653 mac[2] = value >> 8 ; 659 mac[2] = value >> 8 ;
654 mac[3] = value ; 660 mac[3] = value ;
655 661
656 value = readl(&fuse->mac_addr1); 662 value = readl(&fuse->mac_addr1);
657 mac[4] = value >> 24 ; 663 mac[4] = value >> 24 ;
658 mac[5] = value >> 16 ; 664 mac[5] = value >> 16 ;
659 665
660 } else { 666 } else {
661 u32 value = readl(&fuse->mac_addr1); 667 u32 value = readl(&fuse->mac_addr1);
662 mac[0] = (value >> 8); 668 mac[0] = (value >> 8);
663 mac[1] = value ; 669 mac[1] = value ;
664 670
665 value = readl(&fuse->mac_addr0); 671 value = readl(&fuse->mac_addr0);
666 mac[2] = value >> 24 ; 672 mac[2] = value >> 24 ;
667 mac[3] = value >> 16 ; 673 mac[3] = value >> 16 ;
668 mac[4] = value >> 8 ; 674 mac[4] = value >> 8 ;
669 mac[5] = value ; 675 mac[5] = value ;
670 } 676 }
671 677
672 } 678 }
673 #endif 679 #endif
674 680
675 /* 681 /*
676 * cfg_val will be used for 682 * cfg_val will be used for
677 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 683 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
678 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] 684 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
679 * instead of SBMR1 to determine the boot device. 685 * instead of SBMR1 to determine the boot device.
680 */ 686 */
681 const struct boot_mode soc_boot_modes[] = { 687 const struct boot_mode soc_boot_modes[] = {
682 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, 688 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
683 /* reserved value should start rom usb */ 689 /* reserved value should start rom usb */
684 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, 690 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
685 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, 691 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
686 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, 692 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
687 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, 693 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
688 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, 694 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
689 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, 695 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
690 /* 4 bit bus width */ 696 /* 4 bit bus width */
691 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 697 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
692 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 698 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
693 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 699 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
694 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 700 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
695 {NULL, 0}, 701 {NULL, 0},
696 }; 702 };
697 703
698 enum boot_device get_boot_device(void) 704 enum boot_device get_boot_device(void)
699 { 705 {
700 enum boot_device boot_dev = UNKNOWN_BOOT; 706 enum boot_device boot_dev = UNKNOWN_BOOT;
701 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 707 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
702 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; 708 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
703 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; 709 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
704 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11; 710 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11;
705 711
706 switch (bt_mem_ctl) { 712 switch (bt_mem_ctl) {
707 case 0x0: 713 case 0x0:
708 if (bt_mem_type) 714 if (bt_mem_type)
709 boot_dev = ONE_NAND_BOOT; 715 boot_dev = ONE_NAND_BOOT;
710 else 716 else
711 boot_dev = WEIM_NOR_BOOT; 717 boot_dev = WEIM_NOR_BOOT;
712 break; 718 break;
713 case 0x2: 719 case 0x2:
714 boot_dev = SATA_BOOT; 720 boot_dev = SATA_BOOT;
715 break; 721 break;
716 case 0x3: 722 case 0x3:
717 if (bt_mem_type) 723 if (bt_mem_type)
718 boot_dev = I2C_BOOT; 724 boot_dev = I2C_BOOT;
719 else 725 else
720 boot_dev = SPI_NOR_BOOT; 726 boot_dev = SPI_NOR_BOOT;
721 break; 727 break;
722 case 0x4: 728 case 0x4:
723 case 0x5: 729 case 0x5:
724 boot_dev = bt_dev_port + SD1_BOOT; 730 boot_dev = bt_dev_port + SD1_BOOT;
725 break; 731 break;
726 case 0x6: 732 case 0x6:
727 case 0x7: 733 case 0x7:
728 boot_dev = bt_dev_port + MMC1_BOOT; 734 boot_dev = bt_dev_port + MMC1_BOOT;
729 break; 735 break;
730 case 0x8 ... 0xf: 736 case 0x8 ... 0xf:
731 boot_dev = NAND_BOOT; 737 boot_dev = NAND_BOOT;
732 break; 738 break;
733 default: 739 default:
734 boot_dev = UNKNOWN_BOOT; 740 boot_dev = UNKNOWN_BOOT;
735 break; 741 break;
736 } 742 }
737 743
738 return boot_dev; 744 return boot_dev;
739 } 745 }
740 746
741 void set_wdog_reset(struct wdog_regs *wdog) 747 void set_wdog_reset(struct wdog_regs *wdog)
742 { 748 {
743 u32 reg = readw(&wdog->wcr); 749 u32 reg = readw(&wdog->wcr);
744 /* 750 /*
745 * use WDOG_B mode to reset external pmic because it's risky for the 751 * use WDOG_B mode to reset external pmic because it's risky for the
746 * following watchdog reboot in case of cpu freq at lowest 400Mhz with 752 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
747 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So 753 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
748 * in ldo-bypass mode watchdog reset will only triger POR reset, not 754 * in ldo-bypass mode watchdog reset will only triger POR reset, not
749 * WDOG reset. But below code depends on hardware design, if HW didn't 755 * WDOG reset. But below code depends on hardware design, if HW didn't
750 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip 756 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
751 * these code since it assumed boot from 400Mhz always. 757 * these code since it assumed boot from 400Mhz always.
752 */ 758 */
753 reg = readw(&wdog->wcr); 759 reg = readw(&wdog->wcr);
754 reg |= 1 << 3; 760 reg |= 1 << 3;
755 /* 761 /*
756 * WDZST bit is write-once only bit. Align this bit in kernel, 762 * WDZST bit is write-once only bit. Align this bit in kernel,
757 * otherwise kernel code will have no chance to set this bit. 763 * otherwise kernel code will have no chance to set this bit.
758 */ 764 */
759 reg |= 1 << 0; 765 reg |= 1 << 0;
760 writew(reg, &wdog->wcr); 766 writew(reg, &wdog->wcr);
761 } 767 }
762 768
763 void reset_misc(void) 769 void reset_misc(void)
764 { 770 {
765 #ifdef CONFIG_VIDEO_MXS 771 #ifdef CONFIG_VIDEO_MXS
766 lcdif_power_down(); 772 lcdif_power_down();
767 #endif 773 #endif
768 } 774 }
769 775
770 void s_init(void) 776 void s_init(void)
771 { 777 {
772 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 778 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
773 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 779 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
774 u32 mask480; 780 u32 mask480;
775 u32 mask528; 781 u32 mask528;
776 u32 reg, periph1, periph2; 782 u32 reg, periph1, periph2;
777 783
778 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 784 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
779 is_cpu_type(MXC_CPU_MX6ULL)) 785 is_cpu_type(MXC_CPU_MX6ULL))
780 return; 786 return;
781 787
782 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs 788 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
783 * to make sure PFD is working right, otherwise, PFDs may 789 * to make sure PFD is working right, otherwise, PFDs may
784 * not output clock after reset, MX6DL and MX6SL have added 396M pfd 790 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
785 * workaround in ROM code, as bus clock need it 791 * workaround in ROM code, as bus clock need it
786 */ 792 */
787 793
788 mask480 = ANATOP_PFD_CLKGATE_MASK(0) | 794 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
789 ANATOP_PFD_CLKGATE_MASK(1) | 795 ANATOP_PFD_CLKGATE_MASK(1) |
790 ANATOP_PFD_CLKGATE_MASK(2) | 796 ANATOP_PFD_CLKGATE_MASK(2) |
791 ANATOP_PFD_CLKGATE_MASK(3); 797 ANATOP_PFD_CLKGATE_MASK(3);
792 mask528 = ANATOP_PFD_CLKGATE_MASK(1) | 798 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
793 ANATOP_PFD_CLKGATE_MASK(3); 799 ANATOP_PFD_CLKGATE_MASK(3);
794 800
795 reg = readl(&ccm->cbcmr); 801 reg = readl(&ccm->cbcmr);
796 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) 802 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
797 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); 803 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
798 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 804 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
799 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); 805 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
800 806
801 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ 807 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
802 if ((periph2 != 0x2) && (periph1 != 0x2)) 808 if ((periph2 != 0x2) && (periph1 != 0x2))
803 mask528 |= ANATOP_PFD_CLKGATE_MASK(0); 809 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
804 810
805 if ((periph2 != 0x1) && (periph1 != 0x1) && 811 if ((periph2 != 0x1) && (periph1 != 0x1) &&
806 (periph2 != 0x3) && (periph1 != 0x3)) 812 (periph2 != 0x3) && (periph1 != 0x3))
807 mask528 |= ANATOP_PFD_CLKGATE_MASK(2); 813 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
808 814
809 writel(mask480, &anatop->pfd_480_set); 815 writel(mask480, &anatop->pfd_480_set);
810 writel(mask528, &anatop->pfd_528_set); 816 writel(mask528, &anatop->pfd_528_set);
811 writel(mask480, &anatop->pfd_480_clr); 817 writel(mask480, &anatop->pfd_480_clr);
812 writel(mask528, &anatop->pfd_528_clr); 818 writel(mask528, &anatop->pfd_528_clr);
813 } 819 }
814 820
815 #ifdef CONFIG_IMX_HDMI 821 #ifdef CONFIG_IMX_HDMI
816 void imx_enable_hdmi_phy(void) 822 void imx_enable_hdmi_phy(void)
817 { 823 {
818 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 824 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
819 u8 reg; 825 u8 reg;
820 reg = readb(&hdmi->phy_conf0); 826 reg = readb(&hdmi->phy_conf0);
821 reg |= HDMI_PHY_CONF0_PDZ_MASK; 827 reg |= HDMI_PHY_CONF0_PDZ_MASK;
822 writeb(reg, &hdmi->phy_conf0); 828 writeb(reg, &hdmi->phy_conf0);
823 udelay(3000); 829 udelay(3000);
824 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; 830 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
825 writeb(reg, &hdmi->phy_conf0); 831 writeb(reg, &hdmi->phy_conf0);
826 udelay(3000); 832 udelay(3000);
827 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; 833 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
828 writeb(reg, &hdmi->phy_conf0); 834 writeb(reg, &hdmi->phy_conf0);
829 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); 835 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
830 } 836 }
831 837
832 void imx_setup_hdmi(void) 838 void imx_setup_hdmi(void)
833 { 839 {
834 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 840 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
835 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 841 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
836 int reg, count; 842 int reg, count;
837 u8 val; 843 u8 val;
838 844
839 /* Turn on HDMI PHY clock */ 845 /* Turn on HDMI PHY clock */
840 reg = readl(&mxc_ccm->CCGR2); 846 reg = readl(&mxc_ccm->CCGR2);
841 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| 847 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
842 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; 848 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
843 writel(reg, &mxc_ccm->CCGR2); 849 writel(reg, &mxc_ccm->CCGR2);
844 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); 850 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
845 reg = readl(&mxc_ccm->chsccdr); 851 reg = readl(&mxc_ccm->chsccdr);
846 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| 852 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
847 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| 853 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
848 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 854 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
849 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 855 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
850 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) 856 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
851 |(CHSCCDR_IPU_PRE_CLK_540M_PFD 857 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
852 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 858 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
853 writel(reg, &mxc_ccm->chsccdr); 859 writel(reg, &mxc_ccm->chsccdr);
854 860
855 /* Workaround to clear the overflow condition */ 861 /* Workaround to clear the overflow condition */
856 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { 862 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
857 /* TMDS software reset */ 863 /* TMDS software reset */
858 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); 864 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
859 val = readb(&hdmi->fc_invidconf); 865 val = readb(&hdmi->fc_invidconf);
860 for (count = 0 ; count < 5 ; count++) 866 for (count = 0 ; count < 5 ; count++)
861 writeb(val, &hdmi->fc_invidconf); 867 writeb(val, &hdmi->fc_invidconf);
862 } 868 }
863 } 869 }
864 #endif 870 #endif
865 871
866 #ifdef CONFIG_IMX_BOOTAUX 872 #ifdef CONFIG_IMX_BOOTAUX
867 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) 873 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
868 { 874 {
869 struct src *src_reg; 875 struct src *src_reg;
870 u32 stack, pc; 876 u32 stack, pc;
871 877
872 if (!boot_private_data) 878 if (!boot_private_data)
873 return -EINVAL; 879 return -EINVAL;
874 880
875 stack = *(u32 *)boot_private_data; 881 stack = *(u32 *)boot_private_data;
876 pc = *(u32 *)(boot_private_data + 4); 882 pc = *(u32 *)(boot_private_data + 4);
877 883
878 /* Set the stack and pc to M4 bootROM */ 884 /* Set the stack and pc to M4 bootROM */
879 writel(stack, M4_BOOTROM_BASE_ADDR); 885 writel(stack, M4_BOOTROM_BASE_ADDR);
880 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 886 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
881 887
882 /* Enable M4 */ 888 /* Enable M4 */
883 src_reg = (struct src *)SRC_BASE_ADDR; 889 src_reg = (struct src *)SRC_BASE_ADDR;
884 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, 890 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
885 SRC_SCR_M4_ENABLE_MASK); 891 SRC_SCR_M4_ENABLE_MASK);
886 892
887 return 0; 893 return 0;
888 } 894 }
889 895
890 int arch_auxiliary_core_check_up(u32 core_id) 896 int arch_auxiliary_core_check_up(u32 core_id)
891 { 897 {
892 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 898 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
893 unsigned val; 899 unsigned val;
894 900
895 val = readl(&src_reg->scr); 901 val = readl(&src_reg->scr);
896 902
897 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) 903 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
898 return 0; /* assert in reset */ 904 return 0; /* assert in reset */
899 905
900 return 1; 906 return 1;
901 } 907 }
902 #endif 908 #endif
903 909
904 #ifdef CONFIG_LDO_BYPASS_CHECK 910 #ifdef CONFIG_LDO_BYPASS_CHECK
905 DECLARE_GLOBAL_DATA_PTR; 911 DECLARE_GLOBAL_DATA_PTR;
906 static int ldo_bypass; 912 static int ldo_bypass;
907 913
908 int check_ldo_bypass(void) 914 int check_ldo_bypass(void)
909 { 915 {
910 const int *ldo_mode; 916 const int *ldo_mode;
911 int node; 917 int node;
912 918
913 /* get the right fdt_blob from the global working_fdt */ 919 /* get the right fdt_blob from the global working_fdt */
914 gd->fdt_blob = working_fdt; 920 gd->fdt_blob = working_fdt;
915 /* Get the node from FDT for anatop ldo-bypass */ 921 /* Get the node from FDT for anatop ldo-bypass */
916 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 922 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
917 "fsl,imx6q-gpc"); 923 "fsl,imx6q-gpc");
918 if (node < 0) { 924 if (node < 0) {
919 printf("No gpc device node %d, force to ldo-enable.\n", node); 925 printf("No gpc device node %d, force to ldo-enable.\n", node);
920 return 0; 926 return 0;
921 } 927 }
922 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL); 928 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL);
923 /* 929 /*
924 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if 930 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if
925 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property 931 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property
926 */ 932 */
927 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0; 933 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
928 934
929 return ldo_bypass; 935 return ldo_bypass;
930 } 936 }
931 937
932 int check_1_2G(void) 938 int check_1_2G(void)
933 { 939 {
934 u32 reg; 940 u32 reg;
935 int result = 0; 941 int result = 0;
936 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 942 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
937 struct fuse_bank *bank = &ocotp->bank[0]; 943 struct fuse_bank *bank = &ocotp->bank[0];
938 struct fuse_bank0_regs *fuse_bank0 = 944 struct fuse_bank0_regs *fuse_bank0 =
939 (struct fuse_bank0_regs *)bank->fuse_regs; 945 (struct fuse_bank0_regs *)bank->fuse_regs;
940 946
941 reg = readl(&fuse_bank0->cfg3); 947 reg = readl(&fuse_bank0->cfg3);
942 if (((reg >> 16) & 0x3) == 0x3) { 948 if (((reg >> 16) & 0x3) == 0x3) {
943 if (ldo_bypass) { 949 if (ldo_bypass) {
944 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only " 950 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only "
945 "works with ldo-enable mode!\n"); 951 "works with ldo-enable mode!\n");
946 /* 952 /*
947 * Currently, only imx6q-sabresd board might be here, 953 * Currently, only imx6q-sabresd board might be here,
948 * since only i.MX6Q support 1.2G and only Sabresd board 954 * since only i.MX6Q support 1.2G and only Sabresd board
949 * support ldo-bypass mode. So hardcode here. 955 * support ldo-bypass mode. So hardcode here.
950 * You can also modify your board(i.MX6Q) dtb name if it 956 * You can also modify your board(i.MX6Q) dtb name if it
951 * supports both ldo-bypass and ldo-enable mode. 957 * supports both ldo-bypass and ldo-enable mode.
952 */ 958 */
953 printf("Please use imx6q-sabresd-ldo.dtb!\n"); 959 printf("Please use imx6q-sabresd-ldo.dtb!\n");
954 hang(); 960 hang();
955 } 961 }
956 result = 1; 962 result = 1;
957 } 963 }
958 964
959 return result; 965 return result;
960 } 966 }
961 967
962 static int arm_orig_podf; 968 static int arm_orig_podf;
963 void set_arm_freq_400M(bool is_400M) 969 void set_arm_freq_400M(bool is_400M)
964 { 970 {
965 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 971 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
966 972
967 if (is_400M) 973 if (is_400M)
968 writel(0x1, &mxc_ccm->cacrr); 974 writel(0x1, &mxc_ccm->cacrr);
969 else 975 else
970 writel(arm_orig_podf, &mxc_ccm->cacrr); 976 writel(arm_orig_podf, &mxc_ccm->cacrr);
971 } 977 }
972 978
973 void prep_anatop_bypass(void) 979 void prep_anatop_bypass(void)
974 { 980 {
975 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 981 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
976 982
977 arm_orig_podf = readl(&mxc_ccm->cacrr); 983 arm_orig_podf = readl(&mxc_ccm->cacrr);
978 /* 984 /*
979 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo 985 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo
980 * bypassed, also downgrade internal vddarm ldo to 0.975V. 986 * bypassed, also downgrade internal vddarm ldo to 0.975V.
981 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V) 987 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)
982 * otherwise at 800Mhz(i.mx6dl): 988 * otherwise at 800Mhz(i.mx6dl):
983 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V) 989 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)
984 * We need provide enough gap in this case. 990 * We need provide enough gap in this case.
985 * skip if boot from 400M. 991 * skip if boot from 400M.
986 */ 992 */
987 if (!arm_orig_podf) 993 if (!arm_orig_podf)
988 set_arm_freq_400M(true); 994 set_arm_freq_400M(true);
989 995
990 if (!is_cpu_type(MXC_CPU_MX6DL) && !is_cpu_type(MXC_CPU_MX6SX)) 996 if (!is_cpu_type(MXC_CPU_MX6DL) && !is_cpu_type(MXC_CPU_MX6SX))
991 set_ldo_voltage(LDO_ARM, 975); 997 set_ldo_voltage(LDO_ARM, 975);
992 else 998 else
993 set_ldo_voltage(LDO_ARM, 1150); 999 set_ldo_voltage(LDO_ARM, 1150);
994 } 1000 }
995 1001
996 int set_anatop_bypass(int wdog_reset_pin) 1002 int set_anatop_bypass(int wdog_reset_pin)
997 { 1003 {
998 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 1004 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
999 struct wdog_regs *wdog; 1005 struct wdog_regs *wdog;
1000 u32 reg = readl(&anatop->reg_core); 1006 u32 reg = readl(&anatop->reg_core);
1001 1007
1002 /* bypass VDDARM/VDDSOC */ 1008 /* bypass VDDARM/VDDSOC */
1003 reg = reg | (0x1F << 18) | 0x1F; 1009 reg = reg | (0x1F << 18) | 0x1F;
1004 writel(reg, &anatop->reg_core); 1010 writel(reg, &anatop->reg_core);
1005 1011
1006 if (wdog_reset_pin == 2) 1012 if (wdog_reset_pin == 2)
1007 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR; 1013 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
1008 else if (wdog_reset_pin == 1) 1014 else if (wdog_reset_pin == 1)
1009 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR; 1015 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
1010 else 1016 else
1011 return arm_orig_podf; 1017 return arm_orig_podf;
1012 set_wdog_reset(wdog); 1018 set_wdog_reset(wdog);
1013 return arm_orig_podf; 1019 return arm_orig_podf;
1014 } 1020 }
1015 1021
1016 void finish_anatop_bypass(void) 1022 void finish_anatop_bypass(void)
1017 { 1023 {
1018 if (!arm_orig_podf) 1024 if (!arm_orig_podf)
1019 set_arm_freq_400M(false); 1025 set_arm_freq_400M(false);
1020 } 1026 }
1021 #endif 1027 #endif
1022 1028
1023 #ifdef CONFIG_FSL_FASTBOOT 1029 #ifdef CONFIG_FSL_FASTBOOT
1024 1030
1025 #ifdef CONFIG_ANDROID_RECOVERY 1031 #ifdef CONFIG_ANDROID_RECOVERY
1026 #define ANDROID_RECOVERY_BOOT (1 << 7) 1032 #define ANDROID_RECOVERY_BOOT (1 << 7)
1027 /* check if the recovery bit is set by kernel, it can be set by kernel 1033 /* check if the recovery bit is set by kernel, it can be set by kernel
1028 * issue a command '# reboot recovery' */ 1034 * issue a command '# reboot recovery' */
1029 int recovery_check_and_clean_flag(void) 1035 int recovery_check_and_clean_flag(void)
1030 { 1036 {
1031 int flag_set = 0; 1037 int flag_set = 0;
1032 u32 reg; 1038 u32 reg;
1033 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1039 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1034 1040
1035 flag_set = !!(reg & ANDROID_RECOVERY_BOOT); 1041 flag_set = !!(reg & ANDROID_RECOVERY_BOOT);
1036 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set); 1042 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set);
1037 /* clean it in case looping infinite here.... */ 1043 /* clean it in case looping infinite here.... */
1038 if (flag_set) { 1044 if (flag_set) {
1039 reg &= ~ANDROID_RECOVERY_BOOT; 1045 reg &= ~ANDROID_RECOVERY_BOOT;
1040 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1046 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1041 } 1047 }
1042 1048
1043 return flag_set; 1049 return flag_set;
1044 } 1050 }
1045 #endif /*CONFIG_ANDROID_RECOVERY*/ 1051 #endif /*CONFIG_ANDROID_RECOVERY*/
1046 1052
1047 #define ANDROID_FASTBOOT_BOOT (1 << 8) 1053 #define ANDROID_FASTBOOT_BOOT (1 << 8)
1048 /* check if the recovery bit is set by kernel, it can be set by kernel 1054 /* check if the recovery bit is set by kernel, it can be set by kernel
1049 * issue a command '# reboot fastboot' */ 1055 * issue a command '# reboot fastboot' */
1050 int fastboot_check_and_clean_flag(void) 1056 int fastboot_check_and_clean_flag(void)
1051 { 1057 {
1052 int flag_set = 0; 1058 int flag_set = 0;
1053 u32 reg; 1059 u32 reg;
1054 1060
1055 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1061 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1056 1062
1057 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT); 1063 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT);
1058 1064
1059 /* clean it in case looping infinite here.... */ 1065 /* clean it in case looping infinite here.... */
1060 if (flag_set) { 1066 if (flag_set) {
1061 reg &= ~ANDROID_FASTBOOT_BOOT; 1067 reg &= ~ANDROID_FASTBOOT_BOOT;
1062 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1068 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1063 } 1069 }
1064 1070
1065 return flag_set; 1071 return flag_set;
1066 } 1072 }
1067 1073
1068 void fastboot_enable_flag(void) 1074 void fastboot_enable_flag(void)
1069 { 1075 {
1070 setbits_le32(SNVS_BASE_ADDR + SNVS_LPGPR, 1076 setbits_le32(SNVS_BASE_ADDR + SNVS_LPGPR,
1071 ANDROID_FASTBOOT_BOOT); 1077 ANDROID_FASTBOOT_BOOT);
1072 } 1078 }
1073 #endif /*CONFIG_FSL_FASTBOOT*/ 1079 #endif /*CONFIG_FSL_FASTBOOT*/
1074 1080
1075 1081
arch/arm/include/asm/arch-mx6/crm_regs.h
Diff comments   View file @ 91703d0
1 /* 1 /*
2 * Copyright 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
9 9
10 #define CCM_CCOSR 0x020c4060 10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068 11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c 12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070 13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074 14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078 15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c 16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080 17 #define CCM_CCGR6 0x020C4080
18 18
19 #define PMU_MISC2 0x020C8170 19 #define PMU_MISC2 0x020C8170
20 20
21 #ifndef __ASSEMBLY__ 21 #ifndef __ASSEMBLY__
22 struct mxc_ccm_reg { 22 struct mxc_ccm_reg {
23 u32 ccr; /* 0x0000 */ 23 u32 ccr; /* 0x0000 */
24 u32 ccdr; 24 u32 ccdr;
25 u32 csr; 25 u32 csr;
26 u32 ccsr; 26 u32 ccsr;
27 u32 cacrr; /* 0x0010*/ 27 u32 cacrr; /* 0x0010*/
28 u32 cbcdr; 28 u32 cbcdr;
29 u32 cbcmr; 29 u32 cbcmr;
30 u32 cscmr1; 30 u32 cscmr1;
31 u32 cscmr2; /* 0x0020 */ 31 u32 cscmr2; /* 0x0020 */
32 u32 cscdr1; 32 u32 cscdr1;
33 u32 cs1cdr; 33 u32 cs1cdr;
34 u32 cs2cdr; 34 u32 cs2cdr;
35 u32 cdcdr; /* 0x0030 */ 35 u32 cdcdr; /* 0x0030 */
36 u32 chsccdr; 36 u32 chsccdr;
37 u32 cscdr2; 37 u32 cscdr2;
38 u32 cscdr3; 38 u32 cscdr3;
39 u32 cscdr4; /* 0x0040 */ 39 u32 cscdr4; /* 0x0040 */
40 u32 resv0; 40 u32 resv0;
41 u32 cdhipr; 41 u32 cdhipr;
42 u32 cdcr; 42 u32 cdcr;
43 u32 ctor; /* 0x0050 */ 43 u32 ctor; /* 0x0050 */
44 u32 clpcr; 44 u32 clpcr;
45 u32 cisr; 45 u32 cisr;
46 u32 cimr; 46 u32 cimr;
47 u32 ccosr; /* 0x0060 */ 47 u32 ccosr; /* 0x0060 */
48 u32 cgpr; 48 u32 cgpr;
49 u32 CCGR0; 49 u32 CCGR0;
50 u32 CCGR1; 50 u32 CCGR1;
51 u32 CCGR2; /* 0x0070 */ 51 u32 CCGR2; /* 0x0070 */
52 u32 CCGR3; 52 u32 CCGR3;
53 u32 CCGR4; 53 u32 CCGR4;
54 u32 CCGR5; 54 u32 CCGR5;
55 u32 CCGR6; /* 0x0080 */ 55 u32 CCGR6; /* 0x0080 */
56 u32 CCGR7; 56 u32 CCGR7;
57 u32 cmeor; 57 u32 cmeor;
58 u32 resv[0xfdd]; 58 u32 resv[0xfdd];
59 u32 analog_pll_sys; /* 0x4000 */ 59 u32 analog_pll_sys; /* 0x4000 */
60 u32 analog_pll_sys_set; 60 u32 analog_pll_sys_set;
61 u32 analog_pll_sys_clr; 61 u32 analog_pll_sys_clr;
62 u32 analog_pll_sys_tog; 62 u32 analog_pll_sys_tog;
63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
64 u32 analog_usb1_pll_480_ctrl_set; 64 u32 analog_usb1_pll_480_ctrl_set;
65 u32 analog_usb1_pll_480_ctrl_clr; 65 u32 analog_usb1_pll_480_ctrl_clr;
66 u32 analog_usb1_pll_480_ctrl_tog; 66 u32 analog_usb1_pll_480_ctrl_tog;
67 u32 analog_reserved0[4]; 67 u32 analog_reserved0[4];
68 u32 analog_pll_528; /* 0x4030 */ 68 u32 analog_pll_528; /* 0x4030 */
69 u32 analog_pll_528_set; 69 u32 analog_pll_528_set;
70 u32 analog_pll_528_clr; 70 u32 analog_pll_528_clr;
71 u32 analog_pll_528_tog; 71 u32 analog_pll_528_tog;
72 u32 analog_pll_528_ss; /* 0x4040 */ 72 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_reserved1[3]; 73 u32 analog_reserved1[3];
74 u32 analog_pll_528_num; /* 0x4050 */ 74 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_reserved2[3]; 75 u32 analog_reserved2[3];
76 u32 analog_pll_528_denom; /* 0x4060 */ 76 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_reserved3[3]; 77 u32 analog_reserved3[3];
78 u32 analog_pll_audio; /* 0x4070 */ 78 u32 analog_pll_audio; /* 0x4070 */
79 u32 analog_pll_audio_set; 79 u32 analog_pll_audio_set;
80 u32 analog_pll_audio_clr; 80 u32 analog_pll_audio_clr;
81 u32 analog_pll_audio_tog; 81 u32 analog_pll_audio_tog;
82 u32 analog_pll_audio_num; /* 0x4080*/ 82 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_reserved4[3]; 83 u32 analog_reserved4[3];
84 u32 analog_pll_audio_denom; /* 0x4090 */ 84 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_reserved5[3]; 85 u32 analog_reserved5[3];
86 u32 analog_pll_video; /* 0x40a0 */ 86 u32 analog_pll_video; /* 0x40a0 */
87 u32 analog_pll_video_set; 87 u32 analog_pll_video_set;
88 u32 analog_pll_video_clr; 88 u32 analog_pll_video_clr;
89 u32 analog_pll_video_tog; 89 u32 analog_pll_video_tog;
90 u32 analog_pll_video_num; /* 0x40b0 */ 90 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_reserved6[3]; 91 u32 analog_reserved6[3];
92 u32 analog_pll_video_denom; /* 0x40c0 */ 92 u32 analog_pll_video_denom; /* 0x40c0 */
93 u32 analog_reserved7[7]; 93 u32 analog_reserved7[7];
94 u32 analog_pll_enet; /* 0x40e0 */ 94 u32 analog_pll_enet; /* 0x40e0 */
95 u32 analog_pll_enet_set; 95 u32 analog_pll_enet_set;
96 u32 analog_pll_enet_clr; 96 u32 analog_pll_enet_clr;
97 u32 analog_pll_enet_tog; 97 u32 analog_pll_enet_tog;
98 u32 analog_pfd_480; /* 0x40f0 */ 98 u32 analog_pfd_480; /* 0x40f0 */
99 u32 analog_pfd_480_set; 99 u32 analog_pfd_480_set;
100 u32 analog_pfd_480_clr; 100 u32 analog_pfd_480_clr;
101 u32 analog_pfd_480_tog; 101 u32 analog_pfd_480_tog;
102 u32 analog_pfd_528; /* 0x4100 */ 102 u32 analog_pfd_528; /* 0x4100 */
103 u32 analog_pfd_528_set; 103 u32 analog_pfd_528_set;
104 u32 analog_pfd_528_clr; 104 u32 analog_pfd_528_clr;
105 u32 analog_pfd_528_tog; 105 u32 analog_pfd_528_tog;
106 /* PMU Memory Map/Register Definition */ 106 /* PMU Memory Map/Register Definition */
107 u32 pmu_reg_1p1; 107 u32 pmu_reg_1p1;
108 u32 pmu_reg_1p1_set; 108 u32 pmu_reg_1p1_set;
109 u32 pmu_reg_1p1_clr; 109 u32 pmu_reg_1p1_clr;
110 u32 pmu_reg_1p1_tog; 110 u32 pmu_reg_1p1_tog;
111 u32 pmu_reg_3p0; 111 u32 pmu_reg_3p0;
112 u32 pmu_reg_3p0_set; 112 u32 pmu_reg_3p0_set;
113 u32 pmu_reg_3p0_clr; 113 u32 pmu_reg_3p0_clr;
114 u32 pmu_reg_3p0_tog; 114 u32 pmu_reg_3p0_tog;
115 u32 pmu_reg_2p5; 115 u32 pmu_reg_2p5;
116 u32 pmu_reg_2p5_set; 116 u32 pmu_reg_2p5_set;
117 u32 pmu_reg_2p5_clr; 117 u32 pmu_reg_2p5_clr;
118 u32 pmu_reg_2p5_tog; 118 u32 pmu_reg_2p5_tog;
119 u32 pmu_reg_core; 119 u32 pmu_reg_core;
120 u32 pmu_reg_core_set; 120 u32 pmu_reg_core_set;
121 u32 pmu_reg_core_clr; 121 u32 pmu_reg_core_clr;
122 u32 pmu_reg_core_tog; 122 u32 pmu_reg_core_tog;
123 u32 pmu_misc0; 123 u32 pmu_misc0;
124 u32 pmu_misc0_set; 124 u32 pmu_misc0_set;
125 u32 pmu_misc0_clr; 125 u32 pmu_misc0_clr;
126 u32 pmu_misc0_tog; 126 u32 pmu_misc0_tog;
127 u32 pmu_misc1; 127 u32 pmu_misc1;
128 u32 pmu_misc1_set; 128 u32 pmu_misc1_set;
129 u32 pmu_misc1_clr; 129 u32 pmu_misc1_clr;
130 u32 pmu_misc1_tog; 130 u32 pmu_misc1_tog;
131 u32 pmu_misc2; 131 u32 pmu_misc2;
132 u32 pmu_misc2_set; 132 u32 pmu_misc2_set;
133 u32 pmu_misc2_clr; 133 u32 pmu_misc2_clr;
134 u32 pmu_misc2_tog; 134 u32 pmu_misc2_tog;
135 /* TEMPMON Memory Map/Register Definition */ 135 /* TEMPMON Memory Map/Register Definition */
136 u32 tempsense0; 136 u32 tempsense0;
137 u32 tempsense0_set; 137 u32 tempsense0_set;
138 u32 tempsense0_clr; 138 u32 tempsense0_clr;
139 u32 tempsense0_tog; 139 u32 tempsense0_tog;
140 u32 tempsense1; 140 u32 tempsense1;
141 u32 tempsense1_set; 141 u32 tempsense1_set;
142 u32 tempsense1_clr; 142 u32 tempsense1_clr;
143 u32 tempsense1_tog; 143 u32 tempsense1_tog;
144 /* USB Analog Memory Map/Register Definition */ 144 /* USB Analog Memory Map/Register Definition */
145 u32 usb1_vbus_detect; 145 u32 usb1_vbus_detect;
146 u32 usb1_vbus_detect_set; 146 u32 usb1_vbus_detect_set;
147 u32 usb1_vbus_detect_clr; 147 u32 usb1_vbus_detect_clr;
148 u32 usb1_vbus_detect_tog; 148 u32 usb1_vbus_detect_tog;
149 u32 usb1_chrg_detect; 149 u32 usb1_chrg_detect;
150 u32 usb1_chrg_detect_set; 150 u32 usb1_chrg_detect_set;
151 u32 usb1_chrg_detect_clr; 151 u32 usb1_chrg_detect_clr;
152 u32 usb1_chrg_detect_tog; 152 u32 usb1_chrg_detect_tog;
153 u32 usb1_vbus_det_stat; 153 u32 usb1_vbus_det_stat;
154 u32 usb1_vbus_det_stat_set; 154 u32 usb1_vbus_det_stat_set;
155 u32 usb1_vbus_det_stat_clr; 155 u32 usb1_vbus_det_stat_clr;
156 u32 usb1_vbus_det_stat_tog; 156 u32 usb1_vbus_det_stat_tog;
157 u32 usb1_chrg_det_stat; 157 u32 usb1_chrg_det_stat;
158 u32 usb1_chrg_det_stat_set; 158 u32 usb1_chrg_det_stat_set;
159 u32 usb1_chrg_det_stat_clr; 159 u32 usb1_chrg_det_stat_clr;
160 u32 usb1_chrg_det_stat_tog; 160 u32 usb1_chrg_det_stat_tog;
161 u32 usb1_loopback; 161 u32 usb1_loopback;
162 u32 usb1_loopback_set; 162 u32 usb1_loopback_set;
163 u32 usb1_loopback_clr; 163 u32 usb1_loopback_clr;
164 u32 usb1_loopback_tog; 164 u32 usb1_loopback_tog;
165 u32 usb1_misc; 165 u32 usb1_misc;
166 u32 usb1_misc_set; 166 u32 usb1_misc_set;
167 u32 usb1_misc_clr; 167 u32 usb1_misc_clr;
168 u32 usb1_misc_tog; 168 u32 usb1_misc_tog;
169 u32 usb2_vbus_detect; 169 u32 usb2_vbus_detect;
170 u32 usb2_vbus_detect_set; 170 u32 usb2_vbus_detect_set;
171 u32 usb2_vbus_detect_clr; 171 u32 usb2_vbus_detect_clr;
172 u32 usb2_vbus_detect_tog; 172 u32 usb2_vbus_detect_tog;
173 u32 usb2_chrg_detect; 173 u32 usb2_chrg_detect;
174 u32 usb2_chrg_detect_set; 174 u32 usb2_chrg_detect_set;
175 u32 usb2_chrg_detect_clr; 175 u32 usb2_chrg_detect_clr;
176 u32 usb2_chrg_detect_tog; 176 u32 usb2_chrg_detect_tog;
177 u32 usb2_vbus_det_stat; 177 u32 usb2_vbus_det_stat;
178 u32 usb2_vbus_det_stat_set; 178 u32 usb2_vbus_det_stat_set;
179 u32 usb2_vbus_det_stat_clr; 179 u32 usb2_vbus_det_stat_clr;
180 u32 usb2_vbus_det_stat_tog; 180 u32 usb2_vbus_det_stat_tog;
181 u32 usb2_chrg_det_stat; 181 u32 usb2_chrg_det_stat;
182 u32 usb2_chrg_det_stat_set; 182 u32 usb2_chrg_det_stat_set;
183 u32 usb2_chrg_det_stat_clr; 183 u32 usb2_chrg_det_stat_clr;
184 u32 usb2_chrg_det_stat_tog; 184 u32 usb2_chrg_det_stat_tog;
185 u32 usb2_loopback; 185 u32 usb2_loopback;
186 u32 usb2_loopback_set; 186 u32 usb2_loopback_set;
187 u32 usb2_loopback_clr; 187 u32 usb2_loopback_clr;
188 u32 usb2_loopback_tog; 188 u32 usb2_loopback_tog;
189 u32 usb2_misc; 189 u32 usb2_misc;
190 u32 usb2_misc_set; 190 u32 usb2_misc_set;
191 u32 usb2_misc_clr; 191 u32 usb2_misc_clr;
192 u32 usb2_misc_tog; 192 u32 usb2_misc_tog;
193 u32 digprog; 193 u32 digprog;
194 u32 reserved1[7]; 194 u32 reserved1[7];
195 /* For i.MX 6SoloLite */ 195 /* For i.MX 6SoloLite */
196 u32 digprog_sololite; 196 u32 digprog_sololite;
197 }; 197 };
198 #endif 198 #endif
199 199
200 /* Define the bits in register CCR */ 200 /* Define the bits in register CCR */
201 #define MXC_CCM_CCR_RBC_EN (1 << 27) 201 #define MXC_CCM_CCR_RBC_EN (1 << 27)
202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
204 /* CCR_WB does not exist on i.MX6SX/UL */ 204 /* CCR_WB does not exist on i.MX6SX/UL */
205 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 205 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
206 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 206 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
207 #define MXC_CCM_CCR_COSC_EN (1 << 12) 207 #define MXC_CCM_CCR_COSC_EN (1 << 12)
208 #ifdef CONFIG_MX6SX 208 #ifdef CONFIG_MX6SX
209 #define MXC_CCM_CCR_OSCNT_MASK 0x7F 209 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
210 #else 210 #else
211 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 211 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
212 #endif 212 #endif
213 #define MXC_CCM_CCR_OSCNT_OFFSET 0 213 #define MXC_CCM_CCR_OSCNT_OFFSET 0
214 214
215 /* Define the bits in register CCDR */ 215 /* Define the bits in register CCDR */
216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
218 /* Exists on i.MX6QP */ 218 /* Exists on i.MX6QP */
219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) 219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
220 220
221 /* Define the bits in register CSR */ 221 /* Define the bits in register CSR */
222 #define MXC_CCM_CSR_COSC_READY (1 << 5) 222 #define MXC_CCM_CSR_COSC_READY (1 << 5)
223 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 223 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
224 224
225 /* Define the bits in register CCSR */ 225 /* Define the bits in register CCSR */
226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
233 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 233 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
237 237
238 /* Define the bits in register CACRR */ 238 /* Define the bits in register CACRR */
239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
240 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 240 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
241 241
242 /* Define the bits in register CBCDR */ 242 /* Define the bits in register CBCDR */
243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) 245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
247 /* MMDC_CH0 not exists on i.MX6SX */ 247 /* MMDC_CH0 not exists on i.MX6SX */
248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
250 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 250 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
252 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 252 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
254 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 254 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
256 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 256 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
257 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 257 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
262 262
263 /* Define the bits in register CBCMR */ 263 /* Define the bits in register CBCMR */
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
268 /* LCDIF on i.MX6SX/UL */ 268 /* LCDIF on i.MX6SX/UL */
269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) 269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23
271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) 275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
278 #ifndef CONFIG_MX6SX 278 #ifndef CONFIG_MX6SX
279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
283 #endif 283 #endif
284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
286 #ifndef CONFIG_MX6SX 286 #ifndef CONFIG_MX6SX
287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
288 #endif 288 #endif
289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
294 /* Exists on i.MX6QP */ 294 /* Exists on i.MX6QP */
295 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) 295 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
296 296
297 /* Define the bits in register CSCMR1 */ 297 /* Define the bits in register CSCMR1 */
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
300 /* QSPI1 exist on i.MX6SX/UL */ 300 /* QSPI1 exist on i.MX6SX/UL */
301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
307 /* LCFIF2_PODF on i.MX6SX */ 307 /* LCFIF2_PODF on i.MX6SX */
308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) 308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */ 310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ 313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) 314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) 315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
326 /* QSPI1 exist on i.MX6SX/UL */ 326 /* QSPI1 exist on i.MX6SX/UL */
327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ 329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
332 332
333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
334 334
335 /* Define the bits in register CSCMR2 */ 335 /* Define the bits in register CSCMR2 */
336 #ifdef CONFIG_MX6SX 336 #ifdef CONFIG_MX6SX
337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
339 #endif 339 #endif
340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ 344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
347 347
348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
350 350
351 /* Define the bits in register CSCDR1 */ 351 /* Define the bits in register CSCDR1 */
352 #ifndef CONFIG_MX6SX 352 #ifndef CONFIG_MX6SX
353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
355 #endif 355 #endif
356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */ 356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) 357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) 359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
361 361
362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
370 #ifndef CONFIG_MX6SX 370 #ifndef CONFIG_MX6SX
371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
375 #endif 375 #endif
376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */ 378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
379 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 379 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
380 380
381 /* Define the bits in register CS1CDR */ 381 /* Define the bits in register CS1CDR */
382 /* MX6UL, !MX6ULL */ 382 /* MX6UL, !MX6ULL */
383 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) 383 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
384 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 384 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
385 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) 385 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
386 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 386 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
387 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) 387 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
388 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 388 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
389 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F 389 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
390 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 390 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
391 391
392 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 392 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
393 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 393 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
394 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 394 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
395 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 395 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
396 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 396 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
397 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 397 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
398 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 398 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
399 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 399 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
400 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 400 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
401 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 401 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
402 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 402 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
403 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 403 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
404 404
405 /* Define the bits in register CS2CDR */ 405 /* Define the bits in register CS2CDR */
406 /* QSPI2 on i.MX6SX */ 406 /* QSPI2 on i.MX6SX */
407 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 407 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
408 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 408 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
413 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 413 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 414 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
416 416
417 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 417 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
418 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 418 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
420 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 420 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 421 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
423 423
424 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) 424 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) 426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) 427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) 429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
430 430
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ 431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
432 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ 432 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
433 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ 433 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
434 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) 434 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
435 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ 435 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
436 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ 436 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ 437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
438 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) 438 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
439 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ 439 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
440 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ 440 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ 441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
442 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) 442 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
443 443
444 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 444 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
445 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 445 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
446 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 446 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
447 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 447 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
448 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 448 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
449 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 449 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
450 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 450 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
451 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 451 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
452 452
453 /* Define the bits in register CDCDR */ 453 /* Define the bits in register CDCDR */
454 #ifndef CONFIG_MX6SX 454 #ifndef CONFIG_MX6SX
455 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 455 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
456 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 456 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
457 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 457 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
458 #endif 458 #endif
459 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 459 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
460 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 460 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
463 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 463 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
464 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 464 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
465 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 465 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
466 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 466 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
469 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 469 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
470 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 470 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
471 471
472 /* Define the bits in register CHSCCDR */ 472 /* Define the bits in register CHSCCDR */
473 /* i.MX 6SX */ 473 /* i.MX 6SX */
474 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 474 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
475 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 475 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
476 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 476 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
477 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 477 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
478 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 478 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
479 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 479 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
480 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 480 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
481 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 481 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
482 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 482 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
483 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 483 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
484 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 484 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
485 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 485 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
486 486
487 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 487 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
488 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 488 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
491 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 491 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
492 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 492 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
493 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 493 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
494 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 494 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
497 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 497 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
498 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 498 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
499 499
500 /* i.MX6ULL */ 500 /* i.MX6ULL */
501 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) 501 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
502 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 502 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
503 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) 503 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
504 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 504 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
505 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) 505 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
506 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 506 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
507 507
508 #define CHSCCDR_CLK_SEL_LDB_DI0 3 508 #define CHSCCDR_CLK_SEL_LDB_DI0 3
509 #define CHSCCDR_PODF_DIVIDE_BY_3 2 509 #define CHSCCDR_PODF_DIVIDE_BY_3 2
510 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 510 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
511 511
512 /* Define the bits in register CSCDR2 */ 512 /* Define the bits in register CSCDR2 */
513 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 513 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
514 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 514 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
515 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ 515 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
516 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) 516 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
517 /* LCDIF1 on i.MX6SX/UL */ 517 /* LCDIF1 on i.MX6SX/UL */
518 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) 518 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
519 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 519 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15
520 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) 520 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
521 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 521 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12
522 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) 522 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
523 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 523 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9
524 /* LCDIF2 on i.MX6SX */ 524 /* LCDIF2 on i.MX6SX */
525 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) 525 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
526 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 526 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6
527 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) 527 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
528 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 528 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3
529 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) 529 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
530 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 530 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
531 531
532 /* All IPU2_DI1 are LCDIF1 on MX6SX */ 532 /* All IPU2_DI1 are LCDIF1 on MX6SX */
533 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 533 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
534 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 534 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
535 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 535 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
536 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 536 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
537 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 537 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
538 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 538 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
539 /* All IPU2_DI0 are LCDIF2 on MX6SX */ 539 /* All IPU2_DI0 are LCDIF2 on MX6SX */
540 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 540 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
541 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 541 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
542 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 542 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
543 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 543 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
544 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 544 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
545 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 545 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
546 546
547 /* Define the bits in register CSCDR3 */ 547 /* Define the bits in register CSCDR3 */
548 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 548 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
549 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 549 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
550 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 550 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
551 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 551 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
552 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 552 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
553 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 553 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
554 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 554 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
555 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 555 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
556 556
557 /* Define the bits in register CDHIPR */ 557 /* Define the bits in register CDHIPR */
558 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 558 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
559 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 559 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
560 #ifndef CONFIG_MX6SX 560 #ifndef CONFIG_MX6SX
561 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 561 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
562 #endif 562 #endif
563 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 563 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
564 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 564 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
565 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 565 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
566 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 566 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
567 567
568 /* Define the bits in register CLPCR */ 568 /* Define the bits in register CLPCR */
569 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 569 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
570 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 570 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
571 #ifndef CONFIG_MX6SX 571 #ifndef CONFIG_MX6SX
572 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 572 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
573 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 573 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
574 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 574 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
575 #endif 575 #endif
576 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 576 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
577 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 577 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
578 #ifndef CONFIG_MX6SX 578 #ifndef CONFIG_MX6SX
579 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 579 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
580 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 580 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
581 #endif 581 #endif
582 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 582 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
583 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 583 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
584 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 584 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
585 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 585 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
586 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 586 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
587 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 587 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
588 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 588 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
589 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 589 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
590 #ifndef CONFIG_MX6SX 590 #ifndef CONFIG_MX6SX
591 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 591 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
592 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 592 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
593 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 593 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
594 #endif 594 #endif
595 #define MXC_CCM_CLPCR_LPM_MASK 0x3 595 #define MXC_CCM_CLPCR_LPM_MASK 0x3
596 #define MXC_CCM_CLPCR_LPM_OFFSET 0 596 #define MXC_CCM_CLPCR_LPM_OFFSET 0
597 597
598 /* Define the bits in register CISR */ 598 /* Define the bits in register CISR */
599 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 599 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
600 #ifndef CONFIG_MX6SX 600 #ifndef CONFIG_MX6SX
601 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 601 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
602 #endif 602 #endif
603 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 603 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
604 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 604 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
605 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 605 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
606 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 606 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
607 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 607 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
608 #define MXC_CCM_CISR_COSC_READY (1 << 6) 608 #define MXC_CCM_CISR_COSC_READY (1 << 6)
609 #define MXC_CCM_CISR_LRF_PLL 1 609 #define MXC_CCM_CISR_LRF_PLL 1
610 610
611 /* Define the bits in register CIMR */ 611 /* Define the bits in register CIMR */
612 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 612 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
613 #ifndef CONFIG_MX6SX 613 #ifndef CONFIG_MX6SX
614 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 614 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
615 #endif 615 #endif
616 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 616 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
617 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 617 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
618 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 618 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
619 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 619 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
620 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 620 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
621 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 621 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
622 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 622 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
623 623
624 /* Define the bits in register CCOSR */ 624 /* Define the bits in register CCOSR */
625 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 625 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
626 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 626 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
627 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 627 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
628 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 628 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
629 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 629 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
630 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 630 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
631 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 631 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
632 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 632 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
633 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 633 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
634 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 634 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
635 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 635 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
636 636
637 /* Define the bits in registers CGPR */ 637 /* Define the bits in registers CGPR */
638 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 638 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
639 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 639 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
640 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 640 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
641 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 641 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
642 642
643 /* Define the bits in registers CCGRx */ 643 /* Define the bits in registers CCGRx */
644 #define MXC_CCM_CCGR_CG_MASK 3 644 #define MXC_CCM_CCGR_CG_MASK 3
645 645
646 /* i.MX 6ULL */ 646 /* i.MX 6ULL */
647 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 647 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
648 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) 648 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
649 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 649 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
650 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) 650 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
651 651
652 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 652 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
653 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 653 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
654 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 654 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
655 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 655 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
656 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 656 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
657 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 657 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
658 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 658 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
659 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 659 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
660 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 660 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
661 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 661 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
662 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 662 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
663 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 663 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
664 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 664 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
665 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 665 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
666 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 666 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
667 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 667 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
668 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 668 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
669 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 669 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
670 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 670 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
671 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 671 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
672 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 672 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
673 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 673 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
674 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 674 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
675 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 675 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
676 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 676 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
677 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 677 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
678 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 678 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
679 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 679 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
680 #ifdef CONFIG_MX6SX 680 #ifdef CONFIG_MX6SX
681 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 681 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
682 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 682 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
683 #else 683 #else
684 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 684 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
685 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 685 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
686 #endif 686 #endif
687 687
688 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 688 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
689 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 689 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
690 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 690 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
691 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 691 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
692 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 692 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
693 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 693 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
694 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 694 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
695 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 695 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
696 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 696 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
697 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 697 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
698 /* CCGR1_ENET does not exist on i.MX6SX/UL */ 698 /* CCGR1_ENET does not exist on i.MX6SX/UL */
699 #define MXC_CCM_CCGR1_ENET_OFFSET 10 699 #define MXC_CCM_CCGR1_ENET_OFFSET 10
700 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) 700 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
701 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 701 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
702 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 702 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
703 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 703 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
704 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 704 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
705 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 705 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
706 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 706 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
707 #ifdef CONFIG_MX6SX 707 #ifdef CONFIG_MX6SX
708 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 708 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
709 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 709 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
710 #endif 710 #endif
711 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 711 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
712 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 712 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
713 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 713 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
714 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 714 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
715 #ifndef CONFIG_MX6SX 715 #ifndef CONFIG_MX6SX
716 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 716 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
717 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 717 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
718 #endif 718 #endif
719 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 719 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
720 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 720 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
721 #ifdef CONFIG_MX6SX 721 #ifdef CONFIG_MX6SX
722 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 722 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
723 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 723 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
724 #define MXC_CCM_CCGR1_CANFD_OFFSET 30 724 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
725 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 725 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
726 #endif 726 #endif
727 727
728 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 728 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
729 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 729 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
730 730
731 /* i.MX6SX/UL */ 731 /* i.MX6SX/UL */
732 #define MXC_CCM_CCGR2_CSI_OFFSET 2 732 #define MXC_CCM_CCGR2_CSI_OFFSET 2
733 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 733 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
734 734
735 #ifndef CONFIG_MX6SX 735 #ifndef CONFIG_MX6SX
736 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 736 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
737 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 737 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
738 #endif 738 #endif
739 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 739 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
740 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 740 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
741 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 741 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
742 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 742 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
743 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 743 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
744 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 744 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
745 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 745 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
746 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) 746 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
747 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 747 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
748 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 748 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
749 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 749 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
750 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 750 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
751 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 751 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
752 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 752 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
753 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 753 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
754 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 754 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
755 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 755 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
756 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 756 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
757 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 757 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
758 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 758 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
759 /* i.MX6SX/UL LCD and PXP */ 759 /* i.MX6SX/UL LCD and PXP */
760 #define MXC_CCM_CCGR2_LCD_OFFSET 28 760 #define MXC_CCM_CCGR2_LCD_OFFSET 28
761 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 761 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
762 #define MXC_CCM_CCGR2_PXP_OFFSET 30 762 #define MXC_CCM_CCGR2_PXP_OFFSET 30
763 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 763 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
764 764
765 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 765 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
766 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 766 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
767 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 767 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
768 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 768 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
769 769
770 /* i.MX6ULL */ 770 /* i.MX6ULL */
771 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 771 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
772 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) 772 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
773 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 773 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
774 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) 774 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
775 775
776 /* Exist on i.MX6SX */ 776 /* Exist on i.MX6SX */
777 #define MXC_CCM_CCGR3_M4_OFFSET 2 777 #define MXC_CCM_CCGR3_M4_OFFSET 2
778 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 778 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
779 /* i.MX6ULL */ 779 /* i.MX6ULL */
780 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 780 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
781 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) 781 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
782 #define MXC_CCM_CCGR3_ENET_OFFSET 4 782 #define MXC_CCM_CCGR3_ENET_OFFSET 4
783 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 783 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
784 #define MXC_CCM_CCGR3_QSPI_OFFSET 14 784 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
785 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 785 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
786 786
787 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 787 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
788 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 788 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
789 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 789 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
790 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 790 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
791 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 791 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
792 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 792 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
793 793
794 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 794 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
795 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 795 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
796 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 796 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
797 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 797 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
798 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 798 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
799 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 799 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
800 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 800 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
801 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 801 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
802 802
803 /* QSPI1 exists on i.MX6SX/UL */ 803 /* QSPI1 exists on i.MX6SX/UL */
804 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 804 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
805 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 805 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
806 806
807 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 807 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
808 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 808 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
809 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 809 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
810 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 810 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
811 811
812 /* A7_CLKDIV/WDOG1 on i.MX6UL */ 812 /* A7_CLKDIV/WDOG1 on i.MX6UL */
813 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 813 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
814 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) 814 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
815 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 815 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
816 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) 816 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
817 817
818 #define MXC_CCM_CCGR3_MLB_OFFSET 18 818 #define MXC_CCM_CCGR3_MLB_OFFSET 18
819 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 819 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
820 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 820 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
821 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 821 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
822 #ifndef CONFIG_MX6SX 822 #ifndef CONFIG_MX6SX
823 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 823 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
824 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 824 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
825 #endif 825 #endif
826 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 826 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
827 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 827 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
828 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 828 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
829 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 829 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
830 830
831 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 831 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6
832 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) 832 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
833 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 833 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8
834 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) 834 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
835 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 835 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10
836 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) 836 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
837 /* AXI on i.MX6UL */ 837 /* AXI on i.MX6UL */
838 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 838 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
839 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) 839 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
840 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 840 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
841 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 841 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
842 842
843 /* GPIO4 on i.MX6UL/ULL */ 843 /* GPIO4 on i.MX6UL/ULL */
844 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 844 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
845 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) 845 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
846 846
847 #ifndef CONFIG_MX6SX 847 #ifndef CONFIG_MX6SX
848 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 848 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
849 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 849 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
850 #endif 850 #endif
851 851
852 /* i.MX6ULL */ 852 /* i.MX6ULL */
853 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 853 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
854 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) 854 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
855 855
856 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 856 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
857 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 857 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
858 /* QSPI2 on i.MX6SX */ 858 /* QSPI2 on i.MX6SX */
859 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 859 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
860 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 860 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
861 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 861 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
862 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 862 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
863 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 863 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
864 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 864 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
865 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 865 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
866 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 866 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
867 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 867 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
868 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 868 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
869 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 869 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
870 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 870 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
871 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 871 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
872 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 872 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
873 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 873 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
874 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 874 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
875 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 875 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
876 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 876 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
877 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 877 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
878 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 878 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
879 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 879 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
880 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 880 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
881 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 881 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
882 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 882 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
883 883
884 #define MXC_CCM_CCGR5_ROM_OFFSET 0 884 #define MXC_CCM_CCGR5_ROM_OFFSET 0
885 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 885 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
886 #ifndef CONFIG_MX6SX 886 #ifndef CONFIG_MX6SX
887 #define MXC_CCM_CCGR5_SATA_OFFSET 4 887 #define MXC_CCM_CCGR5_SATA_OFFSET 4
888 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 888 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
889 #endif 889 #endif
890 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 890 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
891 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 891 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
892 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 892 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
893 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 893 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
894 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 894 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
895 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 895 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
896 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 896 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
897 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 897 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
898 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 898 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
899 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 899 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
900 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 900 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
901 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 901 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
902 #define MXC_CCM_CCGR5_UART_OFFSET 24 902 #define MXC_CCM_CCGR5_UART_OFFSET 24
903 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 903 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
904 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 904 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
905 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 905 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
906 #ifdef CONFIG_MX6SX 906 #ifdef CONFIG_MX6SX
907 #define MXC_CCM_CCGR5_SAI1_OFFSET 20 907 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
908 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 908 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
909 #define MXC_CCM_CCGR5_SAI2_OFFSET 30 909 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
910 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 910 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
911 #endif 911 #endif
912 912
913 /* PRG_CLK0 exists on i.MX6QP */ 913 /* PRG_CLK0 exists on i.MX6QP */
914 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) 914 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
915 915
916 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 916 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
917 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 917 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
918 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 918 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
919 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 919 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
920 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 920 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
921 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 921 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
922 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 922 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
923 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) 923 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
924 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 924 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
925 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) 925 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
926 /* i.MX6ULL */ 926 /* i.MX6ULL */
927 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 927 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
928 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) 928 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
929 /* GPMI/BCH on i.MX6UL */ 929 /* GPMI/BCH on i.MX6UL */
930 #define MXC_CCM_CCGR6_BCH_OFFSET 6 930 #define MXC_CCM_CCGR6_BCH_OFFSET 6
931 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) 931 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
932 #define MXC_CCM_CCGR6_GPMI_OFFSET 8 932 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
933 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) 933 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
934 934
935 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 935 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
936 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 936 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
937 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 937 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
938 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 938 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
939 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 939 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
940 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 940 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
941 /* i.MX6ULL */ 941 /* i.MX6ULL */
942 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 942 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
943 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) 943 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
944 /* The following *CCGR6* exist only i.MX6SX */ 944 /* The following *CCGR6* exist only i.MX6SX */
945 #define MXC_CCM_CCGR6_PWM8_OFFSET 16 945 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
946 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 946 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
947 #define MXC_CCM_CCGR6_VADC_OFFSET 20 947 #define MXC_CCM_CCGR6_VADC_OFFSET 20
948 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 948 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
949 #define MXC_CCM_CCGR6_GIS_OFFSET 22 949 #define MXC_CCM_CCGR6_GIS_OFFSET 22
950 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 950 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
951 #define MXC_CCM_CCGR6_I2C4_OFFSET 24 951 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
952 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 952 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
953 #define MXC_CCM_CCGR6_PWM5_OFFSET 26 953 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
954 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 954 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
955 #define MXC_CCM_CCGR6_PWM6_OFFSET 28 955 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
956 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 956 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
957 #define MXC_CCM_CCGR6_PWM7_OFFSET 30 957 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
958 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 958 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
959 /* The two does not exist on i.MX6SX */ 959 /* The two does not exist on i.MX6SX */
960 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 960 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
961 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 961 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
962 962
963 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 963 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
964 #define BP_ANADIG_PLL_SYS_RSVD0 20 964 #define BP_ANADIG_PLL_SYS_RSVD0 20
965 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 965 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
966 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 966 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
967 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 967 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
968 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 968 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
969 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 969 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
970 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 970 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
971 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 971 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
972 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 972 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
973 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 973 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
974 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 974 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
975 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 975 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
976 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 976 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
977 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 977 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
978 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 978 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
979 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 979 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
980 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 980 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
981 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 981 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
982 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 982 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
983 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 983 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
984 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 984 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
985 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 985 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
986 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 986 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
987 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 987 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
988 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 988 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
989 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 989 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
990 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 990 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
991 991
992 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 992 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
993 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 993 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
994 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 994 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
995 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 995 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
996 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 996 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
997 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 997 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
998 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 998 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
999 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 999 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
1000 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 1000 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1001 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 1001 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1002 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 1002 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1003 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 1003 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1004 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 1004 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1005 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 1005 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1006 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 1006 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1007 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 1007 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1008 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 1008 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1009 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 1009 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1010 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 1010 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1011 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 1011 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1012 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 1012 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1013 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 1013 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1014 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 1014 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1015 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 1015 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
1016 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 1016 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1017 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 1017 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
1018 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 1018 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1019 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 1019 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1020 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 1020 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1021 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 1021 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
1022 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 1022 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1023 1023
1024 #define BM_ANADIG_PLL_528_LOCK 0x80000000 1024 #define BM_ANADIG_PLL_528_LOCK 0x80000000
1025 #define BP_ANADIG_PLL_528_RSVD1 19 1025 #define BP_ANADIG_PLL_528_RSVD1 19
1026 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 1026 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1027 #define BF_ANADIG_PLL_528_RSVD1(v) \ 1027 #define BF_ANADIG_PLL_528_RSVD1(v) \
1028 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 1028 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1029 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 1029 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1030 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 1030 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1031 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 1031 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
1032 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 1032 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1033 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 1033 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1034 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 1034 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1035 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 1035 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1036 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 1036 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1037 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 1037 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1038 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 1038 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1039 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 1039 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1040 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 1040 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
1041 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 1041 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1042 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 1042 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1043 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 1043 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1044 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 1044 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1045 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 1045 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1046 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 1046 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1047 #define BP_ANADIG_PLL_528_RSVD0 1 1047 #define BP_ANADIG_PLL_528_RSVD0 1
1048 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 1048 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1049 #define BF_ANADIG_PLL_528_RSVD0(v) \ 1049 #define BF_ANADIG_PLL_528_RSVD0(v) \
1050 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 1050 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1051 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 1051 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1052 1052
1053 #define BP_ANADIG_PLL_528_SS_STOP 16 1053 #define BP_ANADIG_PLL_528_SS_STOP 16
1054 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 1054 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1055 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 1055 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1056 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 1056 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1057 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 1057 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1058 #define BP_ANADIG_PLL_528_SS_STEP 0 1058 #define BP_ANADIG_PLL_528_SS_STEP 0
1059 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 1059 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1060 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 1060 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1061 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 1061 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1062 1062
1063 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 1063 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
1064 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 1064 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1065 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 1065 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1066 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 1066 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1067 #define BP_ANADIG_PLL_528_NUM_A 0 1067 #define BP_ANADIG_PLL_528_NUM_A 0
1068 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 1068 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1069 #define BF_ANADIG_PLL_528_NUM_A(v) \ 1069 #define BF_ANADIG_PLL_528_NUM_A(v) \
1070 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 1070 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1071 1071
1072 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 1072 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
1073 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 1073 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1074 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 1074 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1075 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 1075 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1076 #define BP_ANADIG_PLL_528_DENOM_B 0 1076 #define BP_ANADIG_PLL_528_DENOM_B 0
1077 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 1077 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1078 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 1078 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1079 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 1079 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1080 1080
1081 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 1081 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1082 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 1082 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
1083 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 1083 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1084 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 1084 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
1085 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 1085 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1086 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 1086 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1087 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 1087 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1088 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 1088 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1089 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 1089 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1090 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 1090 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1091 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 1091 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1092 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 1092 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1093 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 1093 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1094 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 1094 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1095 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 1095 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1096 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 1096 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1097 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 1097 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1098 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 1098 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1099 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 1099 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1100 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 1100 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1101 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 1101 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1102 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 1102 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1103 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 1103 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1104 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 1104 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1105 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 1105 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1106 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 1106 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1107 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 1107 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1108 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 1108 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1109 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 1109 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1110 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 1110 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1111 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 1111 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1112 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 1112 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1113 1113
1114 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 1114 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
1115 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 1115 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1116 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 1116 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1117 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 1117 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1118 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 1118 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1119 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 1119 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1120 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 1120 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1121 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 1121 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1122 1122
1123 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 1123 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
1124 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 1124 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1125 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 1125 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1126 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 1126 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1127 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 1127 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1128 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 1128 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1129 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 1129 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1130 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 1130 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1131 1131
1132 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 1132 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1133 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 1133 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
1134 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 1134 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1135 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 1135 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
1136 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 1136 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1137 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 1137 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1138 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 1138 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1139 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 1139 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1140 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 1140 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1141 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 1141 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1142 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 1142 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1143 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 1143 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1144 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 1144 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1145 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 1145 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1146 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 1146 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1147 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 1147 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1148 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 1148 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1149 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 1149 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1150 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 1150 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1151 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 1151 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1152 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 1152 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1153 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 1153 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1154 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 1154 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1155 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 1155 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1156 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 1156 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1157 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 1157 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1158 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 1158 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1159 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 1159 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1160 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 1160 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1161 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 1161 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1162 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 1162 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1163 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 1163 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1164 1164
1165 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 1165 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
1166 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 1166 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1167 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 1167 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1168 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 1168 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1169 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 1169 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1170 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 1170 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1171 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 1171 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1172 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 1172 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1173 1173
1174 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 1174 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
1175 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 1175 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1176 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 1176 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1177 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 1177 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1178 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 1178 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1179 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 1179 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1180 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 1180 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1181 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 1181 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1182 1182
1183 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 1183 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1184 #define BP_ANADIG_PLL_ENET_RSVD1 21 1184 #define BP_ANADIG_PLL_ENET_RSVD1 21
1185 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 1185 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1186 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 1186 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
1187 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 1187 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1188 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 1188 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1189 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 1189 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1190 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 1190 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1191 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 1191 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1192 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 1192 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1193 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 1193 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1194 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 1194 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1195 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 1195 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1196 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 1196 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1197 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 1197 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1198 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 1198 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1199 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 1199 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1200 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 1200 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1201 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1201 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1202 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1202 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1203 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1203 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1204 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1204 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1205 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1205 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1206 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1206 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1207 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1207 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1208 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1208 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1209 #define BP_ANADIG_PLL_ENET_RSVD0 2 1209 #define BP_ANADIG_PLL_ENET_RSVD0 2
1210 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1210 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1211 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1211 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1212 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1212 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1213 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1213 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1214 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1214 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1215 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1215 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1216 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1216 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1217 1217
1218 /* ENET2 for i.MX6SX/UL */ 1218 /* ENET2 for i.MX6SX/UL */
1219 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 1219 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1220 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C 1220 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1221 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ 1221 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
1222 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) 1222 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1223 1223
1224 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1224 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1225 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1225 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1226 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 1226 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1227 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1227 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1228 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1228 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1229 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1229 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1230 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1230 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1231 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1231 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1232 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 1232 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1233 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1233 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1234 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1234 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1235 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1235 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1236 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1236 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1237 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1237 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1238 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 1238 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1239 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1239 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1240 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1240 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1241 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1241 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1242 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1242 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1243 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1243 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1244 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 1244 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1245 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1245 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1246 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1246 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1247 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1247 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1248 1248
1249 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1249 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1250 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1250 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1251 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 1251 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1252 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1252 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1253 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1253 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1254 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1254 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1255 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1255 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1256 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1256 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1257 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 1257 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1258 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1258 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1259 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1259 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1260 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1260 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1261 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1261 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1262 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1262 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1263 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 1263 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1264 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1264 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1265 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1265 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1266 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1266 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1267 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1267 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1268 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1268 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1269 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 1269 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1270 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1270 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1271 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1271 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1272 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1272 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1273 1273
1274 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1274 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1275 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
1275 1276
1276 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) 1277 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1277 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23 1278 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
1278 1279
1279 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) 1280 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
1280 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15 1281 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15
1281 1282
1282 #define PMU_MISC2_AUDIO_DIV(v) \ 1283 #define PMU_MISC2_AUDIO_DIV(v) \
1283 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ 1284 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1284 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ 1285 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
1285 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ 1286 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
1286 BP_PMU_MISC2_AUDIO_DIV_LSB)) 1287 BP_PMU_MISC2_AUDIO_DIV_LSB))
1287 1288
1288 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1289 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
1289 1290