MLK-16069 imx6slevk: Workaround to limit the u-boot in low 512MB memory

On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing. And due to MMDC limitation, the script we get from IC team is only doing CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might cause CS0 can NOT be accessed any longer. Because of this HW issue, we found the high 512MB memory needs more time to be stable. Since the u-boot relocates itself to highest address after booting, so this will cause issue. To work around it, we just limit the u-boot running at low 512MB memory. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5fc93379dc3576ee9dc00f108bc18d8d6059d9c3)

MLK-16069 imx6slevk: Workaround to limit the u-boot in low 512MB memory
On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing. And due to MMDC limitation, the script we get from IC team is only doing CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might cause CS0 can NOT be accessed any longer. Because of this HW issue, we found the high 512MB memory needs more time to be stable. Since the u-boot relocates itself to highest address after booting, so this will cause issue. To work around it, we just limit the u-boot running at low 512MB memory. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5fc93379dc3576ee9dc00f108bc18d8d6059d9c3)
Ye Li
1 parent c7aefcba1d
Showing 1 changed file with 11 additions and 0 deletions Side-by-side Diff
board/freescale/mx6slevk/mx6slevk.c
@@ -85,6 +85,17 @@
 	return 0;
 }
  
+phys_size_t get_effective_memsize(void)
+{
+	return SZ_512M;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
...	...	@@ -85,6 +85,17 @@
85	85	return 0;
86	86	}
87	87
	88	+phys_size_t get_effective_memsize(void)
	89	+{
	90	+ return SZ_512M;
	91	+}
	92	+
	93	+void dram_init_banksize(void)
	94	+{
	95	+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	96	+ gd->bd->bi_dram[0].size = gd->ram_size;
	97	+}
	98	+
88	99	static iomux_v3_cfg_t const uart1_pads[] = {
89	100	MX6_PAD_UART1_TXD__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
90	101	MX6_PAD_UART1_RXD__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),