Commit 923a662f2fb09aa67c1ec0de25474c218fad2690

Authored by Simon Glass
Committed by Tom Rini
1 parent 7273ccec61

ppc: Move fpga_state to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 4 changed files with 19 additions and 17 deletions Side-by-side Diff

arch/powerpc/include/asm/global_data.h
... ... @@ -122,6 +122,9 @@
122 122 #if defined(CONFIG_SYS_GT_6426x)
123 123 unsigned int mirror_hack[16];
124 124 #endif
  125 +#ifdef CONFIG_SYS_FPGA_COUNT
  126 + unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
  127 +#endif
125 128 };
126 129  
127 130 /*
... ... @@ -169,9 +172,6 @@
169 172 #endif
170 173 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
171 174 unsigned long kbd_status;
172   -#endif
173   -#ifdef CONFIG_SYS_FPGA_COUNT
174   - unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
175 175 #endif
176 176 #if defined(CONFIG_WD_MAX_RATE)
177 177 unsigned long long wdt_last; /* trace watch-dog triggering rate */
board/gdsys/405ep/405ep.c
... ... @@ -38,14 +38,14 @@
38 38  
39 39 int get_fpga_state(unsigned dev)
40 40 {
41   - return gd->fpga_state[dev];
  41 + return gd->arch.fpga_state[dev];
42 42 }
43 43  
44 44 void print_fpga_state(unsigned dev)
45 45 {
46   - if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  46 + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
47 47 puts(" Waiting for FPGA-DONE timed out.\n");
48   - if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  48 + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
49 49 puts(" FPGA reflection test failed.\n");
50 50 }
51 51  
... ... @@ -54,7 +54,7 @@
54 54 unsigned k;
55 55  
56 56 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
57   - gd->fpga_state[k] = 0;
  57 + gd->arch.fpga_state[k] = 0;
58 58  
59 59 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
60 60 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
... ... @@ -78,7 +78,7 @@
78 78 unsigned ctr;
79 79  
80 80 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
81   - gd->fpga_state[k] = 0;
  81 + gd->arch.fpga_state[k] = 0;
82 82  
83 83 /*
84 84 * reset FPGA
... ... @@ -94,7 +94,8 @@
94 94 while (!gd405ep_get_fpga_done(k)) {
95 95 udelay(100000);
96 96 if (ctr++ > 5) {
97   - gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  97 + gd->arch.fpga_state[k] |=
  98 + FPGA_STATE_DONE_FAILED;
98 99 break;
99 100 }
100 101 }
... ... @@ -126,7 +127,7 @@
126 127  
127 128 udelay(100000);
128 129 if (ctr++ > 5) {
129   - gd->fpga_state[k] |=
  130 + gd->arch.fpga_state[k] |=
130 131 FPGA_STATE_REFLECTION_FAILED;
131 132 break;
132 133 }
board/gdsys/405ex/405ex.c
... ... @@ -15,14 +15,14 @@
15 15  
16 16 int get_fpga_state(unsigned dev)
17 17 {
18   - return gd->fpga_state[dev];
  18 + return gd->arch.fpga_state[dev];
19 19 }
20 20  
21 21 void print_fpga_state(unsigned dev)
22 22 {
23   - if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  23 + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
24 24 puts(" Waiting for FPGA-DONE timed out.\n");
25   - if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  25 + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
26 26 puts(" FPGA reflection test failed.\n");
27 27 }
28 28  
... ... @@ -192,7 +192,7 @@
192 192 unsigned ctr;
193 193  
194 194 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
195   - gd->fpga_state[k] = 0;
  195 + gd->arch.fpga_state[k] = 0;
196 196  
197 197 /*
198 198 * reset FPGA
... ... @@ -208,7 +208,8 @@
208 208 while (!gd405ex_get_fpga_done(k)) {
209 209 udelay(100000);
210 210 if (ctr++ > 5) {
211   - gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  211 + gd->arch.fpga_state[k] |=
  212 + FPGA_STATE_DONE_FAILED;
212 213 break;
213 214 }
214 215 }
... ... @@ -240,7 +241,7 @@
240 241  
241 242 udelay(100000);
242 243 if (ctr++ > 5) {
243   - gd->fpga_state[k] |=
  244 + gd->arch.fpga_state[k] |=
244 245 FPGA_STATE_REFLECTION_FAILED;
245 246 break;
246 247 }
board/gdsys/405ex/io64.c
... ... @@ -359,7 +359,7 @@
359 359  
360 360 if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
361 361 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
362   - gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
  362 + gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
363 363 } else {
364 364 pca9698_direction_output(0x22, 39, 1);
365 365 }