ram: stm32: migrate fmc defines in driver file

Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>

ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard · Tom Rini
1 parent 81d0128d2b
Showing 3 changed files with 58 additions and 76 deletions Side-by-side Diff
arch/arm/include/asm/arch-stm32f7/fmc.h
board/st/stm32f746-disco/stm32f746-disco.c
drivers/ram/stm32_sdram.c
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
-	u32 sdcr1;	/* Control register 1 */
-	u32 sdcr2;	/* Control register 2 */
-	u32 sdtr1;	/* Timing register 1 */
-	u32 sdtr2;	/* Timing register 2 */
-	u32 sdcmr;	/* Mode register */
-	u32 sdrtr;	/* Refresh timing register */
-	u32 sdsr;	/* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC		((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT	13	/* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT	12	/* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT	10	/* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT	9	/* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT	7	/* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT	6	/* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT	4	/* Memory width shift */
-#define FMC_SDCR_NR_SHIFT	2	/* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT	0	/* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT	0	/* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT	4	/* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT	8	/* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT	12	/* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT	16	/* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT	20	/* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT	24	/* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT	5
-
-#define FMC_SDCMR_MODE_NORMAL		0
-#define FMC_SDCMR_MODE_START_CLOCK	1
-#define FMC_SDCMR_MODE_PRECHARGE	2
-#define FMC_SDCMR_MODE_AUTOREFRESH	3
-#define FMC_SDCMR_MODE_WRITE_MODE	4
-#define FMC_SDCMR_MODE_SELFREFRESH	5
-#define FMC_SDCMR_MODE_POWERDOWN	6
-
-#define FMC_SDCMR_BANK_1		BIT(4)
-#define FMC_SDCMR_BANK_2		BIT(3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT	9
-
-#define FMC_SDSR_BUSY			BIT(5)
-
-#define FMC_BUSY_WAIT()		do { \
-		__asm__ __volatile__ ("dsb" : : : "memory"); \
-		while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
-			; \
-	} while (0)
-
-
-#endif /* _MACH_FMC_H_ */
@@ -13,7 +13,6 @@
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
 #include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_defs.h>
 #include <asm/arch/syscfg.h>
@@ -10,10 +10,67 @@
 #include <dm.h>
 #include <ram.h>
 #include <asm/io.h>
-#include <asm/arch/fmc.h>
 #include <asm/arch/stm32.h>
  
 DECLARE_GLOBAL_DATA_PTR;
+
+struct stm32_fmc_regs {
+	u32 sdcr1;	/* Control register 1 */
+	u32 sdcr2;	/* Control register 2 */
+	u32 sdtr1;	/* Timing register 1 */
+	u32 sdtr2;	/* Timing register 2 */
+	u32 sdcmr;	/* Mode register */
+	u32 sdrtr;	/* Refresh timing register */
+	u32 sdsr;	/* Status register */
+};
+
+/*
+ * FMC registers base
+ */
+#define STM32_SDRAM_FMC		((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT	13	/* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT	12	/* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT	10	/* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT	9	/* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT	7	/* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT	6	/* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT	4	/* Memory width shift */
+#define FMC_SDCR_NR_SHIFT	2	/* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT	0	/* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT	0	/* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT	4	/* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT	8	/* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT	12	/* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT	16	/* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT	20	/* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT	24	/* Row-to-column delay */
+
+#define FMC_SDCMR_NRFS_SHIFT	5
+
+#define FMC_SDCMR_MODE_NORMAL		0
+#define FMC_SDCMR_MODE_START_CLOCK	1
+#define FMC_SDCMR_MODE_PRECHARGE	2
+#define FMC_SDCMR_MODE_AUTOREFRESH	3
+#define FMC_SDCMR_MODE_WRITE_MODE	4
+#define FMC_SDCMR_MODE_SELFREFRESH	5
+#define FMC_SDCMR_MODE_POWERDOWN	6
+
+#define FMC_SDCMR_BANK_1		BIT(4)
+#define FMC_SDCMR_BANK_2		BIT(3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT	9
+
+#define FMC_SDSR_BUSY			BIT(5)
+
+#define FMC_BUSY_WAIT()		do { \
+		__asm__ __volatile__ ("dsb" : : : "memory"); \
+		while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
+			; \
+	} while (0)
  
 struct stm32_sdram_control {
 	u8 no_columns;
1		-/*
2		- * (C) Copyright 2013
3		- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
4		- *
5		- * (C) Copyright 2015
6		- * Kamil Lulko, <kamil.lulko@gmail.com>
7		- *
8		- * SPDX-License-Identifier: GPL-2.0+
9		- */
10		-
11		-#ifndef _MACH_FMC_H_
12		-#define _MACH_FMC_H_
13		-
14		-struct stm32_fmc_regs {
15		- u32 sdcr1; /* Control register 1 */
16		- u32 sdcr2; /* Control register 2 */
17		- u32 sdtr1; /* Timing register 1 */
18		- u32 sdtr2; /* Timing register 2 */
19		- u32 sdcmr; /* Mode register */
20		- u32 sdrtr; /* Refresh timing register */
21		- u32 sdsr; /* Status register */
22		-};
23		-
24		-/*
25		- * FMC registers base
26		- */
27		-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
28		-
29		-/* Control register SDCR */
30		-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
31		-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
32		-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
33		-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
34		-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
35		-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
36		-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
37		-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
38		-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
39		-
40		-/* Timings register SDTR */
41		-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
42		-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
43		-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
44		-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
45		-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
46		-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
47		-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
48		-
49		-
50		-#define FMC_SDCMR_NRFS_SHIFT 5
51		-
52		-#define FMC_SDCMR_MODE_NORMAL 0
53		-#define FMC_SDCMR_MODE_START_CLOCK 1
54		-#define FMC_SDCMR_MODE_PRECHARGE 2
55		-#define FMC_SDCMR_MODE_AUTOREFRESH 3
56		-#define FMC_SDCMR_MODE_WRITE_MODE 4
57		-#define FMC_SDCMR_MODE_SELFREFRESH 5
58		-#define FMC_SDCMR_MODE_POWERDOWN 6
59		-
60		-#define FMC_SDCMR_BANK_1 BIT(4)
61		-#define FMC_SDCMR_BANK_2 BIT(3)
62		-
63		-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
64		-
65		-#define FMC_SDSR_BUSY BIT(5)
66		-
67		-#define FMC_BUSY_WAIT() do { \
68		- __asm__ __volatile__ ("dsb" : : : "memory"); \
69		- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
70		- ; \
71		- } while (0)
72		-
73		-
74		-#endif /* _MACH_FMC_H_ */
...	...	@@ -13,7 +13,6 @@
13	13	#include <asm/armv7m.h>
14	14	#include <asm/arch/stm32.h>
15	15	#include <asm/arch/gpio.h>
16		-#include <asm/arch/fmc.h>
17	16	#include <asm/arch/stm32_periph.h>
18	17	#include <asm/arch/stm32_defs.h>
19	18	#include <asm/arch/syscfg.h>
...	...	@@ -10,10 +10,67 @@
10	10	#include <dm.h>
11	11	#include <ram.h>
12	12	#include <asm/io.h>
13		-#include <asm/arch/fmc.h>
14	13	#include <asm/arch/stm32.h>
15	14
16	15	DECLARE_GLOBAL_DATA_PTR;
	16	+
	17	+struct stm32_fmc_regs {
	18	+ u32 sdcr1; /* Control register 1 */
	19	+ u32 sdcr2; /* Control register 2 */
	20	+ u32 sdtr1; /* Timing register 1 */
	21	+ u32 sdtr2; /* Timing register 2 */
	22	+ u32 sdcmr; /* Mode register */
	23	+ u32 sdrtr; /* Refresh timing register */
	24	+ u32 sdsr; /* Status register */
	25	+};
	26	+
	27	+/*
	28	+ * FMC registers base
	29	+ */
	30	+#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
	31	+
	32	+/* Control register SDCR */
	33	+#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
	34	+#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
	35	+#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
	36	+#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
	37	+#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
	38	+#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
	39	+#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
	40	+#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
	41	+#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
	42	+
	43	+/* Timings register SDTR */
	44	+#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
	45	+#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
	46	+#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
	47	+#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
	48	+#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
	49	+#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
	50	+#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
	51	+
	52	+#define FMC_SDCMR_NRFS_SHIFT 5
	53	+
	54	+#define FMC_SDCMR_MODE_NORMAL 0
	55	+#define FMC_SDCMR_MODE_START_CLOCK 1
	56	+#define FMC_SDCMR_MODE_PRECHARGE 2
	57	+#define FMC_SDCMR_MODE_AUTOREFRESH 3
	58	+#define FMC_SDCMR_MODE_WRITE_MODE 4
	59	+#define FMC_SDCMR_MODE_SELFREFRESH 5
	60	+#define FMC_SDCMR_MODE_POWERDOWN 6
	61	+
	62	+#define FMC_SDCMR_BANK_1 BIT(4)
	63	+#define FMC_SDCMR_BANK_2 BIT(3)
	64	+
	65	+#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
	66	+
	67	+#define FMC_SDSR_BUSY BIT(5)
	68	+
	69	+#define FMC_BUSY_WAIT() do { \
	70	+ __asm__ __volatile__ ("dsb" : : : "memory"); \
	71	+ while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
	72	+ ; \
	73	+ } while (0)
17	74
18	75	struct stm32_sdram_control {
19	76	u8 no_columns;