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Commit 92a3188d7d836779915e3a6f9251fa07b9c753e4

Authored by Heiko Schocher
Committed by Tom Rini
1 parent 9d2f6a9ae7
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

bitops: introduce BIT() definition 

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

Showing 16 changed files with 2 additions and 27 deletions Side-by-side Diff

arch/arm/include/asm/arch-am33xx/cpu.h
Diff comments   View file @ 92a3188
... ... @@ -17,7 +17,6 @@
17 17  
18 18 #include <asm/arch/hardware.h>
19 19  
20   -#define BIT(x) (1 << x)
21 20 #define CL_BIT(x) (0 << x)
22 21  
23 22 /* Timer register bits */
arch/arm/include/asm/arch-hi6220/gpio.h
Diff comments   View file @ 92a3188
... ... @@ -11,8 +11,6 @@
11 11 #define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
12 12 0xf7020000 - 0x4000) + (0x1000 * bank))
13 13  
14   -#define BIT(x) (1 << (x))
15   -
16 14 #define HI6220_GPIO_PER_BANK 8
17 15 #define HI6220_GPIO_DIR 0x400
18 16  
arch/arm/include/asm/arch-omap5/cpu.h
Diff comments   View file @ 92a3188
... ... @@ -56,8 +56,6 @@
56 56 #endif /* __ASSEMBLY__ */
57 57 #endif /* __KERNEL_STRICT_NAMES */
58 58  
59   -#define BIT(x) (1 << (x))
60   -
61 59 #define WD_UNLOCK1 0xAAAA
62 60 #define WD_UNLOCK2 0x5555
63 61  
arch/arm/include/asm/arch-tegra/dc.h
Diff comments   View file @ 92a3188
... ... @@ -364,8 +364,6 @@
364 364 struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
365 365 };
366 366  
367   -#define BIT(pos) (1U << pos)
368   -
369 367 /* DC_CMD_DISPLAY_COMMAND 0x032 */
370 368 #define CTRL_MODE_SHIFT 5
371 369 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
arch/arm/mach-davinci/cpu.c
Diff comments   View file @ 92a3188
... ... @@ -28,8 +28,6 @@
28 28 #define PLLC_PLLDIV8 0x170
29 29 #define PLLC_PLLDIV9 0x174
30 30  
31   -#define BIT(x) (1 << (x))
32   -
33 31 /* SOC-specific pll info */
34 32 #ifdef CONFIG_SOC_DM355
35 33 #define ARM_PLLDIV PLLC_PLLDIV1
arch/arm/mach-keystone/include/mach/clock_defs.h
Diff comments   View file @ 92a3188
... ... @@ -11,8 +11,6 @@
11 11  
12 12 #include <asm/arch/hardware.h>
13 13  
14   -#define BIT(x) (1 << (x))
15   -
16 14 /* PLL Control Registers */
17 15 struct pllctl_regs {
18 16 u32 ctl; /* 00 */
arch/arm/mach-keystone/include/mach/hardware.h
Diff comments   View file @ 92a3188
... ... @@ -24,8 +24,6 @@
24 24  
25 25 #endif
26 26  
27   -#define BIT(x) (1 << (x))
28   -
29 27 #define KS2_DDRPHY_PIR_OFFSET 0x04
30 28 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
31 29 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
arch/arm/mach-mvebu/include/mach/soc.h
Diff comments   View file @ 92a3188
... ... @@ -11,8 +11,6 @@
11 11 #ifndef _MVEBU_SOC_H
12 12 #define _MVEBU_SOC_H
13 13  
14   -#define BIT(x) (1 << (x))
15   -
16 14 #define SOC_MV78460_ID 0x7846
17 15 #define SOC_88F6810_ID 0x6810
18 16 #define SOC_88F6820_ID 0x6820
arch/arm/mach-zynq/include/mach/gpio.h
Diff comments   View file @ 92a3188
... ... @@ -71,7 +71,5 @@
71 71 /* GPIO upper 16 bit mask */
72 72 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
73 73  
74   -#define BIT(x) (1<<x)
75   -
76 74 #endif /* _ZYNQ_GPIO_H */
drivers/ddr/marvell/a38x/ddr3_init.h
Diff comments   View file @ 92a3188
... ... @@ -32,8 +32,6 @@
32 32 */
33 33 #define MV_DEBUG_INIT
34 34  
35   -#define BIT(x) (1 << (x))
36   -
37 35 #ifdef MV_DEBUG_INIT
38 36 #define DEBUG_INIT_S(s) puts(s)
39 37 #define DEBUG_INIT_D(d, l) printf("%x", d)
drivers/mtd/nand/jz4740_nand.c
Diff comments   View file @ 92a3188
... ... @@ -16,7 +16,6 @@
16 16 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
17 17 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
18 18  
19   -#define BIT(x) (1 << (x))
20 19 #define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
21 20 #define JZ_NAND_ECC_CTRL_RS BIT(2)
22 21 #define JZ_NAND_ECC_CTRL_RESET BIT(1)
drivers/spi/davinci_spi.c
Diff comments   View file @ 92a3188
... ... @@ -15,8 +15,6 @@
15 15 #include <asm/io.h>
16 16 #include <asm/arch/hardware.h>
17 17  
18   -#define BIT(x) (1 << (x))
19   -
20 18 /* SPIGCR0 */
21 19 #define SPIGCR0_SPIENA_MASK 0x1
22 20 #define SPIGCR0_SPIRST_MASK 0x0
drivers/spi/ep93xx_spi.c
Diff comments   View file @ 92a3188
... ... @@ -16,8 +16,6 @@
16 16  
17 17 #include <asm/arch/ep93xx.h>
18 18  
19   -
20   -#define BIT(x) (1<<(x))
21 19 #define SSPBASE SPI_BASE
22 20  
23 21 #define SSPCR0 0x0000
drivers/video/anx9804.c
Diff comments   View file @ 92a3188
... ... @@ -14,8 +14,6 @@
14 14 #include <i2c.h>
15 15 #include "anx9804.h"
16 16  
17   -#define BIT(x) (1 << (x))
18   -
19 17 /* Registers at i2c address 0x38 */
20 18  
21 19 #define ANX9804_HDCP_CONTROL_0_REG 0x01
include/fsl-mc/fsl_mc.h
Diff comments   View file @ 92a3188
... ... @@ -12,7 +12,6 @@
12 12 #define MC_CCSR_BASE_ADDR \
13 13 ((struct mc_ccsr_registers __iomem *)0x8340000)
14 14  
15   -#define BIT(x) (1 << (x))
16 15 #define GCR1_P1_STOP BIT(31)
17 16 #define GCR1_P2_STOP BIT(30)
18 17 #define GCR1_P1_DE_RST BIT(23)
include/linux/bitops.h
Diff comments   View file @ 92a3188
... ... @@ -3,6 +3,8 @@
3 3  
4 4 #include <asm/types.h>
5 5  
  6 +#define BIT(nr) (1UL << (nr))
  7 +
6 8 /*
7 9 * ffs: find first bit set. This is defined the same way as
8 10 * the libc and compiler builtin ffs routines, therefore