Eric Lee / smarc-uboot

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Commit 92e30c07e02b84a3b63205fcb29ac57defd043f6

Authored by Stefano Babic
Committed by Albert ARIBAUD
1 parent f9c6fac497
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: omap3: add support to Technexion twister board 

The twister board is a development board using
the TAM3517 SOM.

Support for NAND, 2 Ethernet (EMAC and SMC911),
USB (EHCI_OMAP).

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>

Showing 6 changed files with 621 additions and 0 deletions Side-by-side Diff

... ... @@ -572,6 +572,7 @@
572 572 mx51evk i.MX51
573 573 polaris xscale/pxa
574 574 trizepsiv xscale/pxa
  575 + twister omap3
575 576 vision2 i.MX51
576 577  
577 578 Jason Liu <r64343@freescale.com>
board/technexion/twister/Makefile
Diff comments   View file @ 92e30c0
  1 +#
  2 +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
  3 +#
  4 +# Based on ti/evm/Makefile
  5 +#
  6 +# This program is free software; you can redistribute it and/or modify
  7 +# it under the terms of the GNU General Public License as published by
  8 +# the Free Software Foundation; either version 2 of the License, or
  9 +# (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 +#
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB = $(obj)lib$(BOARD).o
  24 +
  25 +COBJS := $(BOARD).o
  26 +
  27 +SRCS := $(COBJS:.o=.c)
  28 +OBJS := $(addprefix $(obj),$(COBJS))
  29 +
  30 +$(LIB): $(obj).depend $(OBJS)
  31 + $(call cmd_link_o_target, $(OBJS))
  32 +
  33 +#########################################################################
  34 +
  35 +# defines $(obj).depend target
  36 +include $(SRCTREE)/rules.mk
  37 +
  38 +sinclude $(obj).depend
board/technexion/twister/twister.c
Diff comments   View file @ 92e30c0
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4 + *
  5 + * Copyright (C) 2009 TechNexion Ltd.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <common.h>
  27 +#include <netdev.h>
  28 +#include <asm/io.h>
  29 +#include <asm/arch/mem.h>
  30 +#include <asm/arch/mux.h>
  31 +#include <asm/arch/sys_proto.h>
  32 +#include <asm/omap_gpio.h>
  33 +#include <asm/arch/mmc_host_def.h>
  34 +#include <i2c.h>
  35 +#include <asm/gpio.h>
  36 +#include "twister.h"
  37 +
  38 +DECLARE_GLOBAL_DATA_PTR;
  39 +
  40 +/* Timing definitions for Ethernet Controller */
  41 +static const u32 gpmc_smc911[] = {
  42 + NET_GPMC_CONFIG1,
  43 + NET_GPMC_CONFIG2,
  44 + NET_GPMC_CONFIG3,
  45 + NET_GPMC_CONFIG4,
  46 + NET_GPMC_CONFIG5,
  47 + NET_GPMC_CONFIG6,
  48 +};
  49 +
  50 +static const u32 gpmc_XR16L2751[] = {
  51 + XR16L2751_GPMC_CONFIG1,
  52 + XR16L2751_GPMC_CONFIG2,
  53 + XR16L2751_GPMC_CONFIG3,
  54 + XR16L2751_GPMC_CONFIG4,
  55 + XR16L2751_GPMC_CONFIG5,
  56 + XR16L2751_GPMC_CONFIG6,
  57 +};
  58 +
  59 +int board_init(void)
  60 +{
  61 + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  62 +
  63 + /* boot param addr */
  64 + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  65 +
  66 + /* Chip select 1 and 3 are used for XR16L2751 UART controller */
  67 + enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
  68 + XR16L2751_UART1_BASE, GPMC_SIZE_16M);
  69 +
  70 + enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
  71 + XR16L2751_UART2_BASE, GPMC_SIZE_16M);
  72 +
  73 + gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
  74 + gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
  75 +
  76 + return 0;
  77 +}
  78 +
  79 +int misc_init_r(void)
  80 +{
  81 + dieid_num_r();
  82 +
  83 + return 0;
  84 +}
  85 +
  86 +/*
  87 + * Routine: set_muxconf_regs
  88 + * Description: Setting up the configuration Mux registers specific to the
  89 + * hardware. Many pins need to be moved from protect to primary
  90 + * mode.
  91 + */
  92 +void set_muxconf_regs(void)
  93 +{
  94 + MUX_TWISTER();
  95 +}
  96 +
  97 +int board_eth_init(bd_t *bis)
  98 +{
  99 + davinci_emac_initialize();
  100 +
  101 + /* init cs for extern lan */
  102 + enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
  103 + CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
  104 + if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
  105 + printf("\nError initializing SMC911x controlleri\n");
  106 +
  107 + return 0;
  108 +}
  109 +
  110 +#if defined(CONFIG_OMAP_HSMMC) && \
  111 + !defined(CONFIG_SPL_BUILD)
  112 +int board_mmc_init(bd_t *bis)
  113 +{
  114 + return omap_mmc_init(0);
  115 +}
  116 +#endif
board/technexion/twister/twister.h
Diff comments   View file @ 92e30c0
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4 + *
  5 + * Copyright (C) 2010 TechNexion Ltd.
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify
  8 + * it under the terms of the GNU General Public License as published by
  9 + * the Free Software Foundation; either version 2 of the License, or
  10 + * (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc.
  20 + */
  21 +
  22 +#ifndef _TAM3517_H_
  23 +#define _TAM3517_H_
  24 +
  25 +const omap3_sysinfo sysinfo = {
  26 + DDR_DISCRETE,
  27 + "TAM3517 TWISTER Board",
  28 + "NAND",
  29 +};
  30 +
  31 +#define XR16L2751_GPMC_CONFIG1 0x00000000
  32 +#define XR16L2751_GPMC_CONFIG2 0x001e1e01
  33 +#define XR16L2751_GPMC_CONFIG3 0x00080300
  34 +#define XR16L2751_GPMC_CONFIG4 0x1c091c09
  35 +#define XR16L2751_GPMC_CONFIG5 0x04181f1f
  36 +#define XR16L2751_GPMC_CONFIG6 0x00000FCF
  37 +
  38 +#define XR16L2751_UART1_BASE 0x21000000
  39 +#define XR16L2751_UART2_BASE 0x23000000
  40 +
  41 +
  42 +/*
  43 + * IEN - Input Enable
  44 + * IDIS - Input Disable
  45 + * PTD - Pull type Down
  46 + * PTU - Pull type Up
  47 + * DIS - Pull type selection is inactive
  48 + * EN - Pull type selection is active
  49 + * M0 - Mode 0
  50 + * The commented string gives the final mux configuration for that pin
  51 + */
  52 +#define MUX_TWISTER() \
  53 + /* SDRC */\
  54 + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
  55 + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
  56 + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
  57 + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
  58 + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
  59 + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
  60 + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
  61 + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
  62 + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
  63 + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
  64 + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
  65 + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
  66 + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
  67 + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
  68 + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
  69 + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
  70 + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
  71 + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
  72 + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
  73 + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
  74 + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
  75 + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
  76 + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
  77 + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
  78 + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
  79 + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
  80 + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
  81 + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
  82 + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
  83 + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
  84 + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
  85 + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
  86 + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
  87 + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
  88 + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
  89 + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
  90 + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
  91 + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
  92 + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
  93 + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
  94 + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
  95 + MUX_VAL(CP(SDRC_CKE0), (M0)) \
  96 + MUX_VAL(CP(SDRC_CKE1), (M0)) \
  97 + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
  98 + /*sdrc_strben_dly0*/\
  99 + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
  100 + /*sdrc_strben_dly1*/\
  101 + /* GPMC */\
  102 + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
  103 + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
  104 + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
  105 + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
  106 + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
  107 + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
  108 + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
  109 + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
  110 + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
  111 + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
  112 + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
  113 + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
  114 + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
  115 + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
  116 + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
  117 + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
  118 + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
  119 + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
  120 + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
  121 + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
  122 + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
  123 + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
  124 + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
  125 + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
  126 + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
  127 + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
  128 + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
  129 + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
  130 + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
  131 + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
  132 + MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
  133 + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
  134 + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
  135 + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
  136 + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
  137 + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
  138 + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
  139 + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
  140 + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
  141 + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
  142 + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
  143 + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
  144 + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
  145 + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
  146 + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
  147 + /* DSS */\
  148 + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
  149 + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
  150 + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
  151 + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
  152 + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
  153 + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
  154 + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
  155 + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
  156 + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
  157 + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
  158 + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
  159 + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
  160 + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
  161 + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
  162 + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
  163 + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
  164 + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
  165 + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
  166 + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
  167 + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
  168 + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
  169 + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
  170 + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
  171 + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
  172 + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
  173 + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
  174 + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
  175 + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
  176 + /* CAMERA */\
  177 + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
  178 + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
  179 + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
  180 + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
  181 + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
  182 + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
  183 + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
  184 + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
  185 + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
  186 + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
  187 + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
  188 + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
  189 + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
  190 + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
  191 + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
  192 + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
  193 + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
  194 + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
  195 + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
  196 + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
  197 + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
  198 + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
  199 + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
  200 + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
  201 + /* MMC */\
  202 + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
  203 + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
  204 + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
  205 + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
  206 + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
  207 + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
  208 + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
  209 + /* CardDetect */\
  210 + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
  211 + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
  212 + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
  213 + \
  214 + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
  215 + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
  216 + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
  217 + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
  218 + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
  219 + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
  220 + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
  221 + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
  222 + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
  223 + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
  224 + /* McBSP */\
  225 + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
  226 + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
  227 + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
  228 + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
  229 + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
  230 + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
  231 + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
  232 + \
  233 + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
  234 + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
  235 + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
  236 + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
  237 + \
  238 + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
  239 + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
  240 + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
  241 + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
  242 + \
  243 + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
  244 + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
  245 + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
  246 + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
  247 + /* UART */\
  248 + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
  249 + MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
  250 + MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
  251 + \
  252 + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
  253 + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
  254 + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
  255 + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
  256 + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
  257 + \
  258 + MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
  259 + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
  260 + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
  261 + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
  262 + /* I2C */\
  263 + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
  264 + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
  265 + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
  266 + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
  267 + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
  268 + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
  269 + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
  270 + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
  271 + /* McSPI */\
  272 + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
  273 + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
  274 + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
  275 + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
  276 + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
  277 + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
  278 + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
  279 + \
  280 + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
  281 + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
  282 + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
  283 + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
  284 + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
  285 + /* CCDC */\
  286 + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
  287 + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
  288 + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
  289 + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
  290 + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
  291 + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
  292 + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
  293 + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
  294 + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
  295 + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
  296 + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
  297 + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
  298 + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
  299 + /* RMII */\
  300 + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
  301 + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
  302 + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
  303 + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
  304 + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
  305 + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
  306 + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
  307 + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
  308 + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
  309 + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
  310 + /* HECC */\
  311 + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
  312 + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
  313 + /* HSUSB */\
  314 + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
  315 + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
  316 + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
  317 + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
  318 + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
  319 + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
  320 + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
  321 + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
  322 + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
  323 + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
  324 + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
  325 + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
  326 + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
  327 + /* HDQ */\
  328 + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
  329 + /* Control and debug */\
  330 + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
  331 + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
  332 + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
  333 + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
  334 + /* - GPIO30 */\
  335 + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
  336 + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
  337 + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
  338 + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
  339 + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
  340 + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
  341 + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
  342 + /* - VIO_1V8*/\
  343 + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
  344 + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
  345 + \
  346 + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
  347 + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
  348 + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
  349 + /* JTAG */\
  350 + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
  351 + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
  352 + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
  353 + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
  354 + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
  355 + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
  356 + /* ETK (ES2 onwards) */\
  357 + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
  358 + /* hsusb1_stp */ \
  359 + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
  360 + /* hsusb1_clk */\
  361 + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
  362 + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
  363 + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
  364 + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
  365 + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
  366 + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
  367 + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
  368 + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
  369 + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
  370 + /* hsusb1_dir */\
  371 + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
  372 + /* hsusb1_nxt */\
  373 + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
  374 + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
  375 + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
  376 + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
  377 + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
  378 + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
  379 + /* Die to Die */\
  380 + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
  381 + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
  382 + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
  383 + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
  384 + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
  385 + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
  386 + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
  387 + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
  388 + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
  389 + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
  390 + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
  391 + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
  392 + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
  393 + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
  394 + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
  395 + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
  396 + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
  397 + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
  398 + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
  399 + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
  400 + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
  401 + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
  402 + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
  403 + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
  404 + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
  405 + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
  406 + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
  407 + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
  408 + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
  409 + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
  410 +
  411 +#endif
... ... @@ -210,6 +210,7 @@
210 210 omap3_evm_quick_nand arm armv7 evm ti omap3
211 211 omap3_sdp3430 arm armv7 sdp3430 ti omap3
212 212 devkit8000 arm armv7 devkit8000 timll omap3
  213 +twister arm armv7 twister technexion omap3
213 214 omap4_panda arm armv7 panda ti omap4
214 215 omap4_sdp4430 arm armv7 sdp4430 ti omap4
215 216 omap5_evm arm armv7 omap5_evm ti omap5
include/configs/twister.h
Diff comments   View file @ 92e30c0
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4 + *
  5 + * Copyright (C) 2009 TechNexion Ltd.
  6 + *
  7 + * Configuration for the Technexion twister board.
  8 + *
  9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc.
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#include "tam3517-common.h"
  28 +
  29 +#define MACH_TYPE_TAM3517 2818
  30 +#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
  31 +
  32 +#define CONFIG_TAM3517_SW3_SETTINGS
  33 +#define CONFIG_XR16L2751
  34 +
  35 +#define CONFIG_BOOTDELAY 10
  36 +
  37 +#define CONFIG_BOOTFILE "uImage"
  38 +
  39 +#define CONFIG_HOSTNAME twister
  40 +
  41 +/*
  42 + * Miscellaneous configurable options
  43 + */
  44 +#define CONFIG_SYS_PROMPT "twister => "
  45 +
  46 +#define CONFIG_SMC911X
  47 +#define CONFIG_SMC911X_16_BIT
  48 +#define CONFIG_SMC911X_BASE 0x2C000000
  49 +#define CONFIG_SMC911X_NO_EEPROM
  50 +
  51 +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
  52 + "bootcmd=run nandboot\0"
  53 +
  54 +#endif /* __CONFIG_H */