Eric Lee / smarc-uboot

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Commit 92ffd0d9ed9a8389a7fb28addcd46547d6fb8539

Authored by Krunal Bhargav
Committed by Tom Rini
1 parent 2b2e1573cf
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

cmd: ti: ddr3: Move the print statement after test 

If the ECC is enabled over the entire memory region, we need to ensure
the printf/put calls do not modify the stack after ECC is disabled.
Moved the printf/put statements after ECC is enabled.

Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 1 changed file with 5 additions and 4 deletions Side-by-side Diff

... ... @@ -202,10 +202,6 @@
202 202 writel(val2, addr);
203 203  
204 204 val3 = readl(addr);
205   - printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
206   - addr, val1, val2, ecc_err, val3);
207   -
208   - puts("\tECC test: Enabling DDR ECC ...\n");
209 205 #ifdef CONFIG_ARCH_KEYSTONE
210 206 ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
211 207 writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
... ... @@ -213,6 +209,11 @@
213 209 #else
214 210 writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
215 211 #endif
  212 +
  213 + printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
  214 + addr, val1, val2, ecc_err, val3);
  215 +
  216 + puts("\tECC test: Enabled DDR ECC ...\n");
216 217  
217 218 val1 = readl(addr);
218 219 printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);