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Commit 931747e517b19387716cd56057e4afa9e2cdfff4

Authored by Stefan Agner
Committed by Stefano Babic
1 parent 984df7add1
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

mtd: nand: mxs_nand: move register structs to driver data 

Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Showing 1 changed file with 17 additions and 17 deletions Inline Diff

drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 931747e
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Freescale i.MX28 NAND flash driver 3 * Freescale i.MX28 NAND flash driver
4 * 4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH 6 * on behalf of DENX Software Engineering GmbH
7 * 7 *
8 * Based on code from LTIB: 8 * Based on code from LTIB:
9 * Freescale GPMI NFC NAND Flash Driver 9 * Freescale GPMI NFC NAND Flash Driver
10 * 10 *
11 * Copyright (C) 2010 Freescale Semiconductor, Inc. 11 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 * Copyright (C) 2008 Embedded Alley Solutions, Inc. 12 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 */ 13 */
14 14
15 #include <common.h> 15 #include <common.h>
16 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h> 17 #include <linux/mtd/rawnand.h>
18 #include <linux/sizes.h> 18 #include <linux/sizes.h>
19 #include <linux/types.h> 19 #include <linux/types.h>
20 #include <malloc.h> 20 #include <malloc.h>
21 #include <nand.h> 21 #include <nand.h>
22 #include <linux/errno.h> 22 #include <linux/errno.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/arch/clock.h> 24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h> 25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/regs-bch.h> 26 #include <asm/mach-imx/regs-bch.h>
27 #include <asm/mach-imx/regs-gpmi.h> 27 #include <asm/mach-imx/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h> 28 #include <asm/arch/sys_proto.h>
29 #include <asm/mach-imx/dma.h> 29 #include <asm/mach-imx/dma.h>
30 #include "mxs_nand.h" 30 #include "mxs_nand.h"
31 31
32 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 32 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 33
34 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) 34 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #else 36 #else
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #endif 38 #endif
39 #define MXS_NAND_METADATA_SIZE 10 39 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_BITS_PER_ECC_LEVEL 13 40 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
41 41
42 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32 42 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
43 #define MXS_NAND_COMMAND_BUFFER_SIZE 32 43 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
44 #else 44 #else
45 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE 45 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
46 #endif 46 #endif
47 47
48 #define MXS_NAND_BCH_TIMEOUT 10000 48 #define MXS_NAND_BCH_TIMEOUT 10000
49 49
50 /** 50 /**
51 * @gf_len: The length of Galois Field. (e.g., 13 or 14) 51 * @gf_len: The length of Galois Field. (e.g., 13 or 14)
52 * @ecc_strength: A number that describes the strength of the ECC 52 * @ecc_strength: A number that describes the strength of the ECC
53 * algorithm. 53 * algorithm.
54 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note 54 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
55 * the first chunk in the page includes both data and 55 * the first chunk in the page includes both data and
56 * metadata, so it's a bit larger than this value. 56 * metadata, so it's a bit larger than this value.
57 * @ecc_chunk_count: The number of ECC chunks in the page, 57 * @ecc_chunk_count: The number of ECC chunks in the page,
58 * @block_mark_byte_offset: The byte offset in the ECC-based page view at 58 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
59 * which the underlying physical block mark appears. 59 * which the underlying physical block mark appears.
60 * @block_mark_bit_offset: The bit offset into the ECC-based page view at 60 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
61 * which the underlying physical block mark appears. 61 * which the underlying physical block mark appears.
62 */ 62 */
63 struct bch_geometry { 63 struct bch_geometry {
64 unsigned int gf_len; 64 unsigned int gf_len;
65 unsigned int ecc_strength; 65 unsigned int ecc_strength;
66 unsigned int ecc_chunk_size; 66 unsigned int ecc_chunk_size;
67 unsigned int ecc_chunk_count; 67 unsigned int ecc_chunk_count;
68 unsigned int block_mark_byte_offset; 68 unsigned int block_mark_byte_offset;
69 unsigned int block_mark_bit_offset; 69 unsigned int block_mark_bit_offset;
70 }; 70 };
71 71
72 struct mxs_nand_info { 72 struct mxs_nand_info {
73 struct nand_chip chip; 73 struct nand_chip chip;
74 int cur_chip; 74 int cur_chip;
75 75
76 uint32_t cmd_queue_len; 76 uint32_t cmd_queue_len;
77 uint32_t data_buf_size; 77 uint32_t data_buf_size;
78 struct bch_geometry bch_geometry; 78 struct bch_geometry bch_geometry;
79 79
80 uint8_t *cmd_buf; 80 uint8_t *cmd_buf;
81 uint8_t *data_buf; 81 uint8_t *data_buf;
82 uint8_t *oob_buf; 82 uint8_t *oob_buf;
83 83
84 uint8_t marking_block_bad; 84 uint8_t marking_block_bad;
85 uint8_t raw_oob_mode; 85 uint8_t raw_oob_mode;
86 86
87 struct mxs_gpmi_regs *gpmi_regs;
88 struct mxs_bch_regs *bch_regs;
89
87 /* Functions with altered behaviour */ 90 /* Functions with altered behaviour */
88 int (*hooked_read_oob)(struct mtd_info *mtd, 91 int (*hooked_read_oob)(struct mtd_info *mtd,
89 loff_t from, struct mtd_oob_ops *ops); 92 loff_t from, struct mtd_oob_ops *ops);
90 int (*hooked_write_oob)(struct mtd_info *mtd, 93 int (*hooked_write_oob)(struct mtd_info *mtd,
91 loff_t to, struct mtd_oob_ops *ops); 94 loff_t to, struct mtd_oob_ops *ops);
92 int (*hooked_block_markbad)(struct mtd_info *mtd, 95 int (*hooked_block_markbad)(struct mtd_info *mtd,
93 loff_t ofs); 96 loff_t ofs);
94 97
95 /* DMA descriptors */ 98 /* DMA descriptors */
96 struct mxs_dma_desc **desc; 99 struct mxs_dma_desc **desc;
97 uint32_t desc_index; 100 uint32_t desc_index;
98 }; 101 };
99 102
100 struct nand_ecclayout fake_ecc_layout; 103 struct nand_ecclayout fake_ecc_layout;
101 104
102 /* 105 /*
103 * Cache management functions 106 * Cache management functions
104 */ 107 */
105 #ifndef CONFIG_SYS_DCACHE_OFF 108 #ifndef CONFIG_SYS_DCACHE_OFF
106 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) 109 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
107 { 110 {
108 uint32_t addr = (uint32_t)info->data_buf; 111 uint32_t addr = (uint32_t)info->data_buf;
109 112
110 flush_dcache_range(addr, addr + info->data_buf_size); 113 flush_dcache_range(addr, addr + info->data_buf_size);
111 } 114 }
112 115
113 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) 116 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
114 { 117 {
115 uint32_t addr = (uint32_t)info->data_buf; 118 uint32_t addr = (uint32_t)info->data_buf;
116 119
117 invalidate_dcache_range(addr, addr + info->data_buf_size); 120 invalidate_dcache_range(addr, addr + info->data_buf_size);
118 } 121 }
119 122
120 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) 123 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
121 { 124 {
122 uint32_t addr = (uint32_t)info->cmd_buf; 125 uint32_t addr = (uint32_t)info->cmd_buf;
123 126
124 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); 127 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
125 } 128 }
126 #else 129 #else
127 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {} 130 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
128 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {} 131 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
129 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {} 132 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
130 #endif 133 #endif
131 134
132 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info) 135 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
133 { 136 {
134 struct mxs_dma_desc *desc; 137 struct mxs_dma_desc *desc;
135 138
136 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) { 139 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
137 printf("MXS NAND: Too many DMA descriptors requested\n"); 140 printf("MXS NAND: Too many DMA descriptors requested\n");
138 return NULL; 141 return NULL;
139 } 142 }
140 143
141 desc = info->desc[info->desc_index]; 144 desc = info->desc[info->desc_index];
142 info->desc_index++; 145 info->desc_index++;
143 146
144 return desc; 147 return desc;
145 } 148 }
146 149
147 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) 150 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
148 { 151 {
149 int i; 152 int i;
150 struct mxs_dma_desc *desc; 153 struct mxs_dma_desc *desc;
151 154
152 for (i = 0; i < info->desc_index; i++) { 155 for (i = 0; i < info->desc_index; i++) {
153 desc = info->desc[i]; 156 desc = info->desc[i];
154 memset(desc, 0, sizeof(struct mxs_dma_desc)); 157 memset(desc, 0, sizeof(struct mxs_dma_desc));
155 desc->address = (dma_addr_t)desc; 158 desc->address = (dma_addr_t)desc;
156 } 159 }
157 160
158 info->desc_index = 0; 161 info->desc_index = 0;
159 } 162 }
160 163
161 static uint32_t mxs_nand_aux_status_offset(void) 164 static uint32_t mxs_nand_aux_status_offset(void)
162 { 165 {
163 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; 166 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
164 } 167 }
165 168
166 static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, 169 static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo,
167 uint32_t page_data_size) 170 uint32_t page_data_size)
168 { 171 {
169 uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8; 172 uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8;
170 uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len; 173 uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len;
171 uint32_t chunk_total_size_in_bits; 174 uint32_t chunk_total_size_in_bits;
172 uint32_t block_mark_chunk_number; 175 uint32_t block_mark_chunk_number;
173 uint32_t block_mark_chunk_bit_offset; 176 uint32_t block_mark_chunk_bit_offset;
174 uint32_t block_mark_bit_offset; 177 uint32_t block_mark_bit_offset;
175 178
176 chunk_total_size_in_bits = 179 chunk_total_size_in_bits =
177 chunk_data_size_in_bits + chunk_ecc_size_in_bits; 180 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
178 181
179 /* Compute the bit offset of the block mark within the physical page. */ 182 /* Compute the bit offset of the block mark within the physical page. */
180 block_mark_bit_offset = page_data_size * 8; 183 block_mark_bit_offset = page_data_size * 8;
181 184
182 /* Subtract the metadata bits. */ 185 /* Subtract the metadata bits. */
183 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; 186 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
184 187
185 /* 188 /*
186 * Compute the chunk number (starting at zero) in which the block mark 189 * Compute the chunk number (starting at zero) in which the block mark
187 * appears. 190 * appears.
188 */ 191 */
189 block_mark_chunk_number = 192 block_mark_chunk_number =
190 block_mark_bit_offset / chunk_total_size_in_bits; 193 block_mark_bit_offset / chunk_total_size_in_bits;
191 194
192 /* 195 /*
193 * Compute the bit offset of the block mark within its chunk, and 196 * Compute the bit offset of the block mark within its chunk, and
194 * validate it. 197 * validate it.
195 */ 198 */
196 block_mark_chunk_bit_offset = block_mark_bit_offset - 199 block_mark_chunk_bit_offset = block_mark_bit_offset -
197 (block_mark_chunk_number * chunk_total_size_in_bits); 200 (block_mark_chunk_number * chunk_total_size_in_bits);
198 201
199 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) 202 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
200 return -EINVAL; 203 return -EINVAL;
201 204
202 /* 205 /*
203 * Now that we know the chunk number in which the block mark appears, 206 * Now that we know the chunk number in which the block mark appears,
204 * we can subtract all the ECC bits that appear before it. 207 * we can subtract all the ECC bits that appear before it.
205 */ 208 */
206 block_mark_bit_offset -= 209 block_mark_bit_offset -=
207 block_mark_chunk_number * chunk_ecc_size_in_bits; 210 block_mark_chunk_number * chunk_ecc_size_in_bits;
208 211
209 geo->block_mark_byte_offset = block_mark_bit_offset >> 3; 212 geo->block_mark_byte_offset = block_mark_bit_offset >> 3;
210 geo->block_mark_bit_offset = block_mark_bit_offset & 0x7; 213 geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;
211 214
212 return 0; 215 return 0;
213 } 216 }
214 217
215 static inline unsigned int mxs_nand_max_ecc_strength_supported(void) 218 static inline unsigned int mxs_nand_max_ecc_strength_supported(void)
216 { 219 {
217 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ 220 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
218 if (is_mx6sx() || is_mx7()) 221 if (is_mx6sx() || is_mx7())
219 return 62; 222 return 62;
220 else 223 else
221 return 40; 224 return 40;
222 } 225 }
223 226
224 static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, 227 static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
225 struct mtd_info *mtd) 228 struct mtd_info *mtd)
226 { 229 {
227 struct nand_chip *chip = mtd_to_nand(mtd); 230 struct nand_chip *chip = mtd_to_nand(mtd);
228 231
229 if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) 232 if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
230 return -ENOTSUPP; 233 return -ENOTSUPP;
231 234
232 switch (chip->ecc_step_ds) { 235 switch (chip->ecc_step_ds) {
233 case SZ_512: 236 case SZ_512:
234 geo->gf_len = 13; 237 geo->gf_len = 13;
235 break; 238 break;
236 case SZ_1K: 239 case SZ_1K:
237 geo->gf_len = 14; 240 geo->gf_len = 14;
238 break; 241 break;
239 default: 242 default:
240 return -EINVAL; 243 return -EINVAL;
241 } 244 }
242 245
243 geo->ecc_chunk_size = chip->ecc_step_ds; 246 geo->ecc_chunk_size = chip->ecc_step_ds;
244 geo->ecc_strength = round_up(chip->ecc_strength_ds, 2); 247 geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
245 248
246 /* Keep the C >= O */ 249 /* Keep the C >= O */
247 if (geo->ecc_chunk_size < mtd->oobsize) 250 if (geo->ecc_chunk_size < mtd->oobsize)
248 return -EINVAL; 251 return -EINVAL;
249 252
250 if (geo->ecc_strength > mxs_nand_max_ecc_strength_supported()) 253 if (geo->ecc_strength > mxs_nand_max_ecc_strength_supported())
251 return -EINVAL; 254 return -EINVAL;
252 255
253 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; 256 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
254 257
255 return 0; 258 return 0;
256 } 259 }
257 260
258 static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, 261 static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,
259 struct mtd_info *mtd) 262 struct mtd_info *mtd)
260 { 263 {
261 /* The default for the length of Galois Field. */ 264 /* The default for the length of Galois Field. */
262 geo->gf_len = 13; 265 geo->gf_len = 13;
263 266
264 /* The default for chunk size. */ 267 /* The default for chunk size. */
265 geo->ecc_chunk_size = 512; 268 geo->ecc_chunk_size = 512;
266 269
267 if (geo->ecc_chunk_size < mtd->oobsize) { 270 if (geo->ecc_chunk_size < mtd->oobsize) {
268 geo->gf_len = 14; 271 geo->gf_len = 14;
269 geo->ecc_chunk_size *= 2; 272 geo->ecc_chunk_size *= 2;
270 } 273 }
271 274
272 if (mtd->oobsize > geo->ecc_chunk_size) { 275 if (mtd->oobsize > geo->ecc_chunk_size) {
273 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", 276 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n",
274 geo->ecc_chunk_size); 277 geo->ecc_chunk_size);
275 return -EINVAL; 278 return -EINVAL;
276 } 279 }
277 280
278 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; 281 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
279 282
280 /* 283 /*
281 * Determine the ECC layout with the formula: 284 * Determine the ECC layout with the formula:
282 * ECC bits per chunk = (total page spare data bits) / 285 * ECC bits per chunk = (total page spare data bits) /
283 * (bits per ECC level) / (chunks per page) 286 * (bits per ECC level) / (chunks per page)
284 * where: 287 * where:
285 * total page spare data bits = 288 * total page spare data bits =
286 * (page oob size - meta data size) * (bits per byte) 289 * (page oob size - meta data size) * (bits per byte)
287 */ 290 */
288 geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) 291 geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
289 / (geo->gf_len * geo->ecc_chunk_count); 292 / (geo->gf_len * geo->ecc_chunk_count);
290 293
291 geo->ecc_strength = min(round_down(geo->ecc_strength, 2), 294 geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
292 mxs_nand_max_ecc_strength_supported()); 295 mxs_nand_max_ecc_strength_supported());
293 296
294 return 0; 297 return 0;
295 } 298 }
296 299
297 /* 300 /*
298 * Wait for BCH complete IRQ and clear the IRQ 301 * Wait for BCH complete IRQ and clear the IRQ
299 */ 302 */
300 static int mxs_nand_wait_for_bch_complete(void) 303 static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
301 { 304 {
302 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
303 int timeout = MXS_NAND_BCH_TIMEOUT; 305 int timeout = MXS_NAND_BCH_TIMEOUT;
304 int ret; 306 int ret;
305 307
306 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, 308 ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
307 BCH_CTRL_COMPLETE_IRQ, timeout); 309 BCH_CTRL_COMPLETE_IRQ, timeout);
308 310
309 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); 311 writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
310 312
311 return ret; 313 return ret;
312 } 314 }
313 315
314 /* 316 /*
315 * This is the function that we install in the cmd_ctrl function pointer of the 317 * This is the function that we install in the cmd_ctrl function pointer of the
316 * owning struct nand_chip. The only functions in the reference implementation 318 * owning struct nand_chip. The only functions in the reference implementation
317 * that use these functions pointers are cmdfunc and select_chip. 319 * that use these functions pointers are cmdfunc and select_chip.
318 * 320 *
319 * In this driver, we implement our own select_chip, so this function will only 321 * In this driver, we implement our own select_chip, so this function will only
320 * be called by the reference implementation's cmdfunc. For this reason, we can 322 * be called by the reference implementation's cmdfunc. For this reason, we can
321 * ignore the chip enable bit and concentrate only on sending bytes to the NAND 323 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
322 * Flash. 324 * Flash.
323 */ 325 */
324 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) 326 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
325 { 327 {
326 struct nand_chip *nand = mtd_to_nand(mtd); 328 struct nand_chip *nand = mtd_to_nand(mtd);
327 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 329 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
328 struct mxs_dma_desc *d; 330 struct mxs_dma_desc *d;
329 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 331 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
330 int ret; 332 int ret;
331 333
332 /* 334 /*
333 * If this condition is true, something is _VERY_ wrong in MTD 335 * If this condition is true, something is _VERY_ wrong in MTD
334 * subsystem! 336 * subsystem!
335 */ 337 */
336 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) { 338 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
337 printf("MXS NAND: Command queue too long\n"); 339 printf("MXS NAND: Command queue too long\n");
338 return; 340 return;
339 } 341 }
340 342
341 /* 343 /*
342 * Every operation begins with a command byte and a series of zero or 344 * Every operation begins with a command byte and a series of zero or
343 * more address bytes. These are distinguished by either the Address 345 * more address bytes. These are distinguished by either the Address
344 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being 346 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
345 * asserted. When MTD is ready to execute the command, it will 347 * asserted. When MTD is ready to execute the command, it will
346 * deasert both latch enables. 348 * deasert both latch enables.
347 * 349 *
348 * Rather than run a separate DMA operation for every single byte, we 350 * Rather than run a separate DMA operation for every single byte, we
349 * queue them up and run a single DMA operation for the entire series 351 * queue them up and run a single DMA operation for the entire series
350 * of command and data bytes. 352 * of command and data bytes.
351 */ 353 */
352 if (ctrl & (NAND_ALE | NAND_CLE)) { 354 if (ctrl & (NAND_ALE | NAND_CLE)) {
353 if (data != NAND_CMD_NONE) 355 if (data != NAND_CMD_NONE)
354 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data; 356 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
355 return; 357 return;
356 } 358 }
357 359
358 /* 360 /*
359 * If control arrives here, MTD has deasserted both the ALE and CLE, 361 * If control arrives here, MTD has deasserted both the ALE and CLE,
360 * which means it's ready to run an operation. Check if we have any 362 * which means it's ready to run an operation. Check if we have any
361 * bytes to send. 363 * bytes to send.
362 */ 364 */
363 if (nand_info->cmd_queue_len == 0) 365 if (nand_info->cmd_queue_len == 0)
364 return; 366 return;
365 367
366 /* Compile the DMA descriptor -- a descriptor that sends command. */ 368 /* Compile the DMA descriptor -- a descriptor that sends command. */
367 d = mxs_nand_get_dma_desc(nand_info); 369 d = mxs_nand_get_dma_desc(nand_info);
368 d->cmd.data = 370 d->cmd.data =
369 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | 371 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
370 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM | 372 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
371 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 373 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
372 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET); 374 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
373 375
374 d->cmd.address = (dma_addr_t)nand_info->cmd_buf; 376 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
375 377
376 d->cmd.pio_words[0] = 378 d->cmd.pio_words[0] =
377 GPMI_CTRL0_COMMAND_MODE_WRITE | 379 GPMI_CTRL0_COMMAND_MODE_WRITE |
378 GPMI_CTRL0_WORD_LENGTH | 380 GPMI_CTRL0_WORD_LENGTH |
379 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 381 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
380 GPMI_CTRL0_ADDRESS_NAND_CLE | 382 GPMI_CTRL0_ADDRESS_NAND_CLE |
381 GPMI_CTRL0_ADDRESS_INCREMENT | 383 GPMI_CTRL0_ADDRESS_INCREMENT |
382 nand_info->cmd_queue_len; 384 nand_info->cmd_queue_len;
383 385
384 mxs_dma_desc_append(channel, d); 386 mxs_dma_desc_append(channel, d);
385 387
386 /* Flush caches */ 388 /* Flush caches */
387 mxs_nand_flush_cmd_buf(nand_info); 389 mxs_nand_flush_cmd_buf(nand_info);
388 390
389 /* Execute the DMA chain. */ 391 /* Execute the DMA chain. */
390 ret = mxs_dma_go(channel); 392 ret = mxs_dma_go(channel);
391 if (ret) 393 if (ret)
392 printf("MXS NAND: Error sending command\n"); 394 printf("MXS NAND: Error sending command\n");
393 395
394 mxs_nand_return_dma_descs(nand_info); 396 mxs_nand_return_dma_descs(nand_info);
395 397
396 /* Reset the command queue. */ 398 /* Reset the command queue. */
397 nand_info->cmd_queue_len = 0; 399 nand_info->cmd_queue_len = 0;
398 } 400 }
399 401
400 /* 402 /*
401 * Test if the NAND flash is ready. 403 * Test if the NAND flash is ready.
402 */ 404 */
403 static int mxs_nand_device_ready(struct mtd_info *mtd) 405 static int mxs_nand_device_ready(struct mtd_info *mtd)
404 { 406 {
405 struct nand_chip *chip = mtd_to_nand(mtd); 407 struct nand_chip *chip = mtd_to_nand(mtd);
406 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); 408 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
407 struct mxs_gpmi_regs *gpmi_regs =
408 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
409 uint32_t tmp; 409 uint32_t tmp;
410 410
411 tmp = readl(&gpmi_regs->hw_gpmi_stat); 411 tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
412 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip); 412 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
413 413
414 return tmp & 1; 414 return tmp & 1;
415 } 415 }
416 416
417 /* 417 /*
418 * Select the NAND chip. 418 * Select the NAND chip.
419 */ 419 */
420 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) 420 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
421 { 421 {
422 struct nand_chip *nand = mtd_to_nand(mtd); 422 struct nand_chip *nand = mtd_to_nand(mtd);
423 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 423 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
424 424
425 nand_info->cur_chip = chip; 425 nand_info->cur_chip = chip;
426 } 426 }
427 427
428 /* 428 /*
429 * Handle block mark swapping. 429 * Handle block mark swapping.
430 * 430 *
431 * Note that, when this function is called, it doesn't know whether it's 431 * Note that, when this function is called, it doesn't know whether it's
432 * swapping the block mark, or swapping it *back* -- but it doesn't matter 432 * swapping the block mark, or swapping it *back* -- but it doesn't matter
433 * because the the operation is the same. 433 * because the the operation is the same.
434 */ 434 */
435 static void mxs_nand_swap_block_mark(struct bch_geometry *geo, 435 static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
436 uint8_t *data_buf, uint8_t *oob_buf) 436 uint8_t *data_buf, uint8_t *oob_buf)
437 { 437 {
438 uint32_t bit_offset = geo->block_mark_bit_offset; 438 uint32_t bit_offset = geo->block_mark_bit_offset;
439 uint32_t buf_offset = geo->block_mark_byte_offset; 439 uint32_t buf_offset = geo->block_mark_byte_offset;
440 440
441 uint32_t src; 441 uint32_t src;
442 uint32_t dst; 442 uint32_t dst;
443 443
444 /* 444 /*
445 * Get the byte from the data area that overlays the block mark. Since 445 * Get the byte from the data area that overlays the block mark. Since
446 * the ECC engine applies its own view to the bits in the page, the 446 * the ECC engine applies its own view to the bits in the page, the
447 * physical block mark won't (in general) appear on a byte boundary in 447 * physical block mark won't (in general) appear on a byte boundary in
448 * the data. 448 * the data.
449 */ 449 */
450 src = data_buf[buf_offset] >> bit_offset; 450 src = data_buf[buf_offset] >> bit_offset;
451 src |= data_buf[buf_offset + 1] << (8 - bit_offset); 451 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
452 452
453 dst = oob_buf[0]; 453 dst = oob_buf[0];
454 454
455 oob_buf[0] = src; 455 oob_buf[0] = src;
456 456
457 data_buf[buf_offset] &= ~(0xff << bit_offset); 457 data_buf[buf_offset] &= ~(0xff << bit_offset);
458 data_buf[buf_offset + 1] &= 0xff << bit_offset; 458 data_buf[buf_offset + 1] &= 0xff << bit_offset;
459 459
460 data_buf[buf_offset] |= dst << bit_offset; 460 data_buf[buf_offset] |= dst << bit_offset;
461 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset); 461 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
462 } 462 }
463 463
464 /* 464 /*
465 * Read data from NAND. 465 * Read data from NAND.
466 */ 466 */
467 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) 467 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
468 { 468 {
469 struct nand_chip *nand = mtd_to_nand(mtd); 469 struct nand_chip *nand = mtd_to_nand(mtd);
470 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 470 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
471 struct mxs_dma_desc *d; 471 struct mxs_dma_desc *d;
472 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 472 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
473 int ret; 473 int ret;
474 474
475 if (length > NAND_MAX_PAGESIZE) { 475 if (length > NAND_MAX_PAGESIZE) {
476 printf("MXS NAND: DMA buffer too big\n"); 476 printf("MXS NAND: DMA buffer too big\n");
477 return; 477 return;
478 } 478 }
479 479
480 if (!buf) { 480 if (!buf) {
481 printf("MXS NAND: DMA buffer is NULL\n"); 481 printf("MXS NAND: DMA buffer is NULL\n");
482 return; 482 return;
483 } 483 }
484 484
485 /* Compile the DMA descriptor - a descriptor that reads data. */ 485 /* Compile the DMA descriptor - a descriptor that reads data. */
486 d = mxs_nand_get_dma_desc(nand_info); 486 d = mxs_nand_get_dma_desc(nand_info);
487 d->cmd.data = 487 d->cmd.data =
488 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ | 488 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
489 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 489 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
490 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 490 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
491 (length << MXS_DMA_DESC_BYTES_OFFSET); 491 (length << MXS_DMA_DESC_BYTES_OFFSET);
492 492
493 d->cmd.address = (dma_addr_t)nand_info->data_buf; 493 d->cmd.address = (dma_addr_t)nand_info->data_buf;
494 494
495 d->cmd.pio_words[0] = 495 d->cmd.pio_words[0] =
496 GPMI_CTRL0_COMMAND_MODE_READ | 496 GPMI_CTRL0_COMMAND_MODE_READ |
497 GPMI_CTRL0_WORD_LENGTH | 497 GPMI_CTRL0_WORD_LENGTH |
498 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 498 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
499 GPMI_CTRL0_ADDRESS_NAND_DATA | 499 GPMI_CTRL0_ADDRESS_NAND_DATA |
500 length; 500 length;
501 501
502 mxs_dma_desc_append(channel, d); 502 mxs_dma_desc_append(channel, d);
503 503
504 /* 504 /*
505 * A DMA descriptor that waits for the command to end and the chip to 505 * A DMA descriptor that waits for the command to end and the chip to
506 * become ready. 506 * become ready.
507 * 507 *
508 * I think we actually should *not* be waiting for the chip to become 508 * I think we actually should *not* be waiting for the chip to become
509 * ready because, after all, we don't care. I think the original code 509 * ready because, after all, we don't care. I think the original code
510 * did that and no one has re-thought it yet. 510 * did that and no one has re-thought it yet.
511 */ 511 */
512 d = mxs_nand_get_dma_desc(nand_info); 512 d = mxs_nand_get_dma_desc(nand_info);
513 d->cmd.data = 513 d->cmd.data =
514 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 514 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
515 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | 515 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
516 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 516 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
517 517
518 d->cmd.address = 0; 518 d->cmd.address = 0;
519 519
520 d->cmd.pio_words[0] = 520 d->cmd.pio_words[0] =
521 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 521 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
522 GPMI_CTRL0_WORD_LENGTH | 522 GPMI_CTRL0_WORD_LENGTH |
523 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 523 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
524 GPMI_CTRL0_ADDRESS_NAND_DATA; 524 GPMI_CTRL0_ADDRESS_NAND_DATA;
525 525
526 mxs_dma_desc_append(channel, d); 526 mxs_dma_desc_append(channel, d);
527 527
528 /* Invalidate caches */ 528 /* Invalidate caches */
529 mxs_nand_inval_data_buf(nand_info); 529 mxs_nand_inval_data_buf(nand_info);
530 530
531 /* Execute the DMA chain. */ 531 /* Execute the DMA chain. */
532 ret = mxs_dma_go(channel); 532 ret = mxs_dma_go(channel);
533 if (ret) { 533 if (ret) {
534 printf("MXS NAND: DMA read error\n"); 534 printf("MXS NAND: DMA read error\n");
535 goto rtn; 535 goto rtn;
536 } 536 }
537 537
538 /* Invalidate caches */ 538 /* Invalidate caches */
539 mxs_nand_inval_data_buf(nand_info); 539 mxs_nand_inval_data_buf(nand_info);
540 540
541 memcpy(buf, nand_info->data_buf, length); 541 memcpy(buf, nand_info->data_buf, length);
542 542
543 rtn: 543 rtn:
544 mxs_nand_return_dma_descs(nand_info); 544 mxs_nand_return_dma_descs(nand_info);
545 } 545 }
546 546
547 /* 547 /*
548 * Write data to NAND. 548 * Write data to NAND.
549 */ 549 */
550 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, 550 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
551 int length) 551 int length)
552 { 552 {
553 struct nand_chip *nand = mtd_to_nand(mtd); 553 struct nand_chip *nand = mtd_to_nand(mtd);
554 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 554 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
555 struct mxs_dma_desc *d; 555 struct mxs_dma_desc *d;
556 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 556 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
557 int ret; 557 int ret;
558 558
559 if (length > NAND_MAX_PAGESIZE) { 559 if (length > NAND_MAX_PAGESIZE) {
560 printf("MXS NAND: DMA buffer too big\n"); 560 printf("MXS NAND: DMA buffer too big\n");
561 return; 561 return;
562 } 562 }
563 563
564 if (!buf) { 564 if (!buf) {
565 printf("MXS NAND: DMA buffer is NULL\n"); 565 printf("MXS NAND: DMA buffer is NULL\n");
566 return; 566 return;
567 } 567 }
568 568
569 memcpy(nand_info->data_buf, buf, length); 569 memcpy(nand_info->data_buf, buf, length);
570 570
571 /* Compile the DMA descriptor - a descriptor that writes data. */ 571 /* Compile the DMA descriptor - a descriptor that writes data. */
572 d = mxs_nand_get_dma_desc(nand_info); 572 d = mxs_nand_get_dma_desc(nand_info);
573 d->cmd.data = 573 d->cmd.data =
574 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | 574 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
575 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 575 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
576 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 576 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
577 (length << MXS_DMA_DESC_BYTES_OFFSET); 577 (length << MXS_DMA_DESC_BYTES_OFFSET);
578 578
579 d->cmd.address = (dma_addr_t)nand_info->data_buf; 579 d->cmd.address = (dma_addr_t)nand_info->data_buf;
580 580
581 d->cmd.pio_words[0] = 581 d->cmd.pio_words[0] =
582 GPMI_CTRL0_COMMAND_MODE_WRITE | 582 GPMI_CTRL0_COMMAND_MODE_WRITE |
583 GPMI_CTRL0_WORD_LENGTH | 583 GPMI_CTRL0_WORD_LENGTH |
584 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 584 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
585 GPMI_CTRL0_ADDRESS_NAND_DATA | 585 GPMI_CTRL0_ADDRESS_NAND_DATA |
586 length; 586 length;
587 587
588 mxs_dma_desc_append(channel, d); 588 mxs_dma_desc_append(channel, d);
589 589
590 /* Flush caches */ 590 /* Flush caches */
591 mxs_nand_flush_data_buf(nand_info); 591 mxs_nand_flush_data_buf(nand_info);
592 592
593 /* Execute the DMA chain. */ 593 /* Execute the DMA chain. */
594 ret = mxs_dma_go(channel); 594 ret = mxs_dma_go(channel);
595 if (ret) 595 if (ret)
596 printf("MXS NAND: DMA write error\n"); 596 printf("MXS NAND: DMA write error\n");
597 597
598 mxs_nand_return_dma_descs(nand_info); 598 mxs_nand_return_dma_descs(nand_info);
599 } 599 }
600 600
601 /* 601 /*
602 * Read a single byte from NAND. 602 * Read a single byte from NAND.
603 */ 603 */
604 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) 604 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
605 { 605 {
606 uint8_t buf; 606 uint8_t buf;
607 mxs_nand_read_buf(mtd, &buf, 1); 607 mxs_nand_read_buf(mtd, &buf, 1);
608 return buf; 608 return buf;
609 } 609 }
610 610
611 /* 611 /*
612 * Read a page from NAND. 612 * Read a page from NAND.
613 */ 613 */
614 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, 614 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
615 uint8_t *buf, int oob_required, 615 uint8_t *buf, int oob_required,
616 int page) 616 int page)
617 { 617 {
618 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 618 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
619 struct bch_geometry *geo = &nand_info->bch_geometry; 619 struct bch_geometry *geo = &nand_info->bch_geometry;
620 struct mxs_dma_desc *d; 620 struct mxs_dma_desc *d;
621 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 621 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
622 uint32_t corrected = 0, failed = 0; 622 uint32_t corrected = 0, failed = 0;
623 uint8_t *status; 623 uint8_t *status;
624 int i, ret; 624 int i, ret;
625 625
626 /* Compile the DMA descriptor - wait for ready. */ 626 /* Compile the DMA descriptor - wait for ready. */
627 d = mxs_nand_get_dma_desc(nand_info); 627 d = mxs_nand_get_dma_desc(nand_info);
628 d->cmd.data = 628 d->cmd.data =
629 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 629 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
630 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | 630 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
631 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 631 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
632 632
633 d->cmd.address = 0; 633 d->cmd.address = 0;
634 634
635 d->cmd.pio_words[0] = 635 d->cmd.pio_words[0] =
636 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 636 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
637 GPMI_CTRL0_WORD_LENGTH | 637 GPMI_CTRL0_WORD_LENGTH |
638 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 638 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
639 GPMI_CTRL0_ADDRESS_NAND_DATA; 639 GPMI_CTRL0_ADDRESS_NAND_DATA;
640 640
641 mxs_dma_desc_append(channel, d); 641 mxs_dma_desc_append(channel, d);
642 642
643 /* Compile the DMA descriptor - enable the BCH block and read. */ 643 /* Compile the DMA descriptor - enable the BCH block and read. */
644 d = mxs_nand_get_dma_desc(nand_info); 644 d = mxs_nand_get_dma_desc(nand_info);
645 d->cmd.data = 645 d->cmd.data =
646 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 646 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
647 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 647 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
648 648
649 d->cmd.address = 0; 649 d->cmd.address = 0;
650 650
651 d->cmd.pio_words[0] = 651 d->cmd.pio_words[0] =
652 GPMI_CTRL0_COMMAND_MODE_READ | 652 GPMI_CTRL0_COMMAND_MODE_READ |
653 GPMI_CTRL0_WORD_LENGTH | 653 GPMI_CTRL0_WORD_LENGTH |
654 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 654 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
655 GPMI_CTRL0_ADDRESS_NAND_DATA | 655 GPMI_CTRL0_ADDRESS_NAND_DATA |
656 (mtd->writesize + mtd->oobsize); 656 (mtd->writesize + mtd->oobsize);
657 d->cmd.pio_words[1] = 0; 657 d->cmd.pio_words[1] = 0;
658 d->cmd.pio_words[2] = 658 d->cmd.pio_words[2] =
659 GPMI_ECCCTRL_ENABLE_ECC | 659 GPMI_ECCCTRL_ENABLE_ECC |
660 GPMI_ECCCTRL_ECC_CMD_DECODE | 660 GPMI_ECCCTRL_ECC_CMD_DECODE |
661 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; 661 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
662 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize; 662 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
663 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; 663 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
664 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; 664 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
665 665
666 mxs_dma_desc_append(channel, d); 666 mxs_dma_desc_append(channel, d);
667 667
668 /* Compile the DMA descriptor - disable the BCH block. */ 668 /* Compile the DMA descriptor - disable the BCH block. */
669 d = mxs_nand_get_dma_desc(nand_info); 669 d = mxs_nand_get_dma_desc(nand_info);
670 d->cmd.data = 670 d->cmd.data =
671 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 671 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
672 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | 672 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
673 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 673 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
674 674
675 d->cmd.address = 0; 675 d->cmd.address = 0;
676 676
677 d->cmd.pio_words[0] = 677 d->cmd.pio_words[0] =
678 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 678 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
679 GPMI_CTRL0_WORD_LENGTH | 679 GPMI_CTRL0_WORD_LENGTH |
680 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 680 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
681 GPMI_CTRL0_ADDRESS_NAND_DATA | 681 GPMI_CTRL0_ADDRESS_NAND_DATA |
682 (mtd->writesize + mtd->oobsize); 682 (mtd->writesize + mtd->oobsize);
683 d->cmd.pio_words[1] = 0; 683 d->cmd.pio_words[1] = 0;
684 d->cmd.pio_words[2] = 0; 684 d->cmd.pio_words[2] = 0;
685 685
686 mxs_dma_desc_append(channel, d); 686 mxs_dma_desc_append(channel, d);
687 687
688 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */ 688 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
689 d = mxs_nand_get_dma_desc(nand_info); 689 d = mxs_nand_get_dma_desc(nand_info);
690 d->cmd.data = 690 d->cmd.data =
691 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 691 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
692 MXS_DMA_DESC_DEC_SEM; 692 MXS_DMA_DESC_DEC_SEM;
693 693
694 d->cmd.address = 0; 694 d->cmd.address = 0;
695 695
696 mxs_dma_desc_append(channel, d); 696 mxs_dma_desc_append(channel, d);
697 697
698 /* Invalidate caches */ 698 /* Invalidate caches */
699 mxs_nand_inval_data_buf(nand_info); 699 mxs_nand_inval_data_buf(nand_info);
700 700
701 /* Execute the DMA chain. */ 701 /* Execute the DMA chain. */
702 ret = mxs_dma_go(channel); 702 ret = mxs_dma_go(channel);
703 if (ret) { 703 if (ret) {
704 printf("MXS NAND: DMA read error\n"); 704 printf("MXS NAND: DMA read error\n");
705 goto rtn; 705 goto rtn;
706 } 706 }
707 707
708 ret = mxs_nand_wait_for_bch_complete(); 708 ret = mxs_nand_wait_for_bch_complete(nand_info);
709 if (ret) { 709 if (ret) {
710 printf("MXS NAND: BCH read timeout\n"); 710 printf("MXS NAND: BCH read timeout\n");
711 goto rtn; 711 goto rtn;
712 } 712 }
713 713
714 /* Invalidate caches */ 714 /* Invalidate caches */
715 mxs_nand_inval_data_buf(nand_info); 715 mxs_nand_inval_data_buf(nand_info);
716 716
717 /* Read DMA completed, now do the mark swapping. */ 717 /* Read DMA completed, now do the mark swapping. */
718 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); 718 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
719 719
720 /* Loop over status bytes, accumulating ECC status. */ 720 /* Loop over status bytes, accumulating ECC status. */
721 status = nand_info->oob_buf + mxs_nand_aux_status_offset(); 721 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
722 for (i = 0; i < geo->ecc_chunk_count; i++) { 722 for (i = 0; i < geo->ecc_chunk_count; i++) {
723 if (status[i] == 0x00) 723 if (status[i] == 0x00)
724 continue; 724 continue;
725 725
726 if (status[i] == 0xff) 726 if (status[i] == 0xff)
727 continue; 727 continue;
728 728
729 if (status[i] == 0xfe) { 729 if (status[i] == 0xfe) {
730 failed++; 730 failed++;
731 continue; 731 continue;
732 } 732 }
733 733
734 corrected += status[i]; 734 corrected += status[i];
735 } 735 }
736 736
737 /* Propagate ECC status to the owning MTD. */ 737 /* Propagate ECC status to the owning MTD. */
738 mtd->ecc_stats.failed += failed; 738 mtd->ecc_stats.failed += failed;
739 mtd->ecc_stats.corrected += corrected; 739 mtd->ecc_stats.corrected += corrected;
740 740
741 /* 741 /*
742 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for 742 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
743 * details about our policy for delivering the OOB. 743 * details about our policy for delivering the OOB.
744 * 744 *
745 * We fill the caller's buffer with set bits, and then copy the block 745 * We fill the caller's buffer with set bits, and then copy the block
746 * mark to the caller's buffer. Note that, if block mark swapping was 746 * mark to the caller's buffer. Note that, if block mark swapping was
747 * necessary, it has already been done, so we can rely on the first 747 * necessary, it has already been done, so we can rely on the first
748 * byte of the auxiliary buffer to contain the block mark. 748 * byte of the auxiliary buffer to contain the block mark.
749 */ 749 */
750 memset(nand->oob_poi, 0xff, mtd->oobsize); 750 memset(nand->oob_poi, 0xff, mtd->oobsize);
751 751
752 nand->oob_poi[0] = nand_info->oob_buf[0]; 752 nand->oob_poi[0] = nand_info->oob_buf[0];
753 753
754 memcpy(buf, nand_info->data_buf, mtd->writesize); 754 memcpy(buf, nand_info->data_buf, mtd->writesize);
755 755
756 rtn: 756 rtn:
757 mxs_nand_return_dma_descs(nand_info); 757 mxs_nand_return_dma_descs(nand_info);
758 758
759 return ret; 759 return ret;
760 } 760 }
761 761
762 /* 762 /*
763 * Write a page to NAND. 763 * Write a page to NAND.
764 */ 764 */
765 static int mxs_nand_ecc_write_page(struct mtd_info *mtd, 765 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
766 struct nand_chip *nand, const uint8_t *buf, 766 struct nand_chip *nand, const uint8_t *buf,
767 int oob_required, int page) 767 int oob_required, int page)
768 { 768 {
769 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 769 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
770 struct bch_geometry *geo = &nand_info->bch_geometry; 770 struct bch_geometry *geo = &nand_info->bch_geometry;
771 struct mxs_dma_desc *d; 771 struct mxs_dma_desc *d;
772 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 772 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
773 int ret; 773 int ret;
774 774
775 memcpy(nand_info->data_buf, buf, mtd->writesize); 775 memcpy(nand_info->data_buf, buf, mtd->writesize);
776 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize); 776 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
777 777
778 /* Handle block mark swapping. */ 778 /* Handle block mark swapping. */
779 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); 779 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
780 780
781 /* Compile the DMA descriptor - write data. */ 781 /* Compile the DMA descriptor - write data. */
782 d = mxs_nand_get_dma_desc(nand_info); 782 d = mxs_nand_get_dma_desc(nand_info);
783 d->cmd.data = 783 d->cmd.data =
784 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 784 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
785 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 785 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
786 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 786 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
787 787
788 d->cmd.address = 0; 788 d->cmd.address = 0;
789 789
790 d->cmd.pio_words[0] = 790 d->cmd.pio_words[0] =
791 GPMI_CTRL0_COMMAND_MODE_WRITE | 791 GPMI_CTRL0_COMMAND_MODE_WRITE |
792 GPMI_CTRL0_WORD_LENGTH | 792 GPMI_CTRL0_WORD_LENGTH |
793 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 793 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
794 GPMI_CTRL0_ADDRESS_NAND_DATA; 794 GPMI_CTRL0_ADDRESS_NAND_DATA;
795 d->cmd.pio_words[1] = 0; 795 d->cmd.pio_words[1] = 0;
796 d->cmd.pio_words[2] = 796 d->cmd.pio_words[2] =
797 GPMI_ECCCTRL_ENABLE_ECC | 797 GPMI_ECCCTRL_ENABLE_ECC |
798 GPMI_ECCCTRL_ECC_CMD_ENCODE | 798 GPMI_ECCCTRL_ECC_CMD_ENCODE |
799 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; 799 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
800 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize); 800 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
801 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; 801 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
802 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; 802 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
803 803
804 mxs_dma_desc_append(channel, d); 804 mxs_dma_desc_append(channel, d);
805 805
806 /* Flush caches */ 806 /* Flush caches */
807 mxs_nand_flush_data_buf(nand_info); 807 mxs_nand_flush_data_buf(nand_info);
808 808
809 /* Execute the DMA chain. */ 809 /* Execute the DMA chain. */
810 ret = mxs_dma_go(channel); 810 ret = mxs_dma_go(channel);
811 if (ret) { 811 if (ret) {
812 printf("MXS NAND: DMA write error\n"); 812 printf("MXS NAND: DMA write error\n");
813 goto rtn; 813 goto rtn;
814 } 814 }
815 815
816 ret = mxs_nand_wait_for_bch_complete(); 816 ret = mxs_nand_wait_for_bch_complete(nand_info);
817 if (ret) { 817 if (ret) {
818 printf("MXS NAND: BCH write timeout\n"); 818 printf("MXS NAND: BCH write timeout\n");
819 goto rtn; 819 goto rtn;
820 } 820 }
821 821
822 rtn: 822 rtn:
823 mxs_nand_return_dma_descs(nand_info); 823 mxs_nand_return_dma_descs(nand_info);
824 return 0; 824 return 0;
825 } 825 }
826 826
827 /* 827 /*
828 * Read OOB from NAND. 828 * Read OOB from NAND.
829 * 829 *
830 * This function is a veneer that replaces the function originally installed by 830 * This function is a veneer that replaces the function originally installed by
831 * the NAND Flash MTD code. 831 * the NAND Flash MTD code.
832 */ 832 */
833 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, 833 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
834 struct mtd_oob_ops *ops) 834 struct mtd_oob_ops *ops)
835 { 835 {
836 struct nand_chip *chip = mtd_to_nand(mtd); 836 struct nand_chip *chip = mtd_to_nand(mtd);
837 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); 837 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
838 int ret; 838 int ret;
839 839
840 if (ops->mode == MTD_OPS_RAW) 840 if (ops->mode == MTD_OPS_RAW)
841 nand_info->raw_oob_mode = 1; 841 nand_info->raw_oob_mode = 1;
842 else 842 else
843 nand_info->raw_oob_mode = 0; 843 nand_info->raw_oob_mode = 0;
844 844
845 ret = nand_info->hooked_read_oob(mtd, from, ops); 845 ret = nand_info->hooked_read_oob(mtd, from, ops);
846 846
847 nand_info->raw_oob_mode = 0; 847 nand_info->raw_oob_mode = 0;
848 848
849 return ret; 849 return ret;
850 } 850 }
851 851
852 /* 852 /*
853 * Write OOB to NAND. 853 * Write OOB to NAND.
854 * 854 *
855 * This function is a veneer that replaces the function originally installed by 855 * This function is a veneer that replaces the function originally installed by
856 * the NAND Flash MTD code. 856 * the NAND Flash MTD code.
857 */ 857 */
858 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, 858 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
859 struct mtd_oob_ops *ops) 859 struct mtd_oob_ops *ops)
860 { 860 {
861 struct nand_chip *chip = mtd_to_nand(mtd); 861 struct nand_chip *chip = mtd_to_nand(mtd);
862 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); 862 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
863 int ret; 863 int ret;
864 864
865 if (ops->mode == MTD_OPS_RAW) 865 if (ops->mode == MTD_OPS_RAW)
866 nand_info->raw_oob_mode = 1; 866 nand_info->raw_oob_mode = 1;
867 else 867 else
868 nand_info->raw_oob_mode = 0; 868 nand_info->raw_oob_mode = 0;
869 869
870 ret = nand_info->hooked_write_oob(mtd, to, ops); 870 ret = nand_info->hooked_write_oob(mtd, to, ops);
871 871
872 nand_info->raw_oob_mode = 0; 872 nand_info->raw_oob_mode = 0;
873 873
874 return ret; 874 return ret;
875 } 875 }
876 876
877 /* 877 /*
878 * Mark a block bad in NAND. 878 * Mark a block bad in NAND.
879 * 879 *
880 * This function is a veneer that replaces the function originally installed by 880 * This function is a veneer that replaces the function originally installed by
881 * the NAND Flash MTD code. 881 * the NAND Flash MTD code.
882 */ 882 */
883 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) 883 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
884 { 884 {
885 struct nand_chip *chip = mtd_to_nand(mtd); 885 struct nand_chip *chip = mtd_to_nand(mtd);
886 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); 886 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
887 int ret; 887 int ret;
888 888
889 nand_info->marking_block_bad = 1; 889 nand_info->marking_block_bad = 1;
890 890
891 ret = nand_info->hooked_block_markbad(mtd, ofs); 891 ret = nand_info->hooked_block_markbad(mtd, ofs);
892 892
893 nand_info->marking_block_bad = 0; 893 nand_info->marking_block_bad = 0;
894 894
895 return ret; 895 return ret;
896 } 896 }
897 897
898 /* 898 /*
899 * There are several places in this driver where we have to handle the OOB and 899 * There are several places in this driver where we have to handle the OOB and
900 * block marks. This is the function where things are the most complicated, so 900 * block marks. This is the function where things are the most complicated, so
901 * this is where we try to explain it all. All the other places refer back to 901 * this is where we try to explain it all. All the other places refer back to
902 * here. 902 * here.
903 * 903 *
904 * These are the rules, in order of decreasing importance: 904 * These are the rules, in order of decreasing importance:
905 * 905 *
906 * 1) Nothing the caller does can be allowed to imperil the block mark, so all 906 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
907 * write operations take measures to protect it. 907 * write operations take measures to protect it.
908 * 908 *
909 * 2) In read operations, the first byte of the OOB we return must reflect the 909 * 2) In read operations, the first byte of the OOB we return must reflect the
910 * true state of the block mark, no matter where that block mark appears in 910 * true state of the block mark, no matter where that block mark appears in
911 * the physical page. 911 * the physical page.
912 * 912 *
913 * 3) ECC-based read operations return an OOB full of set bits (since we never 913 * 3) ECC-based read operations return an OOB full of set bits (since we never
914 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads 914 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
915 * return). 915 * return).
916 * 916 *
917 * 4) "Raw" read operations return a direct view of the physical bytes in the 917 * 4) "Raw" read operations return a direct view of the physical bytes in the
918 * page, using the conventional definition of which bytes are data and which 918 * page, using the conventional definition of which bytes are data and which
919 * are OOB. This gives the caller a way to see the actual, physical bytes 919 * are OOB. This gives the caller a way to see the actual, physical bytes
920 * in the page, without the distortions applied by our ECC engine. 920 * in the page, without the distortions applied by our ECC engine.
921 * 921 *
922 * What we do for this specific read operation depends on whether we're doing 922 * What we do for this specific read operation depends on whether we're doing
923 * "raw" read, or an ECC-based read. 923 * "raw" read, or an ECC-based read.
924 * 924 *
925 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not 925 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
926 * easy. When reading a page, for example, the NAND Flash MTD code calls our 926 * easy. When reading a page, for example, the NAND Flash MTD code calls our
927 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an 927 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
928 * ECC-based or raw view of the page is implicit in which function it calls 928 * ECC-based or raw view of the page is implicit in which function it calls
929 * (there is a similar pair of ECC-based/raw functions for writing). 929 * (there is a similar pair of ECC-based/raw functions for writing).
930 * 930 *
931 * Since MTD assumes the OOB is not covered by ECC, there is no pair of 931 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
932 * ECC-based/raw functions for reading or or writing the OOB. The fact that the 932 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
933 * caller wants an ECC-based or raw view of the page is not propagated down to 933 * caller wants an ECC-based or raw view of the page is not propagated down to
934 * this driver. 934 * this driver.
935 * 935 *
936 * Since our OOB *is* covered by ECC, we need this information. So, we hook the 936 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
937 * ecc.read_oob and ecc.write_oob function pointers in the owning 937 * ecc.read_oob and ecc.write_oob function pointers in the owning
938 * struct mtd_info with our own functions. These hook functions set the 938 * struct mtd_info with our own functions. These hook functions set the
939 * raw_oob_mode field so that, when control finally arrives here, we'll know 939 * raw_oob_mode field so that, when control finally arrives here, we'll know
940 * what to do. 940 * what to do.
941 */ 941 */
942 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, 942 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
943 int page) 943 int page)
944 { 944 {
945 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 945 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
946 946
947 /* 947 /*
948 * First, fill in the OOB buffer. If we're doing a raw read, we need to 948 * First, fill in the OOB buffer. If we're doing a raw read, we need to
949 * get the bytes from the physical page. If we're not doing a raw read, 949 * get the bytes from the physical page. If we're not doing a raw read,
950 * we need to fill the buffer with set bits. 950 * we need to fill the buffer with set bits.
951 */ 951 */
952 if (nand_info->raw_oob_mode) { 952 if (nand_info->raw_oob_mode) {
953 /* 953 /*
954 * If control arrives here, we're doing a "raw" read. Send the 954 * If control arrives here, we're doing a "raw" read. Send the
955 * command to read the conventional OOB and read it. 955 * command to read the conventional OOB and read it.
956 */ 956 */
957 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); 957 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
958 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); 958 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
959 } else { 959 } else {
960 /* 960 /*
961 * If control arrives here, we're not doing a "raw" read. Fill 961 * If control arrives here, we're not doing a "raw" read. Fill
962 * the OOB buffer with set bits and correct the block mark. 962 * the OOB buffer with set bits and correct the block mark.
963 */ 963 */
964 memset(nand->oob_poi, 0xff, mtd->oobsize); 964 memset(nand->oob_poi, 0xff, mtd->oobsize);
965 965
966 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); 966 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
967 mxs_nand_read_buf(mtd, nand->oob_poi, 1); 967 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
968 } 968 }
969 969
970 return 0; 970 return 0;
971 971
972 } 972 }
973 973
974 /* 974 /*
975 * Write OOB data to NAND. 975 * Write OOB data to NAND.
976 */ 976 */
977 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, 977 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
978 int page) 978 int page)
979 { 979 {
980 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 980 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
981 uint8_t block_mark = 0; 981 uint8_t block_mark = 0;
982 982
983 /* 983 /*
984 * There are fundamental incompatibilities between the i.MX GPMI NFC and 984 * There are fundamental incompatibilities between the i.MX GPMI NFC and
985 * the NAND Flash MTD model that make it essentially impossible to write 985 * the NAND Flash MTD model that make it essentially impossible to write
986 * the out-of-band bytes. 986 * the out-of-band bytes.
987 * 987 *
988 * We permit *ONE* exception. If the *intent* of writing the OOB is to 988 * We permit *ONE* exception. If the *intent* of writing the OOB is to
989 * mark a block bad, we can do that. 989 * mark a block bad, we can do that.
990 */ 990 */
991 991
992 if (!nand_info->marking_block_bad) { 992 if (!nand_info->marking_block_bad) {
993 printf("NXS NAND: Writing OOB isn't supported\n"); 993 printf("NXS NAND: Writing OOB isn't supported\n");
994 return -EIO; 994 return -EIO;
995 } 995 }
996 996
997 /* Write the block mark. */ 997 /* Write the block mark. */
998 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 998 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
999 nand->write_buf(mtd, &block_mark, 1); 999 nand->write_buf(mtd, &block_mark, 1);
1000 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1000 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1001 1001
1002 /* Check if it worked. */ 1002 /* Check if it worked. */
1003 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL) 1003 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1004 return -EIO; 1004 return -EIO;
1005 1005
1006 return 0; 1006 return 0;
1007 } 1007 }
1008 1008
1009 /* 1009 /*
1010 * Claims all blocks are good. 1010 * Claims all blocks are good.
1011 * 1011 *
1012 * In principle, this function is *only* called when the NAND Flash MTD system 1012 * In principle, this function is *only* called when the NAND Flash MTD system
1013 * isn't allowed to keep an in-memory bad block table, so it is forced to ask 1013 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1014 * the driver for bad block information. 1014 * the driver for bad block information.
1015 * 1015 *
1016 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so 1016 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1017 * this function is *only* called when we take it away. 1017 * this function is *only* called when we take it away.
1018 * 1018 *
1019 * Thus, this function is only called when we want *all* blocks to look good, 1019 * Thus, this function is only called when we want *all* blocks to look good,
1020 * so it *always* return success. 1020 * so it *always* return success.
1021 */ 1021 */
1022 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) 1022 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1023 { 1023 {
1024 return 0; 1024 return 0;
1025 } 1025 }
1026 1026
1027 /* 1027 /*
1028 * At this point, the physical NAND Flash chips have been identified and 1028 * At this point, the physical NAND Flash chips have been identified and
1029 * counted, so we know the physical geometry. This enables us to make some 1029 * counted, so we know the physical geometry. This enables us to make some
1030 * important configuration decisions. 1030 * important configuration decisions.
1031 * 1031 *
1032 * The return value of this function propagates directly back to this driver's 1032 * The return value of this function propagates directly back to this driver's
1033 * board_nand_init(). Anything other than zero will cause this driver to 1033 * board_nand_init(). Anything other than zero will cause this driver to
1034 * tear everything down and declare failure. 1034 * tear everything down and declare failure.
1035 */ 1035 */
1036 int mxs_nand_setup_ecc(struct mtd_info *mtd) 1036 int mxs_nand_setup_ecc(struct mtd_info *mtd)
1037 { 1037 {
1038 struct nand_chip *nand = mtd_to_nand(mtd); 1038 struct nand_chip *nand = mtd_to_nand(mtd);
1039 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); 1039 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1040 struct bch_geometry *geo = &nand_info->bch_geometry; 1040 struct bch_geometry *geo = &nand_info->bch_geometry;
1041 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; 1041 struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
1042 uint32_t tmp; 1042 uint32_t tmp;
1043 int ret = -ENOTSUPP; 1043 int ret = -ENOTSUPP;
1044 1044
1045 #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC 1045 #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
1046 ret = mxs_nand_calc_ecc_layout_by_info(geo, mtd); 1046 ret = mxs_nand_calc_ecc_layout_by_info(geo, mtd);
1047 #endif 1047 #endif
1048 1048
1049 if (ret == -ENOTSUPP) 1049 if (ret == -ENOTSUPP)
1050 ret = mxs_nand_calc_ecc_layout(geo, mtd); 1050 ret = mxs_nand_calc_ecc_layout(geo, mtd);
1051 1051
1052 if (ret) 1052 if (ret)
1053 return ret; 1053 return ret;
1054 1054
1055 mxs_nand_calc_mark_offset(geo, mtd->writesize); 1055 mxs_nand_calc_mark_offset(geo, mtd->writesize);
1056 1056
1057 /* Configure BCH and set NFC geometry */ 1057 /* Configure BCH and set NFC geometry */
1058 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); 1058 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1059 1059
1060 /* Configure layout 0 */ 1060 /* Configure layout 0 */
1061 tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; 1061 tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1062 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; 1062 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1063 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; 1063 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1064 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; 1064 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1065 tmp |= (geo->gf_len == 14 ? 1 : 0) << 1065 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1066 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; 1066 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1067 writel(tmp, &bch_regs->hw_bch_flash0layout0); 1067 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1068 1068
1069 tmp = (mtd->writesize + mtd->oobsize) 1069 tmp = (mtd->writesize + mtd->oobsize)
1070 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; 1070 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1071 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; 1071 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1072 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; 1072 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1073 tmp |= (geo->gf_len == 14 ? 1 : 0) << 1073 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1074 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; 1074 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1075 writel(tmp, &bch_regs->hw_bch_flash0layout1); 1075 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1076 1076
1077 /* Set *all* chip selects to use layout 0 */ 1077 /* Set *all* chip selects to use layout 0 */
1078 writel(0, &bch_regs->hw_bch_layoutselect); 1078 writel(0, &bch_regs->hw_bch_layoutselect);
1079 1079
1080 /* Enable BCH complete interrupt */ 1080 /* Enable BCH complete interrupt */
1081 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set); 1081 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1082 1082
1083 /* Hook some operations at the MTD level. */ 1083 /* Hook some operations at the MTD level. */
1084 if (mtd->_read_oob != mxs_nand_hook_read_oob) { 1084 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1085 nand_info->hooked_read_oob = mtd->_read_oob; 1085 nand_info->hooked_read_oob = mtd->_read_oob;
1086 mtd->_read_oob = mxs_nand_hook_read_oob; 1086 mtd->_read_oob = mxs_nand_hook_read_oob;
1087 } 1087 }
1088 1088
1089 if (mtd->_write_oob != mxs_nand_hook_write_oob) { 1089 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1090 nand_info->hooked_write_oob = mtd->_write_oob; 1090 nand_info->hooked_write_oob = mtd->_write_oob;
1091 mtd->_write_oob = mxs_nand_hook_write_oob; 1091 mtd->_write_oob = mxs_nand_hook_write_oob;
1092 } 1092 }
1093 1093
1094 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) { 1094 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1095 nand_info->hooked_block_markbad = mtd->_block_markbad; 1095 nand_info->hooked_block_markbad = mtd->_block_markbad;
1096 mtd->_block_markbad = mxs_nand_hook_block_markbad; 1096 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1097 } 1097 }
1098 1098
1099 return 0; 1099 return 0;
1100 } 1100 }
1101 1101
1102 /* 1102 /*
1103 * Allocate DMA buffers 1103 * Allocate DMA buffers
1104 */ 1104 */
1105 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) 1105 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1106 { 1106 {
1107 uint8_t *buf; 1107 uint8_t *buf;
1108 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; 1108 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1109 1109
1110 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT); 1110 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1111 1111
1112 /* DMA buffers */ 1112 /* DMA buffers */
1113 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size); 1113 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1114 if (!buf) { 1114 if (!buf) {
1115 printf("MXS NAND: Error allocating DMA buffers\n"); 1115 printf("MXS NAND: Error allocating DMA buffers\n");
1116 return -ENOMEM; 1116 return -ENOMEM;
1117 } 1117 }
1118 1118
1119 memset(buf, 0, nand_info->data_buf_size); 1119 memset(buf, 0, nand_info->data_buf_size);
1120 1120
1121 nand_info->data_buf = buf; 1121 nand_info->data_buf = buf;
1122 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE; 1122 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1123 /* Command buffers */ 1123 /* Command buffers */
1124 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT, 1124 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1125 MXS_NAND_COMMAND_BUFFER_SIZE); 1125 MXS_NAND_COMMAND_BUFFER_SIZE);
1126 if (!nand_info->cmd_buf) { 1126 if (!nand_info->cmd_buf) {
1127 free(buf); 1127 free(buf);
1128 printf("MXS NAND: Error allocating command buffers\n"); 1128 printf("MXS NAND: Error allocating command buffers\n");
1129 return -ENOMEM; 1129 return -ENOMEM;
1130 } 1130 }
1131 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE); 1131 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1132 nand_info->cmd_queue_len = 0; 1132 nand_info->cmd_queue_len = 0;
1133 1133
1134 return 0; 1134 return 0;
1135 } 1135 }
1136 1136
1137 /* 1137 /*
1138 * Initializes the NFC hardware. 1138 * Initializes the NFC hardware.
1139 */ 1139 */
1140 int mxs_nand_init(struct mxs_nand_info *info) 1140 int mxs_nand_init(struct mxs_nand_info *info)
1141 { 1141 {
1142 struct mxs_gpmi_regs *gpmi_regs =
1143 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1144 struct mxs_bch_regs *bch_regs =
1145 (struct mxs_bch_regs *)MXS_BCH_BASE;
1146 int i = 0, j, ret = 0; 1142 int i = 0, j, ret = 0;
1147 1143
1148 info->desc = malloc(sizeof(struct mxs_dma_desc *) * 1144 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1149 MXS_NAND_DMA_DESCRIPTOR_COUNT); 1145 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1150 if (!info->desc) { 1146 if (!info->desc) {
1151 ret = -ENOMEM; 1147 ret = -ENOMEM;
1152 goto err1; 1148 goto err1;
1153 } 1149 }
1154 1150
1155 /* Allocate the DMA descriptors. */ 1151 /* Allocate the DMA descriptors. */
1156 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { 1152 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1157 info->desc[i] = mxs_dma_desc_alloc(); 1153 info->desc[i] = mxs_dma_desc_alloc();
1158 if (!info->desc[i]) { 1154 if (!info->desc[i]) {
1159 ret = -ENOMEM; 1155 ret = -ENOMEM;
1160 goto err2; 1156 goto err2;
1161 } 1157 }
1162 } 1158 }
1163 1159
1164 /* Init the DMA controller. */ 1160 /* Init the DMA controller. */
1165 mxs_dma_init(); 1161 mxs_dma_init();
1166 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; 1162 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1167 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { 1163 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1168 ret = mxs_dma_init_channel(j); 1164 ret = mxs_dma_init_channel(j);
1169 if (ret) 1165 if (ret)
1170 goto err3; 1166 goto err3;
1171 } 1167 }
1172 1168
1173 /* Reset the GPMI block. */ 1169 /* Reset the GPMI block. */
1174 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); 1170 mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
1175 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); 1171 mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
1176 1172
1177 /* 1173 /*
1178 * Choose NAND mode, set IRQ polarity, disable write protection and 1174 * Choose NAND mode, set IRQ polarity, disable write protection and
1179 * select BCH ECC. 1175 * select BCH ECC.
1180 */ 1176 */
1181 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, 1177 clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
1182 GPMI_CTRL1_GPMI_MODE, 1178 GPMI_CTRL1_GPMI_MODE,
1183 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | 1179 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1184 GPMI_CTRL1_BCH_MODE); 1180 GPMI_CTRL1_BCH_MODE);
1185 1181
1186 return 0; 1182 return 0;
1187 1183
1188 err3: 1184 err3:
1189 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--) 1185 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
1190 mxs_dma_release(j); 1186 mxs_dma_release(j);
1191 err2: 1187 err2:
1192 for (--i; i >= 0; i--) 1188 for (--i; i >= 0; i--)
1193 mxs_dma_desc_free(info->desc[i]); 1189 mxs_dma_desc_free(info->desc[i]);
1194 free(info->desc); 1190 free(info->desc);
1195 err1: 1191 err1:
1196 if (ret == -ENOMEM) 1192 if (ret == -ENOMEM)
1197 printf("MXS NAND: Unable to allocate DMA descriptors\n"); 1193 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1198 return ret; 1194 return ret;
1199 } 1195 }
1200 1196
1201 int mxs_nand_init_spl(struct nand_chip *nand) 1197 int mxs_nand_init_spl(struct nand_chip *nand)
1202 { 1198 {
1203 struct mxs_nand_info *nand_info; 1199 struct mxs_nand_info *nand_info;
1204 int err; 1200 int err;
1205 1201
1206 nand_info = malloc(sizeof(struct mxs_nand_info)); 1202 nand_info = malloc(sizeof(struct mxs_nand_info));
1207 if (!nand_info) { 1203 if (!nand_info) {
1208 printf("MXS NAND: Failed to allocate private data\n"); 1204 printf("MXS NAND: Failed to allocate private data\n");
1209 return -ENOMEM; 1205 return -ENOMEM;
1210 } 1206 }
1211 memset(nand_info, 0, sizeof(struct mxs_nand_info)); 1207 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1212 1208
1209 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1210 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1213 err = mxs_nand_alloc_buffers(nand_info); 1211 err = mxs_nand_alloc_buffers(nand_info);
1214 if (err) 1212 if (err)
1215 return err; 1213 return err;
1216 1214
1217 err = mxs_nand_init(nand_info); 1215 err = mxs_nand_init(nand_info);
1218 if (err) 1216 if (err)
1219 return err; 1217 return err;
1220 1218
1221 nand_set_controller_data(nand, nand_info); 1219 nand_set_controller_data(nand, nand_info);
1222 1220
1223 nand->options |= NAND_NO_SUBPAGE_WRITE; 1221 nand->options |= NAND_NO_SUBPAGE_WRITE;
1224 1222
1225 nand->cmd_ctrl = mxs_nand_cmd_ctrl; 1223 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1226 nand->dev_ready = mxs_nand_device_ready; 1224 nand->dev_ready = mxs_nand_device_ready;
1227 nand->select_chip = mxs_nand_select_chip; 1225 nand->select_chip = mxs_nand_select_chip;
1228 1226
1229 nand->read_byte = mxs_nand_read_byte; 1227 nand->read_byte = mxs_nand_read_byte;
1230 nand->read_buf = mxs_nand_read_buf; 1228 nand->read_buf = mxs_nand_read_buf;
1231 1229
1232 nand->ecc.read_page = mxs_nand_ecc_read_page; 1230 nand->ecc.read_page = mxs_nand_ecc_read_page;
1233 1231
1234 nand->ecc.mode = NAND_ECC_HW; 1232 nand->ecc.mode = NAND_ECC_HW;
1235 nand->ecc.bytes = 9; 1233 nand->ecc.bytes = 9;
1236 nand->ecc.size = 512; 1234 nand->ecc.size = 512;
1237 nand->ecc.strength = 8; 1235 nand->ecc.strength = 8;
1238 1236
1239 return 0; 1237 return 0;
1240 } 1238 }
1241 1239
1242 void board_nand_init(void) 1240 void board_nand_init(void)
1243 { 1241 {
1244 struct mtd_info *mtd; 1242 struct mtd_info *mtd;
1245 struct mxs_nand_info *nand_info; 1243 struct mxs_nand_info *nand_info;
1246 struct nand_chip *nand; 1244 struct nand_chip *nand;
1247 int err; 1245 int err;
1248 1246
1249 nand_info = malloc(sizeof(struct mxs_nand_info)); 1247 nand_info = malloc(sizeof(struct mxs_nand_info));
1250 if (!nand_info) { 1248 if (!nand_info) {
1251 printf("MXS NAND: Failed to allocate private data\n"); 1249 printf("MXS NAND: Failed to allocate private data\n");
1252 return; 1250 return;
1253 } 1251 }
1254 memset(nand_info, 0, sizeof(struct mxs_nand_info)); 1252 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1255 1253
1254 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1255 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1256 nand = &nand_info->chip; 1256 nand = &nand_info->chip;
1257 mtd = nand_to_mtd(nand); 1257 mtd = nand_to_mtd(nand);
1258 err = mxs_nand_alloc_buffers(nand_info); 1258 err = mxs_nand_alloc_buffers(nand_info);
1259 if (err) 1259 if (err)
1260 goto err1; 1260 goto err1;
1261 1261
1262 err = mxs_nand_init(nand_info); 1262 err = mxs_nand_init(nand_info);
1263 if (err) 1263 if (err)
1264 goto err2; 1264 goto err2;
1265 1265
1266 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); 1266 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1267 1267
1268 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 1268 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1269 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 1269 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1270 #endif 1270 #endif
1271 1271
1272 nand_set_controller_data(nand, nand_info); 1272 nand_set_controller_data(nand, nand_info);
1273 nand->options |= NAND_NO_SUBPAGE_WRITE; 1273 nand->options |= NAND_NO_SUBPAGE_WRITE;
1274 1274
1275 nand->cmd_ctrl = mxs_nand_cmd_ctrl; 1275 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1276 1276
1277 nand->dev_ready = mxs_nand_device_ready; 1277 nand->dev_ready = mxs_nand_device_ready;
1278 nand->select_chip = mxs_nand_select_chip; 1278 nand->select_chip = mxs_nand_select_chip;
1279 nand->block_bad = mxs_nand_block_bad; 1279 nand->block_bad = mxs_nand_block_bad;
1280 1280
1281 nand->read_byte = mxs_nand_read_byte; 1281 nand->read_byte = mxs_nand_read_byte;
1282 1282
1283 nand->read_buf = mxs_nand_read_buf; 1283 nand->read_buf = mxs_nand_read_buf;
1284 nand->write_buf = mxs_nand_write_buf; 1284 nand->write_buf = mxs_nand_write_buf;
1285 1285
1286 /* first scan to find the device and get the page size */ 1286 /* first scan to find the device and get the page size */
1287 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) 1287 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
1288 goto err2; 1288 goto err2;
1289 1289
1290 if (mxs_nand_setup_ecc(mtd)) 1290 if (mxs_nand_setup_ecc(mtd))
1291 goto err2; 1291 goto err2;
1292 1292
1293 nand->ecc.read_page = mxs_nand_ecc_read_page; 1293 nand->ecc.read_page = mxs_nand_ecc_read_page;
1294 nand->ecc.write_page = mxs_nand_ecc_write_page; 1294 nand->ecc.write_page = mxs_nand_ecc_write_page;
1295 nand->ecc.read_oob = mxs_nand_ecc_read_oob; 1295 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1296 nand->ecc.write_oob = mxs_nand_ecc_write_oob; 1296 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1297 1297
1298 nand->ecc.layout = &fake_ecc_layout; 1298 nand->ecc.layout = &fake_ecc_layout;
1299 nand->ecc.mode = NAND_ECC_HW; 1299 nand->ecc.mode = NAND_ECC_HW;
1300 nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size; 1300 nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size;
1301 nand->ecc.strength = nand_info->bch_geometry.ecc_strength; 1301 nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
1302 1302
1303 /* second phase scan */ 1303 /* second phase scan */
1304 err = nand_scan_tail(mtd); 1304 err = nand_scan_tail(mtd);
1305 if (err) 1305 if (err)
1306 goto err2; 1306 goto err2;
1307 1307
1308 err = nand_register(0, mtd); 1308 err = nand_register(0, mtd);
1309 if (err) 1309 if (err)
1310 goto err2; 1310 goto err2;
1311 1311
1312 return; 1312 return;
1313 1313
1314 err2: 1314 err2: