Eric Lee / smarc-uboot

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Commit 931747e517b19387716cd56057e4afa9e2cdfff4

Authored by Stefan Agner
Committed by Stefano Babic
1 parent 984df7add1
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

mtd: nand: mxs_nand: move register structs to driver data 

Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Showing 1 changed file with 17 additions and 17 deletions Side-by-side Diff

drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 931747e
... ... @@ -84,6 +84,9 @@
84 84 uint8_t marking_block_bad;
85 85 uint8_t raw_oob_mode;
86 86  
  87 + struct mxs_gpmi_regs *gpmi_regs;
  88 + struct mxs_bch_regs *bch_regs;
  89 +
87 90 /* Functions with altered behaviour */
88 91 int (*hooked_read_oob)(struct mtd_info *mtd,
89 92 loff_t from, struct mtd_oob_ops *ops);
90 93  
91 94  
92 95  
... ... @@ -297,16 +300,15 @@
297 300 /*
298 301 * Wait for BCH complete IRQ and clear the IRQ
299 302 */
300   -static int mxs_nand_wait_for_bch_complete(void)
  303 +static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
301 304 {
302   - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
303 305 int timeout = MXS_NAND_BCH_TIMEOUT;
304 306 int ret;
305 307  
306   - ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
  308 + ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
307 309 BCH_CTRL_COMPLETE_IRQ, timeout);
308 310  
309   - writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
  311 + writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
310 312  
311 313 return ret;
312 314 }
313 315  
... ... @@ -404,11 +406,9 @@
404 406 {
405 407 struct nand_chip *chip = mtd_to_nand(mtd);
406 408 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
407   - struct mxs_gpmi_regs *gpmi_regs =
408   - (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
409 409 uint32_t tmp;
410 410  
411   - tmp = readl(&gpmi_regs->hw_gpmi_stat);
  411 + tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
412 412 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
413 413  
414 414 return tmp & 1;
... ... @@ -705,7 +705,7 @@
705 705 goto rtn;
706 706 }
707 707  
708   - ret = mxs_nand_wait_for_bch_complete();
  708 + ret = mxs_nand_wait_for_bch_complete(nand_info);
709 709 if (ret) {
710 710 printf("MXS NAND: BCH read timeout\n");
711 711 goto rtn;
... ... @@ -813,7 +813,7 @@
813 813 goto rtn;
814 814 }
815 815  
816   - ret = mxs_nand_wait_for_bch_complete();
  816 + ret = mxs_nand_wait_for_bch_complete(nand_info);
817 817 if (ret) {
818 818 printf("MXS NAND: BCH write timeout\n");
819 819 goto rtn;
... ... @@ -1038,7 +1038,7 @@
1038 1038 struct nand_chip *nand = mtd_to_nand(mtd);
1039 1039 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1040 1040 struct bch_geometry *geo = &nand_info->bch_geometry;
1041   - struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1041 + struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
1042 1042 uint32_t tmp;
1043 1043 int ret = -ENOTSUPP;
1044 1044  
... ... @@ -1139,10 +1139,6 @@
1139 1139 */
1140 1140 int mxs_nand_init(struct mxs_nand_info *info)
1141 1141 {
1142   - struct mxs_gpmi_regs *gpmi_regs =
1143   - (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1144   - struct mxs_bch_regs *bch_regs =
1145   - (struct mxs_bch_regs *)MXS_BCH_BASE;
1146 1142 int i = 0, j, ret = 0;
1147 1143  
1148 1144 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1149 1145  
... ... @@ -1171,14 +1167,14 @@
1171 1167 }
1172 1168  
1173 1169 /* Reset the GPMI block. */
1174   - mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1175   - mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  1170 + mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
  1171 + mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
1176 1172  
1177 1173 /*
1178 1174 * Choose NAND mode, set IRQ polarity, disable write protection and
1179 1175 * select BCH ECC.
1180 1176 */
1181   - clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
  1177 + clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
1182 1178 GPMI_CTRL1_GPMI_MODE,
1183 1179 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1184 1180 GPMI_CTRL1_BCH_MODE);
... ... @@ -1210,6 +1206,8 @@
1210 1206 }
1211 1207 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1212 1208  
  1209 + nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  1210 + nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1213 1211 err = mxs_nand_alloc_buffers(nand_info);
1214 1212 if (err)
1215 1213 return err;
... ... @@ -1253,6 +1251,8 @@
1253 1251 }
1254 1252 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1255 1253  
  1254 + nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  1255 + nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1256 1256 nand = &nand_info->chip;
1257 1257 mtd = nand_to_mtd(nand);
1258 1258 err = mxs_nand_alloc_buffers(nand_info);