Commit 9444b8818f1de25dfa322cbe3a283c758a3d20e3
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CHANGELOG
1 | ====================================================================== | 1 | ====================================================================== |
2 | Changes since U-Boot 1.1.4: | 2 | Changes since U-Boot 1.1.4: |
3 | ====================================================================== | 3 | ====================================================================== |
4 | 4 | ||
5 | * Fix comments in include/ppc440.h | ||
6 | Patch by Martin Hicks, 16 Jun 2006 | ||
7 | |||
5 | * Update for CAM5200 board: | 8 | * Update for CAM5200 board: |
6 | - Map in a additional chip selects CS4 and CS5. | 9 | - Map in a additional chip selects CS4 and CS5. |
7 | - Modify the port configration, configure six UARTs and no PCI, | 10 | - Modify the port configration, configure six UARTs and no PCI, |
8 | ATA and USB. | 11 | ATA and USB. |
9 | - Add custom flash driver to handle specific byte swapping | 12 | - Add custom flash driver to handle specific byte swapping |
10 | 13 | ||
11 | * Fix TLB setup for Ocotea board | 14 | * Fix TLB setup for Ocotea board |
12 | Patch by Stefan Roese, 30 Sep 2006 | 15 | Patch by Stefan Roese, 30 Sep 2006 |
13 | 16 | ||
14 | * Fix reset problem in sequoia sdram init code | 17 | * Fix reset problem in sequoia sdram init code |
15 | Patch by Stefan Roese, 23 Sep 2006 | 18 | Patch by Stefan Roese, 23 Sep 2006 |
16 | 19 | ||
17 | * Disable autoboot abort for FO300 when silent mode is enabled | 20 | * Disable autoboot abort for FO300 when silent mode is enabled |
18 | (according to S1 switch setting). | 21 | (according to S1 switch setting). |
19 | 22 | ||
20 | * Cleanup examples binaries | 23 | * Cleanup examples binaries |
21 | 24 | ||
22 | * Add support for AMCC Rainier PPX440GRx eval board | 25 | * Add support for AMCC Rainier PPX440GRx eval board |
23 | Patch by Stefan Roese, 13 Sep 2006 | 26 | Patch by Stefan Roese, 13 Sep 2006 |
24 | 27 | ||
25 | * Add NAND environment support for PPC440EPx Sequoia NAND boot config | 28 | * Add NAND environment support for PPC440EPx Sequoia NAND boot config |
26 | Patch by Stefan Roese, 12 Sep 2006 | 29 | Patch by Stefan Roese, 12 Sep 2006 |
27 | 30 | ||
28 | * Update NAND boot documentation | 31 | * Update NAND boot documentation |
29 | Patch by Stefan Roese, 12 Sep 2006 | 32 | Patch by Stefan Roese, 12 Sep 2006 |
30 | 33 | ||
31 | * Fix alignment problem in "mtdparts" command | 34 | * Fix alignment problem in "mtdparts" command |
32 | 35 | ||
33 | * Add documentation on the latest build environment extensions to | 36 | * Add documentation on the latest build environment extensions to |
34 | the README file. | 37 | the README file. |
35 | 38 | ||
36 | * Remove dead code (i2o and dma) from cpu/mpc824x/drivers/ directory. | 39 | * Remove dead code (i2o and dma) from cpu/mpc824x/drivers/ directory. |
37 | 40 | ||
38 | * Fix LOG_DIR directory creation error. | 41 | * Fix LOG_DIR directory creation error. |
39 | Add support for automatic creation of BUILD_DIR directory. | 42 | Add support for automatic creation of BUILD_DIR directory. |
40 | 43 | ||
41 | * Fix build problem cpu/ppc4xx/ndfc.c | 44 | * Fix build problem cpu/ppc4xx/ndfc.c |
42 | Patch by Stefan Roese, 07 Sep 2006 | 45 | Patch by Stefan Roese, 07 Sep 2006 |
43 | 46 | ||
44 | * Fix build problem with CPCI440 | 47 | * Fix build problem with CPCI440 |
45 | Patch by Stefan Roese, 07 Sep 2006 | 48 | Patch by Stefan Roese, 07 Sep 2006 |
46 | 49 | ||
47 | * Change Yellowstone to use CFI write buffer | 50 | * Change Yellowstone to use CFI write buffer |
48 | Patch by Stefan Roese, 07 Sep 2006 | 51 | Patch by Stefan Roese, 07 Sep 2006 |
49 | 52 | ||
50 | * Add support for AMCC Sequoia PPC440EPx eval board | 53 | * Add support for AMCC Sequoia PPC440EPx eval board |
51 | - Add support for PPC440EPx & PPC440GRx | 54 | - Add support for PPC440EPx & PPC440GRx |
52 | - Add support for PPC440EP(x)/GR(x) NAND controller | 55 | - Add support for PPC440EP(x)/GR(x) NAND controller |
53 | in cpu/ppc4xx directory | 56 | in cpu/ppc4xx directory |
54 | - Add NAND boot functionality for Sequoia board, | 57 | - Add NAND boot functionality for Sequoia board, |
55 | please see doc/README.nand-boot-ppc440 for details | 58 | please see doc/README.nand-boot-ppc440 for details |
56 | - This Sequoia NAND image doesn't support environment | 59 | - This Sequoia NAND image doesn't support environment |
57 | in NAND for now. This will be added in a short while. | 60 | in NAND for now. This will be added in a short while. |
58 | Patch by Stefan Roese, 07 Sep 2006 | 61 | Patch by Stefan Roese, 07 Sep 2006 |
59 | 62 | ||
60 | * Fix mkimage -l bug with multifile images on 64bit platforms | 63 | * Fix mkimage -l bug with multifile images on 64bit platforms |
61 | Patch by David Updegraff, 06 Sep 2006 | 64 | Patch by David Updegraff, 06 Sep 2006 |
62 | 65 | ||
63 | * Fix build problems on sorcery board. | 66 | * Fix build problems on sorcery board. |
64 | 67 | ||
65 | * Fix coldfire build problems. | 68 | * Fix coldfire build problems. |
66 | Patch by Marian Balakowicz, 01 Sep 2006 | 69 | Patch by Marian Balakowicz, 01 Sep 2006 |
67 | 70 | ||
68 | * Add support for a saving build objects in a separate directory. | 71 | * Add support for a saving build objects in a separate directory. |
69 | Modifications are based on the Linux kernel approach and support | 72 | Modifications are based on the Linux kernel approach and support |
70 | two use cases: | 73 | two use cases: |
71 | 1) Add O= to the make command line 'make O=/tmp/build all' | 74 | 1) Add O= to the make command line 'make O=/tmp/build all' |
72 | 2) Set environement variable BUILD_DIR to point to the desired location | 75 | 2) Set environement variable BUILD_DIR to point to the desired location |
73 | 'export BUILD_DIR=/tmp/build' | 76 | 'export BUILD_DIR=/tmp/build' |
74 | 'make' | 77 | 'make' |
75 | The second approach can also be used with a MAKEALL script | 78 | The second approach can also be used with a MAKEALL script |
76 | 'export BUILD_DIR=/tmp/build' | 79 | 'export BUILD_DIR=/tmp/build' |
77 | './MAKEALL' | 80 | './MAKEALL' |
78 | Command line 'O=' setting overrides the BUILD_DIR environent variable. | 81 | Command line 'O=' setting overrides the BUILD_DIR environent variable. |
79 | When none of the above methods is used the local build is performed | 82 | When none of the above methods is used the local build is performed |
80 | and the object files are placed in the source directory. | 83 | and the object files are placed in the source directory. |
81 | 84 | ||
82 | * Remove the board/netstar/crcit binary from git repository. | 85 | * Remove the board/netstar/crcit binary from git repository. |
83 | 86 | ||
84 | * Fix tools/updater build error. | 87 | * Fix tools/updater build error. |
85 | 88 | ||
86 | * Fix tools/easylogo build error. | 89 | * Fix tools/easylogo build error. |
87 | 90 | ||
88 | * Fixed problems on PRS200 board caused by adding splash screen on MCC200 | 91 | * Fixed problems on PRS200 board caused by adding splash screen on MCC200 |
89 | 92 | ||
90 | * Extended README entry on coding style | 93 | * Extended README entry on coding style |
91 | 94 | ||
92 | * Added another example showing simple interrupt interception. | 95 | * Added another example showing simple interrupt interception. |
93 | 96 | ||
94 | * Added simple_strtoul(), getenv() and setenv() to the exported functions. | 97 | * Added simple_strtoul(), getenv() and setenv() to the exported functions. |
95 | Also bumped up ABI version to reflect this change. | 98 | Also bumped up ABI version to reflect this change. |
96 | 99 | ||
97 | * Added interrupt handling capabilities for mpc5xxx processors. | 100 | * Added interrupt handling capabilities for mpc5xxx processors. |
98 | Also added Linux like BUG() macros. | 101 | Also added Linux like BUG() macros. |
99 | 102 | ||
100 | * Coding Style cleanup. | 103 | * Coding Style cleanup. |
101 | Patch by Stefano Babic, 31 Aug 2006 | 104 | Patch by Stefano Babic, 31 Aug 2006 |
102 | 105 | ||
103 | * Add splashscreen support for MCC200 board. | 106 | * Add splashscreen support for MCC200 board. |
104 | 107 | ||
105 | * Make the serial driver framework work with CONFIG_SERIAL_MULTI | 108 | * Make the serial driver framework work with CONFIG_SERIAL_MULTI |
106 | enabled | 109 | enabled |
107 | 110 | ||
108 | * PCIe endpoint support for AMCC Yucca 440SPe board | 111 | * PCIe endpoint support for AMCC Yucca 440SPe board |
109 | Patch by Tirumala R Marri, 26 Aug 2006 | 112 | Patch by Tirumala R Marri, 26 Aug 2006 |
110 | 113 | ||
111 | * Improve DIMM detection for AMCC Yucca 440SPe board | 114 | * Improve DIMM detection for AMCC Yucca 440SPe board |
112 | Improved the memory DIMM detection for the Yucca 440SPe board for | 115 | Improved the memory DIMM detection for the Yucca 440SPe board for |
113 | the case where a memory DIMM is falsely detected as present. | 116 | the case where a memory DIMM is falsely detected as present. |
114 | This issue is seen on some AMCC Yucca 440SPe validation boards if | 117 | This issue is seen on some AMCC Yucca 440SPe validation boards if |
115 | only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is | 118 | only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is |
116 | populated and DIMM slot 1 is empty. In this case, U-Boot does | 119 | populated and DIMM slot 1 is empty. In this case, U-Boot does |
117 | not correctly detect that there is only one DIMM memory module | 120 | not correctly detect that there is only one DIMM memory module |
118 | installed and will falsely detect two DIMM memory modules are | 121 | installed and will falsely detect two DIMM memory modules are |
119 | present and therefore U-Boot will not calculate the correct amount | 122 | present and therefore U-Boot will not calculate the correct amount |
120 | of total memory and u-boot will not booting up. | 123 | of total memory and u-boot will not booting up. |
121 | Patch by Adam Graham, 24 Aug 2006 | 124 | Patch by Adam Graham, 24 Aug 2006 |
122 | 125 | ||
123 | * Fix typo. | 126 | * Fix typo. |
124 | 127 | ||
125 | * Code cleanup | 128 | * Code cleanup |
126 | 129 | ||
127 | * Update for MCC200 / PRS200 boards: | 130 | * Update for MCC200 / PRS200 boards: |
128 | - auto-adjust console device for Linux. | 131 | - auto-adjust console device for Linux. |
129 | - fix typos. | 132 | - fix typos. |
130 | 133 | ||
131 | * Add a fix for a buggy USB device on the FO300 board. | 134 | * Add a fix for a buggy USB device on the FO300 board. |
132 | 135 | ||
133 | * Updates for MCC200 / PRS200 boards: | 136 | * Updates for MCC200 / PRS200 boards: |
134 | - support for configurations with SDRAM or DDR memory, | 137 | - support for configurations with SDRAM or DDR memory, |
135 | - support for highboot and lowboot | 138 | - support for highboot and lowboot |
136 | - adjusting environment definitions | 139 | - adjusting environment definitions |
137 | 140 | ||
138 | * Add support for WTK FO300 board (TQM5200 based). | 141 | * Add support for WTK FO300 board (TQM5200 based). |
139 | 142 | ||
140 | * Fix TQM834x hang. | 143 | * Fix TQM834x hang. |
141 | 144 | ||
142 | * Update for SC520 board. | 145 | * Update for SC520 board. |
143 | Patch by David Updegraff, 02 Dec 2005 | 146 | Patch by David Updegraff, 02 Dec 2005 |
144 | 147 | ||
145 | * Fixed common.h spelling error. | 148 | * Fixed common.h spelling error. |
146 | Patch by Cory Tusar, 30 Nov 2005 | 149 | Patch by Cory Tusar, 30 Nov 2005 |
147 | 150 | ||
148 | * Fix typo. | 151 | * Fix typo. |
149 | Patch by Andreas Engel, 28 Nov 2005 | 152 | Patch by Andreas Engel, 28 Nov 2005 |
150 | 153 | ||
151 | * Fix fatload command on FAT32 formatted partitions. | 154 | * Fix fatload command on FAT32 formatted partitions. |
152 | Patch by Joachim Jaeger, 18 Nov 2005 | 155 | Patch by Joachim Jaeger, 18 Nov 2005 |
153 | 156 | ||
154 | * Fix drivers/dm9000.c when configured in 32 bit mode. | 157 | * Fix drivers/dm9000.c when configured in 32 bit mode. |
155 | Patch by Eric Benard, 17 Nov 2005 | 158 | Patch by Eric Benard, 17 Nov 2005 |
156 | 159 | ||
157 | * Cleanup debug code for yucca board. | 160 | * Cleanup debug code for yucca board. |
158 | 161 | ||
159 | * MCC200: restrict addressable flash space to 32 MB | 162 | * MCC200: restrict addressable flash space to 32 MB |
160 | 163 | ||
161 | * Add debug console on COM12 for MCC200 board | 164 | * Add debug console on COM12 for MCC200 board |
162 | 165 | ||
163 | * Fix control-c handing in CONFIG_CMDLINE_EDITING | 166 | * Fix control-c handing in CONFIG_CMDLINE_EDITING |
164 | Properly pass break code back from readline. | 167 | Properly pass break code back from readline. |
165 | Patch by Roger Blofeld, 31 Jul 2006 | 168 | Patch by Roger Blofeld, 31 Jul 2006 |
166 | 169 | ||
167 | * Add commandline history support to all AMCC eval boards | 170 | * Add commandline history support to all AMCC eval boards |
168 | Patch by Stefan Roese, 07 Aug 2006 | 171 | Patch by Stefan Roese, 07 Aug 2006 |
169 | 172 | ||
170 | * Add Macronix MXLV320T flash support for AMCC Bamboo | 173 | * Add Macronix MXLV320T flash support for AMCC Bamboo |
171 | Patch by Stefan Roese, 07 Aug 2006 | 174 | Patch by Stefan Roese, 07 Aug 2006 |
172 | 175 | ||
173 | * Change "mii info" to not print an error upon missing PHY at address | 176 | * Change "mii info" to not print an error upon missing PHY at address |
174 | Patch by Stefan Roese, 07 Aug 2006 | 177 | Patch by Stefan Roese, 07 Aug 2006 |
175 | 178 | ||
176 | * Fix PCI-Express on PPC440SPe rev. A. | 179 | * Fix PCI-Express on PPC440SPe rev. A. |
177 | 180 | ||
178 | * Fix preboot message on TQM85xx after switching to hush parser. | 181 | * Fix preboot message on TQM85xx after switching to hush parser. |
179 | 182 | ||
180 | * Adapt TQM85xx ramdisk address to Linux kernel memory map | 183 | * Adapt TQM85xx ramdisk address to Linux kernel memory map |
181 | 184 | ||
182 | * Add initial support for PCI-Express on PPC440SPe (Yucca board). | 185 | * Add initial support for PCI-Express on PPC440SPe (Yucca board). |
183 | 186 | ||
184 | * Fix compiler warning for TRAB board. | 187 | * Fix compiler warning for TRAB board. |
185 | Patch by Martin Krause, 07 Aug 2006 | 188 | Patch by Martin Krause, 07 Aug 2006 |
186 | 189 | ||
187 | * Prevent USB commands from working when USB is stopped. | 190 | * Prevent USB commands from working when USB is stopped. |
188 | 191 | ||
189 | * Add rudimentary handling of alternate settings of USB interfaces. | 192 | * Add rudimentary handling of alternate settings of USB interfaces. |
190 | This is in order to fix issues with some USB sticks timing out | 193 | This is in order to fix issues with some USB sticks timing out |
191 | during initialization. Some code readability improvements. | 194 | during initialization. Some code readability improvements. |
192 | 195 | ||
193 | * PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance | 196 | * PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance |
194 | AMCC suggested to set the PMU bit to 0 for best performace on | 197 | AMCC suggested to set the PMU bit to 0 for best performace on |
195 | the PPC440 DDR controller. | 198 | the PPC440 DDR controller. |
196 | Please see doc/README.440-DDR-performance for details. | 199 | Please see doc/README.440-DDR-performance for details. |
197 | Patch by Stefan Roese, 28 Jul 2006 | 200 | Patch by Stefan Roese, 28 Jul 2006 |
198 | 201 | ||
199 | * AMCC bamboo (440EP) U-Boot image reduced to 384kbyte | 202 | * AMCC bamboo (440EP) U-Boot image reduced to 384kbyte |
200 | Please see doc/README.bamboo for details. | 203 | Please see doc/README.bamboo for details. |
201 | Patch by Stefan Roese, 27 Jul 2006 | 204 | Patch by Stefan Roese, 27 Jul 2006 |
202 | 205 | ||
203 | * Fix CONFIG_CMDLINE_EDITING implementation | 206 | * Fix CONFIG_CMDLINE_EDITING implementation |
204 | Patch by Stefan Roese, 27 Jul 2006 | 207 | Patch by Stefan Roese, 27 Jul 2006 |
205 | 208 | ||
206 | * Fix preboot message on TQM5200 after switching to hush parser. | 209 | * Fix preboot message on TQM5200 after switching to hush parser. |
207 | 210 | ||
208 | * MCC200: set default configuration to low_boot DDR, | 211 | * MCC200: set default configuration to low_boot DDR, |
209 | and support for configurable options high_boot and/or SDRAM. | 212 | and support for configurable options high_boot and/or SDRAM. |
210 | 213 | ||
211 | * Add support for 256 MB SDRAM on CPU87 | 214 | * Add support for 256 MB SDRAM on CPU87 |
212 | Patch by Josef Wagner, 25 Nov 2005 | 215 | Patch by Josef Wagner, 25 Nov 2005 |
213 | 216 | ||
214 | * Add configuration for cam5200 board (based on TQM5200S). | 217 | * Add configuration for cam5200 board (based on TQM5200S). |
215 | 218 | ||
216 | * More code cleanup | 219 | * More code cleanup |
217 | 220 | ||
218 | * Disabled kvme080 board in MAKEALL because of build problems. | 221 | * Disabled kvme080 board in MAKEALL because of build problems. |
219 | 222 | ||
220 | * Code cleanup | 223 | * Code cleanup |
221 | 224 | ||
222 | * Update NetStar board | 225 | * Update NetStar board |
223 | Patch by Ladislav Michl, 03 Nov 2005 | 226 | Patch by Ladislav Michl, 03 Nov 2005 |
224 | 227 | ||
225 | * Make code better readable. | 228 | * Make code better readable. |
226 | Patch by Ladislav Michl, 14 Sep 2005 | 229 | Patch by Ladislav Michl, 14 Sep 2005 |
227 | 230 | ||
228 | * Enable initrd ATAG for xm250 board. | 231 | * Enable initrd ATAG for xm250 board. |
229 | Patch by Josef Wagner, 05 Sep 2005 | 232 | Patch by Josef Wagner, 05 Sep 2005 |
230 | 233 | ||
231 | * Add readline cmdline-editing extension | 234 | * Add readline cmdline-editing extension |
232 | Patch by JinHua Luo, 01 Sep 2005 | 235 | Patch by JinHua Luo, 01 Sep 2005 |
233 | 236 | ||
234 | * Add support for friendly-arm SBC-2410X board | 237 | * Add support for friendly-arm SBC-2410X board |
235 | Patch by JinHua Luo, 01 Sep 2005 | 238 | Patch by JinHua Luo, 01 Sep 2005 |
236 | 239 | ||
237 | * Fix multi-part image support on i386 platform. | 240 | * Fix multi-part image support on i386 platform. |
238 | Patch by David Updegraff, 19 Aug 2005 | 241 | Patch by David Updegraff, 19 Aug 2005 |
239 | 242 | ||
240 | * Add support for KVME080 board | 243 | * Add support for KVME080 board |
241 | Patch by Sangmoon Kim, 18 Aug 2005 | 244 | Patch by Sangmoon Kim, 18 Aug 2005 |
242 | 245 | ||
243 | * Fix MIPS LE build problem | 246 | * Fix MIPS LE build problem |
244 | Patch by Matej Kupljen, 10 Aug 2005 | 247 | Patch by Matej Kupljen, 10 Aug 2005 |
245 | 248 | ||
246 | * Check argument count in "mii" command. | 249 | * Check argument count in "mii" command. |
247 | Problem pointed out by Andrew Dyer, 13 Jun 2005 | 250 | Problem pointed out by Andrew Dyer, 13 Jun 2005 |
248 | 251 | ||
249 | * Cleanup TQM5200 board configurations: | 252 | * Cleanup TQM5200 board configurations: |
250 | - make highboot configurations use environment at high end, too, | 253 | - make highboot configurations use environment at high end, too, |
251 | to avoid flash fragmentation | 254 | to avoid flash fragmentation |
252 | - always use redundand environment | 255 | - always use redundand environment |
253 | - don't enable video code for modules without graphics controller | 256 | - don't enable video code for modules without graphics controller |
254 | - provide useful (though different) mtdparts settings | 257 | - provide useful (though different) mtdparts settings |
255 | - get rid of CONFIG_CS_AUTOCONF which was always set anyway | 258 | - get rid of CONFIG_CS_AUTOCONF which was always set anyway |
256 | 259 | ||
257 | * Extend mkconfig tool to print more useful target name | 260 | * Extend mkconfig tool to print more useful target name |
258 | 261 | ||
259 | * Add support for high-boot on TQM5200 and TQM5200S boards. | 262 | * Add support for high-boot on TQM5200 and TQM5200S boards. |
260 | Hint: the CPLD on the TQM5200 must be programmed with a software | 263 | Hint: the CPLD on the TQM5200 must be programmed with a software |
261 | version supporting the high boot option! The new TQM5200S is | 264 | version supporting the high boot option! The new TQM5200S is |
262 | already supporting this option. On the TQM5200 this option will be | 265 | already supporting this option. On the TQM5200 this option will be |
263 | supported in configurations with MPC5200 rev B processors. | 266 | supported in configurations with MPC5200 rev B processors. |
264 | To actually "high boot", set jumper X30 on the STK52xx. | 267 | To actually "high boot", set jumper X30 on the STK52xx. |
265 | Patch by Martin Krause, 12 Jul 2006 | 268 | Patch by Martin Krause, 12 Jul 2006 |
266 | 269 | ||
267 | * Add support for new TQM5200 revisions | 270 | * Add support for new TQM5200 revisions |
268 | - Support for TQM5200S (short version without graphic controller) | 271 | - Support for TQM5200S (short version without graphic controller) |
269 | - Support for modules with 'N' type S29GL128N Spansion flashes | 272 | - Support for modules with 'N' type S29GL128N Spansion flashes |
270 | (requires changes to flash layout) | 273 | (requires changes to flash layout) |
271 | - Support for MPC5200B cpu (mostly support for second SDRAM bank) | 274 | - Support for MPC5200B cpu (mostly support for second SDRAM bank) |
272 | Patch by Martin Krause, 07 Jul 2006 | 275 | Patch by Martin Krause, 07 Jul 2006 |
273 | 276 | ||
274 | * Fix support for PS/2 keyboard on TQM85xx boards | 277 | * Fix support for PS/2 keyboard on TQM85xx boards |
275 | The PS/2 keyobard driver for the TQM85xx modules only supports the | 278 | The PS/2 keyobard driver for the TQM85xx modules only supports the |
276 | internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't | 279 | internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't |
277 | include a DUART, the TQM8560 modules can't be used with the PS/2 | 280 | include a DUART, the TQM8560 modules can't be used with the PS/2 |
278 | keyboard controller on the STK85xx board. | 281 | keyboard controller on the STK85xx board. |
279 | The PS/2 keyboard driver should work with the modules TQM8540, | 282 | The PS/2 keyboard driver should work with the modules TQM8540, |
280 | TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet. | 283 | TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet. |
281 | Make sure the PS/2 controller on the STK85xx is programmed. Jumper | 284 | Make sure the PS/2 controller on the STK85xx is programmed. Jumper |
282 | settings: X66 1-2, 9-10; X61 2-3 | 285 | settings: X66 1-2, 9-10; X61 2-3 |
283 | Patch by Martin Krause, 21 Jun 2006 | 286 | Patch by Martin Krause, 21 Jun 2006 |
284 | 287 | ||
285 | * Adjust RTC century handling on STK52xx board to match Linux driver. | 288 | * Adjust RTC century handling on STK52xx board to match Linux driver. |
286 | Patch by Martin Krause, 12 Jun 2006 | 289 | Patch by Martin Krause, 12 Jun 2006 |
287 | 290 | ||
288 | * Adjust filenames for USB update images on TRAB board. | 291 | * Adjust filenames for USB update images on TRAB board. |
289 | During an automatic update via USB stick, U-Boot searches for | 292 | During an automatic update via USB stick, U-Boot searches for |
290 | images with the name "firmware.img" and "kernel.img". This names | 293 | images with the name "firmware.img" and "kernel.img". This names |
291 | are now changed to "firmw_01.img" and "kernl_01.img". This is done, | 294 | are now changed to "firmw_01.img" and "kernl_01.img". This is done, |
292 | to prevent updates of new boards (with the new macronics "c" step | 295 | to prevent updates of new boards (with the new macronics "c" step |
293 | flashes) with old, incompatible firmware or kernel versions. | 296 | flashes) with old, incompatible firmware or kernel versions. |
294 | Patch by Martin Krause, 21 Jun 2006 | 297 | Patch by Martin Krause, 21 Jun 2006 |
295 | 298 | ||
296 | * Bugfix in VFD routine on TRAB board. | 299 | * Bugfix in VFD routine on TRAB board. |
297 | Make sure upper lext pixel can be set to blue, too | 300 | Make sure upper lext pixel can be set to blue, too |
298 | (so far only red was possible). | 301 | (so far only red was possible). |
299 | Patch by Martin Krause, 15 Feb 2006 | 302 | Patch by Martin Krause, 15 Feb 2006 |
300 | 303 | ||
301 | * Enable buffered flash writes for TB5200 board. | 304 | * Enable buffered flash writes for TB5200 board. |
302 | 305 | ||
303 | * Fix some bugs in TRAB board flash driver. | 306 | * Fix some bugs in TRAB board flash driver. |
304 | - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds | 307 | - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds |
305 | - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT | 308 | - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT |
306 | - remove "Unlock Bypass" mode, because macronix flashes do not support | 309 | - remove "Unlock Bypass" mode, because macronix flashes do not support |
307 | this mode officially | 310 | this mode officially |
308 | - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified | 311 | - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified |
309 | for Intel compatible flashes, not for AMD compatible. | 312 | for Intel compatible flashes, not for AMD compatible. |
310 | Patch by Martin Krause, 15 Feb 2006 | 313 | Patch by Martin Krause, 15 Feb 2006 |
311 | 314 | ||
312 | * Add additional error messages to flash driver on TRAB board | 315 | * Add additional error messages to flash driver on TRAB board |
313 | (for erase errors and timeout errors) | 316 | (for erase errors and timeout errors) |
314 | Patch by Martin Krause, 14 Feb 2006 | 317 | Patch by Martin Krause, 14 Feb 2006 |
315 | 318 | ||
316 | * Add support for TB5200 board | 319 | * Add support for TB5200 board |
317 | The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module | 320 | The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module |
318 | integrated in a little aluminium case. | 321 | integrated in a little aluminium case. |
319 | Patch by Martin Krause, 8 Jun 2006 | 322 | Patch by Martin Krause, 8 Jun 2006 |
320 | 323 | ||
321 | * Enable buffered flash writes for TQM5200 board. | 324 | * Enable buffered flash writes for TQM5200 board. |
322 | 325 | ||
323 | * Fix problems with SanDisk Corporation Cruzer Micro USB memory stick. | 326 | * Fix problems with SanDisk Corporation Cruzer Micro USB memory stick. |
324 | 327 | ||
325 | * Add support for TQM885D board. | 328 | * Add support for TQM885D board. |
326 | Patch by Martin Krause, 20 Mar 2006 | 329 | Patch by Martin Krause, 20 Mar 2006 |
327 | 330 | ||
328 | * Fix FEC initialisation: All MII configuration is done via FEC1 | 331 | * Fix FEC initialisation: All MII configuration is done via FEC1 |
329 | registers, but MII_SPEED was configured according to FEC used. So | 332 | registers, but MII_SPEED was configured according to FEC used. So |
330 | if only FEC2 was used, this caused the real MII_SPEED register in | 333 | if only FEC2 was used, this caused the real MII_SPEED register in |
331 | FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages. | 334 | FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages. |
332 | Fix: always configure MII_SPEED on FEC1 only. | 335 | Fix: always configure MII_SPEED on FEC1 only. |
333 | Patch by Markus Klotzbuecher, 12 Jul 2006 | 336 | Patch by Markus Klotzbuecher, 12 Jul 2006 |
334 | 337 | ||
335 | * Add support for SPC1920 board. | 338 | * Add support for SPC1920 board. |
336 | Patch by Markus Klotzbuecher, 12 Jul 2006 | 339 | Patch by Markus Klotzbuecher, 12 Jul 2006 |
337 | 340 | ||
338 | * MCC200 board: support console on any one of the Quad UART ports. | 341 | * MCC200 board: support console on any one of the Quad UART ports. |
339 | 342 | ||
340 | * Fix error in flash protection calculation on MCC200 board. | 343 | * Fix error in flash protection calculation on MCC200 board. |
341 | 344 | ||
342 | * Major PCMCIA Cleanup to make code better readable and maintainable. | 345 | * Major PCMCIA Cleanup to make code better readable and maintainable. |
343 | Notes: | 346 | Notes: |
344 | - Board-dependend code for RPXLITE and RPXCLASSIC-based boards | 347 | - Board-dependend code for RPXLITE and RPXCLASSIC-based boards |
345 | placed to the drivers/rpx_pmcia.c file to avoid duplication. | 348 | placed to the drivers/rpx_pmcia.c file to avoid duplication. |
346 | Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c). | 349 | Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c). |
347 | - drivers/i82365.c has been split into two parts located at | 350 | - drivers/i82365.c has been split into two parts located at |
348 | board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are | 351 | board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are |
349 | the only boards using CONFIG_82365). | 352 | the only boards using CONFIG_82365). |
350 | - Changes were tested for clean build and *very* *few* boards. | 353 | - Changes were tested for clean build and *very* *few* boards. |
351 | 354 | ||
352 | * Fix timer problems on AMCC yucca board. | 355 | * Fix timer problems on AMCC yucca board. |
353 | Set Timer Clock Select to use CPU clock as a timer input source. | 356 | Set Timer Clock Select to use CPU clock as a timer input source. |
354 | 357 | ||
355 | * Bring yucca config more in line with other AMCC boards. | 358 | * Bring yucca config more in line with other AMCC boards. |
356 | 359 | ||
357 | * Add AMCC bamboo board to MAKEALL build script. | 360 | * Add AMCC bamboo board to MAKEALL build script. |
358 | 361 | ||
359 | * Fix AMCC bamboo eval board compilation errors. | 362 | * Fix AMCC bamboo eval board compilation errors. |
360 | 363 | ||
361 | * Add system memory to the PCI region list for AMCC PPC44x CPUs. | 364 | * Add system memory to the PCI region list for AMCC PPC44x CPUs. |
362 | Enabled it for Yucca board. | 365 | Enabled it for Yucca board. |
363 | 366 | ||
364 | * Cleanup config file and bootup output for Yucca board. | 367 | * Cleanup config file and bootup output for Yucca board. |
365 | 368 | ||
366 | * Fix CONFIG_440_GX define usage. | 369 | * Fix CONFIG_440_GX define usage. |
367 | 370 | ||
368 | * Remove autogenerated bmp_logo.h file. | 371 | * Remove autogenerated bmp_logo.h file. |
369 | 372 | ||
370 | * Add support for AMCC 440SPe CPU based eval board (Yucca). | 373 | * Add support for AMCC 440SPe CPU based eval board (Yucca). |
371 | 374 | ||
372 | * Call serial_initialize() before first debug() is used. | 375 | * Call serial_initialize() before first debug() is used. |
373 | 376 | ||
374 | * Cleanup trab board for GCC-4.x | 377 | * Cleanup trab board for GCC-4.x |
375 | 378 | ||
376 | * VoiceBlue update: use new MTD flash partitioning methods, use more | 379 | * VoiceBlue update: use new MTD flash partitioning methods, use more |
377 | reasonable TEXT_BASE, update default environment and enable keyed | 380 | reasonable TEXT_BASE, update default environment and enable keyed |
378 | autoboot. | 381 | autoboot. |
379 | Patch by Ladislav Michl, 16. Aug 2005 | 382 | Patch by Ladislav Michl, 16. Aug 2005 |
380 | 383 | ||
381 | * Add forgotten changes for the PLEB 2 Board. | 384 | * Add forgotten changes for the PLEB 2 Board. |
382 | Patch by David Snowdon, 13. Aug 2005 | 385 | Patch by David Snowdon, 13. Aug 2005 |
383 | 386 | ||
384 | * Add support for wrPPMC7xx/74xx boards | 387 | * Add support for wrPPMC7xx/74xx boards |
385 | Patch by Richard Danter, 12 Aug 2005 | 388 | Patch by Richard Danter, 12 Aug 2005 |
386 | 389 | ||
387 | * Add support for gth2 board | 390 | * Add support for gth2 board |
388 | Patch by Thomas Lange, Aug 11 2005 | 391 | Patch by Thomas Lange, Aug 11 2005 |
389 | 392 | ||
390 | * Add support for CONFIG_SERIAL_MULTI on MPC5xxx | 393 | * Add support for CONFIG_SERIAL_MULTI on MPC5xxx |
391 | Patch by Martin Krause, 8 Jun 2006 | 394 | Patch by Martin Krause, 8 Jun 2006 |
392 | 395 | ||
393 | This patch supports two serial consoles on boards with | 396 | This patch supports two serial consoles on boards with |
394 | a MPC5xxx CPU. The console can be switched at runtime | 397 | a MPC5xxx CPU. The console can be switched at runtime |
395 | by setting stdin, stdout and stderr to the desired serial | 398 | by setting stdin, stdout and stderr to the desired serial |
396 | interface (serial0 or serial1). The PSCs to be used as | 399 | interface (serial0 or serial1). The PSCs to be used as |
397 | console port are definded by CONFIG_PSC_CONSOLE | 400 | console port are definded by CONFIG_PSC_CONSOLE |
398 | and CONFIG_PSC_CONSOLE2. | 401 | and CONFIG_PSC_CONSOLE2. |
399 | See README.serial_multi for details. | 402 | See README.serial_multi for details. |
400 | 403 | ||
401 | * Bugfix in I2C initialisation on S3C2400. | 404 | * Bugfix in I2C initialisation on S3C2400. |
402 | If the bus is blocked because of a previously interrupted | 405 | If the bus is blocked because of a previously interrupted |
403 | transfer, up to eleven clocks are generated on the I2CSCL | 406 | transfer, up to eleven clocks are generated on the I2CSCL |
404 | line to complete the transfer and to free the bus. | 407 | line to complete the transfer and to free the bus. |
405 | With this fix pin I2CSCL (PG6) is really configured as GPIO | 408 | With this fix pin I2CSCL (PG6) is really configured as GPIO |
406 | so the clock pulses are really generated. | 409 | so the clock pulses are really generated. |
407 | Patch by Martin Krause, 04 Apr 2006 | 410 | Patch by Martin Krause, 04 Apr 2006 |
408 | 411 | ||
409 | * Fix DDR6 errata on TQM834x boards | 412 | * Fix DDR6 errata on TQM834x boards |
410 | Patch by Thomas Waehner, 07 Mar 2006 | 413 | Patch by Thomas Waehner, 07 Mar 2006 |
411 | 414 | ||
412 | * Remove obsolete flash driver board/tqm5200/flash.c | 415 | * Remove obsolete flash driver board/tqm5200/flash.c |
413 | Patch by Martin Krause, 11 Jan 2006 | 416 | Patch by Martin Krause, 11 Jan 2006 |
414 | 417 | ||
415 | * Update configuration for CMC-PU2 board | 418 | * Update configuration for CMC-PU2 board |
416 | Patch by Martin Krause, 17 Nov 2005 | 419 | Patch by Martin Krause, 17 Nov 2005 |
417 | 420 | ||
418 | * Add support for PS/2 keyboard on TQM85xx board | 421 | * Add support for PS/2 keyboard on TQM85xx board |
419 | Patch by Martin Krause, 07 Nov 2005 | 422 | Patch by Martin Krause, 07 Nov 2005 |
420 | 423 | ||
421 | Tested on a STK85XX baseboard. Make sure the PS/2 controller | 424 | Tested on a STK85XX baseboard. Make sure the PS/2 controller |
422 | has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 | 425 | has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 |
423 | 426 | ||
424 | * Fix TRAB channel switching delay for trab_fkt.bin standalone applikation | 427 | * Fix TRAB channel switching delay for trab_fkt.bin standalone applikation |
425 | In tsc2000_read_channel() the delay after setting the multiplexer | 428 | In tsc2000_read_channel() the delay after setting the multiplexer |
426 | to a temperature channel is increased from 1,5 ms to 10 ms. This | 429 | to a temperature channel is increased from 1,5 ms to 10 ms. This |
427 | is to allow the multiplexer inputs to stabilize after huge steps | 430 | is to allow the multiplexer inputs to stabilize after huge steps |
428 | of the input signal level. | 431 | of the input signal level. |
429 | Patch by Martin Krause, 08 Nov 2005 | 432 | Patch by Martin Krause, 08 Nov 2005 |
430 | 433 | ||
431 | * Adjust TQM5200 make targets | 434 | * Adjust TQM5200 make targets |
432 | Make the automatic CS configuration the default. | 435 | Make the automatic CS configuration the default. |
433 | The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB | 436 | The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB |
434 | and CONFIG_TQM5200_AC are removed. | 437 | and CONFIG_TQM5200_AC are removed. |
435 | "TQM5200_config" is now the default for STK52XX.200 base boards. | 438 | "TQM5200_config" is now the default for STK52XX.200 base boards. |
436 | On a STK52XX.100 base board "TQM5200_STK100_config" must be used. | 439 | On a STK52XX.100 base board "TQM5200_STK100_config" must be used. |
437 | Patch by Martin Krause, 07 Nov 2005 | 440 | Patch by Martin Krause, 07 Nov 2005 |
438 | 441 | ||
439 | * Fix setting of environment variable "ver" on trab board | 442 | * Fix setting of environment variable "ver" on trab board |
440 | The environment variable "ver" is now set before | 443 | The environment variable "ver" is now set before |
441 | do_auto_update() is called, so that "ver" can be used | 444 | do_auto_update() is called, so that "ver" can be used |
442 | in USB update scripts. | 445 | in USB update scripts. |
443 | Patch by Martin Krause, 27 Oct 2005 | 446 | Patch by Martin Krause, 27 Oct 2005 |
444 | 447 | ||
445 | * Fix wrong usage of udelay() in led_blink() on trab board | 448 | * Fix wrong usage of udelay() in led_blink() on trab board |
446 | Patch by Martin Krause, 27 Oct 2005 | 449 | Patch by Martin Krause, 27 Oct 2005 |
447 | 450 | ||
448 | * Fix udelay bug in vfd.c for trab board | 451 | * Fix udelay bug in vfd.c for trab board |
449 | Patch by Martin Krause, 27 Oct 2005 | 452 | Patch by Martin Krause, 27 Oct 2005 |
450 | 453 | ||
451 | * Disable JFFS2 support for trab board | 454 | * Disable JFFS2 support for trab board |
452 | Patch by Martin Krause, 27 Oct 2005 | 455 | Patch by Martin Krause, 27 Oct 2005 |
453 | 456 | ||
454 | * Change mtdparts definition on trab board to match current flash map | 457 | * Change mtdparts definition on trab board to match current flash map |
455 | Patch by Martin Krause, 27 Oct 2005 | 458 | Patch by Martin Krause, 27 Oct 2005 |
456 | 459 | ||
457 | * Fix memory init problems on MCC200 board | 460 | * Fix memory init problems on MCC200 board |
458 | 461 | ||
459 | * Fix IxEthDB.h to compile again | 462 | * Fix IxEthDB.h to compile again |
460 | Patch by Stefan Roese, 14 Jun 2006 | 463 | Patch by Stefan Roese, 14 Jun 2006 |
461 | 464 | ||
462 | * Minor cleanup for PCS440EP board | 465 | * Minor cleanup for PCS440EP board |
463 | Patch by Stefan Roese, 13 Jun 2006 | 466 | Patch by Stefan Roese, 13 Jun 2006 |
464 | 467 | ||
465 | * Add MCF5282 support (without preloader) | 468 | * Add MCF5282 support (without preloader) |
466 | relocate ichache_State to ram | 469 | relocate ichache_State to ram |
467 | u-boot can run from internal flash | 470 | u-boot can run from internal flash |
468 | Add EB+MCF-EV123 board support. | 471 | Add EB+MCF-EV123 board support. |
469 | Add m68k Boards to MAKEALL | 472 | Add m68k Boards to MAKEALL |
470 | Patch from Jens Scharsig, 08 Aug 2005 | 473 | Patch from Jens Scharsig, 08 Aug 2005 |
471 | 474 | ||
472 | * Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards | 475 | * Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards |
473 | Patch by Scott McNutt, 08 Jun 2006 | 476 | Patch by Scott McNutt, 08 Jun 2006 |
474 | 477 | ||
475 | * Nios II - Add EPCS Controller bootrom work-around | 478 | * Nios II - Add EPCS Controller bootrom work-around |
476 | -When booting from an epcs controller, the epcs bootrom may leave the | 479 | -When booting from an epcs controller, the epcs bootrom may leave the |
477 | slave select in an asserted state causing soft reset hang. This | 480 | slave select in an asserted state causing soft reset hang. This |
478 | patch ensures slave select is negated at reset. | 481 | patch ensures slave select is negated at reset. |
479 | Patch by Scott McNutt, 08 Jun 2006 | 482 | Patch by Scott McNutt, 08 Jun 2006 |
480 | 483 | ||
481 | * Update PK1C20 board | 484 | * Update PK1C20 board |
482 | -Update base addresses for standard configuration | 485 | -Update base addresses for standard configuration |
483 | -Eliminate use of CACHE_BYPASS in board code | 486 | -Eliminate use of CACHE_BYPASS in board code |
484 | Patch by Scott McNutt, 08 Jun 2006 | 487 | Patch by Scott McNutt, 08 Jun 2006 |
485 | 488 | ||
486 | * Nios II - Fix I/O Macros and mini-app stubs | 489 | * Nios II - Fix I/O Macros and mini-app stubs |
487 | -Fix asm/io.h macros | 490 | -Fix asm/io.h macros |
488 | -Eliminate use of CACHE_BYPASS in cpu code | 491 | -Eliminate use of CACHE_BYPASS in cpu code |
489 | -Eliminate assembler warnings | 492 | -Eliminate assembler warnings |
490 | -Fix mini-app stubs and force no small data | 493 | -Fix mini-app stubs and force no small data |
491 | Patch by Scott McNutt, 08 Jun 2006 | 494 | Patch by Scott McNutt, 08 Jun 2006 |
492 | 495 | ||
493 | * Fix U-Boot environment sector protection on MCC200 board | 496 | * Fix U-Boot environment sector protection on MCC200 board |
494 | 497 | ||
495 | * Minor cleanup for PCS440EP board | 498 | * Minor cleanup for PCS440EP board |
496 | 499 | ||
497 | * Update PCS440EP port to fit into one flash device (incl. environment) | 500 | * Update PCS440EP port to fit into one flash device (incl. environment) |
498 | Patch by Stefan Roese, 06 Jun 2006 | 501 | Patch by Stefan Roese, 06 Jun 2006 |
499 | 502 | ||
500 | * Add support for PCS440EP board | 503 | * Add support for PCS440EP board |
501 | Patch by Stefan Roese, 02 Jun 2006 | 504 | Patch by Stefan Roese, 02 Jun 2006 |
502 | 505 | ||
503 | * Fix examples/Makefile; some build targets were lost | 506 | * Fix examples/Makefile; some build targets were lost |
504 | 507 | ||
505 | * Fix watchdog handling in CFI flash driver | 508 | * Fix watchdog handling in CFI flash driver |
506 | Just use udelay() when waiting for status changes which will | 509 | Just use udelay() when waiting for status changes which will |
507 | implicitely trigger the watchdog. | 510 | implicitely trigger the watchdog. |
508 | 511 | ||
509 | * Fix PCI to memory window size problems on PM82x boards | 512 | * Fix PCI to memory window size problems on PM82x boards |
510 | We use the "automatic" mode that was used for the MPC8266ADS and | 513 | We use the "automatic" mode that was used for the MPC8266ADS and |
511 | MPC8272 boards. Eventually this should be used on all boards?] | 514 | MPC8272 boards. Eventually this should be used on all boards?] |
512 | Patch by Wolfgang Grandegger, 17 Jan 2006 | 515 | Patch by Wolfgang Grandegger, 17 Jan 2006 |
513 | 516 | ||
514 | * Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone | 517 | * Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone |
515 | Patch by Stefan Roese, 29 May 2006 | 518 | Patch by Stefan Roese, 29 May 2006 |
516 | 519 | ||
517 | * Update Intel IXP4xx support | 520 | * Update Intel IXP4xx support |
518 | - Add IXP4xx NPE ethernet MAC support | 521 | - Add IXP4xx NPE ethernet MAC support |
519 | - Add support for Intel IXDPG425 board | 522 | - Add support for Intel IXDPG425 board |
520 | - Add support for Prodrive PDNB3 board | 523 | - Add support for Prodrive PDNB3 board |
521 | - Add IRQ support | 524 | - Add IRQ support |
522 | Patch by Stefan Roese, 23 May 2006 | 525 | Patch by Stefan Roese, 23 May 2006 |
523 | 526 | ||
524 | * Fix problem in PVR detection for 440GR | 527 | * Fix problem in PVR detection for 440GR |
525 | Patch by Stefan Roese, 18 May 2006 | 528 | Patch by Stefan Roese, 18 May 2006 |
526 | 529 | ||
527 | * Fix gcc 3.4.x AFLAGS setting for m68k platform. | 530 | * Fix gcc 3.4.x AFLAGS setting for m68k platform. |
528 | 531 | ||
529 | * Enable autoboot for M5271EVB board. | 532 | * Enable autoboot for M5271EVB board. |
530 | 533 | ||
531 | * Changed default ramdisk addr in yosemite/yellowstone ports | 534 | * Changed default ramdisk addr in yosemite/yellowstone ports |
532 | Patch by Stefan Roese, 15 May 2006 | 535 | Patch by Stefan Roese, 15 May 2006 |
533 | 536 | ||
534 | * Fix PCMCIA support on virtlab2 | 537 | * Fix PCMCIA support on virtlab2 |
535 | 538 | ||
536 | * Add support for VirtLab2 board | 539 | * Add support for VirtLab2 board |
537 | (needed because of differences in the PCMCIA hardware). | 540 | (needed because of differences in the PCMCIA hardware). |
538 | 541 | ||
539 | * Minor cleanup. | 542 | * Minor cleanup. |
540 | 543 | ||
541 | * Update yosemite configuration to enable flash write buffer support | 544 | * Update yosemite configuration to enable flash write buffer support |
542 | Patch by Stefan Roese, 10 May 2006 | 545 | Patch by Stefan Roese, 10 May 2006 |
543 | 546 | ||
544 | * Fix compile warnings in common/xyzModem.c | 547 | * Fix compile warnings in common/xyzModem.c |
545 | Patch by Stefan Roese, 10 May 2006 | 548 | Patch by Stefan Roese, 10 May 2006 |
546 | 549 | ||
547 | * Add support for AMCC 440EP Rev C and 440GR Rev B | 550 | * Add support for AMCC 440EP Rev C and 440GR Rev B |
548 | Patch by John Otken, 08 May 2006 | 551 | Patch by John Otken, 08 May 2006 |
549 | 552 | ||
550 | * OMAP 5912/OSK: update EMIFS CS1 timings: | 553 | * OMAP 5912/OSK: update EMIFS CS1 timings: |
551 | Problems have been seen in the linux kernel's smc91x network driver | 554 | Problems have been seen in the linux kernel's smc91x network driver |
552 | due to improper bus timings. The latest 2.6 OMAP kernels currently | 555 | due to improper bus timings. The latest 2.6 OMAP kernels currently |
553 | have a workaround, but this fix belongs in u-boot. | 556 | have a workaround, but this fix belongs in u-boot. |
554 | Patch by Kevin Hilman, 13 Oct 2005 | 557 | Patch by Kevin Hilman, 13 Oct 2005 |
555 | 558 | ||
556 | * Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports | 559 | * Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports |
557 | Patch by Hiroki Kaminaga, 11 Mar 2006 | 560 | Patch by Hiroki Kaminaga, 11 Mar 2006 |
558 | 561 | ||
559 | * Update omap5912osk board support | 562 | * Update omap5912osk board support |
560 | - Fix OMAP support that omap5912osk compiles in current source tree | 563 | - Fix OMAP support that omap5912osk compiles in current source tree |
561 | - Update with code from "http://omap.spectrumdigital.com/osk5912" | 564 | - Update with code from "http://omap.spectrumdigital.com/osk5912" |
562 | to fix problems with DDR initialization | 565 | to fix problems with DDR initialization |
563 | - Fix timer setup | 566 | - Fix timer setup |
564 | - Use CFI flash driver and support complete 32MB of onboard flash | 567 | - Use CFI flash driver and support complete 32MB of onboard flash |
565 | - Add "print_cpuinfo()" and "checkboard()" functions to display | 568 | - Add "print_cpuinfo()" and "checkboard()" functions to display |
566 | CPU (with frequency) and Board infos | 569 | CPU (with frequency) and Board infos |
567 | Patch by Stefan Roese, 10 May 2006 | 570 | Patch by Stefan Roese, 10 May 2006 |
568 | 571 | ||
569 | * Fix watchdog issues for ColdFire boards. | 572 | * Fix watchdog issues for ColdFire boards. |
570 | 573 | ||
571 | * Add M5271EVB board support. | 574 | * Add M5271EVB board support. |
572 | 575 | ||
573 | * Make R5200 specific low level initialization board conditional. | 576 | * Make R5200 specific low level initialization board conditional. |
574 | 577 | ||
575 | * Update CPU target identification strings for ColdFire family. | 578 | * Update CPU target identification strings for ColdFire family. |
576 | 579 | ||
577 | * Update register definitions for MCF5271. | 580 | * Update register definitions for MCF5271. |
578 | 581 | ||
579 | * Fix serial console support for MCF5271. | 582 | * Fix serial console support for MCF5271. |
580 | 583 | ||
581 | * Fixes for gcc 3.4 based m68k toolchain, | 584 | * Fixes for gcc 3.4 based m68k toolchain, |
582 | based on patch by Jate Sujjavanich. | 585 | based on patch by Jate Sujjavanich. |
583 | 586 | ||
584 | * Fix lowboot support on MCC200 board | 587 | * Fix lowboot support on MCC200 board |
585 | 588 | ||
586 | * Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port: | 589 | * Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port: |
587 | - Removed MPC8349ADS port | 590 | - Removed MPC8349ADS port |
588 | - Added PCI support to MPC8349ADS | 591 | - Added PCI support to MPC8349ADS |
589 | - reworked memory map to allow mapping of all regions with BATs | 592 | - reworked memory map to allow mapping of all regions with BATs |
590 | Patch by Kumar Gala, 20 Apr 2006 | 593 | Patch by Kumar Gala, 20 Apr 2006 |
591 | 594 | ||
592 | * Coding Style cleanup | 595 | * Coding Style cleanup |
593 | 596 | ||
594 | * Write RTC seconds first to maintain settings integrity per | 597 | * Write RTC seconds first to maintain settings integrity per |
595 | Maxim/Dallas DS1306 data sheet. | 598 | Maxim/Dallas DS1306 data sheet. |
596 | Patch by Alan J. Luse, 02 May 2006 | 599 | Patch by Alan J. Luse, 02 May 2006 |
597 | 600 | ||
598 | * Scheduled for removal: strnicmp() which is unused | 601 | * Scheduled for removal: strnicmp() which is unused |
599 | 602 | ||
600 | * Update for Intel Monahans boards: | 603 | * Update for Intel Monahans boards: |
601 | - support for magic key detection and handling on delta board | 604 | - support for magic key detection and handling on delta board |
602 | - NAND support for zylonite board + some minor cleanup | 605 | - NAND support for zylonite board + some minor cleanup |
603 | 606 | ||
604 | * Declare load_serial_ymodem() when using CFG_CMD_LOADB. | 607 | * Declare load_serial_ymodem() when using CFG_CMD_LOADB. |
605 | Patch by Jon Loeliger, 01 May 2006 | 608 | Patch by Jon Loeliger, 01 May 2006 |
606 | 609 | ||
607 | * Fixed handling of bad checksums with "mkimage -l" | 610 | * Fixed handling of bad checksums with "mkimage -l" |
608 | 611 | ||
609 | * Added support for BC3450 board | 612 | * Added support for BC3450 board |
610 | Patch by Stefan Strobl, 21 Oct 2005 | 613 | Patch by Stefan Strobl, 21 Oct 2005 |
611 | 614 | ||
612 | * Update for NC650 board: | 615 | * Update for NC650 board: |
613 | - Support rev1 and rev2 hardware | 616 | - Support rev1 and rev2 hardware |
614 | - adapt to new NAND layer | 617 | - adapt to new NAND layer |
615 | - add CP850 configuration based on NC650 | 618 | - add CP850 configuration based on NC650 |
616 | 619 | ||
617 | * MPC5200: enable snooping of DMA transactions on XLB even if no PCI | 620 | * MPC5200: enable snooping of DMA transactions on XLB even if no PCI |
618 | is configured; othrwise DMA accesses aren't cache coherent which | 621 | is configured; othrwise DMA accesses aren't cache coherent which |
619 | causes for example USB to fail. | 622 | causes for example USB to fail. |
620 | 623 | ||
621 | * Some code cleanup | 624 | * Some code cleanup |
622 | 625 | ||
623 | * Fix dbau1x00 boards broken by dbau1550 patch | 626 | * Fix dbau1x00 boards broken by dbau1550 patch |
624 | PLL:s were not set for boards other than 1550. | 627 | PLL:s were not set for boards other than 1550. |
625 | Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. | 628 | Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. |
626 | Default boot is now bootp for cards other than 1550. | 629 | Default boot is now bootp for cards other than 1550. |
627 | Patch by Thomas Lange, 10 Aug 2005 | 630 | Patch by Thomas Lange, 10 Aug 2005 |
628 | 631 | ||
629 | * Fixes common/cmd_flash.c: | 632 | * Fixes common/cmd_flash.c: |
630 | - fix some compiler/parser error, if using m68k tool chain | 633 | - fix some compiler/parser error, if using m68k tool chain |
631 | - optical fix for protect on/off all messages, if using more | 634 | - optical fix for protect on/off all messages, if using more |
632 | then one bank | 635 | then one bank |
633 | Patch by Jens Scharsig, 28 Jul 2005 | 636 | Patch by Jens Scharsig, 28 Jul 2005 |
634 | 637 | ||
635 | * Fix Quad UART mapping on MCC200 board due to new HW revision | 638 | * Fix Quad UART mapping on MCC200 board due to new HW revision |
636 | 639 | ||
637 | * Fix JFFS2 support for legacy NAND driver. | 640 | * Fix JFFS2 support for legacy NAND driver. |
638 | 641 | ||
639 | * Remove dependencies between DoC code and old legacy NAND driver. | 642 | * Remove dependencies between DoC code and old legacy NAND driver. |
640 | 643 | ||
641 | * Fix PM828_PCI target, for which PCI was *not* configured in. | 644 | * Fix PM828_PCI target, for which PCI was *not* configured in. |
642 | 645 | ||
643 | * Fix Lite5200B support: initialize SDelay register | 646 | * Fix Lite5200B support: initialize SDelay register |
644 | See Freescale's AN3221 "MPC5200B SDRAM Initialization and | 647 | See Freescale's AN3221 "MPC5200B SDRAM Initialization and |
645 | Configuration", 3.3.1 SDelay--MBAR + 0x0190 | 648 | Configuration", 3.3.1 SDelay--MBAR + 0x0190 |
646 | 649 | ||
647 | * Changes/fixes for drivers/cfi_flash.c: | 650 | * Changes/fixes for drivers/cfi_flash.c: |
648 | 651 | ||
649 | - Add Intel legacy lock/unlock support to common CFI driver | 652 | - Add Intel legacy lock/unlock support to common CFI driver |
650 | 653 | ||
651 | On some Intel flash's (e.g. Intel J3) legacy unlocking is | 654 | On some Intel flash's (e.g. Intel J3) legacy unlocking is |
652 | supported, meaning that unlocking of one sector will unlock | 655 | supported, meaning that unlocking of one sector will unlock |
653 | all sectors of this bank. Using this feature, unlocking | 656 | all sectors of this bank. Using this feature, unlocking |
654 | of all sectors upon startup (via env var "unlock=yes") will | 657 | of all sectors upon startup (via env var "unlock=yes") will |
655 | get much faster. | 658 | get much faster. |
656 | 659 | ||
657 | - Fixed problem with multiple reads of envronment variable | 660 | - Fixed problem with multiple reads of envronment variable |
658 | "unlock" as pointed out by Reinhard Arlt & Anders Larsen. | 661 | "unlock" as pointed out by Reinhard Arlt & Anders Larsen. |
659 | 662 | ||
660 | - Removed unwanted linefeeds from "protect" command when | 663 | - Removed unwanted linefeeds from "protect" command when |
661 | CFG_FLASH_PROTECTION is enabled. | 664 | CFG_FLASH_PROTECTION is enabled. |
662 | 665 | ||
663 | - Changed p3p400 board to use CFG_FLASH_PROTECTION | 666 | - Changed p3p400 board to use CFG_FLASH_PROTECTION |
664 | 667 | ||
665 | Patch by Stefan Roese, 01 Apr 2006 | 668 | Patch by Stefan Roese, 01 Apr 2006 |
666 | 669 | ||
667 | * Changes/fixes for drivers/cfi_flash.c: | 670 | * Changes/fixes for drivers/cfi_flash.c: |
668 | - Correctly handle the cases where CFG_HZ != 1000 (several | 671 | - Correctly handle the cases where CFG_HZ != 1000 (several |
669 | XScale-based boards) | 672 | XScale-based boards) |
670 | - Fix the timeout calculation of buffered writes (off by a | 673 | - Fix the timeout calculation of buffered writes (off by a |
671 | factor of 1000) | 674 | factor of 1000) |
672 | Patch by Anders Larsen, 31 Mar 2006 | 675 | Patch by Anders Larsen, 31 Mar 2006 |
673 | 676 | ||
674 | * Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) | 677 | * Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) |
675 | 678 | ||
676 | 405 SDRAM: - The SDRAM parameters can now be defined in the board | 679 | 405 SDRAM: - The SDRAM parameters can now be defined in the board |
677 | config file and the 405 SDRAM controller values will | 680 | config file and the 405 SDRAM controller values will |
678 | be calculated upon bootup (see PPChameleonEVB). | 681 | be calculated upon bootup (see PPChameleonEVB). |
679 | When those settings are not defined in the board | 682 | When those settings are not defined in the board |
680 | config file, the register setup will be as it is now, | 683 | config file, the register setup will be as it is now, |
681 | so this implementation should not break any current | 684 | so this implementation should not break any current |
682 | design using this code. | 685 | design using this code. |
683 | 686 | ||
684 | Thanks to Andrea Marson from DAVE for this patch. | 687 | Thanks to Andrea Marson from DAVE for this patch. |
685 | 688 | ||
686 | 440 DDR: - Added function sdram_tr1_set to auto calculate the | 689 | 440 DDR: - Added function sdram_tr1_set to auto calculate the |
687 | TR1 value for the DDR. | 690 | TR1 value for the DDR. |
688 | - Added ECC support (see p3p440). | 691 | - Added ECC support (see p3p440). |
689 | 692 | ||
690 | Patch by Stefan Roese, 17 Mar 2006 | 693 | Patch by Stefan Roese, 17 Mar 2006 |
691 | 694 | ||
692 | * Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S | 695 | * Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S |
693 | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] | 696 | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] |
694 | 697 | ||
695 | * Add support for ymodem protocol download | 698 | * Add support for ymodem protocol download |
696 | Patch by Stefano Babic, 29 Mar 2006 | 699 | Patch by Stefano Babic, 29 Mar 2006 |
697 | 700 | ||
698 | * Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000 | 701 | * Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000 |
699 | Merge from Markus Klotzbรผcher's repo, 01 Apr 2006 | 702 | Merge from Markus Klotzbรผcher's repo, 01 Apr 2006 |
700 | 703 | ||
701 | * GCC-4.x fixes: clean up global data pointer initialization for all | 704 | * GCC-4.x fixes: clean up global data pointer initialization for all |
702 | boards | 705 | boards |
703 | 706 | ||
704 | * Update for Delta board: | 707 | * Update for Delta board: |
705 | - redundant NAND environment | 708 | - redundant NAND environment |
706 | - misc Monahans cleanups (remove dead code etc.) | 709 | - misc Monahans cleanups (remove dead code etc.) |
707 | - DA9030 Initialization; some minimal changes to PXA I2C driver to | 710 | - DA9030 Initialization; some minimal changes to PXA I2C driver to |
708 | make it work with the Monahans. | 711 | make it work with the Monahans. |
709 | - Make Monahans clock frequency configurable using | 712 | - Make Monahans clock frequency configurable using |
710 | CFG_MONAHANS_RUN_MODE_OSC_RATIO and | 713 | CFG_MONAHANS_RUN_MODE_OSC_RATIO and |
711 | CFG_MONAHANS_TURBO_RUN_MODE_RATIO. | 714 | CFG_MONAHANS_TURBO_RUN_MODE_RATIO. |
712 | Merge from Markus Klotzbรผcher's repo, 25 Mar 2006 | 715 | Merge from Markus Klotzbรผcher's repo, 25 Mar 2006 |
713 | 716 | ||
714 | * Enable Quad UART om MCC200 board. | 717 | * Enable Quad UART om MCC200 board. |
715 | 718 | ||
716 | * Cleanup MCC200 board configuration; omit non-existent stuff. | 719 | * Cleanup MCC200 board configuration; omit non-existent stuff. |
717 | 720 | ||
718 | * Add support for MPC859/866 Rev. A.0 | 721 | * Add support for MPC859/866 Rev. A.0 |
719 | 722 | ||
720 | * Add command for handling DDR ECC registers on MPC8349EE MDS board. | 723 | * Add command for handling DDR ECC registers on MPC8349EE MDS board. |
721 | 724 | ||
722 | * Fix DDR ECC bit definitions for MPC83xx. | 725 | * Fix DDR ECC bit definitions for MPC83xx. |
723 | 726 | ||
724 | * Add initial support for MPC8349E MDS board. | 727 | * Add initial support for MPC8349E MDS board. |
725 | 728 | ||
726 | * Add support for ECC DDR initialization on MPC83xx. | 729 | * Add support for ECC DDR initialization on MPC83xx. |
727 | 730 | ||
728 | * Add DMA support for MPC83xx. | 731 | * Add DMA support for MPC83xx. |
729 | 732 | ||
730 | * Add sync in do_reset() routine for MPC83xx after RPR register | 733 | * Add sync in do_reset() routine for MPC83xx after RPR register |
731 | was written to. It is need on some targets when BAT translation | 734 | was written to. It is need on some targets when BAT translation |
732 | is enabled. | 735 | is enabled. |
733 | 736 | ||
734 | * Add bit definitions for MPC83xx DDR controller registers. | 737 | * Add bit definitions for MPC83xx DDR controller registers. |
735 | 738 | ||
736 | * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. | 739 | * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. |
737 | 740 | ||
738 | * Correct shift offsets in icache_status and dcache_status for MPC83xx. | 741 | * Correct shift offsets in icache_status and dcache_status for MPC83xx. |
739 | 742 | ||
740 | * Add support for DS1374 RTC chip. | 743 | * Add support for DS1374 RTC chip. |
741 | 744 | ||
742 | * Add support for Lite5200B board. | 745 | * Add support for Lite5200B board. |
743 | Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 | 746 | Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 |
744 | 747 | ||
745 | * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific | 748 | * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific |
746 | timer and cpu_reset code from cpu/$(CPU) into the new | 749 | timer and cpu_reset code from cpu/$(CPU) into the new |
747 | cpu/$(CPU)/$(SOC) directories | 750 | cpu/$(CPU)/$(SOC) directories |
748 | Patch by Andreas Engel, 13 Mar 2006 | 751 | Patch by Andreas Engel, 13 Mar 2006 |
749 | 752 | ||
750 | * Change max size of uncompressed uImage's to 8MByte and add | 753 | * Change max size of uncompressed uImage's to 8MByte and add |
751 | CFG_BOOTM_LEN to adjust this setting. | 754 | CFG_BOOTM_LEN to adjust this setting. |
752 | 755 | ||
753 | As mentioned by Robin Getz on 2005-05-24 the size of uncompressed | 756 | As mentioned by Robin Getz on 2005-05-24 the size of uncompressed |
754 | uImages was restricted to 4MBytes. This default size is now | 757 | uImages was restricted to 4MBytes. This default size is now |
755 | increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN | 758 | increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN |
756 | in the board config file. | 759 | in the board config file. |
757 | 760 | ||
758 | Patch by Stefan Roese, 13 Mar 2006 | 761 | Patch by Stefan Roese, 13 Mar 2006 |
759 | 762 | ||
760 | * Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c | 763 | * Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c |
761 | Patch by Stefan Roese, 13 Mar 2006 | 764 | Patch by Stefan Roese, 13 Mar 2006 |
762 | 765 | ||
763 | * cpu/ppc4xx/start.S : exceptions are enabled after relocation | 766 | * cpu/ppc4xx/start.S : exceptions are enabled after relocation |
764 | Patch by Cedric Vincent, 06 Jul 2005 | 767 | Patch by Cedric Vincent, 06 Jul 2005 |
765 | 768 | ||
766 | * au1x00_eth.c: check malloc return value and abort if it failed | 769 | * au1x00_eth.c: check malloc return value and abort if it failed |
767 | Patch by Andrew Dyer, 26 Jul 2005 | 770 | Patch by Andrew Dyer, 26 Jul 2005 |
768 | 771 | ||
769 | * Change the sequence of events in soft_i2c.c:send_ack() to keep from | 772 | * Change the sequence of events in soft_i2c.c:send_ack() to keep from |
770 | incorrectly generating start/stop conditions on the bus. | 773 | incorrectly generating start/stop conditions on the bus. |
771 | Patch by Andrew Dyer, 26 Jul 2005 | 774 | Patch by Andrew Dyer, 26 Jul 2005 |
772 | 775 | ||
773 | * Fix bug in [id]cache_status commands for MPC85xx processors; | 776 | * Fix bug in [id]cache_status commands for MPC85xx processors; |
774 | should look at LSB of L1CSRn registers to determine if L1 cache is | 777 | should look at LSB of L1CSRn registers to determine if L1 cache is |
775 | enabled, not the MSB. | 778 | enabled, not the MSB. |
776 | Patch by Murray Jensen, 19 Jul 2005 | 779 | Patch by Murray Jensen, 19 Jul 2005 |
777 | 780 | ||
778 | * Fix array overflow with fw_setenv on uninitialised environment | 781 | * Fix array overflow with fw_setenv on uninitialised environment |
779 | Patch by Murray Jensen, 15 Jul 2005 | 782 | Patch by Murray Jensen, 15 Jul 2005 |
780 | 783 | ||
781 | * Add support for EmbeddedPlanet EP88x boards | 784 | * Add support for EmbeddedPlanet EP88x boards |
782 | Patch by Yuli Barcohen, 13 Jul 2005 | 785 | Patch by Yuli Barcohen, 13 Jul 2005 |
783 | 786 | ||
784 | * Remove board specific configuration includes from the common xilinx | 787 | * Remove board specific configuration includes from the common xilinx |
785 | ethernet and iic adapter code. | 788 | ethernet and iic adapter code. |
786 | Patch by Michael Libeskind, 12 Jul 2005 | 789 | Patch by Michael Libeskind, 12 Jul 2005 |
787 | 790 | ||
788 | * Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver | 791 | * Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver |
789 | Patch by Murray Jensen, 08 Jul 2005 | 792 | Patch by Murray Jensen, 08 Jul 2005 |
790 | 793 | ||
791 | * Add (some) definitions for the MPC85xx local bus controller | 794 | * Add (some) definitions for the MPC85xx local bus controller |
792 | Patch by Murray Jensen, 08 Jul 2005 | 795 | Patch by Murray Jensen, 08 Jul 2005 |
793 | 796 | ||
794 | * Add CPM2 I/O pin functions for MPC85xx processors | 797 | * Add CPM2 I/O pin functions for MPC85xx processors |
795 | Patch by Murray Jensen, 08 Jul 2005 | 798 | Patch by Murray Jensen, 08 Jul 2005 |
796 | 799 | ||
797 | * Fix compile problem | 800 | * Fix compile problem |
798 | 801 | ||
799 | * Added PCI support for MPC8349ADS board | 802 | * Added PCI support for MPC8349ADS board |
800 | Patch by Kumar Gala 11 Jan 2006 | 803 | Patch by Kumar Gala 11 Jan 2006 |
801 | 804 | ||
802 | * Enable address translation on MPC83xx | 805 | * Enable address translation on MPC83xx |
803 | Patch by Kumar Gala, 10 Feb 2006 | 806 | Patch by Kumar Gala, 10 Feb 2006 |
804 | 807 | ||
805 | * Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx | 808 | * Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx |
806 | Patch by Kumar Gala, 25 Jan 2006 | 809 | Patch by Kumar Gala, 25 Jan 2006 |
807 | 810 | ||
808 | * Fixed defines for MPC83xx SICRL register to match current specs | 811 | * Fixed defines for MPC83xx SICRL register to match current specs |
809 | Patch by Kumar Gala, 23 Jan 2006 | 812 | Patch by Kumar Gala, 23 Jan 2006 |
810 | 813 | ||
811 | * Only disable the MPC83xx watchdog if its enabled out of reset. | 814 | * Only disable the MPC83xx watchdog if its enabled out of reset. |
812 | If its disabled out of reset SW can later enable it if so desired | 815 | If its disabled out of reset SW can later enable it if so desired |
813 | Patch by Kumar Gala, 11 Jan 2006 | 816 | Patch by Kumar Gala, 11 Jan 2006 |
814 | 817 | ||
815 | * Allow config of GPIO direction & data registers at boot on 83xx | 818 | * Allow config of GPIO direction & data registers at boot on 83xx |
816 | Patch by Kumar Gala, 11 Jan 2006 | 819 | Patch by Kumar Gala, 11 Jan 2006 |
817 | 820 | ||
818 | * Enable time handling on 83xx | 821 | * Enable time handling on 83xx |
819 | Patch by Kumar Gala, 11 Jan 2006 | 822 | Patch by Kumar Gala, 11 Jan 2006 |
820 | 823 | ||
821 | * Make System IO Config Registers board configurable on MPC83xx | 824 | * Make System IO Config Registers board configurable on MPC83xx |
822 | Patch by Kumar Gala, 11 Jan 2006 | 825 | Patch by Kumar Gala, 11 Jan 2006 |
823 | 826 | ||
824 | * Fixed PCI indirect config ops to handle multiple PCI controllers | 827 | * Fixed PCI indirect config ops to handle multiple PCI controllers |
825 | We need to adjust the bus number we are trying to access based | 828 | We need to adjust the bus number we are trying to access based |
826 | on which PCI controller its on | 829 | on which PCI controller its on |
827 | Patch by Kumar Gala, 12 Jan 2006 | 830 | Patch by Kumar Gala, 12 Jan 2006 |
828 | 831 | ||
829 | * Report back PCI bus when doing table based device config | 832 | * Report back PCI bus when doing table based device config |
830 | Patch by Kumar Gala, 11 Jan 2006 | 833 | Patch by Kumar Gala, 11 Jan 2006 |
831 | 834 | ||
832 | * Added support for PCI prefetchable region and BARs | 835 | * Added support for PCI prefetchable region and BARs |
833 | If a host controller sets up a region as prefetchable and | 836 | If a host controller sets up a region as prefetchable and |
834 | a device's BAR denotes it as prefetchable, allocate the | 837 | a device's BAR denotes it as prefetchable, allocate the |
835 | BAR into the prefetch region. | 838 | BAR into the prefetch region. |
836 | 839 | ||
837 | If a BAR is prefetchable and no prefetchable region has | 840 | If a BAR is prefetchable and no prefetchable region has |
838 | been setup by the controller we fall back to allocating | 841 | been setup by the controller we fall back to allocating |
839 | the BAR into the normally memory region. | 842 | the BAR into the normally memory region. |
840 | Patch by Kumar Gala, 11 Jan 2006 | 843 | Patch by Kumar Gala, 11 Jan 2006 |
841 | 844 | ||
842 | * Add helper function for generic flat device tree fixups for mpc83xx | 845 | * Add helper function for generic flat device tree fixups for mpc83xx |
843 | Patch by Kumar Gala, 11 Jan 2006 | 846 | Patch by Kumar Gala, 11 Jan 2006 |
844 | 847 | ||
845 | * Add support for passing initrd information via flat device tree | 848 | * Add support for passing initrd information via flat device tree |
846 | Patch by Kumar Gala, 11 Jan 2006 | 849 | Patch by Kumar Gala, 11 Jan 2006 |
847 | 850 | ||
848 | * Added OF_STDOUT_PATH and OF_SOC | 851 | * Added OF_STDOUT_PATH and OF_SOC |
849 | 852 | ||
850 | OF_STDOUT_PATH specifies the path to the device the kernel can use | 853 | OF_STDOUT_PATH specifies the path to the device the kernel can use |
851 | for console output | 854 | for console output |
852 | 855 | ||
853 | OF_SOC specifies the proper name of the SOC node if one exists. | 856 | OF_SOC specifies the proper name of the SOC node if one exists. |
854 | Patch by Kumar Gala, 11 Jan 2006 | 857 | Patch by Kumar Gala, 11 Jan 2006 |
855 | 858 | ||
856 | * Allow board code to fixup the flat device tree before booting a kernel | 859 | * Allow board code to fixup the flat device tree before booting a kernel |
857 | Patch by Kumar Gala, 11 Jan 2006 | 860 | Patch by Kumar Gala, 11 Jan 2006 |
858 | 861 | ||
859 | * Added CONFIG_ options for bd_t and env in flat dev tree | 862 | * Added CONFIG_ options for bd_t and env in flat dev tree |
860 | 863 | ||
861 | CONFIG_OF_HAS_BD_T will put a copy of the bd_t | 864 | CONFIG_OF_HAS_BD_T will put a copy of the bd_t |
862 | into the resulting flat device tree. | 865 | into the resulting flat device tree. |
863 | 866 | ||
864 | CONFIG_OF_HAS_UBOOT_ENV will copy the environment | 867 | CONFIG_OF_HAS_UBOOT_ENV will copy the environment |
865 | variables from u-boot into the flat device tree | 868 | variables from u-boot into the flat device tree |
866 | 869 | ||
867 | Patch by Kumar Gala, 11 Jan 2006 | 870 | Patch by Kumar Gala, 11 Jan 2006 |
868 | 871 | ||
869 | * Add support for the DHCP vendor optional bootfile (#67). | 872 | * Add support for the DHCP vendor optional bootfile (#67). |
870 | Ignores the vendor TFTP server name option (#66). | 873 | Ignores the vendor TFTP server name option (#66). |
871 | Patch by Murray Jensen, 30 Jun 2005 | 874 | Patch by Murray Jensen, 30 Jun 2005 |
872 | 875 | ||
873 | * Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode | 876 | * Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode |
874 | Patch by Andy Fleming, 14 Jun 2005 | 877 | Patch by Andy Fleming, 14 Jun 2005 |
875 | 878 | ||
876 | * Fix bad register definitions for LTX971 PHY on MPC85xx boards. | 879 | * Fix bad register definitions for LTX971 PHY on MPC85xx boards. |
877 | Patch by Gerhard Jaeger, 21 Jun 2005 | 880 | Patch by Gerhard Jaeger, 21 Jun 2005 |
878 | 881 | ||
879 | * Add netconsole and some more commands to RPXlite_DW board | 882 | * Add netconsole and some more commands to RPXlite_DW board |
880 | Patch by Sam Song, 19 Jun 2005 | 883 | Patch by Sam Song, 19 Jun 2005 |
881 | 884 | ||
882 | * Fix bad declaration on pci_cfgfunc_nothing | 885 | * Fix bad declaration on pci_cfgfunc_nothing |
883 | Patch by Sam Song, 19 Jun 2005 | 886 | Patch by Sam Song, 19 Jun 2005 |
884 | 887 | ||
885 | * Adjust "echo" as a default command | 888 | * Adjust "echo" as a default command |
886 | Patch by Sam Song, 19 Jun 2005 | 889 | Patch by Sam Song, 19 Jun 2005 |
887 | 890 | ||
888 | * Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC | 891 | * Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC |
889 | Patch by KokHow Teh, 16 Jun 2005 | 892 | Patch by KokHow Teh, 16 Jun 2005 |
890 | 893 | ||
891 | * Add crc of data to jffs2 (in jffs2_1pass_build_lists()). | 894 | * Add crc of data to jffs2 (in jffs2_1pass_build_lists()). |
892 | Patch by Rick Bronson, 15 Jun 2005 | 895 | Patch by Rick Bronson, 15 Jun 2005 |
893 | 896 | ||
894 | * Coding Style cleanup | 897 | * Coding Style cleanup |
895 | 898 | ||
896 | * Avoid dereferencing NULL in find_cmd() if no valid commands were found | 899 | * Avoid dereferencing NULL in find_cmd() if no valid commands were found |
897 | Patch by Andrew Dyer, 13 Jun 2005 | 900 | Patch by Andrew Dyer, 13 Jun 2005 |
898 | 901 | ||
899 | * Add ADI Blackfin support | 902 | * Add ADI Blackfin support |
900 | - add support for Analog Devices Blackfin BF533 CPU | 903 | - add support for Analog Devices Blackfin BF533 CPU |
901 | - add support for the ADI BF533 Stamp uClinux board | 904 | - add support for the ADI BF533 Stamp uClinux board |
902 | - add support for the ADI BF533 EZKit board | 905 | - add support for the ADI BF533 EZKit board |
903 | Patches by Richard Klingler, 11 Jun 2005 | 906 | Patches by Richard Klingler, 11 Jun 2005 |
904 | 907 | ||
905 | * Add loads of ntohl() in image header handling | 908 | * Add loads of ntohl() in image header handling |
906 | Patch by Steven Scholz, 10 Jun 2005 | 909 | Patch by Steven Scholz, 10 Jun 2005 |
907 | 910 | ||
908 | * Switch MPC86xADS and MPC885ADS boards to use cpuclk environment | 911 | * Switch MPC86xADS and MPC885ADS boards to use cpuclk environment |
909 | variable to set clock | 912 | variable to set clock |
910 | Patch by Yuli Barcohen, 05 Jun 2005 | 913 | Patch by Yuli Barcohen, 05 Jun 2005 |
911 | 914 | ||
912 | * RPXlite configuration fixes | 915 | * RPXlite configuration fixes |
913 | - Use correct flash sector size | 916 | - Use correct flash sector size |
914 | - Use correct memory test end address | 917 | - Use correct memory test end address |
915 | - Add support for bzip2 compression | 918 | - Add support for bzip2 compression |
916 | - Various small fixes | 919 | - Various small fixes |
917 | Patch by Yuli Barcohen, 05 Jun 2005 | 920 | Patch by Yuli Barcohen, 05 Jun 2005 |
918 | 921 | ||
919 | * Memory configuration changes for ZPC.1900 board | 922 | * Memory configuration changes for ZPC.1900 board |
920 | - Fix SDRAM timing on both local bus and 60x bus | 923 | - Fix SDRAM timing on both local bus and 60x bus |
921 | - Add support for second flash bank (SIMM) | 924 | - Add support for second flash bank (SIMM) |
922 | - Change boot flash base | 925 | - Change boot flash base |
923 | Patch by Yuli Barcohen, 05 Jun 2005 | 926 | Patch by Yuli Barcohen, 05 Jun 2005 |
924 | 927 | ||
925 | * Add support for Adder boards with 16MB SDRAM; | 928 | * Add support for Adder boards with 16MB SDRAM; |
926 | add support for second FEC on Adder87x board. | 929 | add support for second FEC on Adder87x board. |
927 | Patch by Yuli Barcohen, 05 Jun 2005 | 930 | Patch by Yuli Barcohen, 05 Jun 2005 |
928 | 931 | ||
929 | * Fix conditional for including ks8695eth driver | 932 | * Fix conditional for including ks8695eth driver |
930 | Patch by Greg Ungerer, 04 Jun 2005 | 933 | Patch by Greg Ungerer, 04 Jun 2005 |
931 | 934 | ||
932 | * Fix Makefile: include config.mk only after CROSS_COMPILE is defined | 935 | * Fix Makefile: include config.mk only after CROSS_COMPILE is defined |
933 | Patch by Friedrich Lobenstock, 02 Jun 2005 | 936 | Patch by Friedrich Lobenstock, 02 Jun 2005 |
934 | 937 | ||
935 | * Fix comment in common/soft_i2c.c | 938 | * Fix comment in common/soft_i2c.c |
936 | Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005 | 939 | Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005 |
937 | 940 | ||
938 | * Cleanup compiler warnings. | 941 | * Cleanup compiler warnings. |
939 | Patch by Greg Ungerer, 21 May 2005 | 942 | Patch by Greg Ungerer, 21 May 2005 |
940 | 943 | ||
941 | * Word alignment fixes for word aligned NS16550 UART | 944 | * Word alignment fixes for word aligned NS16550 UART |
942 | Patch by Jean-Paul Saman, 01 Mar 2005 | 945 | Patch by Jean-Paul Saman, 01 Mar 2005 |
943 | 946 | ||
944 | Fixes bug with UART that only supports word aligned access: removed | 947 | Fixes bug with UART that only supports word aligned access: removed |
945 | "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some | 948 | "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some |
946 | (broken!) versions of GCC generate byte accesses when encountering | 949 | (broken!) versions of GCC generate byte accesses when encountering |
947 | the packed attribute regardless if the struct is already correctly | 950 | the packed attribute regardless if the struct is already correctly |
948 | aligned for a platform. Peripherals that can only handle word | 951 | aligned for a platform. Peripherals that can only handle word |
949 | aligned access won't work properly when accessed with byte access. | 952 | aligned access won't work properly when accessed with byte access. |
950 | The struct NS16550 is already word aligned for REG_SIZE = 4, so | 953 | The struct NS16550 is already word aligned for REG_SIZE = 4, so |
951 | there is no need to packed the struct in that case. | 954 | there is no need to packed the struct in that case. |
952 | 955 | ||
953 | * Fix behaviour if gatewayip is not set | 956 | * Fix behaviour if gatewayip is not set |
954 | Patch by Robin Gilks, 23 Dec 2004 | 957 | Patch by Robin Gilks, 23 Dec 2004 |
955 | 958 | ||
956 | * Fix cleanup for netstart board. | 959 | * Fix cleanup for netstart board. |
957 | Remove build results from repository | 960 | Remove build results from repository |
958 | 961 | ||
959 | * Some code cleanup for GCC 4.x | 962 | * Some code cleanup for GCC 4.x |
960 | 963 | ||
961 | * Fixes to support environment in NAND flash; | 964 | * Fixes to support environment in NAND flash; |
962 | enable NAND flash based environment for delta board. | 965 | enable NAND flash based environment for delta board. |
963 | 966 | ||
964 | * Add support for Intel Monahans CPU on Zylonite and Delta boards | 967 | * Add support for Intel Monahans CPU on Zylonite and Delta boards |
965 | (This is Work in Progress!) | 968 | (This is Work in Progress!) |
966 | 969 | ||
967 | * Add support for TQM8260-AI boards. | 970 | * Add support for TQM8260-AI boards. |
968 | 971 | ||
969 | * Minor code cleanup | 972 | * Minor code cleanup |
970 | 973 | ||
971 | * Merge the new NAND code (testing-NAND brach); see doc/README.nand | 974 | * Merge the new NAND code (testing-NAND brach); see doc/README.nand |
972 | Rewrite of NAND code based on what is in 2.6.12 Linux kernel | 975 | Rewrite of NAND code based on what is in 2.6.12 Linux kernel |
973 | Patch by Ladislav Michl, 29 Jun 2005 | 976 | Patch by Ladislav Michl, 29 Jun 2005 |
974 | 977 | ||
975 | * Add lowboot target to mcc200 board | 978 | * Add lowboot target to mcc200 board |
976 | Patch by Stefan Roese, 4 Mar 2006 | 979 | Patch by Stefan Roese, 4 Mar 2006 |
977 | 980 | ||
978 | * Fix problem with flash_get_size() from CFI driver update | 981 | * Fix problem with flash_get_size() from CFI driver update |
979 | Patch by Stefan Roese, 1 Mar 2006 | 982 | Patch by Stefan Roese, 1 Mar 2006 |
980 | 983 | ||
981 | * Make CFG_NO_FLASH work on ARM systems | 984 | * Make CFG_NO_FLASH work on ARM systems |
982 | Patch by Markus Klotzbuecher, 27 Feb 2006 | 985 | Patch by Markus Klotzbuecher, 27 Feb 2006 |
983 | 986 | ||
984 | * Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock, | 987 | * Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock, |
985 | use hush shell. | 988 | use hush shell. |
986 | 989 | ||
987 | * Convert mcc200 to use common CFI flash driver | 990 | * Convert mcc200 to use common CFI flash driver |
988 | Patch by Stefan Roese, 28 Feb 2006 | 991 | Patch by Stefan Roese, 28 Feb 2006 |
989 | 992 | ||
990 | * Add env-variable "unlock" to handle initial state of sectors | 993 | * Add env-variable "unlock" to handle initial state of sectors |
991 | (locked/unlocked). | 994 | (locked/unlocked). |
992 | 995 | ||
993 | Only the U-Boot image and it's environment is protected, | 996 | Only the U-Boot image and it's environment is protected, |
994 | all other sectors are unprotected (unlocked) if flash | 997 | all other sectors are unprotected (unlocked) if flash |
995 | hardware protection is used (CFG_FLASH_PROTECTION) and | 998 | hardware protection is used (CFG_FLASH_PROTECTION) and |
996 | the environment variable "unlock" is set to "yes". | 999 | the environment variable "unlock" is set to "yes". |
997 | 1000 | ||
998 | Patch by Stefan Roese, 28 Feb 2006 | 1001 | Patch by Stefan Roese, 28 Feb 2006 |
999 | 1002 | ||
1000 | * Update drivers/cfi_flash.c: | 1003 | * Update drivers/cfi_flash.c: |
1001 | - find_sector() called in both versions of flash_write_cfiword() | 1004 | - find_sector() called in both versions of flash_write_cfiword() |
1002 | Patch by Peter Pearse, 27th Feb 2006 | 1005 | Patch by Peter Pearse, 27th Feb 2006 |
1003 | 1006 | ||
1004 | * CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode | 1007 | * CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode |
1005 | Patch by Jose Maria Lopez, 16 Jan 2006 | 1008 | Patch by Jose Maria Lopez, 16 Jan 2006 |
1006 | 1009 | ||
1007 | * Add support for AMD/Spansion Flashes in flash_write_cfibuffer | 1010 | * Add support for AMD/Spansion Flashes in flash_write_cfibuffer |
1008 | Patch by Alex Bastos and Thomas Schaefer, 2005-08-29 | 1011 | Patch by Alex Bastos and Thomas Schaefer, 2005-08-29 |
1009 | 1012 | ||
1010 | * Changes/fixes for drivers/cfi_flash.c: | 1013 | * Changes/fixes for drivers/cfi_flash.c: |
1011 | We *should* check if there are any error bits if the previous call | 1014 | We *should* check if there are any error bits if the previous call |
1012 | returned ERR_OK (Otherwise we will have output an error message in | 1015 | returned ERR_OK (Otherwise we will have output an error message in |
1013 | flash_status_check() already.) The original code would only check for | 1016 | flash_status_check() already.) The original code would only check for |
1014 | error bits if flash_status_check() returns ERR_TIMEOUT. | 1017 | error bits if flash_status_check() returns ERR_TIMEOUT. |
1015 | Patch by Marcus Hall, 23 Aug 2005 | 1018 | Patch by Marcus Hall, 23 Aug 2005 |
1016 | 1019 | ||
1017 | * Changes/fixes for drivers/cfi_flash.c: | 1020 | * Changes/fixes for drivers/cfi_flash.c: |
1018 | - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c | 1021 | - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c |
1019 | - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c | 1022 | - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c |
1020 | Patch by Sangmoon Kim, 19 Aug 2005 | 1023 | Patch by Sangmoon Kim, 19 Aug 2005 |
1021 | 1024 | ||
1022 | * Fixes for drivers/cfi_flash.c: | 1025 | * Fixes for drivers/cfi_flash.c: |
1023 | - Fix wrong timeout value usage in flash_status_check() | 1026 | - Fix wrong timeout value usage in flash_status_check() |
1024 | - Round write_tout up when converting to msec in flash_get_size() | 1027 | - Round write_tout up when converting to msec in flash_get_size() |
1025 | - Remove clearing flash status at the end of flash_write_cfibuffer() | 1028 | - Remove clearing flash status at the end of flash_write_cfibuffer() |
1026 | which sets Intel 28F640J3 flash back to command mode on CSB472 | 1029 | which sets Intel 28F640J3 flash back to command mode on CSB472 |
1027 | Patch by Tolunay Orkun, 02 July 2005 | 1030 | Patch by Tolunay Orkun, 02 July 2005 |
1028 | 1031 | ||
1029 | * Add basic support for the SMMACO4 Board from PanDaCom. | 1032 | * Add basic support for the SMMACO4 Board from PanDaCom. |
1030 | Patch by Heiko Schocher, 20 Feb 2006 | 1033 | Patch by Heiko Schocher, 20 Feb 2006 |
1031 | 1034 | ||
1032 | * Add GIT version information (commid ID) to untagged U-Boot versions | 1035 | * Add GIT version information (commid ID) to untagged U-Boot versions |
1033 | 1036 | ||
1034 | As done in the linux kernel, the U-Boot version (U_BOOT_VERSION) | 1037 | As done in the linux kernel, the U-Boot version (U_BOOT_VERSION) |
1035 | of all unreleased (untagged) U-Boot images will be automatically | 1038 | of all unreleased (untagged) U-Boot images will be automatically |
1036 | extended upon compiletime with a part of the GIT commit ID and | 1039 | extended upon compiletime with a part of the GIT commit ID and |
1037 | possibly with "dirty" if uncommited changes are detected. | 1040 | possibly with "dirty" if uncommited changes are detected. |
1038 | 1041 | ||
1039 | Here an example for the resulting version: | 1042 | Here an example for the resulting version: |
1040 | "U-Boot 1.1.4-g3457ac18-dirty" | 1043 | "U-Boot 1.1.4-g3457ac18-dirty" |
1041 | 1044 | ||
1042 | The version is now maintained in the toplevel Makefile and the | 1045 | The version is now maintained in the toplevel Makefile and the |
1043 | version headers are autogenerated. | 1046 | version headers are autogenerated. |
1044 | 1047 | ||
1045 | Patch by Stefan Roese, 9 Feb 2006 | 1048 | Patch by Stefan Roese, 9 Feb 2006 |
1046 | 1049 | ||
1047 | * Update default environment for INKA4x00 board. | 1050 | * Update default environment for INKA4x00 board. |
1048 | 1051 | ||
1049 | * Convert CPCI750 to use common CFI flash driver | 1052 | * Convert CPCI750 to use common CFI flash driver |
1050 | Patch by Reinhard Arlt, 8 Feb 2006 | 1053 | Patch by Reinhard Arlt, 8 Feb 2006 |
1051 | 1054 | ||
1052 | * Various changes to esd HH405 board specific files | 1055 | * Various changes to esd HH405 board specific files |
1053 | Patch by Matthias Fuchs, 07 Feb 2006 | 1056 | Patch by Matthias Fuchs, 07 Feb 2006 |
1054 | 1057 | ||
1055 | * Cleanup U-Boot boot messages on ARM. | 1058 | * Cleanup U-Boot boot messages on ARM. |
1056 | 1059 | ||
1057 | To match the U-Boot user interface on ARM platforms to the U-Boot | 1060 | To match the U-Boot user interface on ARM platforms to the U-Boot |
1058 | standard (as on PPC platforms), some messages with debug character | 1061 | standard (as on PPC platforms), some messages with debug character |
1059 | are removed from the default U-Boot build. | 1062 | are removed from the default U-Boot build. |
1060 | Enable DEBUG for lib_arm/board.c to enable debug messages. | 1063 | Enable DEBUG for lib_arm/board.c to enable debug messages. |
1061 | New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. | 1064 | New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. |
1062 | Patch by Stefan Roese, 24 Jan 2006 | 1065 | Patch by Stefan Roese, 24 Jan 2006 |
1063 | 1066 | ||
1064 | * Fix various compiler warnings on ppc4xx builds (ELDK 4.0) | 1067 | * Fix various compiler warnings on ppc4xx builds (ELDK 4.0) |
1065 | Patch by Stefan Roese, 18 Jan 2006 | 1068 | Patch by Stefan Roese, 18 Jan 2006 |
1066 | 1069 | ||
1067 | * Add VGA support (CT69000) to CPCI750 board. | 1070 | * Add VGA support (CT69000) to CPCI750 board. |
1068 | Insert missing __le32_to_cpu() for filesize in ext2fs_read_file(). | 1071 | Insert missing __le32_to_cpu() for filesize in ext2fs_read_file(). |
1069 | Patch by Reinhard Arlt, 30 Dec 2005 | 1072 | Patch by Reinhard Arlt, 30 Dec 2005 |
1070 | 1073 | ||
1071 | * PMC405 and CPCI405: Moved configuration of pci resources | 1074 | * PMC405 and CPCI405: Moved configuration of pci resources |
1072 | into config file. | 1075 | into config file. |
1073 | PMC405 and CPCI2DP: Added firmware download and booting via pci. | 1076 | PMC405 and CPCI2DP: Added firmware download and booting via pci. |
1074 | Patch by Matthias Fuchs, 20 Dec 2005 | 1077 | Patch by Matthias Fuchs, 20 Dec 2005 |
1075 | 1078 | ||
1076 | * Add ColdFire targets to MAKEALL script | 1079 | * Add ColdFire targets to MAKEALL script |
1077 | Patch by Zachary Landau, 26 Jan 2006 | 1080 | Patch by Zachary Landau, 26 Jan 2006 |
1078 | 1081 | ||
1079 | * Add support for r5200 board | 1082 | * Add support for r5200 board |
1080 | Patch by Zachary Landau, 26 Jan 2006 | 1083 | Patch by Zachary Landau, 26 Jan 2006 |
1081 | 1084 | ||
1082 | * Add support for Freescale M5271 processor | 1085 | * Add support for Freescale M5271 processor |
1083 | Patch by Zachary Landau, 26 Jan 2006 | 1086 | Patch by Zachary Landau, 26 Jan 2006 |
1084 | 1087 | ||
1085 | * Fix 28F256J3A support on PM520 board | 1088 | * Fix 28F256J3A support on PM520 board |
1086 | (without bank-switching only 32 MB can be accessed) | 1089 | (without bank-switching only 32 MB can be accessed) |
1087 | 1090 | ||
1088 | * Fix mkimage bug with multifile images created on 64 bit systems. | 1091 | * Fix mkimage bug with multifile images created on 64 bit systems. |
1089 | 1092 | ||
1090 | * Add support for 28F256J3A flash (=> 64 MB) on PM520 board | 1093 | * Add support for 28F256J3A flash (=> 64 MB) on PM520 board |
1091 | 1094 | ||
1092 | * Fix compiler problem with at91rm9200dk board. | 1095 | * Fix compiler problem with at91rm9200dk board. |
1093 | Patch by Eugen Bigz, 19 Dec 2005 | 1096 | Patch by Eugen Bigz, 19 Dec 2005 |
1094 | 1097 | ||
1095 | ====================================================================== | 1098 | ====================================================================== |
1096 | Changes for U-Boot 1.1.4: | 1099 | Changes for U-Boot 1.1.4: |
1097 | ====================================================================== | 1100 | ====================================================================== |
1098 | 1101 | ||
1099 | * Changes to Yellowstone & Yosemite 440EP/GR eval boards: | 1102 | * Changes to Yellowstone & Yosemite 440EP/GR eval boards: |
1100 | - Changed GPIO setup to enable another address line in order to | 1103 | - Changed GPIO setup to enable another address line in order to |
1101 | address 64M of FLASH. | 1104 | address 64M of FLASH. |
1102 | - Added function sdram_tr1_set to auto calculate the tr1 value for | 1105 | - Added function sdram_tr1_set to auto calculate the tr1 value for |
1103 | the DDR. | 1106 | the DDR. |
1104 | Patch by Steven Blakeslee, 12 Dec 2005 | 1107 | Patch by Steven Blakeslee, 12 Dec 2005 |
1105 | 1108 | ||
1106 | * MPC5200: Set PCI retry counter to 0 = infinite retry; | 1109 | * MPC5200: Set PCI retry counter to 0 = infinite retry; |
1107 | The default of 255 is too short for slow devices. | 1110 | The default of 255 is too short for slow devices. |
1108 | Patch by Martin Nykodym, 12 Dec 2005 | 1111 | Patch by Martin Nykodym, 12 Dec 2005 |
1109 | 1112 | ||
1110 | * Change port configuration for O2DNT (CODEC1 on PSC1). | 1113 | * Change port configuration for O2DNT (CODEC1 on PSC1). |
1111 | 1114 | ||
1112 | * Fix register for PCI async mode on PPC440EP | 1115 | * Fix register for PCI async mode on PPC440EP |
1113 | Patch by Youngchul Bang, 08 Dec 2005 | 1116 | Patch by Youngchul Bang, 08 Dec 2005 |
1114 | 1117 | ||
1115 | * Fix U-Boot linking problems (add .eh_frame segment to linker script) | 1118 | * Fix U-Boot linking problems (add .eh_frame segment to linker script) |
1116 | This segment may be required by some libgcc.a functions | 1119 | This segment may be required by some libgcc.a functions |
1117 | (like _udivdi3). | 1120 | (like _udivdi3). |
1118 | 1121 | ||
1119 | * Fix DPRAM offset/size for MPC8541/8555. | 1122 | * Fix DPRAM offset/size for MPC8541/8555. |
1120 | Simplify TQM85xx Makefile handling. | 1123 | Simplify TQM85xx Makefile handling. |
1121 | 1124 | ||
1122 | * Fix data overflow (typo?) in rtc/ds1302.c | 1125 | * Fix data overflow (typo?) in rtc/ds1302.c |
1123 | 1126 | ||
1124 | * Fix U-Boot compilation for MIPS boards using ELDK 4.0 | 1127 | * Fix U-Boot compilation for MIPS boards using ELDK 4.0 |
1125 | 1128 | ||
1126 | * Add support for TQM8541/8555 boards, TQM85xx support reworked: | 1129 | * Add support for TQM8541/8555 boards, TQM85xx support reworked: |
1127 | - Support for TQM8541/8555 boards added. | 1130 | - Support for TQM8541/8555 boards added. |
1128 | - Complete rework of TQM8540/8560 support. | 1131 | - Complete rework of TQM8540/8560 support. |
1129 | - Common TQM85xx code now supports all current TQM85xx platforms | 1132 | - Common TQM85xx code now supports all current TQM85xx platforms |
1130 | (TQM8540/8541/8555/8560). | 1133 | (TQM8540/8541/8555/8560). |
1131 | - DDR SDRAM size detection added. | 1134 | - DDR SDRAM size detection added. |
1132 | - CAS latency default values can be overwritten by setting "serial#" | 1135 | - CAS latency default values can be overwritten by setting "serial#" |
1133 | to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. | 1136 | to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. |
1134 | If problems are detected with this non default CAS latency, | 1137 | If problems are detected with this non default CAS latency, |
1135 | the default values will be used instead. | 1138 | the default values will be used instead. |
1136 | - Flash size detection added. | 1139 | - Flash size detection added. |
1137 | - Moved FCC ethernet driver initialization behind TSEC driver init | 1140 | - Moved FCC ethernet driver initialization behind TSEC driver init |
1138 | -> TSEC is first device. | 1141 | -> TSEC is first device. |
1139 | Patch by Stefan Roese, 30 Nov 2005 | 1142 | Patch by Stefan Roese, 30 Nov 2005 |
1140 | 1143 | ||
1141 | * Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. | 1144 | * Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. |
1142 | Patch by John Otken, 23 Nov 2005 | 1145 | Patch by John Otken, 23 Nov 2005 |
1143 | 1146 | ||
1144 | * Changed PPC44x startup message (cpu info, speed...) to common style: | 1147 | * Changed PPC44x startup message (cpu info, speed...) to common style: |
1145 | On PPC44x platforms, the startup message generated in "cpu.c" only | 1148 | On PPC44x platforms, the startup message generated in "cpu.c" only |
1146 | comprised the ppc type and revision but not additional information | 1149 | comprised the ppc type and revision but not additional information |
1147 | like speed etc. Those speed infos where printed in the board specific | 1150 | like speed etc. Those speed infos where printed in the board specific |
1148 | code. This new implementation now prints all CPU infos in the common | 1151 | code. This new implementation now prints all CPU infos in the common |
1149 | cpu specific code. No board specific code is needed anymore and | 1152 | cpu specific code. No board specific code is needed anymore and |
1150 | therefore removed from all current 44x implementations. | 1153 | therefore removed from all current 44x implementations. |
1151 | Patch by Stefan Roese, 27 Nov 2005 | 1154 | Patch by Stefan Roese, 27 Nov 2005 |
1152 | 1155 | ||
1153 | * Adjust TQM834x PHY addresses for latest hardware revision. | 1156 | * Adjust TQM834x PHY addresses for latest hardware revision. |
1154 | 1157 | ||
1155 | * Increase malloc arena on TQM5200 board to 256 kB. | 1158 | * Increase malloc arena on TQM5200 board to 256 kB. |
1156 | With 64 kb uniform flash sector size the old value of 128 kB was | 1159 | With 64 kb uniform flash sector size the old value of 128 kB was |
1157 | too small. | 1160 | too small. |
1158 | 1161 | ||
1159 | * Fix miiphy global data initialization (problem on 4xx boards when | 1162 | * Fix miiphy global data initialization (problem on 4xx boards when |
1160 | no ethaddr is assigned). Initialization moved from | 1163 | no ethaddr is assigned). Initialization moved from |
1161 | miiphy_register() to eth_initialize(). | 1164 | miiphy_register() to eth_initialize(). |
1162 | 1165 | ||
1163 | Based on initial patch for 4xx platform by Matthias Fuchs. | 1166 | Based on initial patch for 4xx platform by Matthias Fuchs. |
1164 | 1167 | ||
1165 | * Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h | 1168 | * Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h |
1166 | 1169 | ||
1167 | * Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code. | 1170 | * Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code. |
1168 | The COPYING file was extended to make clear that these files can be | 1171 | The COPYING file was extended to make clear that these files can be |
1169 | used in non-GPL code, too. | 1172 | used in non-GPL code, too. |
1170 | Also, a corresponding note was placed in the headers of the affected files. | 1173 | Also, a corresponding note was placed in the headers of the affected files. |
1171 | 1174 | ||
1172 | * Add support for Prodrive P3P440 board: | 1175 | * Add support for Prodrive P3P440 board: |
1173 | - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c | 1176 | - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c |
1174 | - CFG_FLASH_QUIET_TEST added to use the common CFI driver | 1177 | - CFG_FLASH_QUIET_TEST added to use the common CFI driver |
1175 | for bank autodetection | 1178 | for bank autodetection |
1176 | Patch by Stefan Roese, 22 Nov 2005 | 1179 | Patch by Stefan Roese, 22 Nov 2005 |
1177 | 1180 | ||
1178 | * Change all '$(...)' variable references into '${...}' | 1181 | * Change all '$(...)' variable references into '${...}' |
1179 | which makes the environment compatible with the hush shell. | 1182 | which makes the environment compatible with the hush shell. |
1180 | WARNING: Support for the old '$(...)' syntax will be | 1183 | WARNING: Support for the old '$(...)' syntax will be |
1181 | discontinued in a later version. | 1184 | discontinued in a later version. |
1182 | 1185 | ||
1183 | * Minor changes to init flags in TQM834x PCI. | 1186 | * Minor changes to init flags in TQM834x PCI. |
1184 | 1187 | ||
1185 | * Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM) | 1188 | * Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM) |
1186 | Patch by Stefan Roese, 15 Nov 2005 | 1189 | Patch by Stefan Roese, 15 Nov 2005 |
1187 | 1190 | ||
1188 | * New PPC 405EP board added: CMS700 | 1191 | * New PPC 405EP board added: CMS700 |
1189 | Added CONFIG_NET_MULTI for VOM405 board. | 1192 | Added CONFIG_NET_MULTI for VOM405 board. |
1190 | Added reset_phy() for VOM405 board. | 1193 | Added reset_phy() for VOM405 board. |
1191 | Patch by Matthias Fuchs, 09 Nov 2005 | 1194 | Patch by Matthias Fuchs, 09 Nov 2005 |
1192 | 1195 | ||
1193 | * Updated PCI mapping for esd CPCI2DP board. | 1196 | * Updated PCI mapping for esd CPCI2DP board. |
1194 | Add support for error LED. | 1197 | Add support for error LED. |
1195 | Patch by Matthias Fuchs, 07 Nov 2005 | 1198 | Patch by Matthias Fuchs, 07 Nov 2005 |
1196 | 1199 | ||
1197 | * Fix MPC85xx PCI support (pci_register_hose() before pci config access) | 1200 | * Fix MPC85xx PCI support (pci_register_hose() before pci config access) |
1198 | Patch by Stefan Roese, 07 Nov 2005 | 1201 | Patch by Stefan Roese, 07 Nov 2005 |
1199 | 1202 | ||
1200 | * Correct PPC Timebase register definitions (SPRN_TBRL...) | 1203 | * Correct PPC Timebase register definitions (SPRN_TBRL...) |
1201 | Patch by Stefan Roese, 07 Nov 2005 | 1204 | Patch by Stefan Roese, 07 Nov 2005 |
1202 | 1205 | ||
1203 | * Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size | 1206 | * Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size |
1204 | Patch by Stefan Roese, 05 Nov 2005 | 1207 | Patch by Stefan Roese, 05 Nov 2005 |
1205 | 1208 | ||
1206 | * Additional fix for external IRQ config on Yellowstone & Yosemite | 1209 | * Additional fix for external IRQ config on Yellowstone & Yosemite |
1207 | Patch by Stefan Roese, 03 Nov 2005 | 1210 | Patch by Stefan Roese, 03 Nov 2005 |
1208 | 1211 | ||
1209 | * Add support for Ocotea pass 3 with 440GX Rev. F | 1212 | * Add support for Ocotea pass 3 with 440GX Rev. F |
1210 | Patch by Stefan Roese, 01 Nov 2005 | 1213 | Patch by Stefan Roese, 01 Nov 2005 |
1211 | 1214 | ||
1212 | * Fix external IRQ configuration on Yellowstone & Yosemite | 1215 | * Fix external IRQ configuration on Yellowstone & Yosemite |
1213 | Patch by Stefan Roese, 28 Oct 2005 | 1216 | Patch by Stefan Roese, 28 Oct 2005 |
1214 | 1217 | ||
1215 | * Add support for multiple PHYs. | 1218 | * Add support for multiple PHYs. |
1216 | Tested on the following boards: | 1219 | Tested on the following boards: |
1217 | cmcpu2 (at91rm9200/ether.c) | 1220 | cmcpu2 (at91rm9200/ether.c) |
1218 | PPChameleon (ppc4xx/4xx_enet.c) | 1221 | PPChameleon (ppc4xx/4xx_enet.c) |
1219 | yukon (mpc8220/fec.c) | 1222 | yukon (mpc8220/fec.c) |
1220 | uc100 (mpc8xx/fec.c) | 1223 | uc100 (mpc8xx/fec.c) |
1221 | tqm834x (mpc834x/tsec.c) with EEPRO100 | 1224 | tqm834x (mpc834x/tsec.c) with EEPRO100 |
1222 | lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) | 1225 | lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) |
1223 | Main changes include: | 1226 | Main changes include: |
1224 | common/miiphyutil.c | 1227 | common/miiphyutil.c |
1225 | - miiphy_register routine was added to allow multiple PHYs to be registered | 1228 | - miiphy_register routine was added to allow multiple PHYs to be registered |
1226 | - miiphy_read and miiphy_write are now defined in this file, and | 1229 | - miiphy_read and miiphy_write are now defined in this file, and |
1227 | require additional argument (char *devname) | 1230 | require additional argument (char *devname) |
1228 | - other miiphy_* routines also require additional device name argument | 1231 | - other miiphy_* routines also require additional device name argument |
1229 | ../lib_i386/board.c | 1232 | ../lib_i386/board.c |
1230 | ../lib_ppc/board.c | 1233 | ../lib_ppc/board.c |
1231 | Calling reset_phy() was moved to be executed *after* eth_initialize(). | 1234 | Calling reset_phy() was moved to be executed *after* eth_initialize(). |
1232 | This is necessary as now some of the implementations of reset_phy() | 1235 | This is necessary as now some of the implementations of reset_phy() |
1233 | may need to use miiphy_reset() which is not allowed before eth_initialize() | 1236 | may need to use miiphy_reset() which is not allowed before eth_initialize() |
1234 | as eth_initialize registers all required miiphy_* routines. | 1237 | as eth_initialize registers all required miiphy_* routines. |
1235 | Tested on IP860 and PHY initializes properly after this change. | 1238 | Tested on IP860 and PHY initializes properly after this change. |
1236 | 1239 | ||
1237 | * Correct includes for flat tree builder. | 1240 | * Correct includes for flat tree builder. |
1238 | 1241 | ||
1239 | * Fix conflicting types (flash_write()) in trab auto_update.c. | 1242 | * Fix conflicting types (flash_write()) in trab auto_update.c. |
1240 | 1243 | ||
1241 | * Add PCI support for the TQM834x board. | 1244 | * Add PCI support for the TQM834x board. |
1242 | 1245 | ||
1243 | * Add missing 4xx board to MAKEALL | 1246 | * Add missing 4xx board to MAKEALL |
1244 | Patch by Stefan Roese, 20 Oct 2005 | 1247 | Patch by Stefan Roese, 20 Oct 2005 |
1245 | 1248 | ||
1246 | * Fix conflicting types (flash_write()) in esd auto_update.c | 1249 | * Fix conflicting types (flash_write()) in esd auto_update.c |
1247 | Patch by Stefan Roese, 20 Oct 2005 | 1250 | Patch by Stefan Roese, 20 Oct 2005 |
1248 | 1251 | ||
1249 | * Fix problem with sleep in NetConsole (use get_timer()) | 1252 | * Fix problem with sleep in NetConsole (use get_timer()) |
1250 | Patch by Stefan Roese, 20 Oct 2005 | 1253 | Patch by Stefan Roese, 20 Oct 2005 |
1251 | 1254 | ||
1252 | * Add NetConsole Support for AMCC eval boards | 1255 | * Add NetConsole Support for AMCC eval boards |
1253 | Patch by Stefan Roese, 20 Oct 2005 | 1256 | Patch by Stefan Roese, 20 Oct 2005 |
1254 | 1257 | ||
1255 | * Fix NetConsole support on 4xx (only print eth link on 1st transfer) | 1258 | * Fix NetConsole support on 4xx (only print eth link on 1st transfer) |
1256 | Patch by Stefan Roese, 18 Oct 2005 | 1259 | Patch by Stefan Roese, 18 Oct 2005 |
1257 | 1260 | ||
1258 | * Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo. | 1261 | * Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo. |
1259 | Fix identation on ext2ls help entry. | 1262 | Fix identation on ext2ls help entry. |
1260 | Patch by Stefan Roese, 14 Oct 2005 | 1263 | Patch by Stefan Roese, 14 Oct 2005 |
1261 | 1264 | ||
1262 | * Add support for TQM834x boards. | 1265 | * Add support for TQM834x boards. |
1263 | Cleanup. | 1266 | Cleanup. |
1264 | 1267 | ||
1265 | * Cleanup for GCC-4.x | 1268 | * Cleanup for GCC-4.x |
1266 | 1269 | ||
1267 | * Add documentation for Open Firmware Flat Tree and usage. | 1270 | * Add documentation for Open Firmware Flat Tree and usage. |
1268 | Patch by Pantelis Antoniou, 13 Oct 2005 | 1271 | Patch by Pantelis Antoniou, 13 Oct 2005 |
1269 | 1272 | ||
1270 | * Add missing files for Pantelis Antoniou's patch | 1273 | * Add missing files for Pantelis Antoniou's patch |
1271 | Patch by Pantelis Antoniou, 04 Sep 2005 | 1274 | Patch by Pantelis Antoniou, 04 Sep 2005 |
1272 | 1275 | ||
1273 | * Fix problem in ppc4xx eth-driver without ethaddr (only without | 1276 | * Fix problem in ppc4xx eth-driver without ethaddr (only without |
1274 | CONFIG_NET_MULTI set) | 1277 | CONFIG_NET_MULTI set) |
1275 | Patch by Stefan Roese, 10 Oct 2005 | 1278 | Patch by Stefan Roese, 10 Oct 2005 |
1276 | 1279 | ||
1277 | * Fix gzip bmp support (test if malloc fails, warning when truncated). | 1280 | * Fix gzip bmp support (test if malloc fails, warning when truncated). |
1278 | Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. | 1281 | Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. |
1279 | Patch by Stefan Roese, 07 Oct 2005 | 1282 | Patch by Stefan Roese, 07 Oct 2005 |
1280 | 1283 | ||
1281 | * Add support for OF flat tree for the STXtc board. | 1284 | * Add support for OF flat tree for the STXtc board. |
1282 | Patch by Pantelis Antoniou, 04 Sep 2005 | 1285 | Patch by Pantelis Antoniou, 04 Sep 2005 |
1283 | 1286 | ||
1284 | * Support passing of OF flat trees to the kernel. | 1287 | * Support passing of OF flat trees to the kernel. |
1285 | Patch by Pantelis Antoniou, 04 Sep 2005 | 1288 | Patch by Pantelis Antoniou, 04 Sep 2005 |
1286 | 1289 | ||
1287 | * Cleanup | 1290 | * Cleanup |
1288 | 1291 | ||
1289 | * Add support for NetSilicon NS7520 processor. | 1292 | * Add support for NetSilicon NS7520 processor. |
1290 | Patch by Art Shipkowski, 12 May 2005 | 1293 | Patch by Art Shipkowski, 12 May 2005 |
1291 | 1294 | ||
1292 | * Add support for AP1000 board. | 1295 | * Add support for AP1000 board. |
1293 | Patch by James MacAulay, 07 Oct 2005 | 1296 | Patch by James MacAulay, 07 Oct 2005 |
1294 | 1297 | ||
1295 | * Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 | 1298 | * Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 |
1296 | Patch by Anders Larsen, 07 Oct 2005 | 1299 | Patch by Anders Larsen, 07 Oct 2005 |
1297 | 1300 | ||
1298 | The Atmel errata #11 states that the transfer buffer descriptor | 1301 | The Atmel errata #11 states that the transfer buffer descriptor |
1299 | table must be aligned on a 16-word boundary. As it turned out, this | 1302 | table must be aligned on a 16-word boundary. As it turned out, this |
1300 | is insufficient - it seems the table must be aligned on a boundary | 1303 | is insufficient - it seems the table must be aligned on a boundary |
1301 | at least as large as the table itself (in Linux this is not an | 1304 | at least as large as the table itself (in Linux this is not an |
1302 | issue - the table is aligned on a PAGE_SIZE (4096) boundary). | 1305 | issue - the table is aligned on a PAGE_SIZE (4096) boundary). |
1303 | 1306 | ||
1304 | * Fixed compilation for ARM when using a (standard) hard-FP toolchain | 1307 | * Fixed compilation for ARM when using a (standard) hard-FP toolchain |
1305 | Patch by Anders Larsen, 07 Oct 2005 | 1308 | Patch by Anders Larsen, 07 Oct 2005 |
1306 | 1309 | ||
1307 | * Cleanup warnings for cpu/arm720t & cpu/arm1136 files. | 1310 | * Cleanup warnings for cpu/arm720t & cpu/arm1136 files. |
1308 | sed the linker scripts, rather than pre-process them. | 1311 | sed the linker scripts, rather than pre-process them. |
1309 | Patch by Peter Pearse, 07 Oct 2005 | 1312 | Patch by Peter Pearse, 07 Oct 2005 |
1310 | 1313 | ||
1311 | * Update make target for ARM supported boards. | 1314 | * Update make target for ARM supported boards. |
1312 | Use lowlevel_init() instead of platformsetup() [rename]. | 1315 | Use lowlevel_init() instead of platformsetup() [rename]. |
1313 | Patch by Peter Pearse, 06 Oct 2005 | 1316 | Patch by Peter Pearse, 06 Oct 2005 |
1314 | 1317 | ||
1315 | * Fix booting from serial dataflash on AT91RM9200 | 1318 | * Fix booting from serial dataflash on AT91RM9200 |
1316 | Patch by Peter Menzebach, 29 Aug 2005 | 1319 | Patch by Peter Menzebach, 29 Aug 2005 |
1317 | 1320 | ||
1318 | * Add JFFS2 support for TRAB board | 1321 | * Add JFFS2 support for TRAB board |
1319 | Patch by Martin Krause, 25 Aug 2005 | 1322 | Patch by Martin Krause, 25 Aug 2005 |
1320 | 1323 | ||
1321 | * Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI | 1324 | * Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI |
1322 | Patch by Marcus Hall, 24 Aug 2005 | 1325 | Patch by Marcus Hall, 24 Aug 2005 |
1323 | 1326 | ||
1324 | * Fix the machine-id of the Cogent csb637 board | 1327 | * Fix the machine-id of the Cogent csb637 board |
1325 | Patch by Anders Larsen, 05 Oct 2005 | 1328 | Patch by Anders Larsen, 05 Oct 2005 |
1326 | 1329 | ||
1327 | * Complete support for the KwikByte KB920x boards | 1330 | * Complete support for the KwikByte KB920x boards |
1328 | Patch by Anders Larsen, 05 Oct 2005 | 1331 | Patch by Anders Larsen, 05 Oct 2005 |
1329 | 1332 | ||
1330 | * Set the AT91RM9200 clock to asynchronous mode | 1333 | * Set the AT91RM9200 clock to asynchronous mode |
1331 | Patch by Anders Larsen, 03 May 2005 | 1334 | Patch by Anders Larsen, 03 May 2005 |
1332 | 1335 | ||
1333 | * Set the AT91RM9200 clock to synchronous mode | 1336 | * Set the AT91RM9200 clock to synchronous mode |
1334 | Patch by Anders Larsen, 29 Apr 2005 | 1337 | Patch by Anders Larsen, 29 Apr 2005 |
1335 | 1338 | ||
1336 | * Add support for Cogent csb637 | 1339 | * Add support for Cogent csb637 |
1337 | Patch by Anders Larsen, 29 Apr 2005 | 1340 | Patch by Anders Larsen, 29 Apr 2005 |
1338 | 1341 | ||
1339 | * Fix dm9161.c initialization | 1342 | * Fix dm9161.c initialization |
1340 | Patch by Anders Larsen, 29 Apr 2005 | 1343 | Patch by Anders Larsen, 29 Apr 2005 |
1341 | 1344 | ||
1342 | * Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005 | 1345 | * Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005 |
1343 | (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5) | 1346 | (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5) |
1344 | 1347 | ||
1345 | * Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 | 1348 | * Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 |
1346 | Patch by Anders Larsen, 29 Apr 2005 | 1349 | Patch by Anders Larsen, 29 Apr 2005 |
1347 | 1350 | ||
1348 | * Fix device partition intialization for SystemACE disks. | 1351 | * Fix device partition intialization for SystemACE disks. |
1349 | Patch by Stephen Williams, 28 Apr 2005 | 1352 | Patch by Stephen Williams, 28 Apr 2005 |
1350 | 1353 | ||
1351 | * Added support for KwikByte KB920x boards (based on AT91RM9200) | 1354 | * Added support for KwikByte KB920x boards (based on AT91RM9200) |
1352 | Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005 | 1355 | Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005 |
1353 | 1356 | ||
1354 | * Add support for S29GL064M-R3 flash chip on xsengine board | 1357 | * Add support for S29GL064M-R3 flash chip on xsengine board |
1355 | Patch by Kurt Stremerch, 18 Apr 2005 | 1358 | Patch by Kurt Stremerch, 18 Apr 2005 |
1356 | 1359 | ||
1357 | * E500 update: repoint IVPR to RAM when code is relocated | 1360 | * E500 update: repoint IVPR to RAM when code is relocated |
1358 | Patch by Kylo Ginsberg, 13 Apr 2005 | 1361 | Patch by Kylo Ginsberg, 13 Apr 2005 |
1359 | 1362 | ||
1360 | * Fix loop end test in lib_generic/string.c:strswab() | 1363 | * Fix loop end test in lib_generic/string.c:strswab() |
1361 | Patch by Andrew Dyer, October 10, 2005 | 1364 | Patch by Andrew Dyer, October 10, 2005 |
1362 | Signed-off-by: Andrew Dyer <amdyer@gmail.com> | 1365 | Signed-off-by: Andrew Dyer <amdyer@gmail.com> |
1363 | 1366 | ||
1364 | * Cleanup | 1367 | * Cleanup |
1365 | 1368 | ||
1366 | * Update ARM Integrator boards: | 1369 | * Update ARM Integrator boards: |
1367 | Correct addessing errors in platform files. | 1370 | Correct addessing errors in platform files. |
1368 | Split off common core module data from Integrator header files to | 1371 | Split off common core module data from Integrator header files to |
1369 | include/armcoremodule.h. | 1372 | include/armcoremodule.h. |
1370 | Patch by Peter Pearse, 04 Oct 2005 | 1373 | Patch by Peter Pearse, 04 Oct 2005 |
1371 | 1374 | ||
1372 | * Make sure only supported compiler options are used | 1375 | * Make sure only supported compiler options are used |
1373 | Import "cc-option" shell function from kernel and | 1376 | Import "cc-option" shell function from kernel and |
1374 | use it to get the correct ARM GCC options for individual CPUs | 1377 | use it to get the correct ARM GCC options for individual CPUs |
1375 | Patch by Peter Pearse, 30 Jun 2005 | 1378 | Patch by Peter Pearse, 30 Jun 2005 |
1376 | 1379 | ||
1377 | * Fix 440GR to print correct cpu revision | 1380 | * Fix 440GR to print correct cpu revision |
1378 | Patch by Stefan Roese, 04 Oct 2005 | 1381 | Patch by Stefan Roese, 04 Oct 2005 |
1379 | 1382 | ||
1380 | * Change board message on AMCC Yosemite & Yellowstone to common style | 1383 | * Change board message on AMCC Yosemite & Yellowstone to common style |
1381 | Patch by Stefan Roese, 03 Oct 2005 | 1384 | Patch by Stefan Roese, 03 Oct 2005 |
1382 | 1385 | ||
1383 | * Fix compiler warning | 1386 | * Fix compiler warning |
1384 | 1387 | ||
1385 | * Fix FEC PHY addresses for TQM85xx boards | 1388 | * Fix FEC PHY addresses for TQM85xx boards |
1386 | 1389 | ||
1387 | * Fix uninitialized variable problem in hush shell | 1390 | * Fix uninitialized variable problem in hush shell |
1388 | Patch by Lars Rostock, 26 Sep 2005 | 1391 | Patch by Lars Rostock, 26 Sep 2005 |
1389 | 1392 | ||
1390 | * Undo change of f6e20fc6ca... to include/configs/trab.h | 1393 | * Undo change of f6e20fc6ca... to include/configs/trab.h |
1391 | (Must have been an accident?) | 1394 | (Must have been an accident?) |
1392 | 1395 | ||
1393 | * Add support for AT91RM9200 OHCI Controller. | 1396 | * Add support for AT91RM9200 OHCI Controller. |
1394 | Patch by Eric Benard, 07 Apr 2005 | 1397 | Patch by Eric Benard, 07 Apr 2005 |
1395 | 1398 | ||
1396 | * Update ARM mach-types.h | 1399 | * Update ARM mach-types.h |
1397 | Patch by Eric Benard, 07 Apr 2005 | 1400 | Patch by Eric Benard, 07 Apr 2005 |
1398 | 1401 | ||
1399 | * Add support for MP2USB board. | 1402 | * Add support for MP2USB board. |
1400 | Patch by Eric Benard, 07 Apr 2005 | 1403 | Patch by Eric Benard, 07 Apr 2005 |
1401 | 1404 | ||
1402 | * Add board support for armadillo HT1070 | 1405 | * Add board support for armadillo HT1070 |
1403 | Patch by Rowel Atienza, 06 Apr 2005 | 1406 | Patch by Rowel Atienza, 06 Apr 2005 |
1404 | 1407 | ||
1405 | * Second Ethernet address enabled for MPC885ADS and MPC8272ADS. | 1408 | * Second Ethernet address enabled for MPC885ADS and MPC8272ADS. |
1406 | Patch by Vitaly Bordug, 30 Mar 2005 | 1409 | Patch by Vitaly Bordug, 30 Mar 2005 |
1407 | 1410 | ||
1408 | * Add iopset command on mpc8xx | 1411 | * Add iopset command on mpc8xx |
1409 | Patch by Daniel Eisenhut, 25 Mar 2005 | 1412 | Patch by Daniel Eisenhut, 25 Mar 2005 |
1410 | 1413 | ||
1411 | * Add support for MII in eepro100 driver. | 1414 | * Add support for MII in eepro100 driver. |
1412 | Patch by Gleb Natapov, 21 Mar 2005 | 1415 | Patch by Gleb Natapov, 21 Mar 2005 |
1413 | 1416 | ||
1414 | * Fixes to the Lubbock (PXA 25x) support: | 1417 | * Fixes to the Lubbock (PXA 25x) support: |
1415 | - Resolve the FIXME with respect to saving the u-boot environment. | 1418 | - Resolve the FIXME with respect to saving the u-boot environment. |
1416 | - Make the default load address land in real memory. | 1419 | - Make the default load address land in real memory. |
1417 | - Fix lan91c96 SMC_{in,out}{b,w,l}() macros | 1420 | - Fix lan91c96 SMC_{in,out}{b,w,l}() macros |
1418 | Patch by David Brownell, 10 Mar 2005 | 1421 | Patch by David Brownell, 10 Mar 2005 |
1419 | 1422 | ||
1420 | * Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board | 1423 | * Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board |
1421 | Patch by Marc Leeman, 04 Mar 2005 | 1424 | Patch by Marc Leeman, 04 Mar 2005 |
1422 | 1425 | ||
1423 | * OMAP242x H4 board update | 1426 | * OMAP242x H4 board update |
1424 | - fix for ES2 differences. | 1427 | - fix for ES2 differences. |
1425 | - switch to using the cfi_flash driver. | 1428 | - switch to using the cfi_flash driver. |
1426 | - fix SRAM build address. | 1429 | - fix SRAM build address. |
1427 | - fix for GP device operation. | 1430 | - fix for GP device operation. |
1428 | - unlock SRAM for GP devices. | 1431 | - unlock SRAM for GP devices. |
1429 | - display more device information. | 1432 | - display more device information. |
1430 | - fix potential deadlock in omap24xx_i2c driver. | 1433 | - fix potential deadlock in omap24xx_i2c driver. |
1431 | - fix DLL load values to match dpllout*1 operation. | 1434 | - fix DLL load values to match dpllout*1 operation. |
1432 | - fix 2nd chip select init for combo DDR device. | 1435 | - fix 2nd chip select init for combo DDR device. |
1433 | - add support for CFI Intel 28F256L18 on H4 board. | 1436 | - add support for CFI Intel 28F256L18 on H4 board. |
1434 | Patch by Richard Woodruff, 03 Mar 2005 | 1437 | Patch by Richard Woodruff, 03 Mar 2005 |
1435 | 1438 | ||
1436 | * Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h | 1439 | * Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h |
1437 | Patch by Steven Scholz, 02 Mar 2005 | 1440 | Patch by Steven Scholz, 02 Mar 2005 |
1438 | 1441 | ||
1439 | * Fix typo in eth.c | 1442 | * Fix typo in eth.c |
1440 | Patch by Ara Avanesyan, 24 Feb 2005 | 1443 | Patch by Ara Avanesyan, 24 Feb 2005 |
1441 | 1444 | ||
1442 | * Remove unneeded #include <malloc.h> | 1445 | * Remove unneeded #include <malloc.h> |
1443 | Patch by Ladislav Michl, 22 Feb 2005 | 1446 | Patch by Ladislav Michl, 22 Feb 2005 |
1444 | 1447 | ||
1445 | * Add cramfs support for m68k | 1448 | * Add cramfs support for m68k |
1446 | Patch by Zachary Landau, 21 Feb 2005 | 1449 | Patch by Zachary Landau, 21 Feb 2005 |
1447 | 1450 | ||
1448 | * Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs | 1451 | * Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs |
1449 | Patch by Jeff Angielski, 21 Feb 2005 | 1452 | Patch by Jeff Angielski, 21 Feb 2005 |
1450 | 1453 | ||
1451 | * Fix au1x00_serial baud rate calculation: | 1454 | * Fix au1x00_serial baud rate calculation: |
1452 | remove hardcoded cpu clock divisor and use register instead; | 1455 | remove hardcoded cpu clock divisor and use register instead; |
1453 | round up instead of truncate | 1456 | round up instead of truncate |
1454 | Patch by Andrew Dyer, 15 Feb 2005 | 1457 | Patch by Andrew Dyer, 15 Feb 2005 |
1455 | 1458 | ||
1456 | * Add Xilinx Spartan3 family FPGA support | 1459 | * Add Xilinx Spartan3 family FPGA support |
1457 | Patch by Kurt Stremerch, 14 Feb 2005 | 1460 | Patch by Kurt Stremerch, 14 Feb 2005 |
1458 | 1461 | ||
1459 | * Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET | 1462 | * Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET |
1460 | Patch by Zachary Landau, 11 Feb 2005 | 1463 | Patch by Zachary Landau, 11 Feb 2005 |
1461 | 1464 | ||
1462 | * Fix VOH405 Support | 1465 | * Fix VOH405 Support |
1463 | Patch by Matthias Fuchs, 25 Sep 2005 | 1466 | Patch by Matthias Fuchs, 25 Sep 2005 |
1464 | 1467 | ||
1465 | * Added support for PCI bridge on MPC8272ADS | 1468 | * Added support for PCI bridge on MPC8272ADS |
1466 | Patch by Vitaly Bordug, Feb 09 2005 | 1469 | Patch by Vitaly Bordug, Feb 09 2005 |
1467 | 1470 | ||
1468 | * Update multicore CM9XX support for Integrator AP to allow booting from flash | 1471 | * Update multicore CM9XX support for Integrator AP to allow booting from flash |
1469 | Patch by Jean-Paul Saman, 8 Feb 2005 | 1472 | Patch by Jean-Paul Saman, 8 Feb 2005 |
1470 | 1473 | ||
1471 | * Fix strswab() to reliably find end of string | 1474 | * Fix strswab() to reliably find end of string |
1472 | Patch by Andrew Dyer, 08 Feb 2005 | 1475 | Patch by Andrew Dyer, 08 Feb 2005 |
1473 | 1476 | ||
1474 | * Fix typos in include/ppc440.h | 1477 | * Fix typos in include/ppc440.h |
1475 | Patch by Andrew E Mileski, 04 Feb 2005 | 1478 | Patch by Andrew E Mileski, 04 Feb 2005 |
1476 | 1479 | ||
1477 | * Add Vibren (was Accelent) PXA255 IDP Support | 1480 | * Add Vibren (was Accelent) PXA255 IDP Support |
1478 | Patch by Cliff Brake, 04 Feb 2005 | 1481 | Patch by Cliff Brake, 04 Feb 2005 |
1479 | 1482 | ||
1480 | * Fix tools/bmp_logo.c using incorrect offset to pixel data | 1483 | * Fix tools/bmp_logo.c using incorrect offset to pixel data |
1481 | Patch by Andrew Dyer, 31 Jan 2005 | 1484 | Patch by Andrew Dyer, 31 Jan 2005 |
1482 | 1485 | ||
1483 | * Add ARM946E cpu and core module targets; remap memory to 0x00000000 | 1486 | * Add ARM946E cpu and core module targets; remap memory to 0x00000000 |
1484 | Patch by Peter Pearse, 2 Feb 2005 | 1487 | Patch by Peter Pearse, 2 Feb 2005 |
1485 | 1488 | ||
1486 | * Fix error handling in tools/env/fw_env.c | 1489 | * Fix error handling in tools/env/fw_env.c |
1487 | Patch by Ara Avanesyan, 01 Feb 2005 | 1490 | Patch by Ara Avanesyan, 01 Feb 2005 |
1488 | 1491 | ||
1489 | * Fix MGT5100 PSC baudrate calculation | 1492 | * Fix MGT5100 PSC baudrate calculation |
1490 | Patch by Sebastian Schau, 27 Jan 2005 | 1493 | Patch by Sebastian Schau, 27 Jan 2005 |
1491 | 1494 | ||
1492 | * OMAP242x fix for GP device booting | 1495 | * OMAP242x fix for GP device booting |
1493 | - Add SRAM unlock for GP devices. | 1496 | - Add SRAM unlock for GP devices. |
1494 | - Change DDR DLL unlock value to allow DPLLout*1 operation. | 1497 | - Change DDR DLL unlock value to allow DPLLout*1 operation. |
1495 | Patches by Richard Woodruff, 21 Jan 2005: | 1498 | Patches by Richard Woodruff, 21 Jan 2005: |
1496 | 1499 | ||
1497 | * Add support for AMD's Pb1x00 eval board; | 1500 | * Add support for AMD's Pb1x00 eval board; |
1498 | add MII routines to the au1x00 ethernet driver; | 1501 | add MII routines to the au1x00 ethernet driver; |
1499 | add USB ohci driver (work in progress) | 1502 | add USB ohci driver (work in progress) |
1500 | Patch by Thomas Sailer, 20 Jan 2005 | 1503 | Patch by Thomas Sailer, 20 Jan 2005 |
1501 | 1504 | ||
1502 | * Update omap5912osk board | 1505 | * Update omap5912osk board |
1503 | Use drivers/cfi_flash.c instead of private flash driver; | 1506 | Use drivers/cfi_flash.c instead of private flash driver; |
1504 | Remove hardcoded personalized settings from omap5912osk.h; | 1507 | Remove hardcoded personalized settings from omap5912osk.h; |
1505 | Fix spacing with (RO) marks in 'flinfo' output. | 1508 | Fix spacing with (RO) marks in 'flinfo' output. |
1506 | Patch by Michael Bendzick, 14 Jan 2005 | 1509 | Patch by Michael Bendzick, 14 Jan 2005 |
1507 | 1510 | ||
1508 | * Fix warnings for PCI code on ixp | 1511 | * Fix warnings for PCI code on ixp |
1509 | Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005 | 1512 | Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005 |
1510 | 1513 | ||
1511 | * virtex2 fix for bogus download error messages | 1514 | * virtex2 fix for bogus download error messages |
1512 | The virtex2 FPGA download code watches for init going active during | 1515 | The virtex2 FPGA download code watches for init going active during |
1513 | a download of config data as an error condition. init also goes | 1516 | a download of config data as an error condition. init also goes |
1514 | active after a configuration is finished in concert with the done | 1517 | active after a configuration is finished in concert with the done |
1515 | signal. So far, the code does not check for done active until all | 1518 | signal. So far, the code does not check for done active until all |
1516 | of the configuration data is sent. If configuration data has a few | 1519 | of the configuration data is sent. If configuration data has a few |
1517 | extra pad bytes at the end, this would cause an error message even | 1520 | extra pad bytes at the end, this would cause an error message even |
1518 | though the download had suceeded. | 1521 | though the download had suceeded. |
1519 | NOTE: virtex2 slave serial and spartan2 versions may still have the | 1522 | NOTE: virtex2 slave serial and spartan2 versions may still have the |
1520 | same problem. | 1523 | same problem. |
1521 | Patch by Andrew Dyer, 12 Jan 2005 | 1524 | Patch by Andrew Dyer, 12 Jan 2005 |
1522 | 1525 | ||
1523 | * Optimize flash_make_cmd in drivers/cfi_flash.c for little endian | 1526 | * Optimize flash_make_cmd in drivers/cfi_flash.c for little endian |
1524 | Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode" | 1527 | Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode" |
1525 | message when probing for nonexistent flash in little endian mode. | 1528 | message when probing for nonexistent flash in little endian mode. |
1526 | As a side effect more efficient and smaller code is generated, | 1529 | As a side effect more efficient and smaller code is generated, |
1527 | which is always a Good Thing (TM). | 1530 | which is always a Good Thing (TM). |
1528 | Patch by Ladislav Michl, 24 Sep 2005 | 1531 | Patch by Ladislav Michl, 24 Sep 2005 |
1529 | 1532 | ||
1530 | * Update for TFTP using a fixed UDP port | 1533 | * Update for TFTP using a fixed UDP port |
1531 | Use the approved environment variable names. Added "tftpdstp" to | 1534 | Use the approved environment variable names. Added "tftpdstp" to |
1532 | allow ports other than 69 per Tolunay Orkun's recommendation. | 1535 | allow ports other than 69 per Tolunay Orkun's recommendation. |
1533 | Patch by Jerry Van Baren, 12 Jan 2005 | 1536 | Patch by Jerry Van Baren, 12 Jan 2005 |
1534 | 1537 | ||
1535 | * Allow to force TFTP to use a fixed UDP port | 1538 | * Allow to force TFTP to use a fixed UDP port |
1536 | (Add a configuration option CONFIG_TFTP_PORT and optional env | 1539 | (Add a configuration option CONFIG_TFTP_PORT and optional env |
1537 | variable tftpport) | 1540 | variable tftpport) |
1538 | Patch by Jerry Van Baren, 10 Jan 2005 | 1541 | Patch by Jerry Van Baren, 10 Jan 2005 |
1539 | 1542 | ||
1540 | * Fix ethernet timeouts on dbau1550 and other au1x00 systems | 1543 | * Fix ethernet timeouts on dbau1550 and other au1x00 systems |
1541 | Patch by Leif Lindholm, 29 Dec 2004 | 1544 | Patch by Leif Lindholm, 29 Dec 2004 |
1542 | 1545 | ||
1543 | * Cleanup: fix broken builds | 1546 | * Cleanup: fix broken builds |
1544 | 1547 | ||
1545 | * Fix PHY address argument passing with mii info command | 1548 | * Fix PHY address argument passing with mii info command |
1546 | Patch by Andrew Dyer, 28 Dec 2004 | 1549 | Patch by Andrew Dyer, 28 Dec 2004 |
1547 | 1550 | ||
1548 | * Cleanup (PPC4xx is AMCC now) | 1551 | * Cleanup (PPC4xx is AMCC now) |
1549 | 1552 | ||
1550 | * esd CPCI2DP board added | 1553 | * esd CPCI2DP board added |
1551 | Patch by Matthias Fuchs, 22 Sep 2005 | 1554 | Patch by Matthias Fuchs, 22 Sep 2005 |
1552 | 1555 | ||
1553 | * esd PMC405 board updated | 1556 | * esd PMC405 board updated |
1554 | Patch by Matthias Fuchs, 22 Sep 2005 | 1557 | Patch by Matthias Fuchs, 22 Sep 2005 |
1555 | 1558 | ||
1556 | * Add SM501 support to HH405 board. | 1559 | * Add SM501 support to HH405 board. |
1557 | Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP). | 1560 | Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP). |
1558 | Add support for eeprom write-enable (CFG_EEPROM_WREN). | 1561 | Add support for eeprom write-enable (CFG_EEPROM_WREN). |
1559 | Patch by Stefan Roese, 22 Sep 2005 | 1562 | Patch by Stefan Roese, 22 Sep 2005 |
1560 | 1563 | ||
1561 | * Fix autonegotiation in tsec ethernet driver | 1564 | * Fix autonegotiation in tsec ethernet driver |
1562 | Patch by Stefan Roese, 21 Sep 2005 | 1565 | Patch by Stefan Roese, 21 Sep 2005 |
1563 | 1566 | ||
1564 | * Fix bug in auto_update (trab board) | 1567 | * Fix bug in auto_update (trab board) |
1565 | Patch by Martin Krause, 16 Sep 2005 | 1568 | Patch by Martin Krause, 16 Sep 2005 |
1566 | 1569 | ||
1567 | * Fix computation of framebuffer palette for 8bpp LCD bitmaps | 1570 | * Fix computation of framebuffer palette for 8bpp LCD bitmaps |
1568 | Patch by Francesco Mandracci, 16 Sep 2005 | 1571 | Patch by Francesco Mandracci, 16 Sep 2005 |
1569 | 1572 | ||
1570 | * Update configuration for INKA4x0 board | 1573 | * Update configuration for INKA4x0 board |
1571 | 1574 | ||
1572 | * Update configuration for PM854 board | 1575 | * Update configuration for PM854 board |
1573 | Based on patch by R. Loeffl, 20 Jul 2005 | 1576 | Based on patch by R. Loeffl, 20 Jul 2005 |
1574 | 1577 | ||
1575 | * Add PCI support to TQM8540 and TQM8560 boards | 1578 | * Add PCI support to TQM8540 and TQM8560 boards |
1576 | Patch by Stefan Roese, 15 Sep 2005 | 1579 | Patch by Stefan Roese, 15 Sep 2005 |
1577 | 1580 | ||
1578 | * Update AMCC Yosemite to get a consistent setup for all AMCC eval | 1581 | * Update AMCC Yosemite to get a consistent setup for all AMCC eval |
1579 | boards (baudrate, environment...). Flash driver fixed. | 1582 | boards (baudrate, environment...). Flash driver fixed. |
1580 | Patch by Stefan Roese, 15 Sep 2005 | 1583 | Patch by Stefan Roese, 15 Sep 2005 |
1581 | 1584 | ||
1582 | * Fix problem in 440GP ethernet driver (ebony). Add support for 2nd | 1585 | * Fix problem in 440GP ethernet driver (ebony). Add support for 2nd |
1583 | ethernet port on ebony. | 1586 | ethernet port on ebony. |
1584 | Patch by Stefan Roese, 7 Sep 2005 | 1587 | Patch by Stefan Roese, 7 Sep 2005 |
1585 | 1588 | ||
1586 | * Added support for mtddevnum and mtddevname variables (mtdparts command) | 1589 | * Added support for mtddevnum and mtddevname variables (mtdparts command) |
1587 | 1590 | ||
1588 | * Change default console baud rate for stxxtc board | 1591 | * Change default console baud rate for stxxtc board |
1589 | 1592 | ||
1590 | * Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT). | 1593 | * Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT). |
1591 | Patch by Stefan Roese, 31 Aug 2005 | 1594 | Patch by Stefan Roese, 31 Aug 2005 |
1592 | 1595 | ||
1593 | * Fix default command set (don't include CFG_CMD_DISPLAY command) | 1596 | * Fix default command set (don't include CFG_CMD_DISPLAY command) |
1594 | Patch by Pantelis Antoniou, 02 Sep 2005 | 1597 | Patch by Pantelis Antoniou, 02 Sep 2005 |
1595 | 1598 | ||
1596 | * Cleanup | 1599 | * Cleanup |
1597 | 1600 | ||
1598 | * Enable SM712 driver support for HMI1001 board. | 1601 | * Enable SM712 driver support for HMI1001 board. |
1599 | 1602 | ||
1600 | * Fix problems with ld version 2.16 (dot outside sections problem) | 1603 | * Fix problems with ld version 2.16 (dot outside sections problem) |
1601 | Pointed out by Gerhard Jaeger, 31 Aug 2005; | 1604 | Pointed out by Gerhard Jaeger, 31 Aug 2005; |
1602 | cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html | 1605 | cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html |
1603 | 1606 | ||
1604 | * Prepare U-Boot for gcc-4.x: fix global data pointer initialization | 1607 | * Prepare U-Boot for gcc-4.x: fix global data pointer initialization |
1605 | 1608 | ||
1606 | * Adjust CS3 timings on HMI1001 board for dot matrix display under Linux | 1609 | * Adjust CS3 timings on HMI1001 board for dot matrix display under Linux |
1607 | 1610 | ||
1608 | * Add keyboard and dot matrix display support for HMI1001 board. | 1611 | * Add keyboard and dot matrix display support for HMI1001 board. |
1609 | 1612 | ||
1610 | * Prepare U-Boot for gcc-4.x | 1613 | * Prepare U-Boot for gcc-4.x |
1611 | 1614 | ||
1612 | * Fixed Bamboo port to enable running without DDR-DIMM | 1615 | * Fixed Bamboo port to enable running without DDR-DIMM |
1613 | (Bamboo has also 64MB onboard DDR) | 1616 | (Bamboo has also 64MB onboard DDR) |
1614 | Patch by Stefan Roese, 24 Aug 2005 | 1617 | Patch by Stefan Roese, 24 Aug 2005 |
1615 | 1618 | ||
1616 | * Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | 1619 | * Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c |
1617 | now handling all 4xx cpu's | 1620 | now handling all 4xx cpu's |
1618 | Patch by Stefan Roese, 16 Aug 2005 | 1621 | Patch by Stefan Roese, 16 Aug 2005 |
1619 | 1622 | ||
1620 | * Fix make dependencies for at91rm9200 and ks8695 cpus | 1623 | * Fix make dependencies for at91rm9200 and ks8695 cpus |
1621 | Patch by Steven Scholz, 23 Aug 2005 | 1624 | Patch by Steven Scholz, 23 Aug 2005 |
1622 | 1625 | ||
1623 | * Add JFFS2 support for TQM5200 board | 1626 | * Add JFFS2 support for TQM5200 board |
1624 | 1627 | ||
1625 | * Add esd cpci5200 and pf5200 boards | 1628 | * Add esd cpci5200 and pf5200 boards |
1626 | Patch by Reinhard Arlt, 22 Aug 2005 | 1629 | Patch by Reinhard Arlt, 22 Aug 2005 |
1627 | 1630 | ||
1628 | * Fix sysclock for TQM8540 and TQM8560 boards | 1631 | * Fix sysclock for TQM8540 and TQM8560 boards |
1629 | Patch by Martin Krause, 25 Jul 2005 | 1632 | Patch by Martin Krause, 25 Jul 2005 |
1630 | 1633 | ||
1631 | * Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2 | 1634 | * Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2 |
1632 | Patch by Martin Krause, 08 Jun 2005 | 1635 | Patch by Martin Krause, 08 Jun 2005 |
1633 | 1636 | ||
1634 | * Add new board specific commands for TQM5200/STK52XX | 1637 | * Add new board specific commands for TQM5200/STK52XX |
1635 | - Sound commands (beep, wav, sound) | 1638 | - Sound commands (beep, wav, sound) |
1636 | - Test commands (led, can, backlight, rs232) | 1639 | - Test commands (led, can, backlight, rs232) |
1637 | Patch by Martin Krause, 02 May 2005 | 1640 | Patch by Martin Krause, 02 May 2005 |
1638 | 1641 | ||
1639 | * Change main clock on CMC-PU2 board from 207 MHz to 179 MHz | 1642 | * Change main clock on CMC-PU2 board from 207 MHz to 179 MHz |
1640 | because of a bug in the AT91RM9200 CPU PLL | 1643 | because of a bug in the AT91RM9200 CPU PLL |
1641 | Patch by Martin Krause, 22 Apr 2005 | 1644 | Patch by Martin Krause, 22 Apr 2005 |
1642 | 1645 | ||
1643 | * Add automatic HW detection for another CMC_PU2 variant | 1646 | * Add automatic HW detection for another CMC_PU2 variant |
1644 | Patch by Martin Krause, 20 Apr 2005 | 1647 | Patch by Martin Krause, 20 Apr 2005 |
1645 | 1648 | ||
1646 | * Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration | 1649 | * Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration |
1647 | Patch by Martin Krause, 19 Apr 2005 | 1650 | Patch by Martin Krause, 19 Apr 2005 |
1648 | 1651 | ||
1649 | * Fix initialization problem on TQM5200 without SM501 | 1652 | * Fix initialization problem on TQM5200 without SM501 |
1650 | Patch by Martin Krause, 08 Apr 2005 | 1653 | Patch by Martin Krause, 08 Apr 2005 |
1651 | 1654 | ||
1652 | * Add RTC support for STK52XX.200 | 1655 | * Add RTC support for STK52XX.200 |
1653 | Patch by Martin Krause, 07 Apr 2005 | 1656 | Patch by Martin Krause, 07 Apr 2005 |
1654 | 1657 | ||
1655 | * Add support for IFM o2dnt board | 1658 | * Add support for IFM o2dnt board |
1656 | 1659 | ||
1657 | * Enable PCI on hmi1001 board | 1660 | * Enable PCI on hmi1001 board |
1658 | 1661 | ||
1659 | * Fix return values of the jffs2 commands ls/fsload/fsinfo, | 1662 | * Fix return values of the jffs2 commands ls/fsload/fsinfo, |
1660 | so we can use them to, e.g., check the existence of a file with | 1663 | so we can use them to, e.g., check the existence of a file with |
1661 | "if ls foo; then this; else that; fi" in the hush shell | 1664 | "if ls foo; then this; else that; fi" in the hush shell |
1662 | Patch by Andreas Engel, 16 August 2005 | 1665 | Patch by Andreas Engel, 16 August 2005 |
1663 | 1666 | ||
1664 | * Coding style cleanup | 1667 | * Coding style cleanup |
1665 | 1668 | ||
1666 | * Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. | 1669 | * Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. |
1667 | Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005 | 1670 | Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005 |
1668 | 1671 | ||
1669 | * Check return value of malloc in 440gx_enet.c | 1672 | * Check return value of malloc in 440gx_enet.c |
1670 | Patch by Travis B. Sawyer, 18 Jul 2005 | 1673 | Patch by Travis B. Sawyer, 18 Jul 2005 |
1671 | 1674 | ||
1672 | * Add Sandburst Metrobox and Sandburst Karef board support packages. | 1675 | * Add Sandburst Metrobox and Sandburst Karef board support packages. |
1673 | Second serial port on 440GX now defined as a system device. | 1676 | Second serial port on 440GX now defined as a system device. |
1674 | Add 'Short Etch' code for Cicada PHY within 440gx_enet.c | 1677 | Add 'Short Etch' code for Cicada PHY within 440gx_enet.c |
1675 | Patch by Travis B. Sawyer, 12 Jul 2005 | 1678 | Patch by Travis B. Sawyer, 12 Jul 2005 |
1676 | 1679 | ||
1677 | ====================================================================== | 1680 | ====================================================================== |
1678 | Changes for U-Boot 1.1.3: | 1681 | Changes for U-Boot 1.1.3: |
1679 | ====================================================================== | 1682 | ====================================================================== |
1680 | 1683 | ||
1681 | * Minor code cleanup | 1684 | * Minor code cleanup |
1682 | 1685 | ||
1683 | * Add forgotten new fils from latest VoiceBlue update | 1686 | * Add forgotten new fils from latest VoiceBlue update |
1684 | 1687 | ||
1685 | * Make bootretry feature work with hush shell. | 1688 | * Make bootretry feature work with hush shell. |
1686 | Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too. | 1689 | Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too. |
1687 | Patch by Andreas Engel, 19 Jul 2005 | 1690 | Patch by Andreas Engel, 19 Jul 2005 |
1688 | 1691 | ||
1689 | * Update Hymod Board Database PHP code in "tools" directory | 1692 | * Update Hymod Board Database PHP code in "tools" directory |
1690 | Patch by Murray Jensen, 01 Jul 2005 | 1693 | Patch by Murray Jensen, 01 Jul 2005 |
1691 | 1694 | ||
1692 | * Make "tr" command use POSIX compliant; export HOSTOS make variable | 1695 | * Make "tr" command use POSIX compliant; export HOSTOS make variable |
1693 | Patch by Murray Jensen, 30 Jun 2005 | 1696 | Patch by Murray Jensen, 30 Jun 2005 |
1694 | 1697 | ||
1695 | * Fix Murray Jensen's mail address. | 1698 | * Fix Murray Jensen's mail address. |
1696 | Patch by Murray Jensen, 30 Jun 2005 | 1699 | Patch by Murray Jensen, 30 Jun 2005 |
1697 | 1700 | ||
1698 | * Preserve PHY_BMCR during a soft reset. | 1701 | * Preserve PHY_BMCR during a soft reset. |
1699 | Patch by Carl Riechers, 24 Jun 2005 | 1702 | Patch by Carl Riechers, 24 Jun 2005 |
1700 | 1703 | ||
1701 | * VoiceBlue update: eeprom tool can also store firmware version now. | 1704 | * VoiceBlue update: eeprom tool can also store firmware version now. |
1702 | eeprom.bin is runable by jumping at load address. | 1705 | eeprom.bin is runable by jumping at load address. |
1703 | Patch by Ladislav Michl, 23 May 2005 | 1706 | Patch by Ladislav Michl, 23 May 2005 |
1704 | 1707 | ||
1705 | * Move the AT91RM9200DK to the ARM Systems list. | 1708 | * Move the AT91RM9200DK to the ARM Systems list. |
1706 | Patch by Anders Larsen, 26 Apr 2005 | 1709 | Patch by Anders Larsen, 26 Apr 2005 |
1707 | 1710 | ||
1708 | * Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3 | 1711 | * Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3 |
1709 | Patch by Anders Larsen, 26 Apr 2005 | 1712 | Patch by Anders Larsen, 26 Apr 2005 |
1710 | 1713 | ||
1711 | * measure_gclk() is needed when DEBUG is enabled | 1714 | * measure_gclk() is needed when DEBUG is enabled |
1712 | Patch by Bryan O'Donoghue, 25 Apr 2005 | 1715 | Patch by Bryan O'Donoghue, 25 Apr 2005 |
1713 | 1716 | ||
1714 | * Add UPD-Checksum code, fix problem in net.c (return instead of break) | 1717 | * Add UPD-Checksum code, fix problem in net.c (return instead of break) |
1715 | Patch by Reinhard Arlt, 12 Aug 2005 | 1718 | Patch by Reinhard Arlt, 12 Aug 2005 |
1716 | 1719 | ||
1717 | * esd PCI405 board updated | 1720 | * esd PCI405 board updated |
1718 | Patch by Matthias Fuchs, 28 Jul 2005 | 1721 | Patch by Matthias Fuchs, 28 Jul 2005 |
1719 | 1722 | ||
1720 | * esd WUH405 and DU405 board updated | 1723 | * esd WUH405 and DU405 board updated |
1721 | Patch by Matthias Fuchs, 27 Jul 2005 | 1724 | Patch by Matthias Fuchs, 27 Jul 2005 |
1722 | 1725 | ||
1723 | * Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I) | 1726 | * Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I) |
1724 | Patch by Matthias Fuchs, 4 May 2005 | 1727 | Patch by Matthias Fuchs, 4 May 2005 |
1725 | 1728 | ||
1726 | * Update AMCC Yosemite to get a consistent setup for all AMCC eval | 1729 | * Update AMCC Yosemite to get a consistent setup for all AMCC eval |
1727 | boards (baudrate, environment...). Flash driver fixed. | 1730 | boards (baudrate, environment...). Flash driver fixed. |
1728 | Patch by Stefan Roese, 11 Aug 2005 | 1731 | Patch by Stefan Roese, 11 Aug 2005 |
1729 | 1732 | ||
1730 | * Changed AMCC Bubinga (405EP) configuration to support 2nd eth port | 1733 | * Changed AMCC Bubinga (405EP) configuration to support 2nd eth port |
1731 | Patch by Stefan Roese, 11 Aug 2005 | 1734 | Patch by Stefan Roese, 11 Aug 2005 |
1732 | 1735 | ||
1733 | * Add NAND FLASH support for AMCC Bamboo 440EP eval board | 1736 | * Add NAND FLASH support for AMCC Bamboo 440EP eval board |
1734 | Patch by Stefan Roese, 11 Aug 2005 | 1737 | Patch by Stefan Roese, 11 Aug 2005 |
1735 | 1738 | ||
1736 | * Add configuration for IFM AEV FIFO board. | 1739 | * Add configuration for IFM AEV FIFO board. |
1737 | Minor coding style cleanup. | 1740 | Minor coding style cleanup. |
1738 | 1741 | ||
1739 | * Add configuration for IFM SPI eval board | 1742 | * Add configuration for IFM SPI eval board |
1740 | 1743 | ||
1741 | * Fix CompactFlash problem on HMI1001 board | 1744 | * Fix CompactFlash problem on HMI1001 board |
1742 | 1745 | ||
1743 | * Make new "mtdparts" code build with older compilers | 1746 | * Make new "mtdparts" code build with older compilers |
1744 | Patch by Andrea Scian, 09 Aug 2005 | 1747 | Patch by Andrea Scian, 09 Aug 2005 |
1745 | 1748 | ||
1746 | * Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to | 1749 | * Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to |
1747 | CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design | 1750 | CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design |
1748 | with the 405 defines and the linux kernel defines. | 1751 | with the 405 defines and the linux kernel defines. |
1749 | Patch by Stefan Roese, 08 Aug 2005 | 1752 | Patch by Stefan Roese, 08 Aug 2005 |
1750 | 1753 | ||
1751 | * Fix compiler warnings with older GCC versions | 1754 | * Fix compiler warnings with older GCC versions |
1752 | 1755 | ||
1753 | * Add common (with Linux) MTD partition scheme and "mtdparts" command | 1756 | * Add common (with Linux) MTD partition scheme and "mtdparts" command |
1754 | 1757 | ||
1755 | Old, obsolete and duplicated code was cleaned up and replace by the | 1758 | Old, obsolete and duplicated code was cleaned up and replace by the |
1756 | new partitioning method. There are two possible approaches now: | 1759 | new partitioning method. There are two possible approaches now: |
1757 | 1760 | ||
1758 | The first one is to define a single, static partition: | 1761 | The first one is to define a single, static partition: |
1759 | 1762 | ||
1760 | #undef CONFIG_JFFS2_CMDLINE | 1763 | #undef CONFIG_JFFS2_CMDLINE |
1761 | #define CONFIG_JFFS2_DEV "nor0" | 1764 | #define CONFIG_JFFS2_DEV "nor0" |
1762 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ | 1765 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ |
1763 | #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ | 1766 | #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ |
1764 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | 1767 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
1765 | 1768 | ||
1766 | The second method uses the mtdparts command line option and dynamic | 1769 | The second method uses the mtdparts command line option and dynamic |
1767 | partitioning: | 1770 | partitioning: |
1768 | 1771 | ||
1769 | /* mtdparts command line support */ | 1772 | /* mtdparts command line support */ |
1770 | #define CONFIG_JFFS2_CMDLINE | 1773 | #define CONFIG_JFFS2_CMDLINE |
1771 | #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" | 1774 | #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" |
1772 | #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" | 1775 | #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" |
1773 | 1776 | ||
1774 | Command line of course produces bigger images, and may be inappropriate | 1777 | Command line of course produces bigger images, and may be inappropriate |
1775 | for some targets, so by default it's off. | 1778 | for some targets, so by default it's off. |
1776 | 1779 | ||
1777 | * Fix build problems for PM856 Board | 1780 | * Fix build problems for PM856 Board |
1778 | 1781 | ||
1779 | * Fix sign extension bug in 'fpga loadb' command; | 1782 | * Fix sign extension bug in 'fpga loadb' command; |
1780 | make 'fpga loadb' always print the file header info | 1783 | make 'fpga loadb' always print the file header info |
1781 | Patch by Andrew Dyer, 11 Jan 2005 | 1784 | Patch by Andrew Dyer, 11 Jan 2005 |
1782 | 1785 | ||
1783 | * Fix errors that occur when accessing SystemACE CF | 1786 | * Fix errors that occur when accessing SystemACE CF |
1784 | Patch by Jeff Angielski, 09 Jan 2005 | 1787 | Patch by Jeff Angielski, 09 Jan 2005 |
1785 | 1788 | ||
1786 | * Document switching between U-Boot and PlanetCore on RPXlite | 1789 | * Document switching between U-Boot and PlanetCore on RPXlite |
1787 | by Sam Song, 24 Dec 2004 | 1790 | by Sam Song, 24 Dec 2004 |
1788 | 1791 | ||
1789 | * Fix PowerQUICC II mask detection. | 1792 | * Fix PowerQUICC II mask detection. |
1790 | Patch by Eugene Surovegin, 20 Dec 2004 | 1793 | Patch by Eugene Surovegin, 20 Dec 2004 |
1791 | 1794 | ||
1792 | * Add support for Altera NIOS DK1C20 board | 1795 | * Add support for Altera NIOS DK1C20 board |
1793 | Patch by Shlomo Kut, 13 Dec 2004 | 1796 | Patch by Shlomo Kut, 13 Dec 2004 |
1794 | 1797 | ||
1795 | * Add support for ep8248 board | 1798 | * Add support for ep8248 board |
1796 | Patch by Yuli Barcohen, 12 Dec 2004 | 1799 | Patch by Yuli Barcohen, 12 Dec 2004 |
1797 | 1800 | ||
1798 | Minor code cleanup. | 1801 | Minor code cleanup. |
1799 | 1802 | ||
1800 | * Fix baudrate setting for KGDB on MPC8260 | 1803 | * Fix baudrate setting for KGDB on MPC8260 |
1801 | Patch by HoJin, 11 Dec 2004 | 1804 | Patch by HoJin, 11 Dec 2004 |
1802 | 1805 | ||
1803 | * Fix 'mii help' text formatting | 1806 | * Fix 'mii help' text formatting |
1804 | Patch by Cory Tusar, 10 Dec 2004 | 1807 | Patch by Cory Tusar, 10 Dec 2004 |
1805 | 1808 | ||
1806 | * Fix return code of NFS command | 1809 | * Fix return code of NFS command |
1807 | Patch by Hiroshi Ito, 11 Dec 2004 | 1810 | Patch by Hiroshi Ito, 11 Dec 2004 |
1808 | 1811 | ||
1809 | * Fix typo | 1812 | * Fix typo |
1810 | 1813 | ||
1811 | * Fix compiler warnings in cpu/ppc4xx/usbdev.c | 1814 | * Fix compiler warnings in cpu/ppc4xx/usbdev.c |
1812 | Patch by Steven Blakeslee, 04 Aug 2005 | 1815 | Patch by Steven Blakeslee, 04 Aug 2005 |
1813 | 1816 | ||
1814 | * Add support for AMCC Bamboo PPC440EP eval board | 1817 | * Add support for AMCC Bamboo PPC440EP eval board |
1815 | Patch by Stefan Roese, 04 Aug 2005 | 1818 | Patch by Stefan Roese, 04 Aug 2005 |
1816 | 1819 | ||
1817 | * Patch by Jon Loeliger | 1820 | * Patch by Jon Loeliger |
1818 | Fix style issues primarily in 85xx and 83xx boards. | 1821 | Fix style issues primarily in 85xx and 83xx boards. |
1819 | - C++ comments | 1822 | - C++ comments |
1820 | - Trailing white space | 1823 | - Trailing white space |
1821 | - Indentation not by TAB | 1824 | - Indentation not by TAB |
1822 | - Excessive amount of empty lines | 1825 | - Excessive amount of empty lines |
1823 | - Trailing empty lines | 1826 | - Trailing empty lines |
1824 | 1827 | ||
1825 | * Patch by Ron Alder, 11 Jul 2005 | 1828 | * Patch by Ron Alder, 11 Jul 2005 |
1826 | Add Xianghua Xiao and Lunsheng Wang's support for the | 1829 | Add Xianghua Xiao and Lunsheng Wang's support for the |
1827 | GDA MPC8540 EVAL board. | 1830 | GDA MPC8540 EVAL board. |
1828 | 1831 | ||
1829 | * Patch by Eran Liberty | 1832 | * Patch by Eran Liberty |
1830 | Add support for the Freescale MPC8349ADS board. | 1833 | Add support for the Freescale MPC8349ADS board. |
1831 | 1834 | ||
1832 | * Patch by Jon Loeliger, 25 Jul 2005 | 1835 | * Patch by Jon Loeliger, 25 Jul 2005 |
1833 | Move the TSEC driver out of cpu/mpc85xx as it will be shared | 1836 | Move the TSEC driver out of cpu/mpc85xx as it will be shared |
1834 | by the upcoming mpc83xx family as well. | 1837 | by the upcoming mpc83xx family as well. |
1835 | 1838 | ||
1836 | * Patch by Jon Loeliger, 05 May 2005 | 1839 | * Patch by Jon Loeliger, 05 May 2005 |
1837 | Implemented support for MPC8548CDS board. | 1840 | Implemented support for MPC8548CDS board. |
1838 | Added DDR II support based on SPD values for MPC85xx boards. | 1841 | Added DDR II support based on SPD values for MPC85xx boards. |
1839 | This roll-up patch also includes bugfies for the previously | 1842 | This roll-up patch also includes bugfies for the previously |
1840 | published patches: | 1843 | published patches: |
1841 | DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O | 1844 | DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O |
1842 | 1845 | ||
1843 | * Patch by Jon Loeliger, 10 Feb 2005 | 1846 | * Patch by Jon Loeliger, 10 Feb 2005 |
1844 | Add config option CONFIG_HAS_FEC calling out 8540 FEC features. | 1847 | Add config option CONFIG_HAS_FEC calling out 8540 FEC features. |
1845 | 1848 | ||
1846 | * Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005 | 1849 | * Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005 |
1847 | For MPC85xxCDS: | 1850 | For MPC85xxCDS: |
1848 | Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow | 1851 | Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow |
1849 | for faster flash parts. | 1852 | for faster flash parts. |
1850 | Add documentation for BR/OR for FLASH. | 1853 | Add documentation for BR/OR for FLASH. |
1851 | 1854 | ||
1852 | * Patch by Jon Loeliger 08 Feb 2005 | 1855 | * Patch by Jon Loeliger 08 Feb 2005 |
1853 | Determine L2 Cache size dynamically on 85XX boards. | 1856 | Determine L2 Cache size dynamically on 85XX boards. |
1854 | 1857 | ||
1855 | * Patch by Jon Loeliger, Kumar Gala 08 Feb 2005 | 1858 | * Patch by Jon Loeliger, Kumar Gala 08 Feb 2005 |
1856 | - Convert the CPM2 based functionality to use new CONFIG_CPM2 | 1859 | - Convert the CPM2 based functionality to use new CONFIG_CPM2 |
1857 | option rather than a myriad of CONFIG_MPC8560-like variants. | 1860 | option rather than a myriad of CONFIG_MPC8560-like variants. |
1858 | Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. | 1861 | Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. |
1859 | Eliminates the CONFIG_MPC8560 option entirely. Distributes the | 1862 | Eliminates the CONFIG_MPC8560 option entirely. Distributes the |
1860 | new CONFIG_CPM2 option to each 8260 board. | 1863 | new CONFIG_CPM2 option to each 8260 board. |
1861 | 1864 | ||
1862 | * Add support for MicroSys PM856 board | 1865 | * Add support for MicroSys PM856 board |
1863 | Patch by Josef Wagner, 03 Aug 2005 | 1866 | Patch by Josef Wagner, 03 Aug 2005 |
1864 | 1867 | ||
1865 | * Minor fixes to PM854 board | 1868 | * Minor fixes to PM854 board |
1866 | Patch by Josef Wagner, 03 Aug 2005 | 1869 | Patch by Josef Wagner, 03 Aug 2005 |
1867 | 1870 | ||
1868 | * Adjust configuration of XENIAX board | 1871 | * Adjust configuration of XENIAX board |
1869 | (chip select and GPIO required for USB operation) | 1872 | (chip select and GPIO required for USB operation) |
1870 | 1873 | ||
1871 | * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be | 1874 | * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be |
1872 | routed to the Watchdog handler | 1875 | routed to the Watchdog handler |
1873 | Patch by Eugene Surovegin, 18 Jun 2005 | 1876 | Patch by Eugene Surovegin, 18 Jun 2005 |
1874 | 1877 | ||
1875 | * (re)enabled scsi commands do_scsi() and do_scsiboot() | 1878 | * (re)enabled scsi commands do_scsi() and do_scsiboot() |
1876 | Patch by Denis Peter, 06 Dec 2004 | 1879 | Patch by Denis Peter, 06 Dec 2004 |
1877 | 1880 | ||
1878 | * Fix endianess problem in TFTP / NFS default filenames | 1881 | * Fix endianess problem in TFTP / NFS default filenames |
1879 | Patch by Hiroshi Ito, 06 Dec 2004 | 1882 | Patch by Hiroshi Ito, 06 Dec 2004 |
1880 | 1883 | ||
1881 | * Ignore broadcast status bit in received frames in 8260 FCC ethernet | 1884 | * Ignore broadcast status bit in received frames in 8260 FCC ethernet |
1882 | loopback test code | 1885 | loopback test code |
1883 | Patch by Murray Jensen, 18 Jul 2005 | 1886 | Patch by Murray Jensen, 18 Jul 2005 |
1884 | 1887 | ||
1885 | * Fix typo in mkconfig script (used == instead of =) | 1888 | * Fix typo in mkconfig script (used == instead of =) |
1886 | Patch by Murray Jensen, 18 Jul 2005 | 1889 | Patch by Murray Jensen, 18 Jul 2005 |
1887 | 1890 | ||
1888 | * Cleanup build problems on 64 bit build hosts | 1891 | * Cleanup build problems on 64 bit build hosts |
1889 | 1892 | ||
1890 | * Update MAINTAINERS file | 1893 | * Update MAINTAINERS file |
1891 | 1894 | ||
1892 | * Patch by Stefan Roese, 01 Aug 2005: | 1895 | * Patch by Stefan Roese, 01 Aug 2005: |
1893 | - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea | 1896 | - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea |
1894 | (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup" | 1897 | (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup" |
1895 | for details. | 1898 | for details. |
1896 | - Sycamore (PPC405GPr) eval board added (Walnut port is extended | 1899 | - Sycamore (PPC405GPr) eval board added (Walnut port is extended |
1897 | to run on both 405GP and 405GPr eval boards). | 1900 | to run on both 405GP and 405GPr eval boards). |
1898 | 1901 | ||
1899 | * Patch by Steven Blakeslee, 27 Jul 2005: | 1902 | * Patch by Steven Blakeslee, 27 Jul 2005: |
1900 | - Add support for AMCC PPC440EP/GR. | 1903 | - Add support for AMCC PPC440EP/GR. |
1901 | - Add support for AMCC Yosemite PPC440EP eval board. | 1904 | - Add support for AMCC Yosemite PPC440EP eval board. |
1902 | - Add support for AMCC Yellowstone PPC440GR eval board. | 1905 | - Add support for AMCC Yellowstone PPC440GR eval board. |
1903 | 1906 | ||
1904 | * Minor fixes for PPChameleon Board: | 1907 | * Minor fixes for PPChameleon Board: |
1905 | - fix alignment of NAND size | 1908 | - fix alignment of NAND size |
1906 | - make code do what the comment says | 1909 | - make code do what the comment says |
1907 | 1910 | ||
1908 | * Implement h/w sector protection status synchronization at boot. | 1911 | * Implement h/w sector protection status synchronization at boot. |
1909 | The code is provided for, and was tested on, the Yukon/Alaska | 1912 | The code is provided for, and was tested on, the Yukon/Alaska |
1910 | and PM520 boards only. | 1913 | and PM520 boards only. |
1911 | 1914 | ||
1912 | A bug in flash_real_protect() for the Yukon board was fixed by | 1915 | A bug in flash_real_protect() for the Yukon board was fixed by |
1913 | adding a function that tells if two banks are on one flash chip. | 1916 | adding a function that tells if two banks are on one flash chip. |
1914 | 1917 | ||
1915 | * Fix sysmon POST problem: check I2C error codes | 1918 | * Fix sysmon POST problem: check I2C error codes |
1916 | This fixes a problem of displaying bogus voltages when the voltages | 1919 | This fixes a problem of displaying bogus voltages when the voltages |
1917 | are so low that the I2C devices start failing while the rest of the | 1920 | are so low that the I2C devices start failing while the rest of the |
1918 | system keeps running. | 1921 | system keeps running. |
1919 | 1922 | ||
1920 | * Patch by Cedric Vincent, 6 Jul 2005: | 1923 | * Patch by Cedric Vincent, 6 Jul 2005: |
1921 | Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c" | 1924 | Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c" |
1922 | 1925 | ||
1923 | * Patch by Jon Loeliger, 20 Jul 2005: | 1926 | * Patch by Jon Loeliger, 20 Jul 2005: |
1924 | Add missing PCI IO port definitions. | 1927 | Add missing PCI IO port definitions. |
1925 | 1928 | ||
1926 | * Add CompactFlash support for HMI1001 board. | 1929 | * Add CompactFlash support for HMI1001 board. |
1927 | 1930 | ||
1928 | * Adjust printed board ID for LWMON board. | 1931 | * Adjust printed board ID for LWMON board. |
1929 | 1932 | ||
1930 | * Fix low-level OHCI transfers for ARM920t and MPC5xxx | 1933 | * Fix low-level OHCI transfers for ARM920t and MPC5xxx |
1931 | 1934 | ||
1932 | * Add new argument format for flash commands to allow for usage like | 1935 | * Add new argument format for flash commands to allow for usage like |
1933 | "erase $(addr) +$(filesize)", i. e. a size argument can be used and | 1936 | "erase $(addr) +$(filesize)", i. e. a size argument can be used and |
1934 | U-Boot will automaticially find the end of the corresponding sector. | 1937 | U-Boot will automaticially find the end of the corresponding sector. |
1935 | 1938 | ||
1936 | * Patch by Stefan Roese, 5 Jul 2005: | 1939 | * Patch by Stefan Roese, 5 Jul 2005: |
1937 | Update uc100 board PHY setup | 1940 | Update uc100 board PHY setup |
1938 | 1941 | ||
1939 | * Patch by Stefan Roese, 1 Jul 2005: | 1942 | * Patch by Stefan Roese, 1 Jul 2005: |
1940 | Fix PHY address for CATcenter board (now correct!) | 1943 | Fix PHY address for CATcenter board (now correct!) |
1941 | 1944 | ||
1942 | * Patch by Stefan Roese, 30 Jun 2005: | 1945 | * Patch by Stefan Roese, 30 Jun 2005: |
1943 | Fix PHY addresses for PPChameleon and CATcenter boards | 1946 | Fix PHY addresses for PPChameleon and CATcenter boards |
1944 | Change MAINTAINER for most esd boards | 1947 | Change MAINTAINER for most esd boards |
1945 | 1948 | ||
1946 | * Patch by Detlev Zundel, 30 Jun 2005: | 1949 | * Patch by Detlev Zundel, 30 Jun 2005: |
1947 | Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code | 1950 | Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code |
1948 | 1951 | ||
1949 | * Fix baudrate calculation problem on MPC5200 systems | 1952 | * Fix baudrate calculation problem on MPC5200 systems |
1950 | 1953 | ||
1951 | * Add EEPROM and RTC support for HMI1001 board | 1954 | * Add EEPROM and RTC support for HMI1001 board |
1952 | 1955 | ||
1953 | * Patch by Detlev Zundel, 20 Jun 2005: | 1956 | * Patch by Detlev Zundel, 20 Jun 2005: |
1954 | Fix initialization of low active GPIO pins on inka4x0 board | 1957 | Fix initialization of low active GPIO pins on inka4x0 board |
1955 | 1958 | ||
1956 | * Enable redundant environment, disable HW flash protection of | 1959 | * Enable redundant environment, disable HW flash protection of |
1957 | HMI1001 board | 1960 | HMI1001 board |
1958 | 1961 | ||
1959 | * Patch by Travis Sawyer, 10 Jun 2005: | 1962 | * Patch by Travis Sawyer, 10 Jun 2005: |
1960 | Initialize allocated dev and private hw structures | 1963 | Initialize allocated dev and private hw structures |
1961 | after their respective allocation in 440gx_enet.c | 1964 | after their respective allocation in 440gx_enet.c |
1962 | 1965 | ||
1963 | * Patch by Steven Scholz, 10 Jun 2005: | 1966 | * Patch by Steven Scholz, 10 Jun 2005: |
1964 | Fix byteorder problems with second argument of "bootm" with | 1967 | Fix byteorder problems with second argument of "bootm" with |
1965 | standalone images; | 1968 | standalone images; |
1966 | 1969 | ||
1967 | * Add support for HMI1001 board | 1970 | * Add support for HMI1001 board |
1968 | 1971 | ||
1969 | * Disable "date" and "sntp" commands on TQM866M | 1972 | * Disable "date" and "sntp" commands on TQM866M |
1970 | 1973 | ||
1971 | * Fix watchdog reset problems on LWMON board | 1974 | * Fix watchdog reset problems on LWMON board |
1972 | 1975 | ||
1973 | * Patch by Juergen Selent, 17 May 2005: | 1976 | * Patch by Juergen Selent, 17 May 2005: |
1974 | Add support for Funkwerk VoVPN gateway module. | 1977 | Add support for Funkwerk VoVPN gateway module. |
1975 | 1978 | ||
1976 | * Cleanup debug code for MPC8220 FEC driver | 1979 | * Cleanup debug code for MPC8220 FEC driver |
1977 | 1980 | ||
1978 | * Extend burst mode RAM test program to take a loop count | 1981 | * Extend burst mode RAM test program to take a loop count |
1979 | (0 = infinite) | 1982 | (0 = infinite) |
1980 | 1983 | ||
1981 | * Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on | 1984 | * Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on |
1982 | those boards that use it. | 1985 | those boards that use it. |
1983 | 1986 | ||
1984 | * Patches by Greg Ungerer, 19 May 2005: | 1987 | * Patches by Greg Ungerer, 19 May 2005: |
1985 | - add support for the KS8695P (ARM 922 based) CPU | 1988 | - add support for the KS8695P (ARM 922 based) CPU |
1986 | - add support for the OpenGear CM4008, CM4116 and CM4148 boards | 1989 | - add support for the OpenGear CM4008, CM4116 and CM4148 boards |
1987 | 1990 | ||
1988 | * Patch by Steven Scholz, 19 May 2005: | 1991 | * Patch by Steven Scholz, 19 May 2005: |
1989 | Add support for CONFIG_SERIAL_TAG on ARM boards | 1992 | Add support for CONFIG_SERIAL_TAG on ARM boards |
1990 | 1993 | ||
1991 | * Add PCI support for Sorcery board. | 1994 | * Add PCI support for Sorcery board. |
1992 | Code cleanup (especially Sorcery / Alaska / Yukon serial driver). | 1995 | Code cleanup (especially Sorcery / Alaska / Yukon serial driver). |
1993 | 1996 | ||
1994 | * Fix compile problems caused by new burst mode SDRAM test; | 1997 | * Fix compile problems caused by new burst mode SDRAM test; |
1995 | make port pins to trigger logic analyzer configurable | 1998 | make port pins to trigger logic analyzer configurable |
1996 | 1999 | ||
1997 | * Fix timer handling on MPC85xx systems | 2000 | * Fix timer handling on MPC85xx systems |
1998 | 2001 | ||
1999 | * Fix debug code in omap5912osk flash driver | 2002 | * Fix debug code in omap5912osk flash driver |
2000 | 2003 | ||
2001 | * Add support for MPC8247 based "IDS8247" board. | 2004 | * Add support for MPC8247 based "IDS8247" board. |
2002 | 2005 | ||
2003 | * Add support for 2 x TSEC interfaces on the TQM8540 board. | 2006 | * Add support for 2 x TSEC interfaces on the TQM8540 board. |
2004 | 2007 | ||
2005 | * On LWMON we must use the watchdog to reset the board as the CPU | 2008 | * On LWMON we must use the watchdog to reset the board as the CPU |
2006 | genereated HRESET pulse is too short to reset the external | 2009 | genereated HRESET pulse is too short to reset the external |
2007 | circuitry. | 2010 | circuitry. |
2008 | 2011 | ||
2009 | * Add test tool to exercise SDRAM accesses in burst mode | 2012 | * Add test tool to exercise SDRAM accesses in burst mode |
2010 | (as standalone program, MPC8xx/PowerPC only) | 2013 | (as standalone program, MPC8xx/PowerPC only) |
2011 | 2014 | ||
2012 | * Increase CFG_MONITOR_LEN for Rattler board to match actual code | 2015 | * Increase CFG_MONITOR_LEN for Rattler board to match actual code |
2013 | size. | 2016 | size. |
2014 | 2017 | ||
2015 | * Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of | 2018 | * Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of |
2016 | March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI | 2019 | March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI |
2017 | added to support LZO and LZARI compression modes (undefined by | 2020 | added to support LZO and LZARI compression modes (undefined by |
2018 | default). | 2021 | default). |
2019 | 2022 | ||
2020 | * Fix problem with symbolic links in JFFS2 code. | 2023 | * Fix problem with symbolic links in JFFS2 code. |
2021 | 2024 | ||
2022 | * Use linker ASSERT statement to prevent undetected overlapping of | 2025 | * Use linker ASSERT statement to prevent undetected overlapping of |
2023 | sections on PPChameleon board; other boards might use this, too. | 2026 | sections on PPChameleon board; other boards might use this, too. |
2024 | 2027 | ||
2025 | * Patch by Stefan Roese, 03 May 2005: | 2028 | * Patch by Stefan Roese, 03 May 2005: |
2026 | Update for P3G4 | 2029 | Update for P3G4 |
2027 | Fix problems in cmd_universe.c | 2030 | Fix problems in cmd_universe.c |
2028 | 2031 | ||
2029 | * Patch by Matthias Fuchs, 03 May 2005: | 2032 | * Patch by Matthias Fuchs, 03 May 2005: |
2030 | Added missing variable declaration in cmd_nand.c | 2033 | Added missing variable declaration in cmd_nand.c |
2031 | Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram | 2034 | Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram |
2032 | 2035 | ||
2033 | * Fix INKA4x0: use CS1 as gpio_wkup_6 output | 2036 | * Fix INKA4x0: use CS1 as gpio_wkup_6 output |
2034 | 2037 | ||
2035 | * Fix bug in the SDRAM initialization code for canmb, IceCube and | 2038 | * Fix bug in the SDRAM initialization code for canmb, IceCube and |
2036 | PM520 boards. | 2039 | PM520 boards. |
2037 | Fix PHY address for canmb board. | 2040 | Fix PHY address for canmb board. |
2038 | 2041 | ||
2039 | * Cleanup serial console baudrate calculation on AT91RM9200; | 2042 | * Cleanup serial console baudrate calculation on AT91RM9200; |
2040 | get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition | 2043 | get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition |
2041 | 2044 | ||
2042 | * Patch by Matthias Fuchs, 18 Apr 2005: | 2045 | * Patch by Matthias Fuchs, 18 Apr 2005: |
2043 | Make PCI target address spaces on PMC405 and CPCI405 boards | 2046 | Make PCI target address spaces on PMC405 and CPCI405 boards |
2044 | configurable via environment variables | 2047 | configurable via environment variables |
2045 | 2048 | ||
2046 | * Auto-size RAM on canmb board. | 2049 | * Auto-size RAM on canmb board. |
2047 | 2050 | ||
2048 | * Add support for canmb board | 2051 | * Add support for canmb board |
2049 | 2052 | ||
2050 | * Patch by Stefan Roese, 13 Apr 2005: | 2053 | * Patch by Stefan Roese, 13 Apr 2005: |
2051 | Update for esd apc405 | 2054 | Update for esd apc405 |
2052 | 2055 | ||
2053 | * Fixes for TQM8560 board: | 2056 | * Fixes for TQM8560 board: |
2054 | - fix clock rates | 2057 | - fix clock rates |
2055 | - remove debug messages | 2058 | - remove debug messages |
2056 | - fix flash sector protection | 2059 | - fix flash sector protection |
2057 | 2060 | ||
2058 | * Patch by Steven Scholz, 07 Apr 2005: | 2061 | * Patch by Steven Scholz, 07 Apr 2005: |
2059 | Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C | 2062 | Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C |
2060 | 2063 | ||
2061 | * Patches by Steven Scholz, 07 Apr 2005: | 2064 | * Patches by Steven Scholz, 07 Apr 2005: |
2062 | Fix compiler warning in altera.c | 2065 | Fix compiler warning in altera.c |
2063 | Fix warning in cpu/arm920t/at91rm9200/i2c.c | 2066 | Fix warning in cpu/arm920t/at91rm9200/i2c.c |
2064 | 2067 | ||
2065 | * Patch by Ladislav Michl, 06 Apr 2005: | 2068 | * Patch by Ladislav Michl, 06 Apr 2005: |
2066 | Fix voiceblue configuration. | 2069 | Fix voiceblue configuration. |
2067 | 2070 | ||
2068 | * Patch by Stefan Roese, 06 Apr 2005: | 2071 | * Patch by Stefan Roese, 06 Apr 2005: |
2069 | Updates for OCOTEA board: | 2072 | Updates for OCOTEA board: |
2070 | - Changed U-Boot size from 512kByte to 256kByte | 2073 | - Changed U-Boot size from 512kByte to 256kByte |
2071 | - Fixed flash driver to support boot from soldered user flash | 2074 | - Fixed flash driver to support boot from soldered user flash |
2072 | - Added README for switch from PIBS firmware to U-Boot | 2075 | - Added README for switch from PIBS firmware to U-Boot |
2073 | 2076 | ||
2074 | * Patch by Travis Sawyer, 05 Apr 2005: | 2077 | * Patch by Travis Sawyer, 05 Apr 2005: |
2075 | - Change timer frequency for ppc 440 from 10 ms to 1 ms. | 2078 | - Change timer frequency for ppc 440 from 10 ms to 1 ms. |
2076 | Problem found by Andrew Wozniak. | 2079 | Problem found by Andrew Wozniak. |
2077 | 2080 | ||
2078 | * Patch by Steven Scholz, 06 Apr 2005: | 2081 | * Patch by Steven Scholz, 06 Apr 2005: |
2079 | - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 | 2082 | - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 |
2080 | - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200 | 2083 | - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200 |
2081 | 2084 | ||
2082 | * Patches by Robert Whaley, 29 Nov 2004: | 2085 | * Patches by Robert Whaley, 29 Nov 2004: |
2083 | - update the pxa-regs.h file for PXA27x chips | 2086 | - update the pxa-regs.h file for PXA27x chips |
2084 | - add PXA27x based ADSVIX board | 2087 | - add PXA27x based ADSVIX board |
2085 | - add support for MMC on PXA27x processors | 2088 | - add support for MMC on PXA27x processors |
2086 | 2089 | ||
2087 | * Patch by Andrew E. Mileski, 28 Nov 2004: | 2090 | * Patch by Andrew E. Mileski, 28 Nov 2004: |
2088 | Fix PPC4xx SPD SDRAM detection bug | 2091 | Fix PPC4xx SPD SDRAM detection bug |
2089 | 2092 | ||
2090 | * Patch by Hiroshi Ito, 26 Nov 2004: | 2093 | * Patch by Hiroshi Ito, 26 Nov 2004: |
2091 | Fix logic of "test -z" and "test -n" commands | 2094 | Fix logic of "test -z" and "test -n" commands |
2092 | 2095 | ||
2093 | * Patch by Ladislav Michl, 05 Apr 2005: | 2096 | * Patch by Ladislav Michl, 05 Apr 2005: |
2094 | Add support for VoiceBlue board. | 2097 | Add support for VoiceBlue board. |
2095 | 2098 | ||
2096 | * Patch by Ladislav Michl, 05 Apr 2005: | 2099 | * Patch by Ladislav Michl, 05 Apr 2005: |
2097 | Fix netboot_common() prototypes. | 2100 | Fix netboot_common() prototypes. |
2098 | 2101 | ||
2099 | * Patch by Steven Scholz, 05 Apr 2005: | 2102 | * Patch by Steven Scholz, 05 Apr 2005: |
2100 | Use i.MX watchdog timer for reset_cpu() | 2103 | Use i.MX watchdog timer for reset_cpu() |
2101 | 2104 | ||
2102 | * Patch by Steven Scholz, 05 Apr 2005: | 2105 | * Patch by Steven Scholz, 05 Apr 2005: |
2103 | Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific | 2106 | Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific |
2104 | subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ | 2107 | subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ |
2105 | (now in interupts.c) | 2108 | (now in interupts.c) |
2106 | 2109 | ||
2107 | * Add support for MPC8220 based "sorcery" board. | 2110 | * Add support for MPC8220 based "sorcery" board. |
2108 | 2111 | ||
2109 | * Add support for TQM8560 board. | 2112 | * Add support for TQM8560 board. |
2110 | 2113 | ||
2111 | * Add FEC support for TQM8540 board. | 2114 | * Add FEC support for TQM8540 board. |
2112 | Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC | 2115 | Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC |
2113 | 2116 | ||
2114 | * Patch by Martin Krause, 04 Apr 2005: | 2117 | * Patch by Martin Krause, 04 Apr 2005: |
2115 | Update default configuration for CMC_PU2 board. | 2118 | Update default configuration for CMC_PU2 board. |
2116 | 2119 | ||
2117 | * Patch by Steven Scholz, 04 Apr 2005: | 2120 | * Patch by Steven Scholz, 04 Apr 2005: |
2118 | - remove all references to CONFIG_INIT_CRITICAL for ARM based boards | 2121 | - remove all references to CONFIG_INIT_CRITICAL for ARM based boards |
2119 | - introduce two new configuration options instead: | 2122 | - introduce two new configuration options instead: |
2120 | CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT | 2123 | CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT |
2121 | 2124 | ||
2122 | * Patch by Steven Scholz, 04 Apr 2005: | 2125 | * Patch by Steven Scholz, 04 Apr 2005: |
2123 | Make sure that MDIO clock does not exceed 2.5 MHz on AT91 | 2126 | Make sure that MDIO clock does not exceed 2.5 MHz on AT91 |
2124 | 2127 | ||
2125 | * Fix timer code for ARM systems: make sure that udelay() does not | 2128 | * Fix timer code for ARM systems: make sure that udelay() does not |
2126 | reset timers so it's save to use udelay() in timeout code. | 2129 | reset timers so it's save to use udelay() in timeout code. |
2127 | 2130 | ||
2128 | * Patch by Mathias Kรผster, 23 Nov 2004: | 2131 | * Patch by Mathias Kรผster, 23 Nov 2004: |
2129 | add udelay support for the mcf5282 cpu | 2132 | add udelay support for the mcf5282 cpu |
2130 | 2133 | ||
2131 | * Patch by Tolunay Orkun, 16 November 2004: | 2134 | * Patch by Tolunay Orkun, 16 November 2004: |
2132 | fix incorrect onboard Xilinx CPLD base address | 2135 | fix incorrect onboard Xilinx CPLD base address |
2133 | 2136 | ||
2134 | * Patch by Jerry Van Baren, 08 Nov 2004: | 2137 | * Patch by Jerry Van Baren, 08 Nov 2004: |
2135 | - Add low-boot option for MPC8260ADS board (if lowboot is selected, | 2138 | - Add low-boot option for MPC8260ADS board (if lowboot is selected, |
2136 | the jumper for the HRCW source should select flash. If lowboot is | 2139 | the jumper for the HRCW source should select flash. If lowboot is |
2137 | not selected, the jumper for the HRCW source should select the | 2140 | not selected, the jumper for the HRCW source should select the |
2138 | BCSR. | 2141 | BCSR. |
2139 | - change default load base address to 0x00400000 | 2142 | - change default load base address to 0x00400000 |
2140 | 2143 | ||
2141 | * Patch by Yuli Barcohen, 08 Nov 2004: | 2144 | * Patch by Yuli Barcohen, 08 Nov 2004: |
2142 | Add support for Analogue & Micro Rattler boards. | 2145 | Add support for Analogue & Micro Rattler boards. |
2143 | Tested on Rattler8248. | 2146 | Tested on Rattler8248. |
2144 | 2147 | ||
2145 | * Patch by Andre Renaud, 08 Nov 2004: | 2148 | * Patch by Andre Renaud, 08 Nov 2004: |
2146 | Fix watchdog support in common/lcd.c | 2149 | Fix watchdog support in common/lcd.c |
2147 | 2150 | ||
2148 | * Patch by Marc Leeman, 05 Nov 2003: | 2151 | * Patch by Marc Leeman, 05 Nov 2003: |
2149 | Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU | 2152 | Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU |
2150 | bug only affects the XPC8245 processors | 2153 | bug only affects the XPC8245 processors |
2151 | 2154 | ||
2152 | * Patches by Josef Wagner, 29 Oct 2004: | 2155 | * Patches by Josef Wagner, 29 Oct 2004: |
2153 | - Add support for MicroSys CPU87 board | 2156 | - Add support for MicroSys CPU87 board |
2154 | - Add support for MicroSys PM854 board | 2157 | - Add support for MicroSys PM854 board |
2155 | 2158 | ||
2156 | * Patch by Jian Zhang, 02 Nov 2004: | 2159 | * Patch by Jian Zhang, 02 Nov 2004: |
2157 | Add 16-bit NAND support | 2160 | Add 16-bit NAND support |
2158 | 2161 | ||
2159 | * Patch by Scott McNutt, 01 Nov 2004: | 2162 | * Patch by Scott McNutt, 01 Nov 2004: |
2160 | Add missing NIOS/NIOS2 support for "iminfo" command | 2163 | Add missing NIOS/NIOS2 support for "iminfo" command |
2161 | 2164 | ||
2162 | * Patch by Detlev Zundel, 29 Oct 2004: | 2165 | * Patch by Detlev Zundel, 29 Oct 2004: |
2163 | Add missing NIOS/NIOS2 support for "mkimage" tool. | 2166 | Add missing NIOS/NIOS2 support for "mkimage" tool. |
2164 | 2167 | ||
2165 | * Patch by David Adair, 27 Oct 2004: | 2168 | * Patch by David Adair, 27 Oct 2004: |
2166 | Add missing 440GX SDRAM Controller reset | 2169 | Add missing 440GX SDRAM Controller reset |
2167 | 2170 | ||
2168 | * Patch by Steven Scholz, 25 Oct 2004: | 2171 | * Patch by Steven Scholz, 25 Oct 2004: |
2169 | Declare reset_cpu() in include/common.h instead locally | 2172 | Declare reset_cpu() in include/common.h instead locally |
2170 | 2173 | ||
2171 | * Patch by Yusdi Santoso, 22 Oct 2004: | 2174 | * Patch by Yusdi Santoso, 22 Oct 2004: |
2172 | - Add support for HIDDEN_DRAGON board | 2175 | - Add support for HIDDEN_DRAGON board |
2173 | - fix endianess problem in driver/rtl1839.c | 2176 | - fix endianess problem in driver/rtl1839.c |
2174 | 2177 | ||
2175 | * Patch by Allen Curtis, 21 Oct 2004: | 2178 | * Patch by Allen Curtis, 21 Oct 2004: |
2176 | support multiple serial ports | 2179 | support multiple serial ports |
2177 | 2180 | ||
2178 | * Patch by Richard Klingler, 03 Apr 2005: | 2181 | * Patch by Richard Klingler, 03 Apr 2005: |
2179 | Add call to eth_halt() in net/net.c when called functions fail | 2182 | Add call to eth_halt() in net/net.c when called functions fail |
2180 | after eth_init() has been called. | 2183 | after eth_init() has been called. |
2181 | 2184 | ||
2182 | * Patch by Sam Song, 3 April 2005: | 2185 | * Patch by Sam Song, 3 April 2005: |
2183 | - Update README.Netconsole | 2186 | - Update README.Netconsole |
2184 | - Update README | 2187 | - Update README |
2185 | 2188 | ||
2186 | * Prepare for SoC rework of ARM code: | 2189 | * Prepare for SoC rework of ARM code: |
2187 | - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL | 2190 | - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL |
2188 | - rename memsetup into lowlevel_init (function name and source files) | 2191 | - rename memsetup into lowlevel_init (function name and source files) |
2189 | Patch by Steven Scholz, 03 Apr 2005: | 2192 | Patch by Steven Scholz, 03 Apr 2005: |
2190 | - create SoC specific directories include/asm-arm/arch-imx and | 2193 | - create SoC specific directories include/asm-arm/arch-imx and |
2191 | include/asm-arm/arch-s3c24x0 | 2194 | include/asm-arm/arch-s3c24x0 |
2192 | 2195 | ||
2193 | * Fix problems with SNTP support; | 2196 | * Fix problems with SNTP support; |
2194 | enable SNTP support in some boards. | 2197 | enable SNTP support in some boards. |
2195 | 2198 | ||
2196 | * Patches by Martin Krause, 01 Apr 2005: | 2199 | * Patches by Martin Krause, 01 Apr 2005: |
2197 | - Fix flash erase timeout on CMC_PU2 | 2200 | - Fix flash erase timeout on CMC_PU2 |
2198 | - Add automatic HW detection for CMC_PU2 and CMC_BASIC | 2201 | - Add automatic HW detection for CMC_PU2 and CMC_BASIC |
2199 | 2202 | ||
2200 | * Patch by Steven Scholz, 13 March 2005: | 2203 | * Patch by Steven Scholz, 13 March 2005: |
2201 | fix cache enabling for AT91RM9200 | 2204 | fix cache enabling for AT91RM9200 |
2202 | 2205 | ||
2203 | * Patch by Masami Komiya, 30 Mar 2005: | 2206 | * Patch by Masami Komiya, 30 Mar 2005: |
2204 | add SNTP support and expand time server and time offset fields of | 2207 | add SNTP support and expand time server and time offset fields of |
2205 | DHCP support. See doc/README.SNTP | 2208 | DHCP support. See doc/README.SNTP |
2206 | 2209 | ||
2207 | * Patch by Steven Scholz, 13 Dec 2004: | 2210 | * Patch by Steven Scholz, 13 Dec 2004: |
2208 | Fix bug in at91rm920 ethernet driver | 2211 | Fix bug in at91rm920 ethernet driver |
2209 | 2212 | ||
2210 | * Patch by Steven Scholz, 13 Dec 2004: | 2213 | * Patch by Steven Scholz, 13 Dec 2004: |
2211 | Remove duplicated code by merging memsetup.S files for | 2214 | Remove duplicated code by merging memsetup.S files for |
2212 | at91rm9200 boards into one cpu/at91rm9200/lowlevel.S | 2215 | at91rm9200 boards into one cpu/at91rm9200/lowlevel.S |
2213 | 2216 | ||
2214 | * Patch by Detlev Zundel, 31 Mar 2005: | 2217 | * Patch by Detlev Zundel, 31 Mar 2005: |
2215 | Cleanup duplicate definition of overwrite_console() | 2218 | Cleanup duplicate definition of overwrite_console() |
2216 | 2219 | ||
2217 | * Update TQM5200 configuration; | 2220 | * Update TQM5200 configuration; |
2218 | prepare for Rev. 200 starter kit boards | 2221 | prepare for Rev. 200 starter kit boards |
2219 | 2222 | ||
2220 | * Patch by Scott McNutt, 21 Oct 2004: | 2223 | * Patch by Scott McNutt, 21 Oct 2004: |
2221 | Add support for Nios-II EPCS Controller core. | 2224 | Add support for Nios-II EPCS Controller core. |
2222 | 2225 | ||
2223 | * Patch by Scott McNutt, 20 Oct 2004: | 2226 | * Patch by Scott McNutt, 20 Oct 2004: |
2224 | Nios-II cleanups: | 2227 | Nios-II cleanups: |
2225 | - Add sysid command (Nios-II only). | 2228 | - Add sysid command (Nios-II only). |
2226 | - Locate default exception trampoline at proper offset. | 2229 | - Locate default exception trampoline at proper offset. |
2227 | - Implement I/O routines (readb, writeb, etc) | 2230 | - Implement I/O routines (readb, writeb, etc) |
2228 | - Implement do_bootm_linux | 2231 | - Implement do_bootm_linux |
2229 | 2232 | ||
2230 | * Patches by Martin Krause, 22 Mar 2005: | 2233 | * Patches by Martin Krause, 22 Mar 2005: |
2231 | - use TQM5200_auto as MAKEALL target for TQM5200 systems | 2234 | - use TQM5200_auto as MAKEALL target for TQM5200 systems |
2232 | - add support for SM501 graphics controller | 2235 | - add support for SM501 graphics controller |
2233 | - add support for graphic console on TQM5200 | 2236 | - add support for graphic console on TQM5200 |
2234 | - add support for TQM5200 Rev 200 | 2237 | - add support for TQM5200 Rev 200 |
2235 | - cleanup, fix typo in include/configs/TQM5200.h | 2238 | - cleanup, fix typo in include/configs/TQM5200.h |
2236 | 2239 | ||
2237 | * Patch by Manfred Baral, 17 Mar 2005: | 2240 | * Patch by Manfred Baral, 17 Mar 2005: |
2238 | Fix typo | 2241 | Fix typo |
2239 | 2242 | ||
2240 | * Fix RTC configuration for PPChameleon board | 2243 | * Fix RTC configuration for PPChameleon board |
2241 | 2244 | ||
2242 | * Cleanup, fix typo in include/configs/TQM5200.h | 2245 | * Cleanup, fix typo in include/configs/TQM5200.h |
2243 | 2246 | ||
2244 | * Patch by Stefan Roese, 16 Mar 2005: | 2247 | * Patch by Stefan Roese, 16 Mar 2005: |
2245 | Update for esd auto_update and hh405 board | 2248 | Update for esd auto_update and hh405 board |
2246 | 2249 | ||
2247 | * Adapt for U-Boot image size (new features enabled) on TQM5200 | 2250 | * Adapt for U-Boot image size (new features enabled) on TQM5200 |
2248 | 2251 | ||
2249 | * Update code for TQM8540 board (and 85xx in general): | 2252 | * Update code for TQM8540 board (and 85xx in general): |
2250 | - Change the name of the Ethernet driver: MOTO ENET -> ENET | 2253 | - Change the name of the Ethernet driver: MOTO ENET -> ENET |
2251 | - Reformat boot messages | 2254 | - Reformat boot messages |
2252 | - Enable redundant environment | 2255 | - Enable redundant environment |
2253 | - Replace the -O2 optimization flag with -mno-string | 2256 | - Replace the -O2 optimization flag with -mno-string |
2254 | 2257 | ||
2255 | * Patch by David Brownell, 10 Mar 2005: | 2258 | * Patch by David Brownell, 10 Mar 2005: |
2256 | Restore copyright statements in OHCI drivers. | 2259 | Restore copyright statements in OHCI drivers. |
2257 | 2260 | ||
2258 | * Add support for TQM8540 board | 2261 | * Add support for TQM8540 board |
2259 | 2262 | ||
2260 | * Patch by Detlev Zundel, 14 Mar 2005: | 2263 | * Patch by Detlev Zundel, 14 Mar 2005: |
2261 | NC650: changed NAND flash addressing to using UPMB | 2264 | NC650: changed NAND flash addressing to using UPMB |
2262 | 2265 | ||
2263 | * Patch by Stefan Roese, 14 Mar 2005: | 2266 | * Patch by Stefan Roese, 14 Mar 2005: |
2264 | Update for esd voh405 fpga image | 2267 | Update for esd voh405 fpga image |
2265 | 2268 | ||
2266 | * INKA4x0: Allow initialization of LCD backlight dimming from | 2269 | * INKA4x0: Allow initialization of LCD backlight dimming from |
2267 | "brightness" environment variable. | 2270 | "brightness" environment variable. |
2268 | 2271 | ||
2269 | * Add port initialization for digital I/O on INKA4x0 | 2272 | * Add port initialization for digital I/O on INKA4x0 |
2270 | 2273 | ||
2271 | * Patch by Stefan Roese, 01 Mar 2005: | 2274 | * Patch by Stefan Roese, 01 Mar 2005: |
2272 | Update for esd boards dp405 and hub405 | 2275 | Update for esd boards dp405 and hub405 |
2273 | 2276 | ||
2274 | * Fix get_partition_info() parameter error in all other calls | 2277 | * Fix get_partition_info() parameter error in all other calls |
2275 | (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c). | 2278 | (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c). |
2276 | 2279 | ||
2277 | * Enable USB and IDE support for INKA4x0 board | 2280 | * Enable USB and IDE support for INKA4x0 board |
2278 | 2281 | ||
2279 | * Patch by Andrew Dyer, 28 Feb 2005: | 2282 | * Patch by Andrew Dyer, 28 Feb 2005: |
2280 | fix ext2load passing an incorrect pointer to get_partition_info() | 2283 | fix ext2load passing an incorrect pointer to get_partition_info() |
2281 | resulting in load failure for devices other than 0 | 2284 | resulting in load failure for devices other than 0 |
2282 | 2285 | ||
2283 | * Add support for SRAM and 2 x Quad UARTs on INKA4x0 board | 2286 | * Add support for SRAM and 2 x Quad UARTs on INKA4x0 board |
2284 | 2287 | ||
2285 | * Cleanup USB and partition defines | 2288 | * Cleanup USB and partition defines |
2286 | 2289 | ||
2287 | * Add support for ext2 filesystems and image timestamps to TQM5200 board | 2290 | * Add support for ext2 filesystems and image timestamps to TQM5200 board |
2288 | 2291 | ||
2289 | * Add reset code for Coral-P on INKA4x0 board | 2292 | * Add reset code for Coral-P on INKA4x0 board |
2290 | 2293 | ||
2291 | * Patch by Martin Krause, 28 Jun 2004: | 2294 | * Patch by Martin Krause, 28 Jun 2004: |
2292 | Update for TRAB board. | 2295 | Update for TRAB board. |
2293 | 2296 | ||
2294 | * Fix some missing "volatile"s in MPC5xxx FEC driver | 2297 | * Fix some missing "volatile"s in MPC5xxx FEC driver |
2295 | 2298 | ||
2296 | * Fix cirrus voltage detection (for CPC45) | 2299 | * Fix cirrus voltage detection (for CPC45) |
2297 | 2300 | ||
2298 | * Fix byteorder problem in usbboot and scsiboot commands. | 2301 | * Fix byteorder problem in usbboot and scsiboot commands. |
2299 | 2302 | ||
2300 | * Patch by Cajus Hahn, 04 Feb 2005: | 2303 | * Patch by Cajus Hahn, 04 Feb 2005: |
2301 | - don't insist on leading '/' for filename in ext2load | 2304 | - don't insist on leading '/' for filename in ext2load |
2302 | - set default partition to useful value (1) in ext2load | 2305 | - set default partition to useful value (1) in ext2load |
2303 | 2306 | ||
2304 | * Patch by Andrew Dyer, 08 Jan 2005: | 2307 | * Patch by Andrew Dyer, 08 Jan 2005: |
2305 | fix wrong return codes in ext2 code | 2308 | fix wrong return codes in ext2 code |
2306 | 2309 | ||
2307 | * Removed '--no-warn-mismatch' option from Makefile. This option | 2310 | * Removed '--no-warn-mismatch' option from Makefile. This option |
2308 | makes 'ld' to overlook binary objects compatibility. | 2311 | makes 'ld' to overlook binary objects compatibility. |
2309 | 2312 | ||
2310 | * Moved $(PLATFORM_LIBS) from the library group (--start-group ... | 2313 | * Moved $(PLATFORM_LIBS) from the library group (--start-group ... |
2311 | --end-group) outside of the group. This will make 'ld' to do | 2314 | --end-group) outside of the group. This will make 'ld' to do |
2312 | _multiple_ search in the library group when resolving symbol | 2315 | _multiple_ search in the library group when resolving symbol |
2313 | references and do only a _single_ seach in libgcc.a after the group | 2316 | references and do only a _single_ seach in libgcc.a after the group |
2314 | search. | 2317 | search. |
2315 | 2318 | ||
2316 | * Fix stability problems on CPC45 board again. | 2319 | * Fix stability problems on CPC45 board again. |
2317 | 2320 | ||
2318 | * Make image detection for diskboot / usbboot / scsiboot more robust | 2321 | * Make image detection for diskboot / usbboot / scsiboot more robust |
2319 | (also check header checksum) | 2322 | (also check header checksum) |
2320 | 2323 | ||
2321 | * Update CPC45 board configuration. | 2324 | * Update CPC45 board configuration. |
2322 | 2325 | ||
2323 | * Add USB and PCI support for INKA4x0 board | 2326 | * Add USB and PCI support for INKA4x0 board |
2324 | 2327 | ||
2325 | * Fix IDE stability problems on CPC45 board (needs 2 x EIEIO). | 2328 | * Fix IDE stability problems on CPC45 board (needs 2 x EIEIO). |
2326 | 2329 | ||
2327 | * Code cleanup | 2330 | * Code cleanup |
2328 | 2331 | ||
2329 | * Patch by Robin Getz, 13 Oct 2004: | 2332 | * Patch by Robin Getz, 13 Oct 2004: |
2330 | Add standalone application to change SMC91C111 MAC addresses, | 2333 | Add standalone application to change SMC91C111 MAC addresses, |
2331 | see examples/README.smc91111_eeprom | 2334 | see examples/README.smc91111_eeprom |
2332 | 2335 | ||
2333 | * Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: | 2336 | * Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: |
2334 | Fix Flash support for ARM Integrator CP. | 2337 | Fix Flash support for ARM Integrator CP. |
2335 | 2338 | ||
2336 | * Patch by Richard Woodruff, 10 Jan 2005: | 2339 | * Patch by Richard Woodruff, 10 Jan 2005: |
2337 | Update support for OMAP2420 (ARM11) and H4 board: | 2340 | Update support for OMAP2420 (ARM11) and H4 board: |
2338 | o clean up and add new types to H4 memory probe code. | 2341 | o clean up and add new types to H4 memory probe code. |
2339 | o fix to work with internal boot. | 2342 | o fix to work with internal boot. |
2340 | o added PRCM config III operation. | 2343 | o added PRCM config III operation. |
2341 | o fix marginal flash timings. | 2344 | o fix marginal flash timings. |
2342 | o add revison ATAG usage. | 2345 | o add revison ATAG usage. |
2343 | o enable voltage scaling at power chip. | 2346 | o enable voltage scaling at power chip. |
2344 | o fix compile error for i2c. | 2347 | o fix compile error for i2c. |
2345 | 2348 | ||
2346 | * Fix network problem (error when receiving multiple ARP packets) | 2349 | * Fix network problem (error when receiving multiple ARP packets) |
2347 | 2350 | ||
2348 | * Patch by Daniel Poirot, 12 Oct 2004: | 2351 | * Patch by Daniel Poirot, 12 Oct 2004: |
2349 | Add support for Wind River sbc405 board | 2352 | Add support for Wind River sbc405 board |
2350 | 2353 | ||
2351 | * Patch by Rainer Brestan, 12 Oct 2004: | 2354 | * Patch by Rainer Brestan, 12 Oct 2004: |
2352 | Make examples/Makefile more robust | 2355 | Make examples/Makefile more robust |
2353 | 2356 | ||
2354 | * Patch by Sam Song, 11 October 2004: | 2357 | * Patch by Sam Song, 11 October 2004: |
2355 | - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board | 2358 | - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board |
2356 | - Adjust CPU:BUS frequency ratio 1:1 when core frequency | 2359 | - Adjust CPU:BUS frequency ratio 1:1 when core frequency |
2357 | less than 50MHz | 2360 | less than 50MHz |
2358 | 2361 | ||
2359 | * Patch by Sam Song, 10 Oct 2004: | 2362 | * Patch by Sam Song, 10 Oct 2004: |
2360 | Fix a parameter error in run_command() in main.c | 2363 | Fix a parameter error in run_command() in main.c |
2361 | 2364 | ||
2362 | * Patch by Richard Woodruff, 01 Oct 2004: | 2365 | * Patch by Richard Woodruff, 01 Oct 2004: |
2363 | add support for the TI OMAP2420 processor and its H4 reference | 2366 | add support for the TI OMAP2420 processor and its H4 reference |
2364 | board | 2367 | board |
2365 | 2368 | ||
2366 | * Patch by Christian Pellegrin, 24 Sep 2004: | 2369 | * Patch by Christian Pellegrin, 24 Sep 2004: |
2367 | Added support for NE2000 compatible (DP8390, DP83902) NICs. | 2370 | Added support for NE2000 compatible (DP8390, DP83902) NICs. |
2368 | 2371 | ||
2369 | * Patch by Leif Lindholm, 23 Sep 2004: | 2372 | * Patch by Leif Lindholm, 23 Sep 2004: |
2370 | add support for the AMD db1550 board | 2373 | add support for the AMD db1550 board |
2371 | 2374 | ||
2372 | * Patch by Travis Sawyer, 15 Sep 2004: | 2375 | * Patch by Travis Sawyer, 15 Sep 2004: |
2373 | Add CONFIG_SERIAL_MULTI support for ppc4xx, | 2376 | Add CONFIG_SERIAL_MULTI support for ppc4xx, |
2374 | update README.serial_multi | 2377 | update README.serial_multi |
2375 | 2378 | ||
2376 | * Patches by David Snowdon, 07 Sep 2004: | 2379 | * Patches by David Snowdon, 07 Sep 2004: |
2377 | - add u-boot.hex target in the top level Makefile | 2380 | - add u-boot.hex target in the top level Makefile |
2378 | - add support for the UNSW/NICTA PLEB 2 board (pleb2) | 2381 | - add support for the UNSW/NICTA PLEB 2 board (pleb2) |
2379 | - use -mtune=xscale and -march=armv5 options for PXA | 2382 | - use -mtune=xscale and -march=armv5 options for PXA |
2380 | 2383 | ||
2381 | * Patch by Florian Schlote, 08 Sep 2004: | 2384 | * Patch by Florian Schlote, 08 Sep 2004: |
2382 | Add support for SenTec-COBRA5272-board (ColdFire). | 2385 | Add support for SenTec-COBRA5272-board (ColdFire). |
2383 | 2386 | ||
2384 | * Patch by Gleb Natapov, 07 Sep 2004: | 2387 | * Patch by Gleb Natapov, 07 Sep 2004: |
2385 | mpc824x: set PCI latency timer to a sane value | 2388 | mpc824x: set PCI latency timer to a sane value |
2386 | (is 0 after reset). | 2389 | (is 0 after reset). |
2387 | 2390 | ||
2388 | * Patch by Kurt Stremerch, 03 Sep 2004: | 2391 | * Patch by Kurt Stremerch, 03 Sep 2004: |
2389 | Add bitstream configuration option for fpga command (Xilinx only). | 2392 | Add bitstream configuration option for fpga command (Xilinx only). |
2390 | 2393 | ||
2391 | * Patch by Kurt Stremerch, 03 Sep 2004: | 2394 | * Patch by Kurt Stremerch, 03 Sep 2004: |
2392 | Add Xilinx Spartan2E family FPGA support | 2395 | Add Xilinx Spartan2E family FPGA support |
2393 | 2396 | ||
2394 | * Patch by Jeff Angielski, 02 Sep 2004: | 2397 | * Patch by Jeff Angielski, 02 Sep 2004: |
2395 | Add Added support for H2 revision of the EP8260 board. | 2398 | Add Added support for H2 revision of the EP8260 board. |
2396 | Fixed formatting for some of the EP8260 related source files. | 2399 | Fixed formatting for some of the EP8260 related source files. |
2397 | 2400 | ||
2398 | * Patch by Jon Loeliger, 02 Sep 2004: | 2401 | * Patch by Jon Loeliger, 02 Sep 2004: |
2399 | Reset monitor size back to 256 so environment can be written | 2402 | Reset monitor size back to 256 so environment can be written |
2400 | to flash on MPC85xx ADS and CDS releases. | 2403 | to flash on MPC85xx ADS and CDS releases. |
2401 | 2404 | ||
2402 | * Patch by Paolo Broggini, 02 Sep 2004: | 2405 | * Patch by Paolo Broggini, 02 Sep 2004: |
2403 | Make BSS clearing on ARM systems more robust | 2406 | Make BSS clearing on ARM systems more robust |
2404 | 2407 | ||
2405 | * Patch by Yue Hu and Joe, 01 Sep 2004: | 2408 | * Patch by Yue Hu and Joe, 01 Sep 2004: |
2406 | - add PCI support for ixp425; | 2409 | - add PCI support for ixp425; |
2407 | - add EEPRO100 suppor tfor ixdp425 board. | 2410 | - add EEPRO100 suppor tfor ixdp425 board. |
2408 | 2411 | ||
2409 | * Fix problem with protected sector detection in driver/cfi_flash.c | 2412 | * Fix problem with protected sector detection in driver/cfi_flash.c |
2410 | 2413 | ||
2411 | ====================================================================== | 2414 | ====================================================================== |
2412 | Changes for U-Boot 1.1.2: | 2415 | Changes for U-Boot 1.1.2: |
2413 | ====================================================================== | 2416 | ====================================================================== |
2414 | 2417 | ||
2415 | * Code cleanup, mostly for GCC-3.3.x | 2418 | * Code cleanup, mostly for GCC-3.3.x |
2416 | 2419 | ||
2417 | * Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to | 2420 | * Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to |
2418 | pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for | 2421 | pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for |
2419 | additional ethernet addresses. | 2422 | additional ethernet addresses. |
2420 | 2423 | ||
2421 | * Cleanup drivers/i82365.c - avoid duplication of code | 2424 | * Cleanup drivers/i82365.c - avoid duplication of code |
2422 | 2425 | ||
2423 | * Fix bogus "cannot span across banks" flash error message | 2426 | * Fix bogus "cannot span across banks" flash error message |
2424 | 2427 | ||
2425 | * Code cleanup | 2428 | * Code cleanup |
2426 | 2429 | ||
2427 | * Add support for CompactFlash for the CPC45 Board. | 2430 | * Add support for CompactFlash for the CPC45 Board. |
2428 | 2431 | ||
2429 | * Fix problems with CMC_PU2 flash driver. | 2432 | * Fix problems with CMC_PU2 flash driver. |
2430 | 2433 | ||
2431 | * Cleanup: | 2434 | * Cleanup: |
2432 | - avoid trigraph warning in fs/ext2/ext2fs.c | 2435 | - avoid trigraph warning in fs/ext2/ext2fs.c |
2433 | - rename UC100 -> uc100 | 2436 | - rename UC100 -> uc100 |
2434 | 2437 | ||
2435 | * Add support for UC100 board | 2438 | * Add support for UC100 board |
2436 | 2439 | ||
2437 | * Patch by Stefan Roese, 16 Dez 2004: | 2440 | * Patch by Stefan Roese, 16 Dez 2004: |
2438 | - ext2fs support added | 2441 | - ext2fs support added |
2439 | - Tundra universe support added | 2442 | - Tundra universe support added |
2440 | - ColdFire MCF5249 support added (no preloader needed!) | 2443 | - ColdFire MCF5249 support added (no preloader needed!) |
2441 | - MCF5249 board TASREG added | 2444 | - MCF5249 board TASREG added |
2442 | - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405, | 2445 | - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405, |
2443 | VOM405, WUH405 | 2446 | VOM405, WUH405 |
2444 | - some esd boards updated | 2447 | - some esd boards updated |
2445 | - memory commands "mdc" and "mwc" added for cyclic read/write | 2448 | - memory commands "mdc" and "mwc" added for cyclic read/write |
2446 | (CONFIG_MX_CYCLIC, see README for further description) | 2449 | (CONFIG_MX_CYCLIC, see README for further description) |
2447 | 2450 | ||
2448 | * Add support for INKA4X0 board | 2451 | * Add support for INKA4X0 board |
2449 | 2452 | ||
2450 | * Patch by Steven Scholz, 12 Dec 2004: | 2453 | * Patch by Steven Scholz, 12 Dec 2004: |
2451 | Fix typo in AT91 memory setup. | 2454 | Fix typo in AT91 memory setup. |
2452 | 2455 | ||
2453 | * Patch by Martin Krause, 27 Oct 2004: | 2456 | * Patch by Martin Krause, 27 Oct 2004: |
2454 | - add support for "STK52xx" board (including PS/2 multiplexer) | 2457 | - add support for "STK52xx" board (including PS/2 multiplexer) |
2455 | - add hardware detection for TQM5200 | 2458 | - add hardware detection for TQM5200 |
2456 | 2459 | ||
2457 | * Clean up CMC PU2 flash driver | 2460 | * Clean up CMC PU2 flash driver |
2458 | 2461 | ||
2459 | * Update MAINTAINERS file | 2462 | * Update MAINTAINERS file |
2460 | 2463 | ||
2461 | * Fix bug in MPC823 LCD driver | 2464 | * Fix bug in MPC823 LCD driver |
2462 | 2465 | ||
2463 | * Fix udelay() on AT91RM9200 for delays < 1 ms. | 2466 | * Fix udelay() on AT91RM9200 for delays < 1 ms. |
2464 | 2467 | ||
2465 | * Enable long help on CMC PU2 board; | 2468 | * Enable long help on CMC PU2 board; |
2466 | fix reset issue; | 2469 | fix reset issue; |
2467 | increase CPU speed from 179 to 207 MHz. | 2470 | increase CPU speed from 179 to 207 MHz. |
2468 | 2471 | ||
2469 | * Fix smc91111 ethernet driver for Xaeniax board (need to handle | 2472 | * Fix smc91111 ethernet driver for Xaeniax board (need to handle |
2470 | unaligned tail part specially). | 2473 | unaligned tail part specially). |
2471 | 2474 | ||
2472 | * Update for AT91RM9200DK and CMC_PU2 boards: | 2475 | * Update for AT91RM9200DK and CMC_PU2 boards: |
2473 | - Enable booting directly from flash | 2476 | - Enable booting directly from flash |
2474 | - fix CMC_PU2 flash driver | 2477 | - fix CMC_PU2 flash driver |
2475 | 2478 | ||
2476 | * Fix mkimage usage message | 2479 | * Fix mkimage usage message |
2477 | 2480 | ||
2478 | * Map SRAM on NC650 board | 2481 | * Map SRAM on NC650 board |
2479 | 2482 | ||
2480 | * Work around for Ethernet problems on Xaeniax board | 2483 | * Work around for Ethernet problems on Xaeniax board |
2481 | 2484 | ||
2482 | * Patch by TsiChung Liew, 23 Sep 2004: | 2485 | * Patch by TsiChung Liew, 23 Sep 2004: |
2483 | - add support for MPC8220 CPU | 2486 | - add support for MPC8220 CPU |
2484 | - Add support for Alaska and Yukon boards | 2487 | - Add support for Alaska and Yukon boards |
2485 | 2488 | ||
2486 | * Fix configuration for ERIC board (needs more room) | 2489 | * Fix configuration for ERIC board (needs more room) |
2487 | 2490 | ||
2488 | * Adjust MIPS compiler options at run-time depending on tools version | 2491 | * Adjust MIPS compiler options at run-time depending on tools version |
2489 | ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, | 2492 | ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, |
2490 | "-mcpu=4kc" for old tools) | 2493 | "-mcpu=4kc" for old tools) |
2491 | 2494 | ||
2492 | * Add passing of the command line and memory size information to the | 2495 | * Add passing of the command line and memory size information to the |
2493 | kernel on xaeniax board. | 2496 | kernel on xaeniax board. |
2494 | 2497 | ||
2495 | * Enable NAND flash support for NC650 board. | 2498 | * Enable NAND flash support for NC650 board. |
2496 | 2499 | ||
2497 | * Patch by Thomas Lange 07 Oct 2004: | 2500 | * Patch by Thomas Lange 07 Oct 2004: |
2498 | Updated README for DBAu1x00 boards to match current status | 2501 | Updated README for DBAu1x00 boards to match current status |
2499 | 2502 | ||
2500 | * Patch by Philippe Robin, 28 Sept 2004: | 2503 | * Patch by Philippe Robin, 28 Sept 2004: |
2501 | Fix Flash support for Versatile. | 2504 | Fix Flash support for Versatile. |
2502 | 2505 | ||
2503 | * Patch by Roger Blofeld, 16 Sep 2004: | 2506 | * Patch by Roger Blofeld, 16 Sep 2004: |
2504 | Fix timeout for DHCP command retry | 2507 | Fix timeout for DHCP command retry |
2505 | 2508 | ||
2506 | * Patch by Pantelis Antoniou, 14 Sep 2004: | 2509 | * Patch by Pantelis Antoniou, 14 Sep 2004: |
2507 | Fix early serial hang when CONFIG_SERIAL_MULTI is defined. | 2510 | Fix early serial hang when CONFIG_SERIAL_MULTI is defined. |
2508 | 2511 | ||
2509 | * Patch by Pantelis Antoniou, 14 Sep 2004: | 2512 | * Patch by Pantelis Antoniou, 14 Sep 2004: |
2510 | Kick watchdog when bz-decompressing | 2513 | Kick watchdog when bz-decompressing |
2511 | 2514 | ||
2512 | * Fix CFG_HZ problems on AT91RM9200 systems | 2515 | * Fix CFG_HZ problems on AT91RM9200 systems |
2513 | [Remember: CFG_HZ should be 1000 on ALL systems!] | 2516 | [Remember: CFG_HZ should be 1000 on ALL systems!] |
2514 | 2517 | ||
2515 | * Patch by Gridish Shlomi, 30 Aug 2004: | 2518 | * Patch by Gridish Shlomi, 30 Aug 2004: |
2516 | - Add support to revA version of PQ27 and PQ27E. | 2519 | - Add support to revA version of PQ27 and PQ27E. |
2517 | - Reverted MPC8260ADS baudrate back to original 115200 | 2520 | - Reverted MPC8260ADS baudrate back to original 115200 |
2518 | 2521 | ||
2519 | * Patch by Hojin, 17 Sep 2004: | 2522 | * Patch by Hojin, 17 Sep 2004: |
2520 | Fix typo in cfi_flash.c | 2523 | Fix typo in cfi_flash.c |
2521 | 2524 | ||
2522 | * Patch by Mark Jonas, 09 September 2004: | 2525 | * Patch by Mark Jonas, 09 September 2004: |
2523 | mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong | 2526 | mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong |
2524 | error message | 2527 | error message |
2525 | 2528 | ||
2526 | * Patch by Mark Jonas, 31 August 2004: | 2529 | * Patch by Mark Jonas, 31 August 2004: |
2527 | Added option CFG_XLB_PIPELINING to enable XLB pipelining. This | 2530 | Added option CFG_XLB_PIPELINING to enable XLB pipelining. This |
2528 | improves FTP performance for MPC5200 systems. Enabled for IceCube | 2531 | improves FTP performance for MPC5200 systems. Enabled for IceCube |
2529 | by default. | 2532 | by default. |
2530 | 2533 | ||
2531 | * Patch by Michael Bendzick, 30 Aug 2004: | 2534 | * Patch by Michael Bendzick, 30 Aug 2004: |
2532 | - Improve platform.S code for omap1510inn that detects whether code | 2535 | - Improve platform.S code for omap1510inn that detects whether code |
2533 | is running from SDRAM or not. Patch allows SDRAM to be configured | 2536 | is running from SDRAM or not. Patch allows SDRAM to be configured |
2534 | if code is running out of SRAM at 0x20000000. | 2537 | if code is running out of SRAM at 0x20000000. |
2535 | 2538 | ||
2536 | * Patch by Frederick Klatt, 30 Aug 2004: | 2539 | * Patch by Frederick Klatt, 30 Aug 2004: |
2537 | Add support for the Wind River SBC8540/SBC8560 boards | 2540 | Add support for the Wind River SBC8540/SBC8560 boards |
2538 | 2541 | ||
2539 | * Configure SX1 board to use drivers/cfi_flash.c | 2542 | * Configure SX1 board to use drivers/cfi_flash.c |
2540 | 2543 | ||
2541 | * Patches by Michael Bendzick, 30 Aug 2004: | 2544 | * Patches by Michael Bendzick, 30 Aug 2004: |
2542 | - Configure omap1510inn board to use drivers/cfi_flash.c | 2545 | - Configure omap1510inn board to use drivers/cfi_flash.c |
2543 | - Make drivers/cfi_flash.c protect environment and redundant | 2546 | - Make drivers/cfi_flash.c protect environment and redundant |
2544 | environment. | 2547 | environment. |
2545 | 2548 | ||
2546 | * Patch by Steven Scholz, 23 Jun 2004: | 2549 | * Patch by Steven Scholz, 23 Jun 2004: |
2547 | - Add script (tools/img2brec.sh) to programm U-Boot into | 2550 | - Add script (tools/img2brec.sh) to programm U-Boot into |
2548 | (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L | 2551 | (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L |
2549 | 2552 | ||
2550 | * Patches by Scott McNutt, 24 Aug 2004: | 2553 | * Patches by Scott McNutt, 24 Aug 2004: |
2551 | - Add support for Altera Nios-II processors. | 2554 | - Add support for Altera Nios-II processors. |
2552 | - Add support for Psyent PCI-5441 board. | 2555 | - Add support for Psyent PCI-5441 board. |
2553 | - Add support for Psyent PK1C20 board. | 2556 | - Add support for Psyent PK1C20 board. |
2554 | 2557 | ||
2555 | * Patches by Jon Loeliger, 24 Aug 2004: | 2558 | * Patches by Jon Loeliger, 24 Aug 2004: |
2556 | - Add support for the MPC8541 and MPC8555 CDS boards | 2559 | - Add support for the MPC8541 and MPC8555 CDS boards |
2557 | - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR | 2560 | - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR |
2558 | - Convert MPC85xxADS to use common CFI flash driver | 2561 | - Convert MPC85xxADS to use common CFI flash driver |
2559 | - Fix PCI window on MPC85xx; remove unneeded PCI initialization | 2562 | - Fix PCI window on MPC85xx; remove unneeded PCI initialization |
2560 | from board_early_init_f() | 2563 | from board_early_init_f() |
2561 | - Provide SW workaround for PCI initialization on 85xx CDS | 2564 | - Provide SW workaround for PCI initialization on 85xx CDS |
2562 | 2565 | ||
2563 | * Patches by George G. Davis, 24 Aug 2004: | 2566 | * Patches by George G. Davis, 24 Aug 2004: |
2564 | - Enable ramdisk/initrd tagged param support for omap1610h2_config | 2567 | - Enable ramdisk/initrd tagged param support for omap1610h2_config |
2565 | - Remove static network setup defaults from mx1ads_config | 2568 | - Remove static network setup defaults from mx1ads_config |
2566 | - update ARM boards to use constants from mach-types.h | 2569 | - update ARM boards to use constants from mach-types.h |
2567 | 2570 | ||
2568 | * Patch by Gary Jennejohn, 04 Oct 2004: | 2571 | * Patch by Gary Jennejohn, 04 Oct 2004: |
2569 | - fix I2C on at91rm9200 | 2572 | - fix I2C on at91rm9200 |
2570 | - add support for Ricoh RS5C372A RTC | 2573 | - add support for Ricoh RS5C372A RTC |
2571 | 2574 | ||
2572 | * Patch by Gary Jennejohn, 01 Oct 2004: | 2575 | * Patch by Gary Jennejohn, 01 Oct 2004: |
2573 | - add support for CMC PU2 board | 2576 | - add support for CMC PU2 board |
2574 | - add support for I2C on at91rm9200 | 2577 | - add support for I2C on at91rm9200 |
2575 | 2578 | ||
2576 | * Patch by Gary Jennejohn, 28 Sep 2004: | 2579 | * Patch by Gary Jennejohn, 28 Sep 2004: |
2577 | fix baudrate handling on at91rm9200 | 2580 | fix baudrate handling on at91rm9200 |
2578 | 2581 | ||
2579 | * Patch by Yuli Barcohen, 22 Aug 2004: | 2582 | * Patch by Yuli Barcohen, 22 Aug 2004: |
2580 | - remove ZPC.1900 board-specific flash driver; | 2583 | - remove ZPC.1900 board-specific flash driver; |
2581 | switch the port to generic CFI driver; | 2584 | switch the port to generic CFI driver; |
2582 | - port clean-up | 2585 | - port clean-up |
2583 | 2586 | ||
2584 | * Patch by Hinko Kocevar, 21 Aug 2004: | 2587 | * Patch by Hinko Kocevar, 21 Aug 2004: |
2585 | Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB | 2588 | Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB |
2586 | 2589 | ||
2587 | * Clean up tools/bmp_logo.c to not add trailing white space | 2590 | * Clean up tools/bmp_logo.c to not add trailing white space |
2588 | 2591 | ||
2589 | * Patch by Hinko Kocevar, 21 Aug 2004: | 2592 | * Patch by Hinko Kocevar, 21 Aug 2004: |
2590 | - Group common framebuffer functions in common/lcd.c | 2593 | - Group common framebuffer functions in common/lcd.c |
2591 | - Group common framebuffer macros and #defines in include/lcd.h | 2594 | - Group common framebuffer macros and #defines in include/lcd.h |
2592 | - Provide calc_fbsize() for video ATAG | 2595 | - Provide calc_fbsize() for video ATAG |
2593 | 2596 | ||
2594 | * Patch by Sam Song, 21 August 2004: | 2597 | * Patch by Sam Song, 21 August 2004: |
2595 | - Fix a typo in README | 2598 | - Fix a typo in README |
2596 | - Align "(RO)" output for "flinfo" after "protect on" | 2599 | - Align "(RO)" output for "flinfo" after "protect on" |
2597 | - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency | 2600 | - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency |
2598 | ratio 1:1 when core frequency less than 50MHz | 2601 | ratio 1:1 when core frequency less than 50MHz |
2599 | 2602 | ||
2600 | * Patches by Hinko Kocevar, 21 Aug 2004: | 2603 | * Patches by Hinko Kocevar, 21 Aug 2004: |
2601 | - fix some "use of label at end of compound statement" warnings | 2604 | - fix some "use of label at end of compound statement" warnings |
2602 | - Define type of LCD panel on lubbock board if CONFIG_LCD is used | 2605 | - Define type of LCD panel on lubbock board if CONFIG_LCD is used |
2603 | 2606 | ||
2604 | * Patch by Steven Scholz, 16 Aug 2004: | 2607 | * Patch by Steven Scholz, 16 Aug 2004: |
2605 | - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" | 2608 | - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" |
2606 | - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 | 2609 | - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 |
2607 | - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ | 2610 | - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ |
2608 | - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ | 2611 | - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ |
2609 | into cpu/arm920t/$(SOC)/ | 2612 | into cpu/arm920t/$(SOC)/ |
2610 | 2613 | ||
2611 | * Patches by Sean Chang, 09 Aug 2004: | 2614 | * Patches by Sean Chang, 09 Aug 2004: |
2612 | - Added support for both 8 and 16 bit mode access to System ACE CF | 2615 | - Added support for both 8 and 16 bit mode access to System ACE CF |
2613 | through MPU. | 2616 | through MPU. |
2614 | - Fixed missing System ACE CF device during get FAT partition info | 2617 | - Fixed missing System ACE CF device during get FAT partition info |
2615 | in fat_register_device function. | 2618 | in fat_register_device function. |
2616 | - Enabled System ACE CF support on ML300. | 2619 | - Enabled System ACE CF support on ML300. |
2617 | 2620 | ||
2618 | * Patch by Sean Chang, 09 Aug 2004: | 2621 | * Patch by Sean Chang, 09 Aug 2004: |
2619 | Synch defines for saveenv and do_saveenv functions so they get | 2622 | Synch defines for saveenv and do_saveenv functions so they get |
2620 | compiled under the same statement. | 2623 | compiled under the same statement. |
2621 | 2624 | ||
2622 | * Patch by Sean Chang, 09 Aug 2004: | 2625 | * Patch by Sean Chang, 09 Aug 2004: |
2623 | - Added I2C support for ML300. | 2626 | - Added I2C support for ML300. |
2624 | - Added support for ML300 to read out its environment information | 2627 | - Added support for ML300 to read out its environment information |
2625 | stored on the EEPROM. | 2628 | stored on the EEPROM. |
2626 | - Added support to use board specific parameters as part of | 2629 | - Added support to use board specific parameters as part of |
2627 | U-Boot's environment information. | 2630 | U-Boot's environment information. |
2628 | - Updated MLD files to support configuration for new features | 2631 | - Updated MLD files to support configuration for new features |
2629 | above. | 2632 | above. |
2630 | 2633 | ||
2631 | * Patches by Travis Sawyer, 05 Aug 2004: | 2634 | * Patches by Travis Sawyer, 05 Aug 2004: |
2632 | - Remove incorrect bridge settings for eth group 6 | 2635 | - Remove incorrect bridge settings for eth group 6 |
2633 | - Add call to setup bridge in ppc_440x_eth_initialize | 2636 | - Add call to setup bridge in ppc_440x_eth_initialize |
2634 | - Fix ppc_440x_eth_init to reset the phy only if its the | 2637 | - Fix ppc_440x_eth_init to reset the phy only if its the |
2635 | first time through, otherwise, just check the phy for the | 2638 | first time through, otherwise, just check the phy for the |
2636 | autonegotiated speed/duplex. This allows the use of netconsole | 2639 | autonegotiated speed/duplex. This allows the use of netconsole |
2637 | - only print the speed/duplex the first time the phy is reset. | 2640 | - only print the speed/duplex the first time the phy is reset. |
2638 | 2641 | ||
2639 | * Patch by Shlomo Kut, 29 Mar 2004: | 2642 | * Patch by Shlomo Kut, 29 Mar 2004: |
2640 | Add support for MKS Instruments "Quantum" board | 2643 | Add support for MKS Instruments "Quantum" board |
2641 | 2644 | ||
2642 | * Fix build problem with Cogent boards; | 2645 | * Fix build problem with Cogent boards; |
2643 | avoid using <asm/byteorder.h> when using the host compiler | 2646 | avoid using <asm/byteorder.h> when using the host compiler |
2644 | 2647 | ||
2645 | * Patch by Ganapathi C, 04 Aug 2004: | 2648 | * Patch by Ganapathi C, 04 Aug 2004: |
2646 | Fix NFS timeout issue | 2649 | Fix NFS timeout issue |
2647 | 2650 | ||
2648 | * Patch by Yuli Barcohen, 19 Jul 2004: | 2651 | * Patch by Yuli Barcohen, 19 Jul 2004: |
2649 | - Fix host tools building in Cygwin environment | 2652 | - Fix host tools building in Cygwin environment |
2650 | - Fix header files search order for host tools | 2653 | - Fix header files search order for host tools |
2651 | 2654 | ||
2652 | * Patch by Tom Armistead, 19 Jul 2004: | 2655 | * Patch by Tom Armistead, 19 Jul 2004: |
2653 | Fix kgdb.S support for 74xx_75x cpu | 2656 | Fix kgdb.S support for 74xx_75x cpu |
2654 | 2657 | ||
2655 | * Patch by Jon Loeliger, 15 Jul 2004: | 2658 | * Patch by Jon Loeliger, 15 Jul 2004: |
2656 | Fix MPC85xx I2C driver | 2659 | Fix MPC85xx I2C driver |
2657 | 2660 | ||
2658 | * Fix problems with CDROM drive as slave device on Lite5200 IDE bus. | 2661 | * Fix problems with CDROM drive as slave device on Lite5200 IDE bus. |
2659 | 2662 | ||
2660 | * Patch by Stephen Williams, 15 July 2004 | 2663 | * Patch by Stephen Williams, 15 July 2004 |
2661 | Set the PCI class code for JSE board as part of PCI interface setup | 2664 | Set the PCI class code for JSE board as part of PCI interface setup |
2662 | 2665 | ||
2663 | * Patch by Michael Bendzick, 15 Jul 2004: | 2666 | * Patch by Michael Bendzick, 15 Jul 2004: |
2664 | Fix problem with writes with odd sizes in drivers/cfi_flash.c when | 2667 | Fix problem with writes with odd sizes in drivers/cfi_flash.c when |
2665 | CFG_FLASH_USE_BUFFER_WRITE is set | 2668 | CFG_FLASH_USE_BUFFER_WRITE is set |
2666 | 2669 | ||
2667 | * Patch by Yuli Barcohen, 13 Jul 2004: | 2670 | * Patch by Yuli Barcohen, 13 Jul 2004: |
2668 | Allow clock setting on MPC866/MPC885 series chips according to | 2671 | Allow clock setting on MPC866/MPC885 series chips according to |
2669 | environment variable `cpuclk' | 2672 | environment variable `cpuclk' |
2670 | 2673 | ||
2671 | * Patch by Yuli Barcohen, 20 Apr 2004: | 2674 | * Patch by Yuli Barcohen, 20 Apr 2004: |
2672 | Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x | 2675 | Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x |
2673 | 2676 | ||
2674 | * Patch by Vincent Dubey, 24 Sep 2004: | 2677 | * Patch by Vincent Dubey, 24 Sep 2004: |
2675 | Add support for xaeniax board | 2678 | Add support for xaeniax board |
2676 | 2679 | ||
2677 | * Add comment about non-GPL character of standalone applications to | 2680 | * Add comment about non-GPL character of standalone applications to |
2678 | COPYING file | 2681 | COPYING file |
2679 | 2682 | ||
2680 | * Fix FEC ethernet problem on NSCU board. | 2683 | * Fix FEC ethernet problem on NSCU board. |
2681 | 2684 | ||
2682 | * Patch by Gary Jennejohn, 09 Sep 2004: | 2685 | * Patch by Gary Jennejohn, 09 Sep 2004: |
2683 | allow to use USART1 as console port on at91rm9200dk boards | 2686 | allow to use USART1 as console port on at91rm9200dk boards |
2684 | 2687 | ||
2685 | * Patch by Stefan Roese, 16 Sep 2004: | 2688 | * Patch by Stefan Roese, 16 Sep 2004: |
2686 | Update AR405 board. | 2689 | Update AR405 board. |
2687 | 2690 | ||
2688 | * Fix SysClk handling for PPChameleon and CATcenter boards | 2691 | * Fix SysClk handling for PPChameleon and CATcenter boards |
2689 | 2692 | ||
2690 | * Patch by Detlev Zundel, 08 Sep 2004: | 2693 | * Patch by Detlev Zundel, 08 Sep 2004: |
2691 | Update etags build target | 2694 | Update etags build target |
2692 | 2695 | ||
2693 | * Improve NetConsole support: add support for broadcast destination | 2696 | * Improve NetConsole support: add support for broadcast destination |
2694 | address and buffered input. | 2697 | address and buffered input. |
2695 | 2698 | ||
2696 | * Cleanup compiler warnings for GCC 3.3.x and later | 2699 | * Cleanup compiler warnings for GCC 3.3.x and later |
2697 | 2700 | ||
2698 | * Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch | 2701 | * Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch |
2699 | 2702 | ||
2700 | * Add support for IDS "NC650" board | 2703 | * Add support for IDS "NC650" board |
2701 | 2704 | ||
2702 | * Add automatic update support for LWMON board | 2705 | * Add automatic update support for LWMON board |
2703 | 2706 | ||
2704 | * Clear Block Lock-Bits when erasing flash on LWMON board. | 2707 | * Clear Block Lock-Bits when erasing flash on LWMON board. |
2705 | 2708 | ||
2706 | * Fix return code of "fatload" command | 2709 | * Fix return code of "fatload" command |
2707 | 2710 | ||
2708 | * Enable MSDOS/VFAT filesystem support for LWMON board | 2711 | * Enable MSDOS/VFAT filesystem support for LWMON board |
2709 | 2712 | ||
2710 | * Patch by Martin Krause, 03 Aug 2004: | 2713 | * Patch by Martin Krause, 03 Aug 2004: |
2711 | change timing for SM501 graphics controller on TQM5200 module | 2714 | change timing for SM501 graphics controller on TQM5200 module |
2712 | 2715 | ||
2713 | * Patch by Mark Jonas, 13 July 2004: | 2716 | * Patch by Mark Jonas, 13 July 2004: |
2714 | - Total5200 LCD now run in little endian mode. Endianess conversion | 2717 | - Total5200 LCD now run in little endian mode. Endianess conversion |
2715 | is done in hardware. | 2718 | is done in hardware. |
2716 | - Removed last reference to "console" environment variable. | 2719 | - Removed last reference to "console" environment variable. |
2717 | 2720 | ||
2718 | * Patches by Lars Munch, 12 Jul 2004: | 2721 | * Patches by Lars Munch, 12 Jul 2004: |
2719 | - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk | 2722 | - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk |
2720 | board specific | 2723 | board specific |
2721 | - split out the LXT971A PHY from ns_9750_eth.h | 2724 | - split out the LXT971A PHY from ns_9750_eth.h |
2722 | - split the dm9161 phy part out of at91rm9200_ether.c | 2725 | - split the dm9161 phy part out of at91rm9200_ether.c |
2723 | 2726 | ||
2724 | * Patch by Andreas Engel, 12 Jul 2004: | 2727 | * Patch by Andreas Engel, 12 Jul 2004: |
2725 | Replaced hardcoded PL011 clock frequency with config variable. | 2728 | Replaced hardcoded PL011 clock frequency with config variable. |
2726 | Fixed wrong CONFIG_CMD_DFL doc. | 2729 | Fixed wrong CONFIG_CMD_DFL doc. |
2727 | 2730 | ||
2728 | * Patch by Thomas Viehweger, 09 Jun 2004: | 2731 | * Patch by Thomas Viehweger, 09 Jun 2004: |
2729 | make it possible to remove chpart when there is only one partition | 2732 | make it possible to remove chpart when there is only one partition |
2730 | 2733 | ||
2731 | * Add support for console over UDP (compatible to Ingo Molnar's | 2734 | * Add support for console over UDP (compatible to Ingo Molnar's |
2732 | netconsole patch under Linux) | 2735 | netconsole patch under Linux) |
2733 | 2736 | ||
2734 | * Patch by Jon Loeliger, 16 Jul 2004: | 2737 | * Patch by Jon Loeliger, 16 Jul 2004: |
2735 | - support larger DDR memories up to 2G on the PC8540/8560ADS and | 2738 | - support larger DDR memories up to 2G on the PC8540/8560ADS and |
2736 | STXGP3 boards | 2739 | STXGP3 boards |
2737 | - Made MPC8540/8560ADS be 33Mhz PCI by default. | 2740 | - Made MPC8540/8560ADS be 33Mhz PCI by default. |
2738 | - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 | 2741 | - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 |
2739 | and CONFIG_L2_INIT_RAM options. | 2742 | and CONFIG_L2_INIT_RAM options. |
2740 | - Refactor Local Bus initialization out of SDRAM setup. | 2743 | - Refactor Local Bus initialization out of SDRAM setup. |
2741 | - Re-implement new version of LBC11/DDR11 errata workarounds. | 2744 | - Re-implement new version of LBC11/DDR11 errata workarounds. |
2742 | - Moved board specific PCI init parts out of CPU directory. | 2745 | - Moved board specific PCI init parts out of CPU directory. |
2743 | - Added TLB entry for PCI-1 IO Memory | 2746 | - Added TLB entry for PCI-1 IO Memory |
2744 | - Updated README.mpc85xxads | 2747 | - Updated README.mpc85xxads |
2745 | 2748 | ||
2746 | * Patch by Sascha Hauer, 28 Jun: | 2749 | * Patch by Sascha Hauer, 28 Jun: |
2747 | - add generic support for Motorola i.MX architecture | 2750 | - add generic support for Motorola i.MX architecture |
2748 | - add support for mx1ads, mx1fs2 and scb9328 boards | 2751 | - add support for mx1ads, mx1fs2 and scb9328 boards |
2749 | 2752 | ||
2750 | * Patches by Marc Leeman, 23 Jul 2004: | 2753 | * Patches by Marc Leeman, 23 Jul 2004: |
2751 | - Add define for the PCI/Memory Buffer Configuration Register | 2754 | - Add define for the PCI/Memory Buffer Configuration Register |
2752 | - corrected comments in cpu/mpc824x/cpu_init.c | 2755 | - corrected comments in cpu/mpc824x/cpu_init.c |
2753 | 2756 | ||
2754 | * Add support for multiple serial interfaces | 2757 | * Add support for multiple serial interfaces |
2755 | (for example to allow modem dial-in / dial-out) | 2758 | (for example to allow modem dial-in / dial-out) |
2756 | 2759 | ||
2757 | * Patch by Stefan Roese, 15 Jul 2004: | 2760 | * Patch by Stefan Roese, 15 Jul 2004: |
2758 | cpu/ppc4xx/sdram.c rewritten now using get_ram_size() | 2761 | cpu/ppc4xx/sdram.c rewritten now using get_ram_size() |
2759 | 2762 | ||
2760 | * Fix NSCU config; add ethernet wakeup code. | 2763 | * Fix NSCU config; add ethernet wakeup code. |
2761 | 2764 | ||
2762 | * Add link for preloader for Motorola ColdFire to README.m68k | 2765 | * Add link for preloader for Motorola ColdFire to README.m68k |
2763 | 2766 | ||
2764 | * Patch by Michael Bendzick, 12 Jul 2004: | 2767 | * Patch by Michael Bendzick, 12 Jul 2004: |
2765 | fix output formatting in drivers/cfi_flash.c | 2768 | fix output formatting in drivers/cfi_flash.c |
2766 | 2769 | ||
2767 | * Patch by Mark Jonas, 02 Jul 2004: | 2770 | * Patch by Mark Jonas, 02 Jul 2004: |
2768 | Fix lowboot (again) on MPC5xxx | 2771 | Fix lowboot (again) on MPC5xxx |
2769 | 2772 | ||
2770 | * Patch by Curt Brune, 07 Jul 2004: | 2773 | * Patch by Curt Brune, 07 Jul 2004: |
2771 | relocate exception vectors on arm720t if needed | 2774 | relocate exception vectors on arm720t if needed |
2772 | 2775 | ||
2773 | * Patch by George G. Davis, 06 Jul 2004: | 2776 | * Patch by George G. Davis, 06 Jul 2004: |
2774 | - update mach-types.h to latest arm.linux.org.uk master list | 2777 | - update mach-types.h to latest arm.linux.org.uk master list |
2775 | - Set correct OMAP1610 bi_arch_number for build target | 2778 | - Set correct OMAP1610 bi_arch_number for build target |
2776 | 2779 | ||
2777 | * Patch by Curt Brune, 06 Jul 2004: | 2780 | * Patch by Curt Brune, 06 Jul 2004: |
2778 | evb4510: add support for timer interrupt; cleanup | 2781 | evb4510: add support for timer interrupt; cleanup |
2779 | 2782 | ||
2780 | * Patch by Dan Poirot, 06 Jul 2004: | 2783 | * Patch by Dan Poirot, 06 Jul 2004: |
2781 | Fix sbc8260 environment variables | 2784 | Fix sbc8260 environment variables |
2782 | 2785 | ||
2783 | * Cleanup redundand "console" environment variable | 2786 | * Cleanup redundand "console" environment variable |
2784 | 2787 | ||
2785 | * Patch by Mark Jonas, 05 Jul 2004: | 2788 | * Patch by Mark Jonas, 05 Jul 2004: |
2786 | add support for the Total5100's and Total5200's LCD screen | 2789 | add support for the Total5100's and Total5200's LCD screen |
2787 | 2790 | ||
2788 | * Patches by Dan Eisenhut, 01 Jul 2004: | 2791 | * Patches by Dan Eisenhut, 01 Jul 2004: |
2789 | - README fixes. | 2792 | - README fixes. |
2790 | - Move doc2000.h include to prevent compiler warning on some boards | 2793 | - Move doc2000.h include to prevent compiler warning on some boards |
2791 | 2794 | ||
2792 | * Patch by Mark Jonas, 01 Jul 2004: | 2795 | * Patch by Mark Jonas, 01 Jul 2004: |
2793 | Added support for Total5100 and Total5200 (Rev.1 and Rev.2) | 2796 | Added support for Total5100 and Total5200 (Rev.1 and Rev.2) |
2794 | MGT5100 and MPC5200 based Freescale platforms. | 2797 | MGT5100 and MPC5200 based Freescale platforms. |
2795 | 2798 | ||
2796 | * Patch by Philippe Robin, 01 Jul 2004: | 2799 | * Patch by Philippe Robin, 01 Jul 2004: |
2797 | Add initialization for Integrator and versatile board files. | 2800 | Add initialization for Integrator and versatile board files. |
2798 | 2801 | ||
2799 | * Patch by Hinko Kocevar, 01 Jun 2004: | 2802 | * Patch by Hinko Kocevar, 01 Jun 2004: |
2800 | Fix VFD FB allocation, add LCD FB allocation on ARM | 2803 | Fix VFD FB allocation, add LCD FB allocation on ARM |
2801 | 2804 | ||
2802 | * Patch by Martin Krause, 30 Jun 2004: | 2805 | * Patch by Martin Krause, 30 Jun 2004: |
2803 | Add support for TQM5200 board | 2806 | Add support for TQM5200 board |
2804 | 2807 | ||
2805 | * Patch by Martin Krause, 29 Jun 2004: | 2808 | * Patch by Martin Krause, 29 Jun 2004: |
2806 | Add loopw command: infinite write loop on address range | 2809 | Add loopw command: infinite write loop on address range |
2807 | 2810 | ||
2808 | * Patches by Yasushi Shoji, 29 Jun 2004: | 2811 | * Patches by Yasushi Shoji, 29 Jun 2004: |
2809 | - add empty include/asm-microblaze/processor.h | 2812 | - add empty include/asm-microblaze/processor.h |
2810 | - add to CREDITS and MAINTAINERS | 2813 | - add to CREDITS and MAINTAINERS |
2811 | - add gd initialization | 2814 | - add gd initialization |
2812 | - add MicroBlaze and SUZAKU board to MAKEALL script | 2815 | - add MicroBlaze and SUZAKU board to MAKEALL script |
2813 | - add reset support for SUZAKU | 2816 | - add reset support for SUZAKU |
2814 | - add flush_cache() for MicroBlaze | 2817 | - add flush_cache() for MicroBlaze |
2815 | - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed | 2818 | - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed |
2816 | size flash memory on SUZAKU | 2819 | size flash memory on SUZAKU |
2817 | 2820 | ||
2818 | * Patch by Prakash Kumar, 27 Jun 2004: | 2821 | * Patch by Prakash Kumar, 27 Jun 2004: |
2819 | Add support for the PXA250 based Intrinsyc Cerf board. | 2822 | Add support for the PXA250 based Intrinsyc Cerf board. |
2820 | 2823 | ||
2821 | * Patch by Yasushi Shoji, 27 Jun 2004: | 2824 | * Patch by Yasushi Shoji, 27 Jun 2004: |
2822 | fix comment in include/common.h | 2825 | fix comment in include/common.h |
2823 | 2826 | ||
2824 | * Rename SBC8560 into sbc8560 for consistency | 2827 | * Rename SBC8560 into sbc8560 for consistency |
2825 | 2828 | ||
2826 | * Patch by Daniel Poirot, 24 Jun 2004: | 2829 | * Patch by Daniel Poirot, 24 Jun 2004: |
2827 | Add support for Wind River's sbc8240 board | 2830 | Add support for Wind River's sbc8240 board |
2828 | 2831 | ||
2829 | * Patches by Yasushi Shoji, 26 Jun 2004: | 2832 | * Patches by Yasushi Shoji, 26 Jun 2004: |
2830 | - drivers/serial_xuartlite.c: fix "return 0" in void function | 2833 | - drivers/serial_xuartlite.c: fix "return 0" in void function |
2831 | - add microblaze support to mkimage tool | 2834 | - add microblaze support to mkimage tool |
2832 | 2835 | ||
2833 | * Patch by Fred Klatt, 25 Jun 2004: | 2836 | * Patch by Fred Klatt, 25 Jun 2004: |
2834 | Add support for WindRiver's sbc8560 board | 2837 | Add support for WindRiver's sbc8560 board |
2835 | 2838 | ||
2836 | * Patch by Nicolas Lacressonniere, 24 Jun 2004 | 2839 | * Patch by Nicolas Lacressonniere, 24 Jun 2004 |
2837 | Small Bugs fixes for "at91rm9200dk" board: | 2840 | Small Bugs fixes for "at91rm9200dk" board: |
2838 | - Timing modifications for SPI DataFlash access | 2841 | - Timing modifications for SPI DataFlash access |
2839 | - Fix NAND flash detection bug | 2842 | - Fix NAND flash detection bug |
2840 | 2843 | ||
2841 | * Patch by Nicolas Lacressonniere, 24 Jun 2004: | 2844 | * Patch by Nicolas Lacressonniere, 24 Jun 2004: |
2842 | Add Support for Flash AT49BV6416 for AT91RM9200DK board | 2845 | Add Support for Flash AT49BV6416 for AT91RM9200DK board |
2843 | 2846 | ||
2844 | * Patch by Jon Loeliger, 17 June 2004: | 2847 | * Patch by Jon Loeliger, 17 June 2004: |
2845 | Completion of the 8540ADS/8560ADS updates: | 2848 | Completion of the 8540ADS/8560ADS updates: |
2846 | Fix some PCI and Rapid I/O memory maps, | 2849 | Fix some PCI and Rapid I/O memory maps, |
2847 | Initialize both TSEC 1 and 2, | 2850 | Initialize both TSEC 1 and 2, |
2848 | Initialize SDRAM | 2851 | Initialize SDRAM |
2849 | Update MAINTAINER for 85xx boards and README.mpc85xxads | 2852 | Update MAINTAINER for 85xx boards and README.mpc85xxads |
2850 | 2853 | ||
2851 | * Patch by Yuli Barcohen, 16 Jun 2004: | 2854 | * Patch by Yuli Barcohen, 16 Jun 2004: |
2852 | Remove obsolete AdderII port which was superseded by unified | 2855 | Remove obsolete AdderII port which was superseded by unified |
2853 | AdderII/Adder87x port | 2856 | AdderII/Adder87x port |
2854 | 2857 | ||
2855 | * Patch by Ladislav Michl, 16 Jun 2004: | 2858 | * Patch by Ladislav Michl, 16 Jun 2004: |
2856 | Fix gcc-3.3.3 warnings for smc91111.c | 2859 | Fix gcc-3.3.3 warnings for smc91111.c |
2857 | 2860 | ||
2858 | * Patch by Stefan Roese, 02 Jul 2004: | 2861 | * Patch by Stefan Roese, 02 Jul 2004: |
2859 | - Fix bug in 405 ethernet driver; allocated data not cleared! | 2862 | - Fix bug in 405 ethernet driver; allocated data not cleared! |
2860 | - Fix problem in 405 i2c driver; don't try to print without console! | 2863 | - Fix problem in 405 i2c driver; don't try to print without console! |
2861 | 2864 | ||
2862 | * Patch by Paul Ruhland, 11 Jun 2004: | 2865 | * Patch by Paul Ruhland, 11 Jun 2004: |
2863 | Remove debug code from 'board/lpd7a40x/flash.c' | 2866 | Remove debug code from 'board/lpd7a40x/flash.c' |
2864 | 2867 | ||
2865 | * Patch by Andrea Marson, 11 Jun 2004: | 2868 | * Patch by Andrea Marson, 11 Jun 2004: |
2866 | Update for PPChameleon board: | 2869 | Update for PPChameleon board: |
2867 | - support for SysClk @ 25MHz | 2870 | - support for SysClk @ 25MHz |
2868 | - support for Silicon Motion SM712 VGA controller | 2871 | - support for Silicon Motion SM712 VGA controller |
2869 | - some clean ups | 2872 | - some clean ups |
2870 | 2873 | ||
2871 | * Patches by Richard Woodruff, 10 Jun 2004: | 2874 | * Patches by Richard Woodruff, 10 Jun 2004: |
2872 | - fix problems with examples/stubs.c for GCC >= 3.4 | 2875 | - fix problems with examples/stubs.c for GCC >= 3.4 |
2873 | - fix problems with gd initialization | 2876 | - fix problems with gd initialization |
2874 | 2877 | ||
2875 | * Patch by Curt Brune, 17 May 2004: | 2878 | * Patch by Curt Brune, 17 May 2004: |
2876 | - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) | 2879 | - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) |
2877 | - Add support for ESPD-Inc. EVB4510 Board | 2880 | - Add support for ESPD-Inc. EVB4510 Board |
2878 | 2881 | ||
2879 | * Patch by Marc Leeman, 11 May 2004: | 2882 | * Patch by Marc Leeman, 11 May 2004: |
2880 | Fix for MPC8245 - reading PPC Memory from another device with the | 2883 | Fix for MPC8245 - reading PPC Memory from another device with the |
2881 | PPC as PCI target device corrupts data due to interenal hardware | 2884 | PPC as PCI target device corrupts data due to interenal hardware |
2882 | buffering. | 2885 | buffering. |
2883 | 2886 | ||
2884 | * Fix "cls" command when used with splash screen | 2887 | * Fix "cls" command when used with splash screen |
2885 | 2888 | ||
2886 | * Increase NFS download timeout (now 1 min - 10 sec is to short for a | 2889 | * Increase NFS download timeout (now 1 min - 10 sec is to short for a |
2887 | slow download of a big image) | 2890 | slow download of a big image) |
2888 | 2891 | ||
2889 | * Add "cls" function to MPC823 LCD driver so we can reinitialize the | 2892 | * Add "cls" function to MPC823 LCD driver so we can reinitialize the |
2890 | display even after showing a bitmap | 2893 | display even after showing a bitmap |
2891 | 2894 | ||
2892 | * Patch by Josef Wagner, 04 Jun 2004: | 2895 | * Patch by Josef Wagner, 04 Jun 2004: |
2893 | - DDR Ram support for PM520 (MPC5200) | 2896 | - DDR Ram support for PM520 (MPC5200) |
2894 | - support for different flash types (PM520) | 2897 | - support for different flash types (PM520) |
2895 | - USB / IDE / CF-Card / DiskOnChip support for PM520 | 2898 | - USB / IDE / CF-Card / DiskOnChip support for PM520 |
2896 | - 8 bit boot rom support for PM520/CE520 | 2899 | - 8 bit boot rom support for PM520/CE520 |
2897 | - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) | 2900 | - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) |
2898 | - I2C and RTC support for CPC45 | 2901 | - I2C and RTC support for CPC45 |
2899 | - support of new flash type (28F160C3T) for CPC45 | 2902 | - support of new flash type (28F160C3T) for CPC45 |
2900 | 2903 | ||
2901 | * Fix flash parameters passed to Linux for PPChameleon board | 2904 | * Fix flash parameters passed to Linux for PPChameleon board |
2902 | 2905 | ||
2903 | * Remove eth_init() from lib_arm/board.c; it's done in net.net.c. | 2906 | * Remove eth_init() from lib_arm/board.c; it's done in net.net.c. |
2904 | 2907 | ||
2905 | * Patch by Paul Ruhland, 10 Jun 2004: | 2908 | * Patch by Paul Ruhland, 10 Jun 2004: |
2906 | fix support for Logic SDK-LH7A404 board and clean up the | 2909 | fix support for Logic SDK-LH7A404 board and clean up the |
2907 | LH7A404 register macros. | 2910 | LH7A404 register macros. |
2908 | 2911 | ||
2909 | * Patch by Matthew McClintock, 10 Jun 2004: | 2912 | * Patch by Matthew McClintock, 10 Jun 2004: |
2910 | Modify code to select correct serial clock on Sandpoint8245 | 2913 | Modify code to select correct serial clock on Sandpoint8245 |
2911 | 2914 | ||
2912 | * Patch by Robert Schwebel, 10 Jun 2004: | 2915 | * Patch by Robert Schwebel, 10 Jun 2004: |
2913 | Add support for Intel K3 strata flash. | 2916 | Add support for Intel K3 strata flash. |
2914 | 2917 | ||
2915 | * Patch by Thomas Brand, 10 Jun 2004: | 2918 | * Patch by Thomas Brand, 10 Jun 2004: |
2916 | Fix "loads" command on DK1S10 board | 2919 | Fix "loads" command on DK1S10 board |
2917 | 2920 | ||
2918 | * Patch by Yuli Barcohen, 09 Jun 2004: | 2921 | * Patch by Yuli Barcohen, 09 Jun 2004: |
2919 | Add support for 8MB flash SIMM and JFFS2 file system on | 2922 | Add support for 8MB flash SIMM and JFFS2 file system on |
2920 | Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). | 2923 | Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). |
2921 | 2924 | ||
2922 | * Patch by Yuli Barcohen, 09 Jun 2004: | 2925 | * Patch by Yuli Barcohen, 09 Jun 2004: |
2923 | Add support for Analogue&Micro Adder87x and the older AdderII board. | 2926 | Add support for Analogue&Micro Adder87x and the older AdderII board. |
2924 | 2927 | ||
2925 | * Patch by Ming-Len Wu, 09 Jun 2004: | 2928 | * Patch by Ming-Len Wu, 09 Jun 2004: |
2926 | Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board | 2929 | Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board |
2927 | 2930 | ||
2928 | * Patch by Sam Song, 09 Jun 2004: | 2931 | * Patch by Sam Song, 09 Jun 2004: |
2929 | - Add support for RPXlite_DW board | 2932 | - Add support for RPXlite_DW board |
2930 | - Update FLASH driver for 4*AM29DL323DB90VI | 2933 | - Update FLASH driver for 4*AM29DL323DB90VI |
2931 | - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board | 2934 | - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board |
2932 | 2935 | ||
2933 | * Patch by Mark Jonas, 08 June 2004: | 2936 | * Patch by Mark Jonas, 08 June 2004: |
2934 | - Make MPC5200 boards evaluate the SVR to print processor name and | 2937 | - Make MPC5200 boards evaluate the SVR to print processor name and |
2935 | version in checkcpu() (cpu/mpc5xxx/cpu.c). | 2938 | version in checkcpu() (cpu/mpc5xxx/cpu.c). |
2936 | 2939 | ||
2937 | * Patch by Kai-Uwe Bloem, 06 May 2004: | 2940 | * Patch by Kai-Uwe Bloem, 06 May 2004: |
2938 | Fix endianess problem in cramfs code | 2941 | Fix endianess problem in cramfs code |
2939 | 2942 | ||
2940 | * Patch by Tom Armistead, 04 Jun 2004: | 2943 | * Patch by Tom Armistead, 04 Jun 2004: |
2941 | Add support for MAX6900 RTC | 2944 | Add support for MAX6900 RTC |
2942 | 2945 | ||
2943 | * Patches by Ladislav Michl, 03 Jun 2004: | 2946 | * Patches by Ladislav Michl, 03 Jun 2004: |
2944 | - fix cfi_flash.c on LE systems | 2947 | - fix cfi_flash.c on LE systems |
2945 | - let 'make mrproper' delete u-boot.img as well | 2948 | - let 'make mrproper' delete u-boot.img as well |
2946 | - turn printf into debug in cfi_flash.c | 2949 | - turn printf into debug in cfi_flash.c |
2947 | 2950 | ||
2948 | * Patch by Kurt Stremerch, 28 May 2004: | 2951 | * Patch by Kurt Stremerch, 28 May 2004: |
2949 | Add support for Exys XSEngine board | 2952 | Add support for Exys XSEngine board |
2950 | 2953 | ||
2951 | * Patch by Martin Krause, 27 May 2004: | 2954 | * Patch by Martin Krause, 27 May 2004: |
2952 | Fix a MPC5xxx I2C timing issue in i2c_probe(). | 2955 | Fix a MPC5xxx I2C timing issue in i2c_probe(). |
2953 | 2956 | ||
2954 | * Patch by Leif Lindholm, 27 May 2004: | 2957 | * Patch by Leif Lindholm, 27 May 2004: |
2955 | Fix board_init_f() for dbau1x00 board. | 2958 | Fix board_init_f() for dbau1x00 board. |
2956 | 2959 | ||
2957 | * Patch by Imre Deak, 26 May 2004: | 2960 | * Patch by Imre Deak, 26 May 2004: |
2958 | On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). | 2961 | On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). |
2959 | Set flash base accordingly, and decide whether to do or skip board | 2962 | Set flash base accordingly, and decide whether to do or skip board |
2960 | specific setup steps. | 2963 | specific setup steps. |
2961 | 2964 | ||
2962 | * Patch by Josef Baumgartner, 26 May 2004: | 2965 | * Patch by Josef Baumgartner, 26 May 2004: |
2963 | Add missing define in include/asm-m68k/global_data.h | 2966 | Add missing define in include/asm-m68k/global_data.h |
2964 | 2967 | ||
2965 | * Patch by Josef Baumgartner, 25 May 2004: | 2968 | * Patch by Josef Baumgartner, 25 May 2004: |
2966 | Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c | 2969 | Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c |
2967 | 2970 | ||
2968 | * Patch by Paul Ruhland, 24 May 2004: | 2971 | * Patch by Paul Ruhland, 24 May 2004: |
2969 | fix SDRAM initialization for LPD7A400 board. | 2972 | fix SDRAM initialization for LPD7A400 board. |
2970 | 2973 | ||
2971 | * Patch by Jian Zhang, 20 May 2004: | 2974 | * Patch by Jian Zhang, 20 May 2004: |
2972 | add support for environment in NAND flash | 2975 | add support for environment in NAND flash |
2973 | 2976 | ||
2974 | * Patch by Yuli Barcohen, 20 May 2004: | 2977 | * Patch by Yuli Barcohen, 20 May 2004: |
2975 | Add support for Interphase iSPAN boards. | 2978 | Add support for Interphase iSPAN boards. |
2976 | 2979 | ||
2977 | * Patches by Paul Ruhland, 17 May 2004: | 2980 | * Patches by Paul Ruhland, 17 May 2004: |
2978 | - Add I/O functions to the smc91111 ethernet driver to support the | 2981 | - Add I/O functions to the smc91111 ethernet driver to support the |
2979 | Logic LPD7A40x boards. | 2982 | Logic LPD7A40x boards. |
2980 | - Add support for the Logic Zoom LH7A40x based SDK board(s), | 2983 | - Add support for the Logic Zoom LH7A40x based SDK board(s), |
2981 | specifically the LPD7A400. | 2984 | specifically the LPD7A400. |
2982 | 2985 | ||
2983 | * Patches by Robert Schwebel, 15 May 2004: | 2986 | * Patches by Robert Schwebel, 15 May 2004: |
2984 | - call MAC address reading code also for SMSC91C111; | 2987 | - call MAC address reading code also for SMSC91C111; |
2985 | - make SMSC91C111 timeout configurable, remove duplicate code | 2988 | - make SMSC91C111 timeout configurable, remove duplicate code |
2986 | - fix get_timer() for PXA | 2989 | - fix get_timer() for PXA |
2987 | - update doc/README.JFFS2 | 2990 | - update doc/README.JFFS2 |
2988 | - use "bootfile" env variable also for jffs2 | 2991 | - use "bootfile" env variable also for jffs2 |
2989 | 2992 | ||
2990 | * Patch by Tolunay Orkun, 14 May 2004: | 2993 | * Patch by Tolunay Orkun, 14 May 2004: |
2991 | Add support for Cogent CSB472 board (8MB Flash Rev) | 2994 | Add support for Cogent CSB472 board (8MB Flash Rev) |
2992 | 2995 | ||
2993 | * Patch by Thomas Viehweger, 14 May 2004: | 2996 | * Patch by Thomas Viehweger, 14 May 2004: |
2994 | - flash.h: more flash types added | 2997 | - flash.h: more flash types added |
2995 | - immap_8260.h: some bits added (useful for RMII) | 2998 | - immap_8260.h: some bits added (useful for RMII) |
2996 | - cmd_coninfo.c: typo corrected, printf -> puts | 2999 | - cmd_coninfo.c: typo corrected, printf -> puts |
2997 | - reduced size by replacing spaces with tab | 3000 | - reduced size by replacing spaces with tab |
2998 | 3001 | ||
2999 | * Patch by Robert Schwebel, 13 May 2004: | 3002 | * Patch by Robert Schwebel, 13 May 2004: |
3000 | Add 'imgextract' command: extract one part of a multi file image. | 3003 | Add 'imgextract' command: extract one part of a multi file image. |
3001 | 3004 | ||
3002 | * Patches by Jon Loeliger, 11 May 2004: | 3005 | * Patches by Jon Loeliger, 11 May 2004: |
3003 | Dynamically handle REV1 and REV2 MPC85xx parts. | 3006 | Dynamically handle REV1 and REV2 MPC85xx parts. |
3004 | (Jon Loeliger, 10-May-2004). | 3007 | (Jon Loeliger, 10-May-2004). |
3005 | New consistent memory map and Local Access Window across MPC85xx line. | 3008 | New consistent memory map and Local Access Window across MPC85xx line. |
3006 | New CCSRBAR at 0xE000_0000 now. | 3009 | New CCSRBAR at 0xE000_0000 now. |
3007 | Add RAPID I/O memory map. | 3010 | Add RAPID I/O memory map. |
3008 | New memory map in README.MPC85xxads | 3011 | New memory map in README.MPC85xxads |
3009 | (Kumar Gala, 10-May-2004) | 3012 | (Kumar Gala, 10-May-2004) |
3010 | Better board and CPU identification on MPC85xx boards at boot. | 3013 | Better board and CPU identification on MPC85xx boards at boot. |
3011 | (Jon Loeliger, 10-May-2004) | 3014 | (Jon Loeliger, 10-May-2004) |
3012 | SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. | 3015 | SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. |
3013 | Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. | 3016 | Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. |
3014 | (Jim Robertson, 10-May-2004) | 3017 | (Jim Robertson, 10-May-2004) |
3015 | Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. | 3018 | Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. |
3016 | Supports multiple PHYs. | 3019 | Supports multiple PHYs. |
3017 | (Andy Fleming, 10-May-2004) | 3020 | (Andy Fleming, 10-May-2004) |
3018 | Some README.MPC85xxads updates. | 3021 | Some README.MPC85xxads updates. |
3019 | (Kumar Gala, 10-May-2004) | 3022 | (Kumar Gala, 10-May-2004) |
3020 | Copyright updates for "Freescale" | 3023 | Copyright updates for "Freescale" |
3021 | (Andy Fleming, 10-May-2004) | 3024 | (Andy Fleming, 10-May-2004) |
3022 | 3025 | ||
3023 | * Patch by Stephen Williams, 11 May 2004: | 3026 | * Patch by Stephen Williams, 11 May 2004: |
3024 | Add flash support for ST M29W040B | 3027 | Add flash support for ST M29W040B |
3025 | Reduce JSE specific flash.c to remove dead code. | 3028 | Reduce JSE specific flash.c to remove dead code. |
3026 | 3029 | ||
3027 | * Patch by Markus Pietrek, 04 May 2004: | 3030 | * Patch by Markus Pietrek, 04 May 2004: |
3028 | Fix clear_bss code for ARM systems (all except s3c44b0 which | 3031 | Fix clear_bss code for ARM systems (all except s3c44b0 which |
3029 | doesn't clear BSS at all?) | 3032 | doesn't clear BSS at all?) |
3030 | 3033 | ||
3031 | * Fix "ping" problem on INC-IP board. Strange problem: | 3034 | * Fix "ping" problem on INC-IP board. Strange problem: |
3032 | Sometimes the store word instruction hangs while writing to one of | 3035 | Sometimes the store word instruction hangs while writing to one of |
3033 | the Switch registers, but only if the next instruction is 16-byte | 3036 | the Switch registers, but only if the next instruction is 16-byte |
3034 | aligned. Moving the instruction into a separate function somehow | 3037 | aligned. Moving the instruction into a separate function somehow |
3035 | makes the problem go away. | 3038 | makes the problem go away. |
3036 | 3039 | ||
3037 | * Patch by Rishi Bhattacharya, 08 May 2004: | 3040 | * Patch by Rishi Bhattacharya, 08 May 2004: |
3038 | Add support for TI OMAP5912 OSK Board | 3041 | Add support for TI OMAP5912 OSK Board |
3039 | 3042 | ||
3040 | * Patch by Sam Song May, 07 May 2004: | 3043 | * Patch by Sam Song May, 07 May 2004: |
3041 | Fix typo of UPM table for rmu board | 3044 | Fix typo of UPM table for rmu board |
3042 | 3045 | ||
3043 | * Patch by Pantelis Antoniou, 05 May 2004: | 3046 | * Patch by Pantelis Antoniou, 05 May 2004: |
3044 | - Intracom board update. | 3047 | - Intracom board update. |
3045 | - Add Codec POST. | 3048 | - Add Codec POST. |
3046 | 3049 | ||
3047 | * Add support for the second Ethernet interface for the 'PPChameleon' | 3050 | * Add support for the second Ethernet interface for the 'PPChameleon' |
3048 | board. | 3051 | board. |
3049 | 3052 | ||
3050 | * Patch by Dave Peverley, 30 Apr 2004: | 3053 | * Patch by Dave Peverley, 30 Apr 2004: |
3051 | Add support for OMAP730 Perseus2 Development board | 3054 | Add support for OMAP730 Perseus2 Development board |
3052 | 3055 | ||
3053 | * Patch by Alan J. Luse, 29 Apr 2004: | 3056 | * Patch by Alan J. Luse, 29 Apr 2004: |
3054 | Fix flash chip-select (OR0) option register setting on FADS boards. | 3057 | Fix flash chip-select (OR0) option register setting on FADS boards. |
3055 | 3058 | ||
3056 | * Patch by Alan J. Luse, 29 Apr 2004: | 3059 | * Patch by Alan J. Luse, 29 Apr 2004: |
3057 | Report MII network speed and duplex setting properly when | 3060 | Report MII network speed and duplex setting properly when |
3058 | auto-negotiate is not enabled. | 3061 | auto-negotiate is not enabled. |
3059 | 3062 | ||
3060 | * Patch by Jarrett Redd, 29 Apr 2004: | 3063 | * Patch by Jarrett Redd, 29 Apr 2004: |
3061 | Fix hang on reset on Ocotea board due to flash in wrong mode. | 3064 | Fix hang on reset on Ocotea board due to flash in wrong mode. |
3062 | 3065 | ||
3063 | * Patch by Dave Peverley, 29 Apr 2004: | 3066 | * Patch by Dave Peverley, 29 Apr 2004: |
3064 | add MAC address detection to smc91111 driver | 3067 | add MAC address detection to smc91111 driver |
3065 | 3068 | ||
3066 | * Patch by David Mรผller, 28 Apr 2004: | 3069 | * Patch by David Mรผller, 28 Apr 2004: |
3067 | fix typo in lib_arm/board.c | 3070 | fix typo in lib_arm/board.c |
3068 | 3071 | ||
3069 | * Patch by Tolunay Orkun, 20 Apr 2004: | 3072 | * Patch by Tolunay Orkun, 20 Apr 2004: |
3070 | - README update: add CONFIG_CSB272 and csb272_config | 3073 | - README update: add CONFIG_CSB272 and csb272_config |
3071 | - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and | 3074 | - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and |
3072 | i2cfast environment variable | 3075 | i2cfast environment variable |
3073 | 3076 | ||
3074 | * Patch by Yuli Barcohen, 19 Apr 2004: | 3077 | * Patch by Yuli Barcohen, 19 Apr 2004: |
3075 | - Rename DUET_ADS to MPC885ADS | 3078 | - Rename DUET_ADS to MPC885ADS |
3076 | - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY | 3079 | - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY |
3077 | - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY | 3080 | - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY |
3078 | - Clean up FADS family port to use the new defines | 3081 | - Clean up FADS family port to use the new defines |
3079 | 3082 | ||
3080 | * Fix PCI support on CPC45 board | 3083 | * Fix PCI support on CPC45 board |
3081 | 3084 | ||
3082 | * Patch by Scott McNutt, 25 Apr 2004: | 3085 | * Patch by Scott McNutt, 25 Apr 2004: |
3083 | Add Nios GDB/JTAG Console support: | 3086 | Add Nios GDB/JTAG Console support: |
3084 | - Add stubs to support gdb via JTAG. | 3087 | - Add stubs to support gdb via JTAG. |
3085 | - Add support for console over JTAG. | 3088 | - Add support for console over JTAG. |
3086 | - Minor cleanup. | 3089 | - Minor cleanup. |
3087 | 3090 | ||
3088 | * Add support for CATcenter board (based on PPChameleon ME module) | 3091 | * Add support for CATcenter board (based on PPChameleon ME module) |
3089 | 3092 | ||
3090 | * Patch by Klaus Heydeck, 12 May 2004: | 3093 | * Patch by Klaus Heydeck, 12 May 2004: |
3091 | Using external watchdog for KUP4 boards in mpc8xx/cpu.c; | 3094 | Using external watchdog for KUP4 boards in mpc8xx/cpu.c; |
3092 | load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; | 3095 | load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; |
3093 | various changes to KUP4 board specific files | 3096 | various changes to KUP4 board specific files |
3094 | 3097 | ||
3095 | * Fix minor network problem on MPC5200: need some delay between | 3098 | * Fix minor network problem on MPC5200: need some delay between |
3096 | resetting the PHY and sending the first packet. Implemented in a | 3099 | resetting the PHY and sending the first packet. Implemented in a |
3097 | "natural" way by invoking the PHY reset and initialization code | 3100 | "natural" way by invoking the PHY reset and initialization code |
3098 | only once after power on vs. each time the interface is brought up. | 3101 | only once after power on vs. each time the interface is brought up. |
3099 | 3102 | ||
3100 | * Add some limited support for low-speed devices to SL811 USB controller | 3103 | * Add some limited support for low-speed devices to SL811 USB controller |
3101 | (at least "usb reset" now passes successfully and "usb info" displays | 3104 | (at least "usb reset" now passes successfully and "usb info" displays |
3102 | correct information) | 3105 | correct information) |
3103 | 3106 | ||
3104 | * Change init sequence for multiple network interfaces: initialize | 3107 | * Change init sequence for multiple network interfaces: initialize |
3105 | on-chip interfaces before external cards. | 3108 | on-chip interfaces before external cards. |
3106 | 3109 | ||
3107 | * Fix memory leak in the NAND-specific JFFS2 code | 3110 | * Fix memory leak in the NAND-specific JFFS2 code |
3108 | 3111 | ||
3109 | * Fix SL811 USB controller when attached to a USB hub | 3112 | * Fix SL811 USB controller when attached to a USB hub |
3110 | 3113 | ||
3111 | * Fix config option spelling in PM520 config file | 3114 | * Fix config option spelling in PM520 config file |
3112 | 3115 | ||
3113 | * Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by | 3116 | * Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by |
3114 | patches by Pantelis Antoniou, 30 Mar 2004) | 3117 | patches by Pantelis Antoniou, 30 Mar 2004) |
3115 | 3118 | ||
3116 | * Fix minor NAND JFFS2 related issue | 3119 | * Fix minor NAND JFFS2 related issue |
3117 | 3120 | ||
3118 | * Fixes for SL811 USB controller: | 3121 | * Fixes for SL811 USB controller: |
3119 | - implement workaround for broken memory stick | 3122 | - implement workaround for broken memory stick |
3120 | - improve error handling | 3123 | - improve error handling |
3121 | 3124 | ||
3122 | * Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better | 3125 | * Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better |
3123 | cope with congested networks. | 3126 | cope with congested networks. |
3124 | 3127 | ||
3125 | ====================================================================== | 3128 | ====================================================================== |
3126 | Changes for U-Boot 1.1.1: | 3129 | Changes for U-Boot 1.1.1: |
3127 | ====================================================================== | 3130 | ====================================================================== |
3128 | 3131 | ||
3129 | * Patch by Travis Sawyer, 23 Apr 2004: | 3132 | * Patch by Travis Sawyer, 23 Apr 2004: |
3130 | Fix VSC/CIS 8201 phy descrambler interoperability timing due to | 3133 | Fix VSC/CIS 8201 phy descrambler interoperability timing due to |
3131 | errata from Vitesse Semiconductor. | 3134 | errata from Vitesse Semiconductor. |
3132 | 3135 | ||
3133 | * Patch by Philippe Robin, 22 Apr 2004: | 3136 | * Patch by Philippe Robin, 22 Apr 2004: |
3134 | Fix ethernet configuration for "versatile" board | 3137 | Fix ethernet configuration for "versatile" board |
3135 | 3138 | ||
3136 | * Patch by Kshitij Gupta, 21 Apr 2004: | 3139 | * Patch by Kshitij Gupta, 21 Apr 2004: |
3137 | Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards | 3140 | Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards |
3138 | 3141 | ||
3139 | * Patch by Steven Scholz, 24 Feb 2004: | 3142 | * Patch by Steven Scholz, 24 Feb 2004: |
3140 | Fix a bug in AT91RM9200 ethernet driver: | 3143 | Fix a bug in AT91RM9200 ethernet driver: |
3141 | The MII interface is now initialized before accessing the PHY. | 3144 | The MII interface is now initialized before accessing the PHY. |
3142 | 3145 | ||
3143 | * Patch by John Kerl, 19 Apr 2004: | 3146 | * Patch by John Kerl, 19 Apr 2004: |
3144 | Use U-boot's miiphy.h for PHY register names, rather than | 3147 | Use U-boot's miiphy.h for PHY register names, rather than |
3145 | introducing a new header file. | 3148 | introducing a new header file. |
3146 | 3149 | ||
3147 | * Update pci_ids.h from linux-2.4.26 | 3150 | * Update pci_ids.h from linux-2.4.26 |
3148 | 3151 | ||
3149 | * Patch by Masami Komiya, 19 Apr 2004: | 3152 | * Patch by Masami Komiya, 19 Apr 2004: |
3150 | Fix problem cause by VLAN function on little endian architecture | 3153 | Fix problem cause by VLAN function on little endian architecture |
3151 | without VLAN environment | 3154 | without VLAN environment |
3152 | 3155 | ||
3153 | * Clean up the TQM8xx_YYMHz configurations; allow to use the same | 3156 | * Clean up the TQM8xx_YYMHz configurations; allow to use the same |
3154 | binary image for all clock frequencies. Implement run-time | 3157 | binary image for all clock frequencies. Implement run-time |
3155 | optimization of flash access timing based on the actual bus | 3158 | optimization of flash access timing based on the actual bus |
3156 | frequency. | 3159 | frequency. |
3157 | 3160 | ||
3158 | * Modify KUP4X board configuration to use SL811 driver for USB memory | 3161 | * Modify KUP4X board configuration to use SL811 driver for USB memory |
3159 | sticks (including FAT / VFAT filesystem support) | 3162 | sticks (including FAT / VFAT filesystem support) |
3160 | 3163 | ||
3161 | * Add SL811 Host Controller Interface driver for USB | 3164 | * Add SL811 Host Controller Interface driver for USB |
3162 | 3165 | ||
3163 | * Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README | 3166 | * Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README |
3164 | 3167 | ||
3165 | * Patch by Pantelis Antoniou, 19 Apr 2004: | 3168 | * Patch by Pantelis Antoniou, 19 Apr 2004: |
3166 | Allow to use shell style syntax (i. e. ${var} ) with standard parser. | 3169 | Allow to use shell style syntax (i. e. ${var} ) with standard parser. |
3167 | Minor patches for Intracom boards. | 3170 | Minor patches for Intracom boards. |
3168 | 3171 | ||
3169 | * Patch by Christian Pell, 19 Apr 2004: | 3172 | * Patch by Christian Pell, 19 Apr 2004: |
3170 | cleanup support for CF/IDE on PCMCIA for PXA25X | 3173 | cleanup support for CF/IDE on PCMCIA for PXA25X |
3171 | 3174 | ||
3172 | * Temporarily disabled John Kerl's extended MII command code because | 3175 | * Temporarily disabled John Kerl's extended MII command code because |
3173 | "miivals.h" is missing | 3176 | "miivals.h" is missing |
3174 | 3177 | ||
3175 | * Patches by Mark Jonas, 13 Apr 2004: | 3178 | * Patches by Mark Jonas, 13 Apr 2004: |
3176 | - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S | 3179 | - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S |
3177 | - Add sync instructions to IceCube SDRAM init code | 3180 | - Add sync instructions to IceCube SDRAM init code |
3178 | - Move SDRAM chip constants into seperate include files | 3181 | - Move SDRAM chip constants into seperate include files |
3179 | - Unify DDR and SDR initialization code | 3182 | - Unify DDR and SDR initialization code |
3180 | - Unify all IceCube (Lite5xxx) target names | 3183 | - Unify all IceCube (Lite5xxx) target names |
3181 | 3184 | ||
3182 | * Patch by John Kerl, 16 Apr 2004: | 3185 | * Patch by John Kerl, 16 Apr 2004: |
3183 | Enable ranges in mii command, e.g. mii read 0-1f 0 or | 3186 | Enable ranges in mii command, e.g. mii read 0-1f 0 or |
3184 | mii read 4-7 18-1a. Also add mii dump subcommand for | 3187 | mii read 4-7 18-1a. Also add mii dump subcommand for |
3185 | pretty-printing standard regs 0-5. | 3188 | pretty-printing standard regs 0-5. |
3186 | 3189 | ||
3187 | * Patch by Stephen Williams, 16 April 2004: | 3190 | * Patch by Stephen Williams, 16 April 2004: |
3188 | fix typo in JSE.h; update MAINTAINERS | 3191 | fix typo in JSE.h; update MAINTAINERS |
3189 | 3192 | ||
3190 | * Patch by Matthew S. McClintock, 14 Apr 2004: | 3193 | * Patch by Matthew S. McClintock, 14 Apr 2004: |
3191 | fix initdram function for utx8245 board | 3194 | fix initdram function for utx8245 board |
3192 | 3195 | ||
3193 | * Patch by Markus Pietrek, 14 Apr 2004: | 3196 | * Patch by Markus Pietrek, 14 Apr 2004: |
3194 | use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag | 3197 | use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag |
3195 | 3198 | ||
3196 | * Patch by Reinhard Meyer, 18 Apr 2004: | 3199 | * Patch by Reinhard Meyer, 18 Apr 2004: |
3197 | provide the IDE Reset Function for EMK 5200 boards | 3200 | provide the IDE Reset Function for EMK 5200 boards |
3198 | 3201 | ||
3199 | * Patch by Masami Komiya, 12 Apr 2004: | 3202 | * Patch by Masami Komiya, 12 Apr 2004: |
3200 | fix pci_hose_write_config_{byte,word}_via_dword problems | 3203 | fix pci_hose_write_config_{byte,word}_via_dword problems |
3201 | 3204 | ||
3202 | * Patch by Sangmoon Kim, 12 Apr 2004: | 3205 | * Patch by Sangmoon Kim, 12 Apr 2004: |
3203 | Update max RAM size for debris board | 3206 | Update max RAM size for debris board |
3204 | 3207 | ||
3205 | * Patch by Travis Sawyer, 08 Apr 2004: | 3208 | * Patch by Travis Sawyer, 08 Apr 2004: |
3206 | Add TLB entry for second DIMM slot on ocotea | 3209 | Add TLB entry for second DIMM slot on ocotea |
3207 | 3210 | ||
3208 | * Patch by Masami Komiya, 08 Apr 2004: | 3211 | * Patch by Masami Komiya, 08 Apr 2004: |
3209 | add RTL8169 network driver | 3212 | add RTL8169 network driver |
3210 | 3213 | ||
3211 | * Patch by Dan Malek, 07 Apr 2004: | 3214 | * Patch by Dan Malek, 07 Apr 2004: |
3212 | - Add support for RPC/STx GP3, Motorola 8560 board | 3215 | - Add support for RPC/STx GP3, Motorola 8560 board |
3213 | - Update 85xx TSEC driver so it searches MII for first available PHY | 3216 | - Update 85xx TSEC driver so it searches MII for first available PHY |
3214 | and uses that one. | 3217 | and uses that one. |
3215 | - Add functions to support console MII commands. | 3218 | - Add functions to support console MII commands. |
3216 | 3219 | ||
3217 | * Patch by Tolunay Orkun, 07 Apr 2004: | 3220 | * Patch by Tolunay Orkun, 07 Apr 2004: |
3218 | Move initialization of bi_iic_fast[] | 3221 | Move initialization of bi_iic_fast[] |
3219 | from board_init_f() to board_init_r() | 3222 | from board_init_f() to board_init_r() |
3220 | 3223 | ||
3221 | * Patch by Yasushi Shoji, 07 Apr 2004: | 3224 | * Patch by Yasushi Shoji, 07 Apr 2004: |
3222 | Cleanup microblaze port | 3225 | Cleanup microblaze port |
3223 | 3226 | ||
3224 | * Patch by Sangmoon Kim, 07 Apr 2004: | 3227 | * Patch by Sangmoon Kim, 07 Apr 2004: |
3225 | Add auto SDRAM module detection for Debris board | 3228 | Add auto SDRAM module detection for Debris board |
3226 | 3229 | ||
3227 | * Patch by Rune Torgersen, 06 Apr 2004: | 3230 | * Patch by Rune Torgersen, 06 Apr 2004: |
3228 | - Fix some PCI problems on the MPC8266ADS board | 3231 | - Fix some PCI problems on the MPC8266ADS board |
3229 | - Fix the location of some PCI entries in the immap structure | 3232 | - Fix the location of some PCI entries in the immap structure |
3230 | 3233 | ||
3231 | * Patch by Yasushi Shoji, 07 Apr 2004: | 3234 | * Patch by Yasushi Shoji, 07 Apr 2004: |
3232 | - add support for microblaze processors | 3235 | - add support for microblaze processors |
3233 | - add support for AtmarkTechno "suzaku" board | 3236 | - add support for AtmarkTechno "suzaku" board |
3234 | 3237 | ||
3235 | * Configure PPChameleon board to use redundand environment in flash | 3238 | * Configure PPChameleon board to use redundand environment in flash |
3236 | 3239 | ||
3237 | * Configure PPChameleon board to use JFFS2 NAND support. | 3240 | * Configure PPChameleon board to use JFFS2 NAND support. |
3238 | 3241 | ||
3239 | * Added support for JFFS2 filesystem (read-only) on top of NAND flash | 3242 | * Added support for JFFS2 filesystem (read-only) on top of NAND flash |
3240 | 3243 | ||
3241 | * Patch by Rune Torgersen, 16 Apr 2004: | 3244 | * Patch by Rune Torgersen, 16 Apr 2004: |
3242 | LBA48 fixes | 3245 | LBA48 fixes |
3243 | 3246 | ||
3244 | * Patches by Pantelis Antoniou, 16 Apr 2004: | 3247 | * Patches by Pantelis Antoniou, 16 Apr 2004: |
3245 | - add support for a new version of an Intracom board and fix | 3248 | - add support for a new version of an Intracom board and fix |
3246 | various other things on others. | 3249 | various other things on others. |
3247 | - add verify support to the crc32 command (define | 3250 | - add verify support to the crc32 command (define |
3248 | CONFIG_CRC32_VERIFY to enable it) | 3251 | CONFIG_CRC32_VERIFY to enable it) |
3249 | - fix FEC driver for MPC8xx systems: | 3252 | - fix FEC driver for MPC8xx systems: |
3250 | 1. fix compilation problems for boards that use dynamic | 3253 | 1. fix compilation problems for boards that use dynamic |
3251 | allocation of DPRAM | 3254 | allocation of DPRAM |
3252 | 2. shut down FEC after network transfers | 3255 | 2. shut down FEC after network transfers |
3253 | - HUSH parser fixes: | 3256 | - HUSH parser fixes: |
3254 | 1. A new test command was added. This is a simplified version of | 3257 | 1. A new test command was added. This is a simplified version of |
3255 | the one in the bourne shell. | 3258 | the one in the bourne shell. |
3256 | 2. A new exit command was added which terminates the current | 3259 | 2. A new exit command was added which terminates the current |
3257 | executing script. | 3260 | executing script. |
3258 | 3. Fixed handing of $? (exit code of last executed command) | 3261 | 3. Fixed handing of $? (exit code of last executed command) |
3259 | - Fix some compile problems; | 3262 | - Fix some compile problems; |
3260 | add "once" functionality for the netretry variable | 3263 | add "once" functionality for the netretry variable |
3261 | 3264 | ||
3262 | * Patch by George G. Davis, 02 Apr 2004: | 3265 | * Patch by George G. Davis, 02 Apr 2004: |
3263 | add support for Intel Assabet board | 3266 | add support for Intel Assabet board |
3264 | 3267 | ||
3265 | * Patch by Stephen Williams, 01 Apr 2004: | 3268 | * Patch by Stephen Williams, 01 Apr 2004: |
3266 | Add support for Picture Elements JSE board | 3269 | Add support for Picture Elements JSE board |
3267 | 3270 | ||
3268 | * Patch by Christian Pell, 01 Apr 2004: | 3271 | * Patch by Christian Pell, 01 Apr 2004: |
3269 | Add CompactFlash support for PXA systems. | 3272 | Add CompactFlash support for PXA systems. |
3270 | 3273 | ||
3271 | * Patches by Pantelis Antoniou, 30 Mar 2004: | 3274 | * Patches by Pantelis Antoniou, 30 Mar 2004: |
3272 | - add auto-complete support to the U-Boot CLI | 3275 | - add auto-complete support to the U-Boot CLI |
3273 | - add support for NETTA and NETPHONE boards; fix NETVIA board | 3276 | - add support for NETTA and NETPHONE boards; fix NETVIA board |
3274 | - add support for the Epson 156x series of graphical displays | 3277 | - add support for the Epson 156x series of graphical displays |
3275 | (These displays are serial and not suitable for using a normal | 3278 | (These displays are serial and not suitable for using a normal |
3276 | framebuffer console on them) | 3279 | framebuffer console on them) |
3277 | - add infrastructure needed in order to POST any DSPs in a board | 3280 | - add infrastructure needed in order to POST any DSPs in a board |
3278 | - improve and fix various things in the MPC8xx FEC driver: | 3281 | - improve and fix various things in the MPC8xx FEC driver: |
3279 | 1. The new 87x and 88x series of processors have two FECs, | 3282 | 1. The new 87x and 88x series of processors have two FECs, |
3280 | and the new driver supports them both. | 3283 | and the new driver supports them both. |
3281 | 2. Another change in the 87x/88x series is support for | 3284 | 2. Another change in the 87x/88x series is support for |
3282 | the RMII (Reduced MII) interface. However numerous | 3285 | the RMII (Reduced MII) interface. However numerous |
3283 | changes are needed to make it work since the PHYs | 3286 | changes are needed to make it work since the PHYs |
3284 | are connected to the same lines. That means that | 3287 | are connected to the same lines. That means that |
3285 | you have to address them correctly over the MII | 3288 | you have to address them correctly over the MII |
3286 | interface. | 3289 | interface. |
3287 | 3. We now correctly match the MII/RMII interface | 3290 | 3. We now correctly match the MII/RMII interface |
3288 | configuration to what the PHY reports. | 3291 | configuration to what the PHY reports. |
3289 | - Fix problem when readingthe MII status register. Due to the | 3292 | - Fix problem when readingthe MII status register. Due to the |
3290 | internal design of many PHYs you have to read the register | 3293 | internal design of many PHYs you have to read the register |
3291 | twice. The problem is more apparent in 10Mbit mode. | 3294 | twice. The problem is more apparent in 10Mbit mode. |
3292 | - add new mode ".jffs2s" for reading from a NAND device: it just | 3295 | - add new mode ".jffs2s" for reading from a NAND device: it just |
3293 | skips over bad blocks. | 3296 | skips over bad blocks. |
3294 | - add networking support for VLANs (802.1q), and CDP (Cisco | 3297 | - add networking support for VLANs (802.1q), and CDP (Cisco |
3295 | Discovery Protocol) | 3298 | Discovery Protocol) |
3296 | - some minor patches / cleanup | 3299 | - some minor patches / cleanup |
3297 | 3300 | ||
3298 | * Patch by Yuli Barcohen, 28 Mar 2004: | 3301 | * Patch by Yuli Barcohen, 28 Mar 2004: |
3299 | - Add support for MPC8272 family including MPC8247/8248/8271/8272 | 3302 | - Add support for MPC8272 family including MPC8247/8248/8271/8272 |
3300 | - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) | 3303 | - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) |
3301 | - Change configuration method for MPC8260ADS family | 3304 | - Change configuration method for MPC8260ADS family |
3302 | 3305 | ||
3303 | * add startup code to clear the BSS of standalone applications | 3306 | * add startup code to clear the BSS of standalone applications |
3304 | 3307 | ||
3305 | * Fix if / elif handling bug in HUSH shell | 3308 | * Fix if / elif handling bug in HUSH shell |
3306 | 3309 | ||
3307 | ====================================================================== | 3310 | ====================================================================== |
3308 | Changes for U-Boot 1.1.0: | 3311 | Changes for U-Boot 1.1.0: |
3309 | ====================================================================== | 3312 | ====================================================================== |
3310 | 3313 | ||
3311 | * Patch by Mark Jonas: Remove config.tmp files only when | 3314 | * Patch by Mark Jonas: Remove config.tmp files only when |
3312 | unconfiguring the board | 3315 | unconfiguring the board |
3313 | 3316 | ||
3314 | * Adapt RMU board for bigger flash memory | 3317 | * Adapt RMU board for bigger flash memory |
3315 | 3318 | ||
3316 | * Patch by Klaus Heydeck, 13 Mar 2003: | 3319 | * Patch by Klaus Heydeck, 13 Mar 2003: |
3317 | Add support for KUP4X Board | 3320 | Add support for KUP4X Board |
3318 | 3321 | ||
3319 | * Patch by Pavel Bartusek, 21 Mar 2004 | 3322 | * Patch by Pavel Bartusek, 21 Mar 2004 |
3320 | Add Reiserfs support | 3323 | Add Reiserfs support |
3321 | 3324 | ||
3322 | * Patch by Hinko Kocevar, 20 Mar 2004 | 3325 | * Patch by Hinko Kocevar, 20 Mar 2004 |
3323 | - Add auto-release for SMSC LAN91c111 driver | 3326 | - Add auto-release for SMSC LAN91c111 driver |
3324 | - Add save/restore of PTR and PNR regs as suggested in datasheet | 3327 | - Add save/restore of PTR and PNR regs as suggested in datasheet |
3325 | 3328 | ||
3326 | * Patch by Stephen Williams, 19 March 2004 | 3329 | * Patch by Stephen Williams, 19 March 2004 |
3327 | Increase speed of sector reads from SystemACE, | 3330 | Increase speed of sector reads from SystemACE, |
3328 | shorten poll timeout and remove a useless reset | 3331 | shorten poll timeout and remove a useless reset |
3329 | 3332 | ||
3330 | * Patch by Tolunay Orkun, 19 Mar 2004: | 3333 | * Patch by Tolunay Orkun, 19 Mar 2004: |
3331 | Make GigE PHY 1000Mbps Speed/Duplex detection conditional | 3334 | Make GigE PHY 1000Mbps Speed/Duplex detection conditional |
3332 | (CONFIG_PHY_GIGE) | 3335 | (CONFIG_PHY_GIGE) |
3333 | 3336 | ||
3334 | * Patch by Brad Kemp, 18 Mar 2004: | 3337 | * Patch by Brad Kemp, 18 Mar 2004: |
3335 | prevent machine checks during a PCI scan | 3338 | prevent machine checks during a PCI scan |
3336 | 3339 | ||
3337 | * Patch by Pierre Aubert, 18 Mar 2004: | 3340 | * Patch by Pierre Aubert, 18 Mar 2004: |
3338 | Fix string cleaning in IDE identification | 3341 | Fix string cleaning in IDE identification |
3339 | 3342 | ||
3340 | * Patch by Pierre Aubert, 18 Mar 2004: | 3343 | * Patch by Pierre Aubert, 18 Mar 2004: |
3341 | - Unify video mode handling for Chips & Technologies 69000 Video | 3344 | - Unify video mode handling for Chips & Technologies 69000 Video |
3342 | chip and Silicon Motion SMI 712/710/810 Video chip | 3345 | chip and Silicon Motion SMI 712/710/810 Video chip |
3343 | - Add selection of the video output (CRT or LCD) via 'videoout' | 3346 | - Add selection of the video output (CRT or LCD) via 'videoout' |
3344 | environment variable for the Silicon Motion | 3347 | environment variable for the Silicon Motion |
3345 | - README update | 3348 | - README update |
3346 | 3349 | ||
3347 | * Patch by Pierre Aubert, 18 Mar 2004: | 3350 | * Patch by Pierre Aubert, 18 Mar 2004: |
3348 | include/common.h typo fix | 3351 | include/common.h typo fix |
3349 | 3352 | ||
3350 | * Patches by Tolunay Orkun, 17 Mar 2004: | 3353 | * Patches by Tolunay Orkun, 17 Mar 2004: |
3351 | - Add support for bd->bi_iic_fast[] initialization via environment | 3354 | - Add support for bd->bi_iic_fast[] initialization via environment |
3352 | variable "i2cfast" (CONFIG_I2CFAST) | 3355 | variable "i2cfast" (CONFIG_I2CFAST) |
3353 | - Add "i2cfast" u-boot environment variable support for csb272 | 3356 | - Add "i2cfast" u-boot environment variable support for csb272 |
3354 | 3357 | ||
3355 | * Patch by Carl Riechers, 17 Mar 2004: | 3358 | * Patch by Carl Riechers, 17 Mar 2004: |
3356 | Ignore '\0' characters in console input for use with telnet and | 3359 | Ignore '\0' characters in console input for use with telnet and |
3357 | telco pads. | 3360 | telco pads. |
3358 | 3361 | ||
3359 | * Patch by Leon Kukovec, 17 Mar 2004: | 3362 | * Patch by Leon Kukovec, 17 Mar 2004: |
3360 | typo fix for strswab prototype #ifdef | 3363 | typo fix for strswab prototype #ifdef |
3361 | 3364 | ||
3362 | * Patches by Thomas Viehweger, 16 Mar 2004: | 3365 | * Patches by Thomas Viehweger, 16 Mar 2004: |
3363 | - show PCI clock frequency on MPC8260 systems | 3366 | - show PCI clock frequency on MPC8260 systems |
3364 | - add FCC_PSMR_RMII flag for HiP7 processors | 3367 | - add FCC_PSMR_RMII flag for HiP7 processors |
3365 | - in do_jffs2_fsload(), take load address from load_addr if not set | 3368 | - in do_jffs2_fsload(), take load address from load_addr if not set |
3366 | explicit, update load_addr otherwise | 3369 | explicit, update load_addr otherwise |
3367 | - replaced printf by putc/puts when no formatting is needed | 3370 | - replaced printf by putc/puts when no formatting is needed |
3368 | (smaller code size, faster execution) | 3371 | (smaller code size, faster execution) |
3369 | 3372 | ||
3370 | * Patch by Phillippe Robin, 16 Mar 2004: | 3373 | * Patch by Phillippe Robin, 16 Mar 2004: |
3371 | avoid dereferencing NULL pointer in lib_arm/armlinux.c | 3374 | avoid dereferencing NULL pointer in lib_arm/armlinux.c |
3372 | 3375 | ||
3373 | * Patch by Stephen Williams, 15 Mar 2004: | 3376 | * Patch by Stephen Williams, 15 Mar 2004: |
3374 | Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation | 3377 | Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation |
3375 | 3378 | ||
3376 | * Patch by Tolunay Orkun, 15 Mar 2004: | 3379 | * Patch by Tolunay Orkun, 15 Mar 2004: |
3377 | Initialize bi_opbfreq to real OPB frequency via get_OPB_freq() | 3380 | Initialize bi_opbfreq to real OPB frequency via get_OPB_freq() |
3378 | 3381 | ||
3379 | * Patch by Travis Sawyer, 15 Mar 2004: | 3382 | * Patch by Travis Sawyer, 15 Mar 2004: |
3380 | Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port | 3383 | Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port |
3381 | 3384 | ||
3382 | * Add start-up delay to make sure power has stabilized before | 3385 | * Add start-up delay to make sure power has stabilized before |
3383 | attempting to switch on USB on SX1 board. | 3386 | attempting to switch on USB on SX1 board. |
3384 | 3387 | ||
3385 | * Patch by Josef Wagner, 18 Mar 2004: | 3388 | * Patch by Josef Wagner, 18 Mar 2004: |
3386 | - Add support for MicroSys XM250 board (PXA255) | 3389 | - Add support for MicroSys XM250 board (PXA255) |
3387 | - Add support for MicroSys PM828 board (MPC8280) | 3390 | - Add support for MicroSys PM828 board (MPC8280) |
3388 | - Add support for 32 MB Flash on PM825/826 | 3391 | - Add support for 32 MB Flash on PM825/826 |
3389 | - new SDRAM refresh rate for PM825/PM826 | 3392 | - new SDRAM refresh rate for PM825/PM826 |
3390 | - added support for MicroSys PM520 (MPC5200) | 3393 | - added support for MicroSys PM520 (MPC5200) |
3391 | - replaced Query by Identify command in CPU86/flash.c | 3394 | - replaced Query by Identify command in CPU86/flash.c |
3392 | to support 28F160F3B | 3395 | to support 28F160F3B |
3393 | 3396 | ||
3394 | * Fix wrap around problem with udelay() on ARM920T | 3397 | * Fix wrap around problem with udelay() on ARM920T |
3395 | 3398 | ||
3396 | * Add support for Macronix flash on TRAB board | 3399 | * Add support for Macronix flash on TRAB board |
3397 | 3400 | ||
3398 | * Patch by Pierre Aubert, 15 Mar 2004: | 3401 | * Patch by Pierre Aubert, 15 Mar 2004: |
3399 | Fix buffer overflow in IDE identification | 3402 | Fix buffer overflow in IDE identification |
3400 | 3403 | ||
3401 | * Fix power-off of LCD for out-of-band temperatures on LWMON board | 3404 | * Fix power-off of LCD for out-of-band temperatures on LWMON board |
3402 | 3405 | ||
3403 | * Remove redundand #define in IceCube.h | 3406 | * Remove redundand #define in IceCube.h |
3404 | 3407 | ||
3405 | * Patch by Steven Scholz, 27 Feb 2004: | 3408 | * Patch by Steven Scholz, 27 Feb 2004: |
3406 | - Adding get_ticks() and get_tbclk() for AT91RM9200 | 3409 | - Adding get_ticks() and get_tbclk() for AT91RM9200 |
3407 | - Many white space fixes in cpu/at91rm9200/interrupts.c | 3410 | - Many white space fixes in cpu/at91rm9200/interrupts.c |
3408 | 3411 | ||
3409 | * Patches by Steven Scholz, 20 Feb 2004: | 3412 | * Patches by Steven Scholz, 20 Feb 2004: |
3410 | some cleanup in AT91RM9200 related code | 3413 | some cleanup in AT91RM9200 related code |
3411 | 3414 | ||
3412 | * Patches by Travis Sawyer, 12 Mar 2004: | 3415 | * Patches by Travis Sawyer, 12 Mar 2004: |
3413 | - Fix Gigabit Ethernet support for 440GX | 3416 | - Fix Gigabit Ethernet support for 440GX |
3414 | - Add Gigabit Ethernet Support to MII PHY utilities | 3417 | - Add Gigabit Ethernet Support to MII PHY utilities |
3415 | 3418 | ||
3416 | * Patch by Brad Kemp, 12 Mar 2004: | 3419 | * Patch by Brad Kemp, 12 Mar 2004: |
3417 | Fixes for drivers/cfi_flash.c: | 3420 | Fixes for drivers/cfi_flash.c: |
3418 | - Better support for x8/x16 implementations | 3421 | - Better support for x8/x16 implementations |
3419 | - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE | 3422 | - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE |
3420 | - Added defines for AMD command and address constants | 3423 | - Added defines for AMD command and address constants |
3421 | 3424 | ||
3422 | * Patch by Leon Kukovec, 12 Mar 2004: | 3425 | * Patch by Leon Kukovec, 12 Mar 2004: |
3423 | Fix get_dentfromdir() to correctly handle deleted dentries | 3426 | Fix get_dentfromdir() to correctly handle deleted dentries |
3424 | 3427 | ||
3425 | * Patch by George G. Davis, 11 Mar 2004: | 3428 | * Patch by George G. Davis, 11 Mar 2004: |
3426 | Remove hard coded network settings in TI OMAP1610 H2 | 3429 | Remove hard coded network settings in TI OMAP1610 H2 |
3427 | default board config | 3430 | default board config |
3428 | 3431 | ||
3429 | * Patch by George G. Davis, 11 Mar 2004: | 3432 | * Patch by George G. Davis, 11 Mar 2004: |
3430 | add support for ADS GraphicsClient+ board. | 3433 | add support for ADS GraphicsClient+ board. |
3431 | 3434 | ||
3432 | * Patch by Pierre Aubert, 11 Mar 2004: | 3435 | * Patch by Pierre Aubert, 11 Mar 2004: |
3433 | - add bitmap command and splash screen support in cfb console | 3436 | - add bitmap command and splash screen support in cfb console |
3434 | - add [optional] origin in the bitmap display command | 3437 | - add [optional] origin in the bitmap display command |
3435 | 3438 | ||
3436 | * Patch by Travis Sawyer, 11 Mar 2004: | 3439 | * Patch by Travis Sawyer, 11 Mar 2004: |
3437 | Fix ocotea board early init interrupt setup. | 3440 | Fix ocotea board early init interrupt setup. |
3438 | 3441 | ||
3439 | * Patch by Thomas Viehweger, 11 Mar 2004: | 3442 | * Patch by Thomas Viehweger, 11 Mar 2004: |
3440 | Remove redundand code; add PCI-specific bits to include/mpc8260.h | 3443 | Remove redundand code; add PCI-specific bits to include/mpc8260.h |
3441 | 3444 | ||
3442 | * Patch by Stephan Linz, 09 Mar 2004 | 3445 | * Patch by Stephan Linz, 09 Mar 2004 |
3443 | - Add support for the SSV ADNP/ESC1 (Nios Softcore) | 3446 | - Add support for the SSV ADNP/ESC1 (Nios Softcore) |
3444 | 3447 | ||
3445 | * Patch by George G. Davis, 9 Mar 2004: | 3448 | * Patch by George G. Davis, 9 Mar 2004: |
3446 | fix recent build failure for SA1100 target | 3449 | fix recent build failure for SA1100 target |
3447 | 3450 | ||
3448 | * Patch by Travis Sawyer, 09 Mar 2004: | 3451 | * Patch by Travis Sawyer, 09 Mar 2004: |
3449 | Support native interrupt mode for the IBM440GX. | 3452 | Support native interrupt mode for the IBM440GX. |
3450 | Previously it was running in 440GP compatibility mode. | 3453 | Previously it was running in 440GP compatibility mode. |
3451 | 3454 | ||
3452 | * Patch by Philippe Robin, 09 Mar 2004: | 3455 | * Patch by Philippe Robin, 09 Mar 2004: |
3453 | Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference | 3456 | Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference |
3454 | Platform support. | 3457 | Platform support. |
3455 | 3458 | ||
3456 | * Patch by Masami Komiya, 08 Mar 2004: | 3459 | * Patch by Masami Komiya, 08 Mar 2004: |
3457 | Don't overwrite server IP address or boot file name | 3460 | Don't overwrite server IP address or boot file name |
3458 | when the boot server does not return values | 3461 | when the boot server does not return values |
3459 | 3462 | ||
3460 | * Patch by Tolunay Orkun, 5 Mar 2004: | 3463 | * Patch by Tolunay Orkun, 5 Mar 2004: |
3461 | Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC | 3464 | Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC |
3462 | 3465 | ||
3463 | * Patch by Tolunay Orkun, 5 Mar 2004: | 3466 | * Patch by Tolunay Orkun, 5 Mar 2004: |
3464 | Fix early board initialization for Cogent CSB272 board | 3467 | Fix early board initialization for Cogent CSB272 board |
3465 | 3468 | ||
3466 | * Patch by Ed Okerson, 3 Mar 2004: | 3469 | * Patch by Ed Okerson, 3 Mar 2004: |
3467 | fix CFI flash writes for little endian systems | 3470 | fix CFI flash writes for little endian systems |
3468 | 3471 | ||
3469 | * Patch by Reinhard Meyer, 01 Mar 2004: | 3472 | * Patch by Reinhard Meyer, 01 Mar 2004: |
3470 | generalize USB and IDE support for MPC5200 with according | 3473 | generalize USB and IDE support for MPC5200 with according |
3471 | changes to IceCube.h and TOP5200.h | 3474 | changes to IceCube.h and TOP5200.h |
3472 | add Am29LV256 256 MBit FLASH support for TOP5200 boards | 3475 | add Am29LV256 256 MBit FLASH support for TOP5200 boards |
3473 | add info about USB and IDE to README | 3476 | add info about USB and IDE to README |
3474 | 3477 | ||
3475 | * Patch by Yuli Barcohen, 4 Mar 2004: | 3478 | * Patch by Yuli Barcohen, 4 Mar 2004: |
3476 | Fix problems with GCC 3.3.x which changed handling of global | 3479 | Fix problems with GCC 3.3.x which changed handling of global |
3477 | variables explicitly initialized to zero (now in .bss instead of | 3480 | variables explicitly initialized to zero (now in .bss instead of |
3478 | .data as before). | 3481 | .data as before). |
3479 | 3482 | ||
3480 | * Patch by Leon Kukovec, 02 Mar 2004: | 3483 | * Patch by Leon Kukovec, 02 Mar 2004: |
3481 | add strswab() to fix IDE LBA capacity, firmware and model numbers | 3484 | add strswab() to fix IDE LBA capacity, firmware and model numbers |
3482 | on little endian machines | 3485 | on little endian machines |
3483 | 3486 | ||
3484 | * Patch by Masami Komiya, 02 Mar 2004: | 3487 | * Patch by Masami Komiya, 02 Mar 2004: |
3485 | - Remove get_ticks() from NFS code | 3488 | - Remove get_ticks() from NFS code |
3486 | - Add verification of RPC transaction ID | 3489 | - Add verification of RPC transaction ID |
3487 | 3490 | ||
3488 | * Patch by Pierre Aubert, 02 Mar 2004: | 3491 | * Patch by Pierre Aubert, 02 Mar 2004: |
3489 | cleanup for IDE and USB drivers for MPC5200 | 3492 | cleanup for IDE and USB drivers for MPC5200 |
3490 | 3493 | ||
3491 | * Patch by Travis Sawyer, 01 Mar 2004: | 3494 | * Patch by Travis Sawyer, 01 Mar 2004: |
3492 | Ocotea: | 3495 | Ocotea: |
3493 | - Add IBM PPC440GX Ref Platform support (Ocotea) | 3496 | - Add IBM PPC440GX Ref Platform support (Ocotea) |
3494 | Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> | 3497 | Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> |
3495 | Adapted to U-Boot and 440GX port | 3498 | Adapted to U-Boot and 440GX port |
3496 | 440gx_enet.c: | 3499 | 440gx_enet.c: |
3497 | - Add gracious handling of all Ethernet Pin Selections for 440GX | 3500 | - Add gracious handling of all Ethernet Pin Selections for 440GX |
3498 | - Add RGMII selection for Cicada CIS8201 Gigabit PHY | 3501 | - Add RGMII selection for Cicada CIS8201 Gigabit PHY |
3499 | ppc440.h: | 3502 | ppc440.h: |
3500 | - Add needed bit definitions | 3503 | - Add needed bit definitions |
3501 | - Fix formatting | 3504 | - Fix formatting |
3502 | 3505 | ||
3503 | * Patch by Carl Riechers, 1 Mar 2004: | 3506 | * Patch by Carl Riechers, 1 Mar 2004: |
3504 | Add PPC440GX prbdv0 divider to fix memory clock calculation. | 3507 | Add PPC440GX prbdv0 divider to fix memory clock calculation. |
3505 | 3508 | ||
3506 | * Patch by Stephan Linz, 27 Feb 2004 | 3509 | * Patch by Stephan Linz, 27 Feb 2004 |
3507 | - avoid problems for targets without NFS download support | 3510 | - avoid problems for targets without NFS download support |
3508 | 3511 | ||
3509 | * Patch by Rune Torgersen, 27 Feb 2004: | 3512 | * Patch by Rune Torgersen, 27 Feb 2004: |
3510 | - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA) | 3513 | - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA) |
3511 | - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF) | 3514 | - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF) |
3512 | - Added support for 64bit strtoul (CFG_64BIT_STRTOUL) | 3515 | - Added support for 64bit strtoul (CFG_64BIT_STRTOUL) |
3513 | 3516 | ||
3514 | * Patch by Masami Komiya, 27 Feb 2004: | 3517 | * Patch by Masami Komiya, 27 Feb 2004: |
3515 | Fix rarpboot: add autoload by NFS | 3518 | Fix rarpboot: add autoload by NFS |
3516 | 3519 | ||
3517 | * Patch by Dan Eisenhut, 26 Feb 2004: | 3520 | * Patch by Dan Eisenhut, 26 Feb 2004: |
3518 | fix flash_write return value in saveenv | 3521 | fix flash_write return value in saveenv |
3519 | 3522 | ||
3520 | * Patch by Stephan Linz, 11 Dec 2003 | 3523 | * Patch by Stephan Linz, 11 Dec 2003 |
3521 | expand config.mk to avoid trigraph warnings on NIOS | 3524 | expand config.mk to avoid trigraph warnings on NIOS |
3522 | 3525 | ||
3523 | * Rename "BMS2003" board into "HMI10" | 3526 | * Rename "BMS2003" board into "HMI10" |
3524 | 3527 | ||
3525 | * SX1 patches: use "serial#" for USB serial #; use redundand environment | 3528 | * SX1 patches: use "serial#" for USB serial #; use redundand environment |
3526 | storage; auto-set console on USB port (using preboot command) | 3529 | storage; auto-set console on USB port (using preboot command) |
3527 | 3530 | ||
3528 | * Add support for SX1 mobile phone; add support for USB-based console | 3531 | * Add support for SX1 mobile phone; add support for USB-based console |
3529 | (enable with "setenv stdout usbtty; setenv stdin usbtty") | 3532 | (enable with "setenv stdout usbtty; setenv stdin usbtty") |
3530 | 3533 | ||
3531 | * Fix LOWBOOT configuration for MPC5200 with DDR memory | 3534 | * Fix LOWBOOT configuration for MPC5200 with DDR memory |
3532 | 3535 | ||
3533 | * Fix SDRAM timings for LITE5200 / IceCube board | 3536 | * Fix SDRAM timings for LITE5200 / IceCube board |
3534 | 3537 | ||
3535 | * Handle Auti-MDIX / connection status for INCA-IP | 3538 | * Handle Auti-MDIX / connection status for INCA-IP |
3536 | 3539 | ||
3537 | * Fix USB problems when attempting to read 0 bytes | 3540 | * Fix USB problems when attempting to read 0 bytes |
3538 | 3541 | ||
3539 | * Patch by Travis Sawyer, 26 Feb 2004: | 3542 | * Patch by Travis Sawyer, 26 Feb 2004: |
3540 | Fix broken compile for XPEDITE1K target. | 3543 | Fix broken compile for XPEDITE1K target. |
3541 | 3544 | ||
3542 | * Patch by Stephan Linz, 26 Feb 2004: | 3545 | * Patch by Stephan Linz, 26 Feb 2004: |
3543 | Bug fix for NFS code on NIOS targets | 3546 | Bug fix for NFS code on NIOS targets |
3544 | 3547 | ||
3545 | * Patch by Stephen Williams, 26 Feb 2004: | 3548 | * Patch by Stephen Williams, 26 Feb 2004: |
3546 | Break up SystemACE reads of large block counts | 3549 | Break up SystemACE reads of large block counts |
3547 | 3550 | ||
3548 | * Patch by Pierre Aubert, 26 Feb 2004 | 3551 | * Patch by Pierre Aubert, 26 Feb 2004 |
3549 | add IDE support for MPC5200 | 3552 | add IDE support for MPC5200 |
3550 | 3553 | ||
3551 | * Patch by Masami Komiya, 26 Feb 2004: | 3554 | * Patch by Masami Komiya, 26 Feb 2004: |
3552 | add autoload via NFS | 3555 | add autoload via NFS |
3553 | 3556 | ||
3554 | * Patch by Stephen Williams | 3557 | * Patch by Stephen Williams |
3555 | Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses | 3558 | Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses |
3556 | elsewhere in the source. | 3559 | elsewhere in the source. |
3557 | 3560 | ||
3558 | * Patch by Steven Scholz, 25 Feb 2004: | 3561 | * Patch by Steven Scholz, 25 Feb 2004: |
3559 | - Timeouts in FPGA code should be based on CFG_HZ | 3562 | - Timeouts in FPGA code should be based on CFG_HZ |
3560 | - Minor cleanup in code for Altera FPGA ACEX1K | 3563 | - Minor cleanup in code for Altera FPGA ACEX1K |
3561 | 3564 | ||
3562 | * Patch by Steven Scholz, 25 Feb 2004: | 3565 | * Patch by Steven Scholz, 25 Feb 2004: |
3563 | Changed "Directory Hierarchy" section in README | 3566 | Changed "Directory Hierarchy" section in README |
3564 | 3567 | ||
3565 | * Patch by Masami Komiya, 25 Feb 2004: | 3568 | * Patch by Masami Komiya, 25 Feb 2004: |
3566 | Reduce copy count in nfs_read_reply() of NFS code | 3569 | Reduce copy count in nfs_read_reply() of NFS code |
3567 | 3570 | ||
3568 | * Patch by Markus Pietrek, 24 Feb 2004: | 3571 | * Patch by Markus Pietrek, 24 Feb 2004: |
3569 | NS9750 DevBoard added | 3572 | NS9750 DevBoard added |
3570 | 3573 | ||
3571 | * Patch by Pierre Aubert, 24 Feb 2004 | 3574 | * Patch by Pierre Aubert, 24 Feb 2004 |
3572 | add USB support for MPC5200 | 3575 | add USB support for MPC5200 |
3573 | 3576 | ||
3574 | * Patch by Steven Scholz, 24 Feb 2004: | 3577 | * Patch by Steven Scholz, 24 Feb 2004: |
3575 | - fix MII commands to use values from last command | 3578 | - fix MII commands to use values from last command |
3576 | 3579 | ||
3577 | * Patch by Torsten Demke, 24 Feb 2004: | 3580 | * Patch by Torsten Demke, 24 Feb 2004: |
3578 | Add support for the eXalion platform (SPSW-8240, F-30, F-300) | 3581 | Add support for the eXalion platform (SPSW-8240, F-30, F-300) |
3579 | 3582 | ||
3580 | * Patch by Rahul Shanbhag, 19 Feb 2004: | 3583 | * Patch by Rahul Shanbhag, 19 Feb 2004: |
3581 | Fixes for for OMAP1610 board: | 3584 | Fixes for for OMAP1610 board: |
3582 | - shift some IRQ specific code to platform.S file | 3585 | - shift some IRQ specific code to platform.S file |
3583 | - remove duplicatewatchdog reset code from start.S | 3586 | - remove duplicatewatchdog reset code from start.S |
3584 | 3587 | ||
3585 | * Make Auto-MDIX Support configurable on INCA-IP board | 3588 | * Make Auto-MDIX Support configurable on INCA-IP board |
3586 | 3589 | ||
3587 | * Fix license for mkimage tool | 3590 | * Fix license for mkimage tool |
3588 | 3591 | ||
3589 | * Patch by Masami Komiya, 24 Feb 2004: | 3592 | * Patch by Masami Komiya, 24 Feb 2004: |
3590 | Update NetBootFileXferSize in NFS code | 3593 | Update NetBootFileXferSize in NFS code |
3591 | 3594 | ||
3592 | * Patch by Scott McNutt, 24 Feb 2004: | 3595 | * Patch by Scott McNutt, 24 Feb 2004: |
3593 | fix packet length in NFS code | 3596 | fix packet length in NFS code |
3594 | 3597 | ||
3595 | * Patch by Masami Komiy, 22 Feb 2004: | 3598 | * Patch by Masami Komiy, 22 Feb 2004: |
3596 | Add support for NFS for file download | 3599 | Add support for NFS for file download |
3597 | 3600 | ||
3598 | * Patch by Andrea Scian, 17 Feb 2004: | 3601 | * Patch by Andrea Scian, 17 Feb 2004: |
3599 | Add support for S3C44B0 processor and DAVE B2 board | 3602 | Add support for S3C44B0 processor and DAVE B2 board |
3600 | 3603 | ||
3601 | * Patch by Steven Scholz, 20 Feb 2004: | 3604 | * Patch by Steven Scholz, 20 Feb 2004: |
3602 | - Add support for MII commands on AT91RM9200 boards | 3605 | - Add support for MII commands on AT91RM9200 boards |
3603 | - some cleanup in AT91RM9200 ethernet code | 3606 | - some cleanup in AT91RM9200 ethernet code |
3604 | 3607 | ||
3605 | * Patch by Peter Ryser, 20 Feb 2004: | 3608 | * Patch by Peter Ryser, 20 Feb 2004: |
3606 | Add support for the Xilinx ML300 platform | 3609 | Add support for the Xilinx ML300 platform |
3607 | 3610 | ||
3608 | * Patch by Stephan Linz, 17 Feb 2004: | 3611 | * Patch by Stephan Linz, 17 Feb 2004: |
3609 | Fix watchdog support for NIOS | 3612 | Fix watchdog support for NIOS |
3610 | 3613 | ||
3611 | * Patch by Josh Fryman, 16 Feb 2004: | 3614 | * Patch by Josh Fryman, 16 Feb 2004: |
3612 | Fix byte-swapping for cfi_flash.c for different bus widths | 3615 | Fix byte-swapping for cfi_flash.c for different bus widths |
3613 | 3616 | ||
3614 | * Patch by Jon Diekema, 14 Jeb 2004: | 3617 | * Patch by Jon Diekema, 14 Jeb 2004: |
3615 | Remove duplicate "FPGA Support" notes from the README file | 3618 | Remove duplicate "FPGA Support" notes from the README file |
3616 | 3619 | ||
3617 | * Patches by Reinhard Meyer, 14 Feb 2004: | 3620 | * Patches by Reinhard Meyer, 14 Feb 2004: |
3618 | - update board/emk tree; use common flash driver | 3621 | - update board/emk tree; use common flash driver |
3619 | - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c | 3622 | - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c |
3620 | [adapted for other PPC CPUs -- wd] | 3623 | [adapted for other PPC CPUs -- wd] |
3621 | - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c | 3624 | - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c |
3622 | 3625 | ||
3623 | * Patch by Jon Diekema, 13 Feb 2004: | 3626 | * Patch by Jon Diekema, 13 Feb 2004: |
3624 | Call show_boot_progress() whenever POST "FAILED" is printed. | 3627 | Call show_boot_progress() whenever POST "FAILED" is printed. |
3625 | 3628 | ||
3626 | * Patch by Nishant Kamat, 13 Feb 2004: | 3629 | * Patch by Nishant Kamat, 13 Feb 2004: |
3627 | Add support for TI OMAP1610 H2 Board | 3630 | Add support for TI OMAP1610 H2 Board |
3628 | Fixes for cpu/arm926ejs/interrupt.c | 3631 | Fixes for cpu/arm926ejs/interrupt.c |
3629 | (based on Richard Woodruff's patch for arm925, 16 Oct 03) | 3632 | (based on Richard Woodruff's patch for arm925, 16 Oct 03) |
3630 | Fix for a timer bug in OMAP1610 Innovator | 3633 | Fix for a timer bug in OMAP1610 Innovator |
3631 | Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 | 3634 | Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 |
3632 | 3635 | ||
3633 | * Patches by Stephan Linz, 12 Feb 2004: | 3636 | * Patches by Stephan Linz, 12 Feb 2004: |
3634 | - add support for NIOS timer with variable period preload counter value | 3637 | - add support for NIOS timer with variable period preload counter value |
3635 | - prepare POST framework support for NIOS targets | 3638 | - prepare POST framework support for NIOS targets |
3636 | 3639 | ||
3637 | * Patch by Denis Peter, 11 Feb 2004: | 3640 | * Patch by Denis Peter, 11 Feb 2004: |
3638 | add POST support for the MIP405 board | 3641 | add POST support for the MIP405 board |
3639 | 3642 | ||
3640 | * Patch by Laurent Mohin, 10 Feb 2004: | 3643 | * Patch by Laurent Mohin, 10 Feb 2004: |
3641 | Fix buffer overflow in common/usb.c | 3644 | Fix buffer overflow in common/usb.c |
3642 | 3645 | ||
3643 | * Patch by Tolunay Orkun, 10 Feb 2004: | 3646 | * Patch by Tolunay Orkun, 10 Feb 2004: |
3644 | Add support for Cogent CSB272 board | 3647 | Add support for Cogent CSB272 board |
3645 | 3648 | ||
3646 | * Patch by Thomas Elste, 10 Feb 2004: | 3649 | * Patch by Thomas Elste, 10 Feb 2004: |
3647 | Add support for NET+50 CPU and ModNET50 board | 3650 | Add support for NET+50 CPU and ModNET50 board |
3648 | 3651 | ||
3649 | * Patch by Sam Song, 10 Feb 2004: | 3652 | * Patch by Sam Song, 10 Feb 2004: |
3650 | Fix typos in cfi_flash.c | 3653 | Fix typos in cfi_flash.c |
3651 | 3654 | ||
3652 | * Patch by Leon Kukovec, 10 Feb 2004 | 3655 | * Patch by Leon Kukovec, 10 Feb 2004 |
3653 | Fixed long dir entry slot id calculation in get_vfatname | 3656 | Fixed long dir entry slot id calculation in get_vfatname |
3654 | 3657 | ||
3655 | * Patch by Robin Gilks, 10 Feb 2004: | 3658 | * Patch by Robin Gilks, 10 Feb 2004: |
3656 | add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, | 3659 | add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, |
3657 | !=, <>, <, >, <=, >=) | 3660 | !=, <>, <, >, <=, >=) |
3658 | 3661 | ||
3659 | * Fix problem with side effects in macros in include/usb.h | 3662 | * Fix problem with side effects in macros in include/usb.h |
3660 | 3663 | ||
3661 | * Patch by David Benson, 13 Nov 2003: | 3664 | * Patch by David Benson, 13 Nov 2003: |
3662 | bug 841358 - fix TFTP download size limit | 3665 | bug 841358 - fix TFTP download size limit |
3663 | 3666 | ||
3664 | * Fixing bug 850768: | 3667 | * Fixing bug 850768: |
3665 | improper flush_cache() in load_serial() | 3668 | improper flush_cache() in load_serial() |
3666 | 3669 | ||
3667 | * Fixing bug 834943: | 3670 | * Fixing bug 834943: |
3668 | MPC8540 - missing volatile declarations | 3671 | MPC8540 - missing volatile declarations |
3669 | 3672 | ||
3670 | * Patch by Stephen Williams, 09 Feb 2004: | 3673 | * Patch by Stephen Williams, 09 Feb 2004: |
3671 | Add support for Xilinx SystemACE chip: | 3674 | Add support for Xilinx SystemACE chip: |
3672 | - New files common/cmd_ace.c and include/systemace.h | 3675 | - New files common/cmd_ace.c and include/systemace.h |
3673 | - Hook systemace support into cmd_fat and the partition manager | 3676 | - Hook systemace support into cmd_fat and the partition manager |
3674 | 3677 | ||
3675 | * Patch by Travis Sawyer, 09 Feb 2004: | 3678 | * Patch by Travis Sawyer, 09 Feb 2004: |
3676 | Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux | 3679 | Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux |
3677 | 3680 | ||
3678 | * Patch by Travis Sawyer, 09 Feb 2004: | 3681 | * Patch by Travis Sawyer, 09 Feb 2004: |
3679 | o 440GX: | 3682 | o 440GX: |
3680 | - Fix PCI Indirect access for type 1 config cycles with ppc440. | 3683 | - Fix PCI Indirect access for type 1 config cycles with ppc440. |
3681 | - Add phymode for 440 enet | 3684 | - Add phymode for 440 enet |
3682 | - fix pci pre init | 3685 | - fix pci pre init |
3683 | o XPedite1K: | 3686 | o XPedite1K: |
3684 | - Change board_pre_init to board_early_init_f | 3687 | - Change board_pre_init to board_early_init_f |
3685 | - Add user flash to bus controller setup | 3688 | - Add user flash to bus controller setup |
3686 | - Fix pci pre init | 3689 | - Fix pci pre init |
3687 | - Fix is_pci_host to check GPIO for monarch bit | 3690 | - Fix is_pci_host to check GPIO for monarch bit |
3688 | - Force xpedite1k to pci conventional mode (via #define option) | 3691 | - Force xpedite1k to pci conventional mode (via #define option) |
3689 | 3692 | ||
3690 | * Patch by Brad Kemp, 4 Feb 2004: | 3693 | * Patch by Brad Kemp, 4 Feb 2004: |
3691 | - handle the machine check that is generated during the PCI scans | 3694 | - handle the machine check that is generated during the PCI scans |
3692 | on 82xx processors. | 3695 | on 82xx processors. |
3693 | - define the registers used in the IMMR by the PCI subsystem. | 3696 | - define the registers used in the IMMR by the PCI subsystem. |
3694 | 3697 | ||
3695 | * Patch by Pierre Aubert, 03 Feb 2004: | 3698 | * Patch by Pierre Aubert, 03 Feb 2004: |
3696 | cpu/mpc5xxx/start.S: copy MBAR into SPR311 | 3699 | cpu/mpc5xxx/start.S: copy MBAR into SPR311 |
3697 | 3700 | ||
3698 | * Patch by Jeff Angielski, 03 Feb 2004: | 3701 | * Patch by Jeff Angielski, 03 Feb 2004: |
3699 | Fix copy & paste error in cpu/mpc8260/pci.c | 3702 | Fix copy & paste error in cpu/mpc8260/pci.c |
3700 | 3703 | ||
3701 | * Patch by Reinhard Meyer, 24 Jan 2004: | 3704 | * Patch by Reinhard Meyer, 24 Jan 2004: |
3702 | Fix typo in cpu/mpc5xxx/pci_mpc5200.c | 3705 | Fix typo in cpu/mpc5xxx/pci_mpc5200.c |
3703 | 3706 | ||
3704 | * Add Auto-MDIX support for INCA-IP | 3707 | * Add Auto-MDIX support for INCA-IP |
3705 | 3708 | ||
3706 | * Some code cleanup | 3709 | * Some code cleanup |
3707 | 3710 | ||
3708 | * Patch by Josef Baumgartner, 10 Feb 2004: | 3711 | * Patch by Josef Baumgartner, 10 Feb 2004: |
3709 | Fixes for ColdFire port | 3712 | Fixes for ColdFire port |
3710 | 3713 | ||
3711 | * Patch by Brad Kemp, 11 Feb 2004: | 3714 | * Patch by Brad Kemp, 11 Feb 2004: |
3712 | Fix CFI flash driver problems | 3715 | Fix CFI flash driver problems |
3713 | 3716 | ||
3714 | * Make sure to use a bus clock divider of 2 only when running TQM8xxM | 3717 | * Make sure to use a bus clock divider of 2 only when running TQM8xxM |
3715 | modules at CPU clock frequencies above 66 MHz. | 3718 | modules at CPU clock frequencies above 66 MHz. |
3716 | 3719 | ||
3717 | * Optimize flash programming speed for LWMON (by another 100% :-) | 3720 | * Optimize flash programming speed for LWMON (by another 100% :-) |
3718 | 3721 | ||
3719 | * Patch by Jian Zhang, 3 Feb 2004: | 3722 | * Patch by Jian Zhang, 3 Feb 2004: |
3720 | - Changed the incorrect FAT12BUFSIZE | 3723 | - Changed the incorrect FAT12BUFSIZE |
3721 | - data_begin in fsdata can be negative. Changed it to be short. | 3724 | - data_begin in fsdata can be negative. Changed it to be short. |
3722 | 3725 | ||
3723 | * Patches by Stephan Linz, 30 Jan 2004: | 3726 | * Patches by Stephan Linz, 30 Jan 2004: |
3724 | 1: - board/altera/common/flash.c:flash_erase(): | 3727 | 1: - board/altera/common/flash.c:flash_erase(): |
3725 | o allow interrupts befor get_timer() call | 3728 | o allow interrupts befor get_timer() call |
3726 | o check-up each erased sector and avoid unexpected timeouts | 3729 | o check-up each erased sector and avoid unexpected timeouts |
3727 | - board/altera/dk1c20/dk1s10.c:board_early_init_f(): | 3730 | - board/altera/dk1c20/dk1s10.c:board_early_init_f(): |
3728 | o enclose sevenseg_set() in cpp condition | 3731 | o enclose sevenseg_set() in cpp condition |
3729 | - remove the ASMI configuration for DK1S10_standard_32 (never present) | 3732 | - remove the ASMI configuration for DK1S10_standard_32 (never present) |
3730 | - fix some typed in mistakes in the NIOS documentation | 3733 | - fix some typed in mistakes in the NIOS documentation |
3731 | 2: - split DK1C20 configuration into several header files: | 3734 | 2: - split DK1C20 configuration into several header files: |
3732 | o two new files for each NIOS CPU description | 3735 | o two new files for each NIOS CPU description |
3733 | o U-Boot related part is remaining in DK1C20.h | 3736 | o U-Boot related part is remaining in DK1C20.h |
3734 | 3: - split DK1S10 configuration into several header files: | 3737 | 3: - split DK1S10 configuration into several header files: |
3735 | o two new files for each NIOS CPU description | 3738 | o two new files for each NIOS CPU description |
3736 | o U-Boot related part is remaining in DK1S10.h | 3739 | o U-Boot related part is remaining in DK1S10.h |
3737 | 4: - Add support for the Microtronix Linux Development Kit | 3740 | 4: - Add support for the Microtronix Linux Development Kit |
3738 | NIOS CPU configuration at the Altera Nios Development Kit, | 3741 | NIOS CPU configuration at the Altera Nios Development Kit, |
3739 | Stratix Edition (DK-1S10) | 3742 | Stratix Edition (DK-1S10) |
3740 | 5: - Add documentation for the Altera Nios Development Kit, | 3743 | 5: - Add documentation for the Altera Nios Development Kit, |
3741 | Stratix Edition (DK-1S10) | 3744 | Stratix Edition (DK-1S10) |
3742 | 6: - Add support for the Nios Serial Peripharel Interface (SPI) | 3745 | 6: - Add support for the Nios Serial Peripharel Interface (SPI) |
3743 | (master only) | 3746 | (master only) |
3744 | 7: - Add support for the common U-Boot SPI framework at | 3747 | 7: - Add support for the common U-Boot SPI framework at |
3745 | RTC driver DS1306 | 3748 | RTC driver DS1306 |
3746 | 3749 | ||
3747 | * Patch by Rahul Shanbhag, 28 Jan 2004: | 3750 | * Patch by Rahul Shanbhag, 28 Jan 2004: |
3748 | Fix flash protection/locking handling for OMAP1610 innovator board. | 3751 | Fix flash protection/locking handling for OMAP1610 innovator board. |
3749 | 3752 | ||
3750 | * Patch by Rolf Peukert, 28 Jan 2004: | 3753 | * Patch by Rolf Peukert, 28 Jan 2004: |
3751 | fix flash write problems on CSB226 board (write with 32 bit bus width) | 3754 | fix flash write problems on CSB226 board (write with 32 bit bus width) |
3752 | 3755 | ||
3753 | * Patches by Mark Jonas, 16 Jan 2004: | 3756 | * Patches by Mark Jonas, 16 Jan 2004: |
3754 | - fix rounding error when calculating baudrates for MPC5200 PSCs | 3757 | - fix rounding error when calculating baudrates for MPC5200 PSCs |
3755 | - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same | 3758 | - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same |
3756 | time which is not supported | 3759 | time which is not supported |
3757 | 3760 | ||
3758 | * Patch by Yuli Barcohen, 26 Jan 2004: | 3761 | * Patch by Yuli Barcohen, 26 Jan 2004: |
3759 | Allow bzip2 compression for small memory footprint boards | 3762 | Allow bzip2 compression for small memory footprint boards |
3760 | 3763 | ||
3761 | * Patch by Brad Kemp, 21 Jan 2004: | 3764 | * Patch by Brad Kemp, 21 Jan 2004: |
3762 | Add support for CFI flash driver for both the Intel and the AMD | 3765 | Add support for CFI flash driver for both the Intel and the AMD |
3763 | command sets. | 3766 | command sets. |
3764 | 3767 | ||
3765 | * Patch by Travis Sawyer, 20 Jan 2004: | 3768 | * Patch by Travis Sawyer, 20 Jan 2004: |
3766 | Fix pci bridge auto enumeration of sibling p2p bridges. | 3769 | Fix pci bridge auto enumeration of sibling p2p bridges. |
3767 | 3770 | ||
3768 | * Patch by Tolunay Orkun, 12 Jan 2004: | 3771 | * Patch by Tolunay Orkun, 12 Jan 2004: |
3769 | Add some delays as needed for Intel LXT971A PHY support | 3772 | Add some delays as needed for Intel LXT971A PHY support |
3770 | 3773 | ||
3771 | * Patches by Stephan Linz, 09 Jan 2004: | 3774 | * Patches by Stephan Linz, 09 Jan 2004: |
3772 | - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c | 3775 | - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c |
3773 | - make DK1C20 board configuration related to ASMI conform to | 3776 | - make DK1C20 board configuration related to ASMI conform to |
3774 | documentation | 3777 | documentation |
3775 | 3778 | ||
3776 | * Patch by Anders Larsen, 09 Jan 2004: | 3779 | * Patch by Anders Larsen, 09 Jan 2004: |
3777 | 3780 | ||
3778 | ARM memory layout fixes: the abort-stack is now set up in the | 3781 | ARM memory layout fixes: the abort-stack is now set up in the |
3779 | correct RAM area, and the BSS is zeroed out as it should be. | 3782 | correct RAM area, and the BSS is zeroed out as it should be. |
3780 | 3783 | ||
3781 | Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' | 3784 | Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' |
3782 | of the linker scripts are replaced by '__bss_start' and '_end', | 3785 | of the linker scripts are replaced by '__bss_start' and '_end', |
3783 | resp., which is a further step to eliminate unnecessary differences | 3786 | resp., which is a further step to eliminate unnecessary differences |
3784 | between the implementation of the CPU architectures. | 3787 | between the implementation of the CPU architectures. |
3785 | 3788 | ||
3786 | * Patch by liang a lei, 9 Jan 2004: | 3789 | * Patch by liang a lei, 9 Jan 2004: |
3787 | Fix Intel 28F128J3 ID in include/flash.h | 3790 | Fix Intel 28F128J3 ID in include/flash.h |
3788 | 3791 | ||
3789 | * Patch by Masami Komiya, 09 Jan 2004: | 3792 | * Patch by Masami Komiya, 09 Jan 2004: |
3790 | add support for TB0229 board (NEC VR4131 MIPS processor) | 3793 | add support for TB0229 board (NEC VR4131 MIPS processor) |
3791 | 3794 | ||
3792 | * Patch by Leon Kukovec, 12 Dec 2003: | 3795 | * Patch by Leon Kukovec, 12 Dec 2003: |
3793 | changed extern __inline__ into static __inline__ in | 3796 | changed extern __inline__ into static __inline__ in |
3794 | include/linux/byteorder/swab.h | 3797 | include/linux/byteorder/swab.h |
3795 | 3798 | ||
3796 | * Patch by Travis Sawyer, 30 Dec 2003: | 3799 | * Patch by Travis Sawyer, 30 Dec 2003: |
3797 | Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, | 3800 | Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, |
3798 | select MDI port based on enabled EMAC device. | 3801 | select MDI port based on enabled EMAC device. |
3799 | Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX | 3802 | Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX |
3800 | base PrPMC board. | 3803 | base PrPMC board. |
3801 | 3804 | ||
3802 | * Patch by Wolter Kamphuis, 15 Dec 2003: | 3805 | * Patch by Wolter Kamphuis, 15 Dec 2003: |
3803 | made CONFIG_SILENT_CONSOLE usable on all architectures | 3806 | made CONFIG_SILENT_CONSOLE usable on all architectures |
3804 | 3807 | ||
3805 | * Disable date command on TQM866M - there is no RTC on MPC866 | 3808 | * Disable date command on TQM866M - there is no RTC on MPC866 |
3806 | 3809 | ||
3807 | * Fix variable CPU clock for MPC859/866 systems for low CPU clocks | 3810 | * Fix variable CPU clock for MPC859/866 systems for low CPU clocks |
3808 | 3811 | ||
3809 | * Implement adaptive SDRAM timing configuration based on actual CPU | 3812 | * Implement adaptive SDRAM timing configuration based on actual CPU |
3810 | clock frequency for INCA-IP; fix problem with board hanging when | 3813 | clock frequency for INCA-IP; fix problem with board hanging when |
3811 | switching from 150MHz to 100MHz | 3814 | switching from 150MHz to 100MHz |
3812 | 3815 | ||
3813 | * Add PCMCIA CS support for BMS2003 board | 3816 | * Add PCMCIA CS support for BMS2003 board |
3814 | 3817 | ||
3815 | * Add variable CPU clock for MPC859/866 systems (so far only TQM866M): | 3818 | * Add variable CPU clock for MPC859/866 systems (so far only TQM866M): |
3816 | see doc/README.MPC866 for details; | 3819 | see doc/README.MPC866 for details; |
3817 | implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; | 3820 | implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; |
3818 | calculate CPU clock frequency from PLL register values. | 3821 | calculate CPU clock frequency from PLL register values. |
3819 | 3822 | ||
3820 | * Add support for 128 MB RAM on TQM8xxL/M modules | 3823 | * Add support for 128 MB RAM on TQM8xxL/M modules |
3821 | 3824 | ||
3822 | * Fix PS/2 keyboard problem caused by statically initialized variable | 3825 | * Fix PS/2 keyboard problem caused by statically initialized variable |
3823 | pointing to a location in flash | 3826 | pointing to a location in flash |
3824 | 3827 | ||
3825 | * Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130. | 3828 | * Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130. |
3826 | 3829 | ||
3827 | * The PS/2 mux on the BMS2003 board needs 450 ms after power on | 3830 | * The PS/2 mux on the BMS2003 board needs 450 ms after power on |
3828 | before we can access it; add delay in case we are faster (with no | 3831 | before we can access it; add delay in case we are faster (with no |
3829 | CF card inserted) | 3832 | CF card inserted) |
3830 | 3833 | ||
3831 | * Cleanup of some init functions | 3834 | * Cleanup of some init functions |
3832 | 3835 | ||
3833 | * Make sure SCC Ethernet is always stopped by the time we boot Linux | 3836 | * Make sure SCC Ethernet is always stopped by the time we boot Linux |
3834 | to avoid Linux crashes by early packets coming in. | 3837 | to avoid Linux crashes by early packets coming in. |
3835 | 3838 | ||
3836 | * Accelerate flash accesses on LWMON board by using buffered writes | 3839 | * Accelerate flash accesses on LWMON board by using buffered writes |
3837 | 3840 | ||
3838 | * Fix typo in Makefile; | 3841 | * Fix typo in Makefile; |
3839 | fix problem with PARTNUM detection | 3842 | fix problem with PARTNUM detection |
3840 | 3843 | ||
3841 | * Patch by Reinhard Meyer, 09 Jan 2004: | 3844 | * Patch by Reinhard Meyer, 09 Jan 2004: |
3842 | - add RTC support for MPC5200 based boards (requires RTC_XTAL) | 3845 | - add RTC support for MPC5200 based boards (requires RTC_XTAL) |
3843 | 3846 | ||
3844 | * Add support for IDE LED on BMS2003 board | 3847 | * Add support for IDE LED on BMS2003 board |
3845 | (exclusive with status LED!) | 3848 | (exclusive with status LED!) |
3846 | 3849 | ||
3847 | * Add support for PS/2 keyboard (used with PS/2 multiplexor on | 3850 | * Add support for PS/2 keyboard (used with PS/2 multiplexor on |
3848 | BMS2003 board) | 3851 | BMS2003 board) |
3849 | 3852 | ||
3850 | * Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004: | 3853 | * Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004: |
3851 | Add common files for "emk" boards | 3854 | Add common files for "emk" boards |
3852 | 3855 | ||
3853 | * Add a common get_ram_size() function and modify the the | 3856 | * Add a common get_ram_size() function and modify the the |
3854 | board-specific files to invoke that common implementation. | 3857 | board-specific files to invoke that common implementation. |
3855 | 3858 | ||
3856 | ====================================================================== | 3859 | ====================================================================== |
3857 | Changes for U-Boot 1.0.1: | 3860 | Changes for U-Boot 1.0.1: |
3858 | ====================================================================== | 3861 | ====================================================================== |
3859 | 3862 | ||
3860 | * Set default clock for INCA-IP to 150 MHz | 3863 | * Set default clock for INCA-IP to 150 MHz |
3861 | 3864 | ||
3862 | * Make BMS2003 use a separate config file to avoid #ifdef mess; | 3865 | * Make BMS2003 use a separate config file to avoid #ifdef mess; |
3863 | add I2C support; add support for DS1337 RTC | 3866 | add I2C support; add support for DS1337 RTC |
3864 | 3867 | ||
3865 | * Add CompactFlash support for BMS2003 board | 3868 | * Add CompactFlash support for BMS2003 board |
3866 | 3869 | ||
3867 | * Add support for status LED on BMS2003 board | 3870 | * Add support for status LED on BMS2003 board |
3868 | 3871 | ||
3869 | * Patch by Scott McNutt, 02 Jan 2004: | 3872 | * Patch by Scott McNutt, 02 Jan 2004: |
3870 | Add support for the Nios Active Serial Memory Interface (ASMI) | 3873 | Add support for the Nios Active Serial Memory Interface (ASMI) |
3871 | on Cyclone devices | 3874 | on Cyclone devices |
3872 | 3875 | ||
3873 | * Patch by Andrea Marson, 16 Dec 2003: | 3876 | * Patch by Andrea Marson, 16 Dec 2003: |
3874 | Add support for the PPChameleon ME and HI modules | 3877 | Add support for the PPChameleon ME and HI modules |
3875 | 3878 | ||
3876 | * Patch by Yuli Barcohen, 22 Dec 2003: | 3879 | * Patch by Yuli Barcohen, 22 Dec 2003: |
3877 | Add support for Motorola DUET ADS board (MPC87x/88x) | 3880 | Add support for Motorola DUET ADS board (MPC87x/88x) |
3878 | 3881 | ||
3879 | * Patch by Robert Schwebel, 15 Dec 2003: | 3882 | * Patch by Robert Schwebel, 15 Dec 2003: |
3880 | add support for cramfs (uses JFFS2 command interface) | 3883 | add support for cramfs (uses JFFS2 command interface) |
3881 | 3884 | ||
3882 | * Patches by Stephan Linz, 11 Dec 2003: | 3885 | * Patches by Stephan Linz, 11 Dec 2003: |
3883 | - more documentation for NIOS port | 3886 | - more documentation for NIOS port |
3884 | - new struct nios_pio_t, struct nios_spi_t | 3887 | - new struct nios_pio_t, struct nios_spi_t |
3885 | - Reconfiguration for NIOS Development Kit DK1C20: | 3888 | - Reconfiguration for NIOS Development Kit DK1C20: |
3886 | o move board related code from board/dk1c20 | 3889 | o move board related code from board/dk1c20 |
3887 | to board/altera/dk1c20 | 3890 | to board/altera/dk1c20 |
3888 | o create a new common source path board/altera/common | 3891 | o create a new common source path board/altera/common |
3889 | and move generic flash access stuff into it | 3892 | and move generic flash access stuff into it |
3890 | o change/expand configuration file DK1C20.h | 3893 | o change/expand configuration file DK1C20.h |
3891 | - Add support for NIOS Development Kit DK1S10 | 3894 | - Add support for NIOS Development Kit DK1S10 |
3892 | - Add status LED support for NIOS systems | 3895 | - Add status LED support for NIOS systems |
3893 | - Add dual 7-segment LED support for Altera NIOS DevKits | 3896 | - Add dual 7-segment LED support for Altera NIOS DevKits |
3894 | 3897 | ||
3895 | * Patch by Ronen Shitrit, 10 Dec 2003: | 3898 | * Patch by Ronen Shitrit, 10 Dec 2003: |
3896 | Add support for the Marvell DB64360 / DB64460 development boards | 3899 | Add support for the Marvell DB64360 / DB64460 development boards |
3897 | 3900 | ||
3898 | * Patch by Detlev Zundel, 10 Dec 2003: | 3901 | * Patch by Detlev Zundel, 10 Dec 2003: |
3899 | fix dependency problem in examples/Makefile | 3902 | fix dependency problem in examples/Makefile |
3900 | 3903 | ||
3901 | * Patch by Denis Peter, 8 Dec 2003 | 3904 | * Patch by Denis Peter, 8 Dec 2003 |
3902 | - add support for the PATI board (MPC555) | 3905 | - add support for the PATI board (MPC555) |
3903 | - add SPI support for the MPC5xx | 3906 | - add SPI support for the MPC5xx |
3904 | 3907 | ||
3905 | * Patch by Anders Larsen, 08 Dec 2003: | 3908 | * Patch by Anders Larsen, 08 Dec 2003: |
3906 | add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG | 3909 | add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG |
3907 | to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; | 3910 | to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; |
3908 | cleanup some redundand #defines | 3911 | cleanup some redundand #defines |
3909 | 3912 | ||
3910 | * Patch by Andrรฉ Schwarz, 8 Dec 2003: | 3913 | * Patch by Andrรฉ Schwarz, 8 Dec 2003: |
3911 | fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): | 3914 | fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): |
3912 | - TX and RX deskriptors must be quad-word aligned | 3915 | - TX and RX deskriptors must be quad-word aligned |
3913 | - does not work with only one TX deskriptor | 3916 | - does not work with only one TX deskriptor |
3914 | - standard reset method does not work | 3917 | - standard reset method does not work |
3915 | 3918 | ||
3916 | * Patch by Masami Komiya, 08 Dec 2003: | 3919 | * Patch by Masami Komiya, 08 Dec 2003: |
3917 | add RTL8139 ethernet driver | 3920 | add RTL8139 ethernet driver |
3918 | 3921 | ||
3919 | * Patches by Ed Okerson, 07 Dec 2003: | 3922 | * Patches by Ed Okerson, 07 Dec 2003: |
3920 | - fix ethernet for the AU1x00 processors in little-endian mode. | 3923 | - fix ethernet for the AU1x00 processors in little-endian mode. |
3921 | - extend memsetup.S for the AU1x00 processors in BE and LE modes | 3924 | - extend memsetup.S for the AU1x00 processors in BE and LE modes |
3922 | 3925 | ||
3923 | * Minor code cleanup (coding style) | 3926 | * Minor code cleanup (coding style) |
3924 | 3927 | ||
3925 | * Patch by Reinhard Meyer, 30 Dec 2003: | 3928 | * Patch by Reinhard Meyer, 30 Dec 2003: |
3926 | - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE, | 3929 | - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE, |
3927 | - added CONFIG_PHY_ADDR to include/configs/IceCube.h, | 3930 | - added CONFIG_PHY_ADDR to include/configs/IceCube.h, |
3928 | - turned debug print of PHY registers into a function (called in two places) | 3931 | - turned debug print of PHY registers into a function (called in two places) |
3929 | - added support for EMK MPC5200 based modules | 3932 | - added support for EMK MPC5200 based modules |
3930 | 3933 | ||
3931 | * Fix MPC8xx PLPRCR_MFD_SHIFT typo | 3934 | * Fix MPC8xx PLPRCR_MFD_SHIFT typo |
3932 | 3935 | ||
3933 | * Add support for TQM866M modules | 3936 | * Add support for TQM866M modules |
3934 | 3937 | ||
3935 | * Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash) | 3938 | * Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash) |
3936 | 3939 | ||
3937 | * Fix a few compiler warnings | 3940 | * Fix a few compiler warnings |
3938 | 3941 | ||
3939 | * Patch by Reinhard Meyer, 28 Dec 2003: | 3942 | * Patch by Reinhard Meyer, 28 Dec 2003: |
3940 | Add initial support for TOP5200 board | 3943 | Add initial support for TOP5200 board |
3941 | 3944 | ||
3942 | * Make CPU clock on ICA-IP board controllable by a "cpuclk" | 3945 | * Make CPU clock on ICA-IP board controllable by a "cpuclk" |
3943 | environment variable which can set to "100", "133", or "150". The | 3946 | environment variable which can set to "100", "133", or "150". The |
3944 | CPU clock will be configured accordingly upon next reboot. Other | 3947 | CPU clock will be configured accordingly upon next reboot. Other |
3945 | values are ignored. In case of an invalid or undefined "cpuclk" | 3948 | values are ignored. In case of an invalid or undefined "cpuclk" |
3946 | value, the compile-time default CPU clock speed will be used. | 3949 | value, the compile-time default CPU clock speed will be used. |
3947 | 3950 | ||
3948 | * Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory | 3951 | * Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory |
3949 | window that is used to access the UART registers by the Linux driver) | 3952 | window that is used to access the UART registers by the Linux driver) |
3950 | 3953 | ||
3951 | * Patch by Reinhard Meyer, 20 Dec 2003: | 3954 | * Patch by Reinhard Meyer, 20 Dec 2003: |
3952 | Fix clock calculation for the MPC5200 for higher clock frequencies | 3955 | Fix clock calculation for the MPC5200 for higher clock frequencies |
3953 | (above 2**32 / 10 = 429.5 MHz). | 3956 | (above 2**32 / 10 = 429.5 MHz). |
3954 | 3957 | ||
3955 | * Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration | 3958 | * Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration |
3956 | 3959 | ||
3957 | * Fix IceCube CLKIN configuration (it's 33.000000MHz) | 3960 | * Fix IceCube CLKIN configuration (it's 33.000000MHz) |
3958 | 3961 | ||
3959 | * Add new configuration for IceCube board with DDR memory | 3962 | * Add new configuration for IceCube board with DDR memory |
3960 | 3963 | ||
3961 | * Update TRAB memory configurations | 3964 | * Update TRAB memory configurations |
3962 | 3965 | ||
3963 | * Add JFFS2 support for INCA-IP board | 3966 | * Add JFFS2 support for INCA-IP board |
3964 | 3967 | ||
3965 | * Patch by Bill Hargen, 09 Dec 2003: | 3968 | * Patch by Bill Hargen, 09 Dec 2003: |
3966 | - BUBINGA405EP: changed flash driver to protect top sector containing | 3969 | - BUBINGA405EP: changed flash driver to protect top sector containing |
3967 | first instruction. | 3970 | first instruction. |
3968 | - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM. | 3971 | - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM. |
3969 | - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access). | 3972 | - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access). |
3970 | - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1). | 3973 | - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1). |
3971 | - 405EP: added/fixed support for "reginfo" command. | 3974 | - 405EP: added/fixed support for "reginfo" command. |
3972 | - 4xx: removed spurious MII error messages on "mii info" command. | 3975 | - 4xx: removed spurious MII error messages on "mii info" command. |
3973 | 3976 | ||
3974 | * Patch by Bernhard Kuhn, 28 Nov 2003: | 3977 | * Patch by Bernhard Kuhn, 28 Nov 2003: |
3975 | add support for ColdFire CPU | 3978 | add support for ColdFire CPU |
3976 | add support for Motorola M5272C3 and M5282EVB boards | 3979 | add support for Motorola M5272C3 and M5282EVB boards |
3977 | 3980 | ||
3978 | * Patch by Pierre Aubert, 24 Nov 2003: | 3981 | * Patch by Pierre Aubert, 24 Nov 2003: |
3979 | - add a return value for the fpga command | 3982 | - add a return value for the fpga command |
3980 | - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT | 3983 | - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT |
3981 | is defined. If ide_preinit fails, ide_init is aborted. | 3984 | is defined. If ide_preinit fails, ide_init is aborted. |
3982 | - fix an endianess problem in fat.h | 3985 | - fix an endianess problem in fat.h |
3983 | 3986 | ||
3984 | * Patch by Wolter Kamphuis, 05 Dec 2003: | 3987 | * Patch by Wolter Kamphuis, 05 Dec 2003: |
3985 | Add support for SNMC's QS850/QS823/QS860T boards | 3988 | Add support for SNMC's QS850/QS823/QS860T boards |
3986 | 3989 | ||
3987 | * Patch by Yuli Barcohen, 3 Dec 2003: | 3990 | * Patch by Yuli Barcohen, 3 Dec 2003: |
3988 | "revive" U-Boot support for old Motorola MPC860ADS board | 3991 | "revive" U-Boot support for old Motorola MPC860ADS board |
3989 | 3992 | ||
3990 | * Patch by Cam(ilo?), 03 Dec 2003: | 3993 | * Patch by Cam(ilo?), 03 Dec 2003: |
3991 | make examples build even with broken Montavista objcopy | 3994 | make examples build even with broken Montavista objcopy |
3992 | 3995 | ||
3993 | * Patch by Pavel Bartusek, 27 Nov 2003: | 3996 | * Patch by Pavel Bartusek, 27 Nov 2003: |
3994 | fix conversion problem with "bootretry" evironment variable | 3997 | fix conversion problem with "bootretry" evironment variable |
3995 | 3998 | ||
3996 | * Patch by Andre Schwarz, 24 Nov 2003: | 3999 | * Patch by Andre Schwarz, 24 Nov 2003: |
3997 | add support for mvblue (mvBlueLYNX and mvBlueBOX) boards | 4000 | add support for mvblue (mvBlueLYNX and mvBlueBOX) boards |
3998 | 4001 | ||
3999 | * Patch by Pavel Bartusek, 21 Nov 2003: | 4002 | * Patch by Pavel Bartusek, 21 Nov 2003: |
4000 | set ZMII bridge speed on 440 | 4003 | set ZMII bridge speed on 440 |
4001 | 4004 | ||
4002 | * Patch by Anders Larsen, 17 Nov 2003: | 4005 | * Patch by Anders Larsen, 17 Nov 2003: |
4003 | Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h | 4006 | Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h |
4004 | 4007 | ||
4005 | * Patches by David Mรผller, 14 Nov 2003: | 4008 | * Patches by David Mรผller, 14 Nov 2003: |
4006 | - board/mpl/common/common_util.c | 4009 | - board/mpl/common/common_util.c |
4007 | * implement support for BZIP2 compressed images | 4010 | * implement support for BZIP2 compressed images |
4008 | * various cleanups (printf -> puts, ...) | 4011 | * various cleanups (printf -> puts, ...) |
4009 | - board/mpl/common/flash.c | 4012 | - board/mpl/common/flash.c |
4010 | * report correct errors to upper layers | 4013 | * report correct errors to upper layers |
4011 | * check the erase fail and VPP low bits in status reg | 4014 | * check the erase fail and VPP low bits in status reg |
4012 | - board/mpl/vcma9/cmd_vcma9.c | 4015 | - board/mpl/vcma9/cmd_vcma9.c |
4013 | - board/mpl/vcma9/flash.c | 4016 | - board/mpl/vcma9/flash.c |
4014 | * various cleanups (printf -> puts, ...) | 4017 | * various cleanups (printf -> puts, ...) |
4015 | - common/cmd_usb.c | 4018 | - common/cmd_usb.c |
4016 | * fix typo in comment | 4019 | * fix typo in comment |
4017 | - cpu/arm920t/usb_ohci.c | 4020 | - cpu/arm920t/usb_ohci.c |
4018 | * support for S3C2410 is missing in #if line | 4021 | * support for S3C2410 is missing in #if line |
4019 | - drivers/cs8900.c | 4022 | - drivers/cs8900.c |
4020 | * reinit some registers in case of error (cable missing, ...) | 4023 | * reinit some registers in case of error (cable missing, ...) |
4021 | - fs/fat/fat.c | 4024 | - fs/fat/fat.c |
4022 | * support for USB/MMC devices is missing in #if line | 4025 | * support for USB/MMC devices is missing in #if line |
4023 | - include/configs/MIP405.h | 4026 | - include/configs/MIP405.h |
4024 | - include/configs/PIP405.h | 4027 | - include/configs/PIP405.h |
4025 | * enable BZIP2 support | 4028 | * enable BZIP2 support |
4026 | * enlarge malloc space to 1MiB because of BZIP2 support | 4029 | * enlarge malloc space to 1MiB because of BZIP2 support |
4027 | - include/configs/VCMA9.h | 4030 | - include/configs/VCMA9.h |
4028 | * enable BZIP2 support | 4031 | * enable BZIP2 support |
4029 | * enlarge malloc space to 1MiB because of BZIP2 support | 4032 | * enlarge malloc space to 1MiB because of BZIP2 support |
4030 | * enable USB support | 4033 | * enable USB support |
4031 | - lib_arm/armlinux.c | 4034 | - lib_arm/armlinux.c |
4032 | * change calling convention of ARM Linux kernel as | 4035 | * change calling convention of ARM Linux kernel as |
4033 | described on http://www.arm.linux.org.uk/developer/booting.php | 4036 | described on http://www.arm.linux.org.uk/developer/booting.php |
4034 | 4037 | ||
4035 | * Patch by Thomas Lange, 14 Nov 2003: | 4038 | * Patch by Thomas Lange, 14 Nov 2003: |
4036 | Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to | 4039 | Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to |
4037 | support all these AMD boards. | 4040 | support all these AMD boards. |
4038 | 4041 | ||
4039 | * Patch by Thomas Lange, 14 Nov 2003: | 4042 | * Patch by Thomas Lange, 14 Nov 2003: |
4040 | Workaround for mips au1x00 physical memory accesses (the au1x00 | 4043 | Workaround for mips au1x00 physical memory accesses (the au1x00 |
4041 | uses a 36 bit bus internally and cannot access physical memory | 4044 | uses a 36 bit bus internally and cannot access physical memory |
4042 | directly. Use the uncached SDRAM address instead of the physical | 4045 | directly. Use the uncached SDRAM address instead of the physical |
4043 | one.) | 4046 | one.) |
4044 | 4047 | ||
4045 | * Patch by Xue Ligong (Joe), 13 Nov 2003: | 4048 | * Patch by Xue Ligong (Joe), 13 Nov 2003: |
4046 | add Realtek 8019 ethernet driver | 4049 | add Realtek 8019 ethernet driver |
4047 | 4050 | ||
4048 | * Patch by Yuli Barcohen, 13 Nov 2003: | 4051 | * Patch by Yuli Barcohen, 13 Nov 2003: |
4049 | MPC826xADS/PQ2FADS cleanup | 4052 | MPC826xADS/PQ2FADS cleanup |
4050 | 4053 | ||
4051 | * Patch by Anders Larsen, 12 Nov 2003: | 4054 | * Patch by Anders Larsen, 12 Nov 2003: |
4052 | Update README to mark the PORTIO commands non-standard | 4055 | Update README to mark the PORTIO commands non-standard |
4053 | 4056 | ||
4054 | * Patch by Nicolas Lacressonniรจre, 12 Nov 2003: | 4057 | * Patch by Nicolas Lacressonniรจre, 12 Nov 2003: |
4055 | update for for Atmel AT91RM9200DK development kit: | 4058 | update for for Atmel AT91RM9200DK development kit: |
4056 | - support for environment variables in DataFlash | 4059 | - support for environment variables in DataFlash |
4057 | - Atmel DataFlash AT45DB1282 support | 4060 | - Atmel DataFlash AT45DB1282 support |
4058 | 4061 | ||
4059 | * Patch by Jeff Carr, 11 Nov 2003: | 4062 | * Patch by Jeff Carr, 11 Nov 2003: |
4060 | add support for new version of 8270 processors | 4063 | add support for new version of 8270 processors |
4061 | 4064 | ||
4062 | * Patches by George G. Davis, 05 Nov 2003: | 4065 | * Patches by George G. Davis, 05 Nov 2003: |
4063 | - only pass the ARM linux initrd tag to the kernel when an initrd | 4066 | - only pass the ARM linux initrd tag to the kernel when an initrd |
4064 | is actually present | 4067 | is actually present |
4065 | - update omap1510inn configuration file | 4068 | - update omap1510inn configuration file |
4066 | 4069 | ||
4067 | * Patches by Stephan Linz, 3 Nov 2003: | 4070 | * Patches by Stephan Linz, 3 Nov 2003: |
4068 | - more endianess fixes for LAN91C111 driver | 4071 | - more endianess fixes for LAN91C111 driver |
4069 | - CFG_HZ configuration patch for NIOS Cyclone board | 4072 | - CFG_HZ configuration patch for NIOS Cyclone board |
4070 | 4073 | ||
4071 | * Patch by Stephan Linz, 28 Oct 2003: | 4074 | * Patch by Stephan Linz, 28 Oct 2003: |
4072 | fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c | 4075 | fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c |
4073 | 4076 | ||
4074 | * Patch by Steven Scholz, 20 Oct 2003: | 4077 | * Patch by Steven Scholz, 20 Oct 2003: |
4075 | - make "mii info <addr>" show infor for PHY at "addr" only | 4078 | - make "mii info <addr>" show infor for PHY at "addr" only |
4076 | - Endian fix for miiphy_info() | 4079 | - Endian fix for miiphy_info() |
4077 | 4080 | ||
4078 | * Patch by Gleb Natapov, 19 Sep 2003: | 4081 | * Patch by Gleb Natapov, 19 Sep 2003: |
4079 | Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c | 4082 | Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c |
4080 | 4083 | ||
4081 | * Patch by Anders Larsen, 17 Sep 2003: | 4084 | * Patch by Anders Larsen, 17 Sep 2003: |
4082 | Bring ARM memory layout in sync with the documentation: | 4085 | Bring ARM memory layout in sync with the documentation: |
4083 | stack and malloc-heap are now located _below_ the U-Boot code | 4086 | stack and malloc-heap are now located _below_ the U-Boot code |
4084 | 4087 | ||
4085 | * Accelerate booting on TRAB board: read and check autoupdate image | 4088 | * Accelerate booting on TRAB board: read and check autoupdate image |
4086 | headers first instead of always reading the whole images. | 4089 | headers first instead of always reading the whole images. |
4087 | 4090 | ||
4088 | * Fix type in MPC5XXX code (pointed out by Victor Wren) | 4091 | * Fix type in MPC5XXX code (pointed out by Victor Wren) |
4089 | 4092 | ||
4090 | * Enabled password check on RMU board | 4093 | * Enabled password check on RMU board |
4091 | 4094 | ||
4092 | * Fix configuration problem with IceCube in LOWBOOT configuration: | 4095 | * Fix configuration problem with IceCube in LOWBOOT configuration: |
4093 | envrionment got embedded, corrupting the image layout. | 4096 | envrionment got embedded, corrupting the image layout. |
4094 | 4097 | ||
4095 | * Fix NEC display names (it's 6440 [for 640x480], not 6640). | 4098 | * Fix NEC display names (it's 6440 [for 640x480], not 6640). |
4096 | 4099 | ||
4097 | * Added BMS2003 board | 4100 | * Added BMS2003 board |
4098 | add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display | 4101 | add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display |
4099 | 4102 | ||
4100 | * Fix flash driver for TRAB board (must use Unlock Bypass Reset | 4103 | * Fix flash driver for TRAB board (must use Unlock Bypass Reset |
4101 | command to exit Unlock Bypass Mode); adjust timings for flash, SRAM | 4104 | command to exit Unlock Bypass Mode); adjust timings for flash, SRAM |
4102 | and CPLD | 4105 | and CPLD |
4103 | 4106 | ||
4104 | * Use "-fPIC" instead of "-mrelocatable" to prevent problems with | 4107 | * Use "-fPIC" instead of "-mrelocatable" to prevent problems with |
4105 | recent tools | 4108 | recent tools |
4106 | 4109 | ||
4107 | * Add checksum verification to 'imls' command | 4110 | * Add checksum verification to 'imls' command |
4108 | 4111 | ||
4109 | * Add bd_info fields needed for 4xx Linux I2C driver | 4112 | * Add bd_info fields needed for 4xx Linux I2C driver |
4110 | 4113 | ||
4111 | * Patch by Martin Krause, 4 Nov. 2003: | 4114 | * Patch by Martin Krause, 4 Nov. 2003: |
4112 | Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) | 4115 | Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) |
4113 | 4116 | ||
4114 | * Print used network interface when CONFIG_NET_MULTI is set | 4117 | * Print used network interface when CONFIG_NET_MULTI is set |
4115 | 4118 | ||
4116 | * Patch by Bernhard Kuhn, 28 Oct 2003: | 4119 | * Patch by Bernhard Kuhn, 28 Oct 2003: |
4117 | Add low boot support for MPC5200 | 4120 | Add low boot support for MPC5200 |
4118 | 4121 | ||
4119 | * Fix problem with dual PCMCIA support (NSCU) | 4122 | * Fix problem with dual PCMCIA support (NSCU) |
4120 | 4123 | ||
4121 | * Fix MPC5200 I2C initialization function | 4124 | * Fix MPC5200 I2C initialization function |
4122 | 4125 | ||
4123 | ====================================================================== | 4126 | ====================================================================== |
4124 | Changes for U-Boot 1.0.0: | 4127 | Changes for U-Boot 1.0.0: |
4125 | ====================================================================== | 4128 | ====================================================================== |
4126 | 4129 | ||
4127 | * Fix parameter passing to standalone images with bootm command | 4130 | * Fix parameter passing to standalone images with bootm command |
4128 | 4131 | ||
4129 | * Patch by Kyle Harris, 30 Oct 2003: | 4132 | * Patch by Kyle Harris, 30 Oct 2003: |
4130 | Fix build errors for ixdp425 board | 4133 | Fix build errors for ixdp425 board |
4131 | 4134 | ||
4132 | * Patch by David M. Horn, 29 Oct 2003: | 4135 | * Patch by David M. Horn, 29 Oct 2003: |
4133 | Fixes to build under CYGWIN | 4136 | Fixes to build under CYGWIN |
4134 | 4137 | ||
4135 | * Get IceCube MGT5100 working (again) | 4138 | * Get IceCube MGT5100 working (again) |
4136 | 4139 | ||
4137 | * Fix problems in memory test on some boards (which was not | 4140 | * Fix problems in memory test on some boards (which was not |
4138 | non-destructive as intended) | 4141 | non-destructive as intended) |
4139 | 4142 | ||
4140 | * Patch by Gary Jennejohn, 28 Oct 2003: | 4143 | * Patch by Gary Jennejohn, 28 Oct 2003: |
4141 | Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack | 4144 | Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack |
4142 | to prevent stack overflow on ARM systems | 4145 | to prevent stack overflow on ARM systems |
4143 | 4146 | ||
4144 | * Patch by Stephan Linz, 28 Oct 2003: | 4147 | * Patch by Stephan Linz, 28 Oct 2003: |
4145 | fix init sequence error for NIOS port | 4148 | fix init sequence error for NIOS port |
4146 | 4149 | ||
4147 | * Allow lowercase spelling for IceCube_5200; support MPC5200LITE name | 4150 | * Allow lowercase spelling for IceCube_5200; support MPC5200LITE name |
4148 | 4151 | ||
4149 | * Add CONFIG_VERSION_VARIABLE to TRAB configuration | 4152 | * Add CONFIG_VERSION_VARIABLE to TRAB configuration |
4150 | 4153 | ||
4151 | * Patch by Xiao Xianghua, 23 Oct 2003: | 4154 | * Patch by Xiao Xianghua, 23 Oct 2003: |
4152 | small patch for mpc85xx | 4155 | small patch for mpc85xx |
4153 | 4156 | ||
4154 | * Fix small problem in MPC5200 I2C driver | 4157 | * Fix small problem in MPC5200 I2C driver |
4155 | 4158 | ||
4156 | * Fix FCC3 support on ATC board | 4159 | * Fix FCC3 support on ATC board |
4157 | 4160 | ||
4158 | * Correct header printing for multi-image files in do_bootm() | 4161 | * Correct header printing for multi-image files in do_bootm() |
4159 | 4162 | ||
4160 | * Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED | 4163 | * Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED |
4161 | 4164 | ||
4162 | * Fix PCI problems on PPChameleon board | 4165 | * Fix PCI problems on PPChameleon board |
4163 | 4166 | ||
4164 | * Patch by Steven Scholz, 18 Oct 2003: | 4167 | * Patch by Steven Scholz, 18 Oct 2003: |
4165 | Fix AT91RM9200 ethernet driver | 4168 | Fix AT91RM9200 ethernet driver |
4166 | 4169 | ||
4167 | * Patch by Nye Liu, 17 Oct 2003: | 4170 | * Patch by Nye Liu, 17 Oct 2003: |
4168 | Fix typo in include/mpc8xx.h | 4171 | Fix typo in include/mpc8xx.h |
4169 | 4172 | ||
4170 | * Patch by Richard Woodruff, 16 Oct 03: | 4173 | * Patch by Richard Woodruff, 16 Oct 03: |
4171 | Fixes for cpu/arm925/interrupt.c | 4174 | Fixes for cpu/arm925/interrupt.c |
4172 | - Initialize timestamp & lastdec vars. | 4175 | - Initialize timestamp & lastdec vars. |
4173 | - fix timestamp overflows. | 4176 | - fix timestamp overflows. |
4174 | - fix lastdec overflow. | 4177 | - fix lastdec overflow. |
4175 | - smarter normalization to allow udelay() below 1ms to work. | 4178 | - smarter normalization to allow udelay() below 1ms to work. |
4176 | 4179 | ||
4177 | * Patch by Scott McNutt, 16 Oct | 4180 | * Patch by Scott McNutt, 16 Oct |
4178 | add networking support for the Altera Nios Development Kit, | 4181 | add networking support for the Altera Nios Development Kit, |
4179 | Cyclone Edition (DK-1C20) | 4182 | Cyclone Edition (DK-1C20) |
4180 | 4183 | ||
4181 | * Patch by Jon Diekema, 14 Oct 2003: | 4184 | * Patch by Jon Diekema, 14 Oct 2003: |
4182 | add hint about doc/README.silent to README file | 4185 | add hint about doc/README.silent to README file |
4183 | 4186 | ||
4184 | * Add CompactFlash support for NSCU | 4187 | * Add CompactFlash support for NSCU |
4185 | 4188 | ||
4186 | * Fix PCI problems on PPChameleonEVB | 4189 | * Fix PCI problems on PPChameleonEVB |
4187 | 4190 | ||
4188 | * TRAB auto-update: Base decision if we have to strip the image | 4191 | * TRAB auto-update: Base decision if we have to strip the image |
4189 | header on image type as encoded in the header | 4192 | header on image type as encoded in the header |
4190 | (include image type patch by Martin Krause, 17 Oct 2003) | 4193 | (include image type patch by Martin Krause, 17 Oct 2003) |
4191 | 4194 | ||
4192 | * Patches by Xianghua Xiao, 15 Oct 2003: | 4195 | * Patches by Xianghua Xiao, 15 Oct 2003: |
4193 | 4196 | ||
4194 | - Added Motorola CPU 8540/8560 support (cpu/85xx) | 4197 | - Added Motorola CPU 8540/8560 support (cpu/85xx) |
4195 | - Added Motorola MPC8540ADS board support (board/mpc8540ads) | 4198 | - Added Motorola MPC8540ADS board support (board/mpc8540ads) |
4196 | - Added Motorola MPC8560ADS board support (board/mpc8560ads) | 4199 | - Added Motorola MPC8560ADS board support (board/mpc8560ads) |
4197 | 4200 | ||
4198 | * Fix flash timings on TRAB board | 4201 | * Fix flash timings on TRAB board |
4199 | 4202 | ||
4200 | * Make sure HUSH is initialized for running auto-update scripts | 4203 | * Make sure HUSH is initialized for running auto-update scripts |
4201 | 4204 | ||
4202 | * Make 5200 reset command _really_ reset the board, without running | 4205 | * Make 5200 reset command _really_ reset the board, without running |
4203 | any other code after it | 4206 | any other code after it |
4204 | 4207 | ||
4205 | * Fix errors with flash erase when range spans across banks | 4208 | * Fix errors with flash erase when range spans across banks |
4206 | that are mapped in reverse order | 4209 | that are mapped in reverse order |
4207 | 4210 | ||
4208 | * Fix flash mapping and display on P3G4 board | 4211 | * Fix flash mapping and display on P3G4 board |
4209 | 4212 | ||
4210 | * Patch by Kyle Harris, 15 Jul 2003: | 4213 | * Patch by Kyle Harris, 15 Jul 2003: |
4211 | - add support for Intel IXP425 CPU | 4214 | - add support for Intel IXP425 CPU |
4212 | - add support for IXDP425 eval board | 4215 | - add support for IXDP425 eval board |
4213 | 4216 | ||
4214 | * Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent | 4217 | * Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent |
4215 | for more information | 4218 | for more information |
4216 | 4219 | ||
4217 | * Patch by Steven Scholz, 10 Oct 2003 | 4220 | * Patch by Steven Scholz, 10 Oct 2003 |
4218 | - Add support for Altera FPGA ACEX1K | 4221 | - Add support for Altera FPGA ACEX1K |
4219 | 4222 | ||
4220 | * Patches by Thomas Lange, 09 Oct 2003: | 4223 | * Patches by Thomas Lange, 09 Oct 2003: |
4221 | - fix cmd_ide.c for non ppc boards (read/write functions did not | 4224 | - fix cmd_ide.c for non ppc boards (read/write functions did not |
4222 | add ATA base address) | 4225 | add ATA base address) |
4223 | - fix for shannon board | 4226 | - fix for shannon board |
4224 | - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code | 4227 | - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code |
4225 | - Endian swap ATA identity for all big endian CPUs, not just PPC | 4228 | - Endian swap ATA identity for all big endian CPUs, not just PPC |
4226 | - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize | 4229 | - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize |
4227 | args to linux | 4230 | args to linux |
4228 | - add support for dbau1x00 board (MIPS32) | 4231 | - add support for dbau1x00 board (MIPS32) |
4229 | 4232 | ||
4230 | * Patch by Sangmoon Kim, 07 Oct 2003: | 4233 | * Patch by Sangmoon Kim, 07 Oct 2003: |
4231 | add support for debris board | 4234 | add support for debris board |
4232 | 4235 | ||
4233 | * Patch by Martin Krause, 09 Oct 2003: | 4236 | * Patch by Martin Krause, 09 Oct 2003: |
4234 | Fixes for TRAB board | 4237 | Fixes for TRAB board |
4235 | - /board/trab/rs485.c: correct baudrate | 4238 | - /board/trab/rs485.c: correct baudrate |
4236 | - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in | 4239 | - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in |
4237 | udelay(); fix some timing problems with adc controller | 4240 | udelay(); fix some timing problems with adc controller |
4238 | - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; | 4241 | - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; |
4239 | modify commands: touch and buzzer | 4242 | modify commands: touch and buzzer |
4240 | 4243 | ||
4241 | * Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE | 4244 | * Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE |
4242 | (quick & dirty workaround for rogue pointer problem in get_vfatname()); | 4245 | (quick & dirty workaround for rogue pointer problem in get_vfatname()); |
4243 | Use direct function calls for auto_update instead of hush commands | 4246 | Use direct function calls for auto_update instead of hush commands |
4244 | 4247 | ||
4245 | * Patch by Scott McNutt, 04 Oct 2003: | 4248 | * Patch by Scott McNutt, 04 Oct 2003: |
4246 | - add support for Altera Nios-32 CPU | 4249 | - add support for Altera Nios-32 CPU |
4247 | - add support for Nios Cyclone Development Kit (DK-1C20) | 4250 | - add support for Nios Cyclone Development Kit (DK-1C20) |
4248 | 4251 | ||
4249 | * Patch by Steven Scholz, 29 Sep 2003: | 4252 | * Patch by Steven Scholz, 29 Sep 2003: |
4250 | - A second parameter for bootm overwrites the load address for | 4253 | - A second parameter for bootm overwrites the load address for |
4251 | "Standalone Application" images. | 4254 | "Standalone Application" images. |
4252 | - bootm sets environment variable "filesize" to the resulting | 4255 | - bootm sets environment variable "filesize" to the resulting |
4253 | (uncompressed) data length for "Standalone Application" images | 4256 | (uncompressed) data length for "Standalone Application" images |
4254 | when autostart is set to "no". Now you can do something like | 4257 | when autostart is set to "no". Now you can do something like |
4255 | if bootm $fpgadata $some_free_ram ; then | 4258 | if bootm $fpgadata $some_free_ram ; then |
4256 | fpga load 0 $some_free_ram $filesize | 4259 | fpga load 0 $some_free_ram $filesize |
4257 | fi | 4260 | fi |
4258 | 4261 | ||
4259 | * Patch by Denis Peter, 25 Sept 2003: | 4262 | * Patch by Denis Peter, 25 Sept 2003: |
4260 | add support for the MIP405 Rev. C board | 4263 | add support for the MIP405 Rev. C board |
4261 | 4264 | ||
4262 | * Patch by Yuli Barcohen, 25 Sep 2003: | 4265 | * Patch by Yuli Barcohen, 25 Sep 2003: |
4263 | add support for Zephyr Engineering ZPC.1900 board | 4266 | add support for Zephyr Engineering ZPC.1900 board |
4264 | 4267 | ||
4265 | * Patch by Anders Larsen, 23 Sep 2003: | 4268 | * Patch by Anders Larsen, 23 Sep 2003: |
4266 | add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only | 4269 | add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only |
4267 | implemented for the x86 architecture) | 4270 | implemented for the x86 architecture) |
4268 | 4271 | ||
4269 | * Patch by Sangmoon Kim, 23 Sep 2003: | 4272 | * Patch by Sangmoon Kim, 23 Sep 2003: |
4270 | fix pll_pci_to_mem_multiplier table for MPC8245 | 4273 | fix pll_pci_to_mem_multiplier table for MPC8245 |
4271 | 4274 | ||
4272 | * Patch by Anders Larsen, 22 Sep 2003: | 4275 | * Patch by Anders Larsen, 22 Sep 2003: |
4273 | enable timed autoboot on PXA | 4276 | enable timed autoboot on PXA |
4274 | 4277 | ||
4275 | * Patch by David Mรผller, 22 Sep 2003: | 4278 | * Patch by David Mรผller, 22 Sep 2003: |
4276 | - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver | 4279 | - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver |
4277 | returns correct libgcc file path | 4280 | returns correct libgcc file path |
4278 | - "latency" reduction of busy-loop waiting to improve "U-Boot" boot | 4281 | - "latency" reduction of busy-loop waiting to improve "U-Boot" boot |
4279 | time on s3c24x0 systems | 4282 | time on s3c24x0 systems |
4280 | 4283 | ||
4281 | * Patch by Jon Diekema, 19 Sep 2003: | 4284 | * Patch by Jon Diekema, 19 Sep 2003: |
4282 | - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet | 4285 | - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet |
4283 | link state to the fault LED. | 4286 | link state to the fault LED. |
4284 | - In NetLoop, make the Fault LED reflect the link status. The link | 4287 | - In NetLoop, make the Fault LED reflect the link status. The link |
4285 | status gets updated on entry, and on timeouts. | 4288 | status gets updated on entry, and on timeouts. |
4286 | 4289 | ||
4287 | * Patch by Anders Larsen, 18 Sep 2003: | 4290 | * Patch by Anders Larsen, 18 Sep 2003: |
4288 | allow mkimage to build and run on Cygwin-hosted systems | 4291 | allow mkimage to build and run on Cygwin-hosted systems |
4289 | 4292 | ||
4290 | * Patch by Frank Mรผller, 18 Sep 2003: | 4293 | * Patch by Frank Mรผller, 18 Sep 2003: |
4291 | use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in | 4294 | use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in |
4292 | cpu/mpc8xx/fec.c | 4295 | cpu/mpc8xx/fec.c |
4293 | 4296 | ||
4294 | * Patch by Pantelis Antoniou, 16 Sep 2003: | 4297 | * Patch by Pantelis Antoniou, 16 Sep 2003: |
4295 | add tool to compute fileds in the PLPRCR register for MPC86x | 4298 | add tool to compute fileds in the PLPRCR register for MPC86x |
4296 | 4299 | ||
4297 | * Use IH_TYPE_FILESYSTEM for TRAB "disk" images. | 4300 | * Use IH_TYPE_FILESYSTEM for TRAB "disk" images. |
4298 | 4301 | ||
4299 | * Fix build problems under FreeBSD | 4302 | * Fix build problems under FreeBSD |
4300 | 4303 | ||
4301 | * Add generic filesystem image type | 4304 | * Add generic filesystem image type |
4302 | 4305 | ||
4303 | * Make fatload set filesize environment variable | 4306 | * Make fatload set filesize environment variable |
4304 | 4307 | ||
4305 | * enable basic / medium / high-end configurations for PPChameleonEVB | 4308 | * enable basic / medium / high-end configurations for PPChameleonEVB |
4306 | board; fix NAND code | 4309 | board; fix NAND code |
4307 | 4310 | ||
4308 | * enable TFTP client code to specify to the server the desired | 4311 | * enable TFTP client code to specify to the server the desired |
4309 | timeout value (see RFC-2349) | 4312 | timeout value (see RFC-2349) |
4310 | 4313 | ||
4311 | * Improve SDRAM setup for TRAB board | 4314 | * Improve SDRAM setup for TRAB board |
4312 | 4315 | ||
4313 | * Suppress all output with splashscreen configured only if "splashimage" | 4316 | * Suppress all output with splashscreen configured only if "splashimage" |
4314 | is set | 4317 | is set |
4315 | 4318 | ||
4316 | * Fix problems with I2C support for mpc5200 | 4319 | * Fix problems with I2C support for mpc5200 |
4317 | 4320 | ||
4318 | * Adapt TRAB configuration and auto_update to new memory layout | 4321 | * Adapt TRAB configuration and auto_update to new memory layout |
4319 | 4322 | ||
4320 | * Add configuration for wtk board | 4323 | * Add configuration for wtk board |
4321 | 4324 | ||
4322 | * Add support for the Sharp LQ065T9DR51U LCD display | 4325 | * Add support for the Sharp LQ065T9DR51U LCD display |
4323 | 4326 | ||
4324 | * Patch by Rune Torgersen, 17 Sep 2003: | 4327 | * Patch by Rune Torgersen, 17 Sep 2003: |
4325 | - Fixes for MPC8266 default config | 4328 | - Fixes for MPC8266 default config |
4326 | - Allow eth_loopback_test() on 8260 to use a subset of the FCC's | 4329 | - Allow eth_loopback_test() on 8260 to use a subset of the FCC's |
4327 | 4330 | ||
4328 | * Patches by Jon Diekema, 17 Sep 2003: | 4331 | * Patches by Jon Diekema, 17 Sep 2003: |
4329 | - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and | 4332 | - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and |
4330 | env_common.c) | 4333 | env_common.c) |
4331 | - sbc8260 tweaks | 4334 | - sbc8260 tweaks |
4332 | - adjust "help" output | 4335 | - adjust "help" output |
4333 | 4336 | ||
4334 | * Patches by Anders Larsen, 17 Sep 2003: | 4337 | * Patches by Anders Larsen, 17 Sep 2003: |
4335 | - fix spelling errors | 4338 | - fix spelling errors |
4336 | - set GD_FLG_DEVINIT flag only after device function pointers | 4339 | - set GD_FLG_DEVINIT flag only after device function pointers |
4337 | are valid | 4340 | are valid |
4338 | - Allow CFG_ALT_MEMTEST on systems where address zero isn't | 4341 | - Allow CFG_ALT_MEMTEST on systems where address zero isn't |
4339 | writeable | 4342 | writeable |
4340 | - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs | 4343 | - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs |
4341 | - trigger watchdog while waiting in serial driver | 4344 | - trigger watchdog while waiting in serial driver |
4342 | 4345 | ||
4343 | * Add auto-update code for TRAB board using USB memory sticks, | 4346 | * Add auto-update code for TRAB board using USB memory sticks, |
4344 | support new configuration with more memory | 4347 | support new configuration with more memory |
4345 | 4348 | ||
4346 | * disable MPC5200 bus pipelining as workaround for bus contention | 4349 | * disable MPC5200 bus pipelining as workaround for bus contention |
4347 | 4350 | ||
4348 | * Modify XLB arbiter priorities on MPC5200 so all devices use same | 4351 | * Modify XLB arbiter priorities on MPC5200 so all devices use same |
4349 | priority; configure critical interrupts to be handled like external | 4352 | priority; configure critical interrupts to be handled like external |
4350 | interrupts | 4353 | interrupts |
4351 | 4354 | ||
4352 | * Make IPB clock on MGT5100/MPC5200 configurable in board config file; | 4355 | * Make IPB clock on MGT5100/MPC5200 configurable in board config file; |
4353 | go back to 66 MHz for stability | 4356 | go back to 66 MHz for stability |
4354 | 4357 | ||
4355 | * Patches by Jon Diekema, 15 Sep 2003: | 4358 | * Patches by Jon Diekema, 15 Sep 2003: |
4356 | - add description for missing CFG_CMD_* entries in the README file | 4359 | - add description for missing CFG_CMD_* entries in the README file |
4357 | - sacsng tweaks | 4360 | - sacsng tweaks |
4358 | 4361 | ||
4359 | * Patch by Gleb Natapov, 14 Sep 2003: | 4362 | * Patch by Gleb Natapov, 14 Sep 2003: |
4360 | enable watchdog support for all MPC824x boards that have a watchdog | 4363 | enable watchdog support for all MPC824x boards that have a watchdog |
4361 | 4364 | ||
4362 | * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the | 4365 | * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the |
4363 | "Non-octet Aligned Frame" errors we see at 100 Mbps | 4366 | "Non-octet Aligned Frame" errors we see at 100 Mbps |
4364 | 4367 | ||
4365 | * Patch by Sharad Gupta, 14 Sep 2003: | 4368 | * Patch by Sharad Gupta, 14 Sep 2003: |
4366 | fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL]) | 4369 | fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL]) |
4367 | 4370 | ||
4368 | * Patch by llandre, 11 Sep 2003: | 4371 | * Patch by llandre, 11 Sep 2003: |
4369 | update configuration for PPChameleonEVB board | 4372 | update configuration for PPChameleonEVB board |
4370 | 4373 | ||
4371 | * Patch by David Mรผller, 13 Sep 2003: | 4374 | * Patch by David Mรผller, 13 Sep 2003: |
4372 | various changes to VCMA9 board specific files | 4375 | various changes to VCMA9 board specific files |
4373 | 4376 | ||
4374 | * Add I2C support for MGT5100 / MPC5200 | 4377 | * Add I2C support for MGT5100 / MPC5200 |
4375 | 4378 | ||
4376 | * Patch by Rune Torgersen, 11 Sep 2003: | 4379 | * Patch by Rune Torgersen, 11 Sep 2003: |
4377 | Changed default memory option on MPC8266ADS to NOT be Page Based | 4380 | Changed default memory option on MPC8266ADS to NOT be Page Based |
4378 | Interleave, since this doesn't work very well with the standard | 4381 | Interleave, since this doesn't work very well with the standard |
4379 | 16MB DIMM | 4382 | 16MB DIMM |
4380 | 4383 | ||
4381 | * Patch by George G. Davis, 12 Sep 2003: | 4384 | * Patch by George G. Davis, 12 Sep 2003: |
4382 | fix Makefile settings for sk98 driver | 4385 | fix Makefile settings for sk98 driver |
4383 | 4386 | ||
4384 | * Patch by Stefan Roese, 12 Sep 2003: | 4387 | * Patch by Stefan Roese, 12 Sep 2003: |
4385 | - new boards added: DP405, HUB405, PLU405, VOH405 | 4388 | - new boards added: DP405, HUB405, PLU405, VOH405 |
4386 | - some esd boards updated | 4389 | - some esd boards updated |
4387 | - cpu/ppc4xx/sdram.c: disable memory controller before setting | 4390 | - cpu/ppc4xx/sdram.c: disable memory controller before setting |
4388 | first values | 4391 | first values |
4389 | - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems | 4392 | - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems |
4390 | 4393 | ||
4391 | * Patch by Martin Krause, 11 Sep 2003: | 4394 | * Patch by Martin Krause, 11 Sep 2003: |
4392 | add burn-in tests for TRAB board | 4395 | add burn-in tests for TRAB board |
4393 | 4396 | ||
4394 | * Enable instruction cache on MPC5200 board | 4397 | * Enable instruction cache on MPC5200 board |
4395 | 4398 | ||
4396 | * Patch by Denis Peter, 11 Sep 2003: | 4399 | * Patch by Denis Peter, 11 Sep 2003: |
4397 | - fix USB data pointer assignment for bulk only transfer. | 4400 | - fix USB data pointer assignment for bulk only transfer. |
4398 | - prevent to display erased directories in FAT filesystem. | 4401 | - prevent to display erased directories in FAT filesystem. |
4399 | 4402 | ||
4400 | * Change output format for NAND flash - make it look like for other | 4403 | * Change output format for NAND flash - make it look like for other |
4401 | memory, too | 4404 | memory, too |
4402 | 4405 | ||
4403 | ====================================================================== | 4406 | ====================================================================== |
4404 | Changes for U-Boot 0.4.8: | 4407 | Changes for U-Boot 0.4.8: |
4405 | ====================================================================== | 4408 | ====================================================================== |
4406 | 4409 | ||
4407 | * Add I2C and RTC support for RMU board | 4410 | * Add I2C and RTC support for RMU board |
4408 | 4411 | ||
4409 | * Patches by Denis Peter, 9 Sep 2003: | 4412 | * Patches by Denis Peter, 9 Sep 2003: |
4410 | add FAT support for IDE, SCSI and USB | 4413 | add FAT support for IDE, SCSI and USB |
4411 | 4414 | ||
4412 | * Patches by Gleb Natapov, 2 Sep 2003: | 4415 | * Patches by Gleb Natapov, 2 Sep 2003: |
4413 | - cleanup of POST code for unsupported architectures | 4416 | - cleanup of POST code for unsupported architectures |
4414 | - MPC824x locks way0 of data cache for use as initial RAM; | 4417 | - MPC824x locks way0 of data cache for use as initial RAM; |
4415 | this patch unlocks it after relocation to RAM and invalidates | 4418 | this patch unlocks it after relocation to RAM and invalidates |
4416 | the locked entries. | 4419 | the locked entries. |
4417 | 4420 | ||
4418 | * Patch by Gleb Natapov, 30 Aug 2003: | 4421 | * Patch by Gleb Natapov, 30 Aug 2003: |
4419 | new I2C driver for mpc107 bridge. Now works from flash. | 4422 | new I2C driver for mpc107 bridge. Now works from flash. |
4420 | 4423 | ||
4421 | * Patch by Dave Ellis, 11 Aug 2003: | 4424 | * Patch by Dave Ellis, 11 Aug 2003: |
4422 | - JFFS2: fix typo in common/cmd_jffs2.c | 4425 | - JFFS2: fix typo in common/cmd_jffs2.c |
4423 | - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option | 4426 | - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option |
4424 | - JFFS2: remove node version 0 warning | 4427 | - JFFS2: remove node version 0 warning |
4425 | - JFFS2: accept JFFS2 PADDING nodes | 4428 | - JFFS2: accept JFFS2 PADDING nodes |
4426 | - SXNI855T: add AM29LV800 support | 4429 | - SXNI855T: add AM29LV800 support |
4427 | - SXNI855T: move environment from EEPROM to flash | 4430 | - SXNI855T: move environment from EEPROM to flash |
4428 | - SXNI855T: boot from JFFS2 in NOR or NAND flash | 4431 | - SXNI855T: boot from JFFS2 in NOR or NAND flash |
4429 | 4432 | ||
4430 | * Patch by Bill Hargen, 11 Aug 2003: | 4433 | * Patch by Bill Hargen, 11 Aug 2003: |
4431 | fixes for I2C on MPC8240 | 4434 | fixes for I2C on MPC8240 |
4432 | - fix i2c_write routine | 4435 | - fix i2c_write routine |
4433 | - fix iprobe command | 4436 | - fix iprobe command |
4434 | - eliminates use of global variables, plus dead code, cleanup. | 4437 | - eliminates use of global variables, plus dead code, cleanup. |
4435 | 4438 | ||
4436 | * Add support for USB Mass Storage Devices (BBB) | 4439 | * Add support for USB Mass Storage Devices (BBB) |
4437 | (tested with USB memory sticks only) | 4440 | (tested with USB memory sticks only) |
4438 | 4441 | ||
4439 | * Avoid flicker on TRAB's VFD | 4442 | * Avoid flicker on TRAB's VFD |
4440 | 4443 | ||
4441 | * Add support for SK98xx driver | 4444 | * Add support for SK98xx driver |
4442 | 4445 | ||
4443 | * Add PCI support for SL8245 board | 4446 | * Add PCI support for SL8245 board |
4444 | 4447 | ||
4445 | * Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) | 4448 | * Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) |
4446 | or 1 x AM29LV652 (two LV065 in one chip = 16 MB); | 4449 | or 1 x AM29LV652 (two LV065 in one chip = 16 MB); |
4447 | Run IPB at 133 Mhz; adjust the MII clock frequency accordingly | 4450 | Run IPB at 133 Mhz; adjust the MII clock frequency accordingly |
4448 | 4451 | ||
4449 | * Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) | 4452 | * Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) |
4450 | to allow for more accurate baudrate settings | 4453 | to allow for more accurate baudrate settings |
4451 | (error now 0.7% at 115 kbps, instead of 3.5% before) | 4454 | (error now 0.7% at 115 kbps, instead of 3.5% before) |
4452 | 4455 | ||
4453 | * Patch by Andreas Mohr, 4 Sep 2003: | 4456 | * Patch by Andreas Mohr, 4 Sep 2003: |
4454 | Fix a lot of spelling errors | 4457 | Fix a lot of spelling errors |
4455 | 4458 | ||
4456 | * Add support for PPChameleon Eval Board | 4459 | * Add support for PPChameleon Eval Board |
4457 | 4460 | ||
4458 | * Add support for P3G4 board | 4461 | * Add support for P3G4 board |
4459 | 4462 | ||
4460 | * Fix problem with MGT5100 FEC driver: add "early" MAC address | 4463 | * Fix problem with MGT5100 FEC driver: add "early" MAC address |
4461 | initialization | 4464 | initialization |
4462 | 4465 | ||
4463 | * Patch by Yuli Barcohen, 7 Aug 2003: | 4466 | * Patch by Yuli Barcohen, 7 Aug 2003: |
4464 | check BCSR to detect if the board is configured in PCI mode | 4467 | check BCSR to detect if the board is configured in PCI mode |
4465 | 4468 | ||
4466 | ====================================================================== | 4469 | ====================================================================== |
4467 | Changes for U-Boot 0.4.7: | 4470 | Changes for U-Boot 0.4.7: |
4468 | ====================================================================== | 4471 | ====================================================================== |
4469 | 4472 | ||
4470 | * Patch by Raghu Krishnaprasad, 7 Aug 2003: | 4473 | * Patch by Raghu Krishnaprasad, 7 Aug 2003: |
4471 | add support for Adder II MPC852T module | 4474 | add support for Adder II MPC852T module |
4472 | 4475 | ||
4473 | * Patch by George G. Davis, 19 Aug 2003: | 4476 | * Patch by George G. Davis, 19 Aug 2003: |
4474 | fix TI Innovator/OMAP1510 pin configs | 4477 | fix TI Innovator/OMAP1510 pin configs |
4475 | 4478 | ||
4476 | * Patches by Kshitij, 18 Aug 2003 | 4479 | * Patches by Kshitij, 18 Aug 2003 |
4477 | - add support for arm926ejs cpu core | 4480 | - add support for arm926ejs cpu core |
4478 | - add support for TI OMAP 1610 Innovator Board | 4481 | - add support for TI OMAP 1610 Innovator Board |
4479 | 4482 | ||
4480 | * Patch by Yuli Barcohen, 14 Aug 2003: | 4483 | * Patch by Yuli Barcohen, 14 Aug 2003: |
4481 | add support for bzip2 uncompression | 4484 | add support for bzip2 uncompression |
4482 | 4485 | ||
4483 | * Add GCC library to examples/Makefile so GCC utility functions will | 4486 | * Add GCC library to examples/Makefile so GCC utility functions will |
4484 | be resolved, too | 4487 | be resolved, too |
4485 | 4488 | ||
4486 | * Add I2C and RTC support for RMU board using software I2C driver | 4489 | * Add I2C and RTC support for RMU board using software I2C driver |
4487 | (because of better response to iprobe command); fix problem with | 4490 | (because of better response to iprobe command); fix problem with |
4488 | "reset" command | 4491 | "reset" command |
4489 | 4492 | ||
4490 | * Patch by Matthias Fuchs, 28 Aug 2003: | 4493 | * Patch by Matthias Fuchs, 28 Aug 2003: |
4491 | Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to | 4494 | Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to |
4492 | CONFIG_BOOTP_MAKS (see README). | 4495 | CONFIG_BOOTP_MAKS (see README). |
4493 | 4496 | ||
4494 | * Fix ICU862 environment problem | 4497 | * Fix ICU862 environment problem |
4495 | 4498 | ||
4496 | * Fix RAM size detection for RMU board | 4499 | * Fix RAM size detection for RMU board |
4497 | 4500 | ||
4498 | * Implement "reset" for MGT5100/MPC5200 systems | 4501 | * Implement "reset" for MGT5100/MPC5200 systems |
4499 | 4502 | ||
4500 | ====================================================================== | 4503 | ====================================================================== |
4501 | Changes for U-Boot 0.4.6: | 4504 | Changes for U-Boot 0.4.6: |
4502 | ====================================================================== | 4505 | ====================================================================== |
4503 | 4506 | ||
4504 | * Make Ethernet autonegotiation on INCA-IP work for all clock rates; | 4507 | * Make Ethernet autonegotiation on INCA-IP work for all clock rates; |
4505 | allow selection of clock frequency as "make" target | 4508 | allow selection of clock frequency as "make" target |
4506 | 4509 | ||
4507 | * Implement memory autosizing code for IceCube boards | 4510 | * Implement memory autosizing code for IceCube boards |
4508 | 4511 | ||
4509 | * Configure network port on INCA-IP for autonegotiation | 4512 | * Configure network port on INCA-IP for autonegotiation |
4510 | 4513 | ||
4511 | * Fix overflow problem in network timeout code | 4514 | * Fix overflow problem in network timeout code |
4512 | 4515 | ||
4513 | * Patch by Richard Woodruff, 8 Aug 2003: | 4516 | * Patch by Richard Woodruff, 8 Aug 2003: |
4514 | Allow crc32 to be used at address 0x000 (crc32_no_comp, too). | 4517 | Allow crc32 to be used at address 0x000 (crc32_no_comp, too). |
4515 | 4518 | ||
4516 | ====================================================================== | 4519 | ====================================================================== |
4517 | Changes for U-Boot 0.4.5: | 4520 | Changes for U-Boot 0.4.5: |
4518 | ====================================================================== | 4521 | ====================================================================== |
4519 | 4522 | ||
4520 | * Update for TQM board defaults: | 4523 | * Update for TQM board defaults: |
4521 | disable clocks_in_mhz, enable boot count limit | 4524 | disable clocks_in_mhz, enable boot count limit |
4522 | 4525 | ||
4523 | * Removed tools/gdb from "make all" target. Added make target "gdbtools" | 4526 | * Removed tools/gdb from "make all" target. Added make target "gdbtools" |
4524 | in toplevel directory instead. Removed astest.c from tools/gdb because | 4527 | in toplevel directory instead. Removed astest.c from tools/gdb because |
4525 | it is no longer relevant. | 4528 | it is no longer relevant. |
4526 | 4529 | ||
4527 | * Fix PCI support for MPC5200 / IceCube Board | 4530 | * Fix PCI support for MPC5200 / IceCube Board |
4528 | 4531 | ||
4529 | * Map ISP1362 USB OTG controller for NSCU board | 4532 | * Map ISP1362 USB OTG controller for NSCU board |
4530 | 4533 | ||
4531 | * Patch by Brad Parker, 02 Aug 2003: | 4534 | * Patch by Brad Parker, 02 Aug 2003: |
4532 | fix sc520_cdp problems | 4535 | fix sc520_cdp problems |
4533 | 4536 | ||
4534 | * Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements) | 4537 | * Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements) |
4535 | 4538 | ||
4536 | * Allow erase command to cross flash bank boundaries | 4539 | * Allow erase command to cross flash bank boundaries |
4537 | 4540 | ||
4538 | * Patch by Scott McNutt, 21 Jul 2003: | 4541 | * Patch by Scott McNutt, 21 Jul 2003: |
4539 | Add support for LynuxWorks Kernel Downloadable Images (KDIs). | 4542 | Add support for LynuxWorks Kernel Downloadable Images (KDIs). |
4540 | Both LynxOS and BlueCat linux KDIs are supported. | 4543 | Both LynxOS and BlueCat linux KDIs are supported. |
4541 | 4544 | ||
4542 | * Patch by Richard Woodruff, 25 Jul 2003: | 4545 | * Patch by Richard Woodruff, 25 Jul 2003: |
4543 | use more reliable reset for OMAP/925T | 4546 | use more reliable reset for OMAP/925T |
4544 | 4547 | ||
4545 | * Patch by Nye Liu, 25 Jul 2003: | 4548 | * Patch by Nye Liu, 25 Jul 2003: |
4546 | fix typo in mpc8xx.h | 4549 | fix typo in mpc8xx.h |
4547 | 4550 | ||
4548 | * Patch by Richard Woodruff, 24 Jul 2003: | 4551 | * Patch by Richard Woodruff, 24 Jul 2003: |
4549 | Fixes for cmd_nand.c: | 4552 | Fixes for cmd_nand.c: |
4550 | - Fixed null dereferece which could result in incorrect ECC values. | 4553 | - Fixed null dereferece which could result in incorrect ECC values. |
4551 | - Added support for devices with no Ready/Busy signal hooked up. | 4554 | - Added support for devices with no Ready/Busy signal hooked up. |
4552 | - Added OMAP1510 read/write protect handling. | 4555 | - Added OMAP1510 read/write protect handling. |
4553 | - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock | 4556 | - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock |
4554 | for non-JFFS2. | 4557 | for non-JFFS2. |
4555 | - Switched default ECC to be JFFS2. | 4558 | - Switched default ECC to be JFFS2. |
4556 | 4559 | ||
4557 | * Allow crc32 to be used at address 0x000 | 4560 | * Allow crc32 to be used at address 0x000 |
4558 | 4561 | ||
4559 | * Provide consistent interface to standalone applications to access | 4562 | * Provide consistent interface to standalone applications to access |
4560 | the 'global_data' structure | 4563 | the 'global_data' structure |
4561 | Provide a doc/README.standalone more useful to users/developers. | 4564 | Provide a doc/README.standalone more useful to users/developers. |
4562 | 4565 | ||
4563 | * Make IceCube MGT5100 FEC driver work | 4566 | * Make IceCube MGT5100 FEC driver work |
4564 | 4567 | ||
4565 | * Implement new mechanism to export U-Boot's functions to standalone | 4568 | * Implement new mechanism to export U-Boot's functions to standalone |
4566 | applications: instead of using (PPC-specific) system calls we now | 4569 | applications: instead of using (PPC-specific) system calls we now |
4567 | use a jump table; please see doc/README.standalone for details | 4570 | use a jump table; please see doc/README.standalone for details |
4568 | 4571 | ||
4569 | * Patch by Dave Westwood, 24 Jul 2003: | 4572 | * Patch by Dave Westwood, 24 Jul 2003: |
4570 | added support for Unity OS (a proprietary OS) | 4573 | added support for Unity OS (a proprietary OS) |
4571 | 4574 | ||
4572 | * Patch by Detlev Zundel, 23 Jul 2003: | 4575 | * Patch by Detlev Zundel, 23 Jul 2003: |
4573 | add "imls" command to print flash table of contents | 4576 | add "imls" command to print flash table of contents |
4574 | 4577 | ||
4575 | * Fix cold boot detection for log buffer reset | 4578 | * Fix cold boot detection for log buffer reset |
4576 | 4579 | ||
4577 | * Return error for invalid length specifiers with "cp.X" etc. | 4580 | * Return error for invalid length specifiers with "cp.X" etc. |
4578 | 4581 | ||
4579 | * Fix startup problem on MIPS | 4582 | * Fix startup problem on MIPS |
4580 | 4583 | ||
4581 | * Allow for CONFIG_SPLASH_SCREEN even when no explicit | 4584 | * Allow for CONFIG_SPLASH_SCREEN even when no explicit |
4582 | bitmap support is configured | 4585 | bitmap support is configured |
4583 | 4586 | ||
4584 | * Patch by Bill Hargen, 18 Jul 2003: | 4587 | * Patch by Bill Hargen, 18 Jul 2003: |
4585 | - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c | 4588 | - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c |
4586 | 4589 | ||
4587 | * Patch by Denis Peter, 18 Jul 2003: | 4590 | * Patch by Denis Peter, 18 Jul 2003: |
4588 | - fix memory configuration for MIP405T | 4591 | - fix memory configuration for MIP405T |
4589 | - fix printout of baudrate for "loadb <loadaddr> <baudrate>" | 4592 | - fix printout of baudrate for "loadb <loadaddr> <baudrate>" |
4590 | 4593 | ||
4591 | * Cleanup of TQM82xx configurations; use "official" board types | 4594 | * Cleanup of TQM82xx configurations; use "official" board types |
4592 | to make selection easier. | 4595 | to make selection easier. |
4593 | 4596 | ||
4594 | * Patch by Martin Krause, 17 Jul 2003: | 4597 | * Patch by Martin Krause, 17 Jul 2003: |
4595 | add delay to get I2C working with "imm" command and s3c24x0_i2c.c | 4598 | add delay to get I2C working with "imm" command and s3c24x0_i2c.c |
4596 | 4599 | ||
4597 | * Patch by Richard Woodruff, 17 July 03: | 4600 | * Patch by Richard Woodruff, 17 July 03: |
4598 | - Fixed bug in OMAP1510 baud rate divisor settings. | 4601 | - Fixed bug in OMAP1510 baud rate divisor settings. |
4599 | 4602 | ||
4600 | * Patch by Nye Liu, 16 July 2003: | 4603 | * Patch by Nye Liu, 16 July 2003: |
4601 | MPC860FADS fixes: | 4604 | MPC860FADS fixes: |
4602 | - add MPC86xADS support (uses MPC86xADS.h) | 4605 | - add MPC86xADS support (uses MPC86xADS.h) |
4603 | - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) | 4606 | - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) |
4604 | o PLPRCR changes | 4607 | o PLPRCR changes |
4605 | o BRG changes (EXTAL/XTAL restricted to 10MHz) | 4608 | o BRG changes (EXTAL/XTAL restricted to 10MHz) |
4606 | o don't trust gclk() software measurement by default, depend on | 4609 | o don't trust gclk() software measurement by default, depend on |
4607 | CONFIG_8xx_GCLK_FREQ | 4610 | CONFIG_8xx_GCLK_FREQ |
4608 | - add DRAM SIMM not installed detection | 4611 | - add DRAM SIMM not installed detection |
4609 | - use more "correct" SDRAM initialization sequence | 4612 | - use more "correct" SDRAM initialization sequence |
4610 | - allow different SDRAM sizes (8xxADS has 8M) | 4613 | - allow different SDRAM sizes (8xxADS has 8M) |
4611 | - default DER is 0 | 4614 | - default DER is 0 |
4612 | - remove unused MAMR defines from FADS860T.h (all done in fads.c) | 4615 | - remove unused MAMR defines from FADS860T.h (all done in fads.c) |
4613 | - rename MAMR/MBMR defines to be more consistent. Should eventually | 4616 | - rename MAMR/MBMR defines to be more consistent. Should eventually |
4614 | be merged into MxMR to better reflect the PowerQUICC datasheet. | 4617 | be merged into MxMR to better reflect the PowerQUICC datasheet. |
4615 | 4618 | ||
4616 | * Patch by Yuli Barcohen, 16 Jul 2003: | 4619 | * Patch by Yuli Barcohen, 16 Jul 2003: |
4617 | support new Motorola PQ2FADS-ZU evaluation board which replaced | 4620 | support new Motorola PQ2FADS-ZU evaluation board which replaced |
4618 | MPC8260ADS and MPC8266ADS | 4621 | MPC8260ADS and MPC8266ADS |
4619 | 4622 | ||
4620 | ====================================================================== | 4623 | ====================================================================== |
4621 | Changes for U-Boot 0.4.4: | 4624 | Changes for U-Boot 0.4.4: |
4622 | ====================================================================== | 4625 | ====================================================================== |
4623 | 4626 | ||
4624 | * Add support for IceCube board (with MGT5100 and MPC5200 CPUs) | 4627 | * Add support for IceCube board (with MGT5100 and MPC5200 CPUs) |
4625 | 4628 | ||
4626 | * Add support for MGT5100 and MPC5200 processors | 4629 | * Add support for MGT5100 and MPC5200 processors |
4627 | 4630 | ||
4628 | * Patch by Lutz Dennig, 15 Jul 2003: | 4631 | * Patch by Lutz Dennig, 15 Jul 2003: |
4629 | update for R360MPI board | 4632 | update for R360MPI board |
4630 | 4633 | ||
4631 | ====================================================================== | 4634 | ====================================================================== |
4632 | Changes for U-Boot 0.4.3: | 4635 | Changes for U-Boot 0.4.3: |
4633 | ====================================================================== | 4636 | ====================================================================== |
4634 | 4637 | ||
4635 | * Patches by Kshitij, 04 Jul 2003 | 4638 | * Patches by Kshitij, 04 Jul 2003 |
4636 | - added support for arm925t cpu core | 4639 | - added support for arm925t cpu core |
4637 | - added support for TI OMAP 1510 Innovator Board | 4640 | - added support for TI OMAP 1510 Innovator Board |
4638 | 4641 | ||
4639 | * Patches by Martin Krause, 14 Jul 2003: | 4642 | * Patches by Martin Krause, 14 Jul 2003: |
4640 | - add I2C support for s3c2400 systems (trab board) | 4643 | - add I2C support for s3c2400 systems (trab board) |
4641 | - (re-) add "ping" to command table | 4644 | - (re-) add "ping" to command table |
4642 | 4645 | ||
4643 | * Fix handling of "slow" POST routines | 4646 | * Fix handling of "slow" POST routines |
4644 | 4647 | ||
4645 | * Patches by Yuli Barcohen, 13 Jul 2003: | 4648 | * Patches by Yuli Barcohen, 13 Jul 2003: |
4646 | - Correct flash and JFFS2 support for MPC8260ADS | 4649 | - Correct flash and JFFS2 support for MPC8260ADS |
4647 | - fix PVR values and clock generation for PowerQUICC II family | 4650 | - fix PVR values and clock generation for PowerQUICC II family |
4648 | (8270/8275/8280) | 4651 | (8270/8275/8280) |
4649 | 4652 | ||
4650 | * Patch by Bernhard Kuhn, 08 Jul 2003: | 4653 | * Patch by Bernhard Kuhn, 08 Jul 2003: |
4651 | - add support for M68K targets | 4654 | - add support for M68K targets |
4652 | 4655 | ||
4653 | * Patch by Ken Chou, 3 Jul: | 4656 | * Patch by Ken Chou, 3 Jul: |
4654 | - Fix PCI config table for A3000 | 4657 | - Fix PCI config table for A3000 |
4655 | - Fix iobase for natsemi.c | 4658 | - Fix iobase for natsemi.c |
4656 | (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) | 4659 | (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) |
4657 | 4660 | ||
4658 | * Allow to enable "slow" POST routines by key press on power-on | 4661 | * Allow to enable "slow" POST routines by key press on power-on |
4659 | * Fix temperature dependend switching of LCD backlight on LWMON | 4662 | * Fix temperature dependend switching of LCD backlight on LWMON |
4660 | * Tweak output format for LWMON | 4663 | * Tweak output format for LWMON |
4661 | 4664 | ||
4662 | * Patch by Stefan Roese, 11 Jul 2003: | 4665 | * Patch by Stefan Roese, 11 Jul 2003: |
4663 | - Fix bug in CONFIG_VERSION_VARIABLE. | 4666 | - Fix bug in CONFIG_VERSION_VARIABLE. |
4664 | - AR405 config updated. | 4667 | - AR405 config updated. |
4665 | - OCRTC/ORSG: bsp command added. | 4668 | - OCRTC/ORSG: bsp command added. |
4666 | - ASH405 bsp update. | 4669 | - ASH405 bsp update. |
4667 | 4670 | ||
4668 | ====================================================================== | 4671 | ====================================================================== |
4669 | Changes for U-Boot 0.4.2: | 4672 | Changes for U-Boot 0.4.2: |
4670 | ====================================================================== | 4673 | ====================================================================== |
4671 | 4674 | ||
4672 | * Add support for NSCU board | 4675 | * Add support for NSCU board |
4673 | 4676 | ||
4674 | * Add support for TQM823M, TQM850M, TQM855M and TQM860M modules | 4677 | * Add support for TQM823M, TQM850M, TQM855M and TQM860M modules |
4675 | 4678 | ||
4676 | * Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML | 4679 | * Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML |
4677 | mirror bit flash on TQM8xxM modules | 4680 | mirror bit flash on TQM8xxM modules |
4678 | 4681 | ||
4679 | * Patch by Kenneth Johansson, 30 Jun 2003: | 4682 | * Patch by Kenneth Johansson, 30 Jun 2003: |
4680 | get rid of MK_CMD_ENTRY macro; update doc/README.command | 4683 | get rid of MK_CMD_ENTRY macro; update doc/README.command |
4681 | 4684 | ||
4682 | * Patch by Seb James, 30 Jun 2003: | 4685 | * Patch by Seb James, 30 Jun 2003: |
4683 | Improve documentation of I2C configuration in README | 4686 | Improve documentation of I2C configuration in README |
4684 | 4687 | ||
4685 | * Fix problems with previous log buffer "fixes" | 4688 | * Fix problems with previous log buffer "fixes" |
4686 | 4689 | ||
4687 | * Fix minor help text issues | 4690 | * Fix minor help text issues |
4688 | 4691 | ||
4689 | * "log append" did not append a newline | 4692 | * "log append" did not append a newline |
4690 | 4693 | ||
4691 | ====================================================================== | 4694 | ====================================================================== |
4692 | Changes for U-Boot 0.4.1: | 4695 | Changes for U-Boot 0.4.1: |
4693 | ====================================================================== | 4696 | ====================================================================== |
4694 | 4697 | ||
4695 | * Fix some missing commands, cleanup header files | 4698 | * Fix some missing commands, cleanup header files |
4696 | (autoscript, bmp, bsp, fat, mmc, nand, portio, ...) | 4699 | (autoscript, bmp, bsp, fat, mmc, nand, portio, ...) |
4697 | 4700 | ||
4698 | * Rewrite command lookup and help command (fix problems with bubble | 4701 | * Rewrite command lookup and help command (fix problems with bubble |
4699 | sort when sorting command name list). Minor cleanup here and there. | 4702 | sort when sorting command name list). Minor cleanup here and there. |
4700 | 4703 | ||
4701 | * Merge from "stable branch", tag LABEL_2003_06_28_1800-stable: | 4704 | * Merge from "stable branch", tag LABEL_2003_06_28_1800-stable: |
4702 | - Allow to call sysmon function interactively | 4705 | - Allow to call sysmon function interactively |
4703 | - PIC on LWMON board needs delay after power-on | 4706 | - PIC on LWMON board needs delay after power-on |
4704 | - Add missing RSR definitions for MPC8xx | 4707 | - Add missing RSR definitions for MPC8xx |
4705 | - Improve log buffer handling: guarantee clean reset after power-on | 4708 | - Improve log buffer handling: guarantee clean reset after power-on |
4706 | - Add support for EXBITGEN board (aka "genie") | 4709 | - Add support for EXBITGEN board (aka "genie") |
4707 | - Add support for SL8245 board | 4710 | - Add support for SL8245 board |
4708 | 4711 | ||
4709 | * Code cleanup: | 4712 | * Code cleanup: |
4710 | - remove trailing white space, trailing empty lines, C++ comments, etc. | 4713 | - remove trailing white space, trailing empty lines, C++ comments, etc. |
4711 | - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) | 4714 | - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) |
4712 | 4715 | ||
4713 | * Patches by Kenneth Johansson, 25 Jun 2003: | 4716 | * Patches by Kenneth Johansson, 25 Jun 2003: |
4714 | - major rework of command structure | 4717 | - major rework of command structure |
4715 | (work done mostly by Michal Cendrowski and Joakim Kristiansen) | 4718 | (work done mostly by Michal Cendrowski and Joakim Kristiansen) |
4716 | 4719 | ||
4717 | ====================================================================== | 4720 | ====================================================================== |
4718 | Changes for U-Boot 0.4.0: | 4721 | Changes for U-Boot 0.4.0: |
4719 | ====================================================================== | 4722 | ====================================================================== |
4720 | 4723 | ||
4721 | * Patches by Robert Schwebel, 26 Jun 2003: | 4724 | * Patches by Robert Schwebel, 26 Jun 2003: |
4722 | - csb226 configuration updated | 4725 | - csb226 configuration updated |
4723 | - credits for logodl port updated | 4726 | - credits for logodl port updated |
4724 | - innokom configuration updated | 4727 | - innokom configuration updated |
4725 | - logodl tree update, still with coding style inconsistencies | 4728 | - logodl tree update, still with coding style inconsistencies |
4726 | - added OCM for ppc405 warning to README | 4729 | - added OCM for ppc405 warning to README |
4727 | 4730 | ||
4728 | * Patch by Pantelis Antoniou, 25 Jun 2003: | 4731 | * Patch by Pantelis Antoniou, 25 Jun 2003: |
4729 | update NetVia with V2 board support | 4732 | update NetVia with V2 board support |
4730 | 4733 | ||
4731 | * Header file cleanup for ARM | 4734 | * Header file cleanup for ARM |
4732 | 4735 | ||
4733 | * Patch by Murray Jensen, 24 Jun 2003: | 4736 | * Patch by Murray Jensen, 24 Jun 2003: |
4734 | - make sure to use only U-boot provided header files | 4737 | - make sure to use only U-boot provided header files |
4735 | - fix problems with ".rodata.str1.4" section as used by GCC-3.x | 4738 | - fix problems with ".rodata.str1.4" section as used by GCC-3.x |
4736 | 4739 | ||
4737 | * Patch by Stefan Roese, 24 Jun 2003: | 4740 | * Patch by Stefan Roese, 24 Jun 2003: |
4738 | - Update esd ASH405 board files. | 4741 | - Update esd ASH405 board files. |
4739 | - Update esd DASA_SIM config file. | 4742 | - Update esd DASA_SIM config file. |
4740 | - Add ping command to some esd boards. | 4743 | - Add ping command to some esd boards. |
4741 | 4744 | ||
4742 | * Patch by Yuli Barcohen, 23 Jun 2003: | 4745 | * Patch by Yuli Barcohen, 23 Jun 2003: |
4743 | Update for MPC8260ADS board | 4746 | Update for MPC8260ADS board |
4744 | 4747 | ||
4745 | * Patch by Murray Jensen, 23 Jun 2003: | 4748 | * Patch by Murray Jensen, 23 Jun 2003: |
4746 | - cleanup of GCC 3.x compiler warnings | 4749 | - cleanup of GCC 3.x compiler warnings |
4747 | 4750 | ||
4748 | * Patch by Rune Torgersen, 4 Jun 2003: | 4751 | * Patch by Rune Torgersen, 4 Jun 2003: |
4749 | add large memory support for MPC8266ADS board | 4752 | add large memory support for MPC8266ADS board |
4750 | 4753 | ||
4751 | * Patch by Richard Woodruff, 19 June 03: | 4754 | * Patch by Richard Woodruff, 19 June 03: |
4752 | - Enabled standard u-boot device abstraction for ARM | 4755 | - Enabled standard u-boot device abstraction for ARM |
4753 | - Enabled console device for ARM | 4756 | - Enabled console device for ARM |
4754 | - Initilized bi_baudrate for ARM | 4757 | - Initilized bi_baudrate for ARM |
4755 | 4758 | ||
4756 | * Patch by Bill Hargen, 23 Apr 2003: | 4759 | * Patch by Bill Hargen, 23 Apr 2003: |
4757 | fix byte order for 824x I2C addresses (write op) | 4760 | fix byte order for 824x I2C addresses (write op) |
4758 | 4761 | ||
4759 | * Patch by Murray Jensen, 20 Jun 2003: | 4762 | * Patch by Murray Jensen, 20 Jun 2003: |
4760 | - hymod update | 4763 | - hymod update |
4761 | - cleanup (especially for gcc-3.x compilers) | 4764 | - cleanup (especially for gcc-3.x compilers) |
4762 | 4765 | ||
4763 | * Patch by Tom Guilliams, 20 Jun 2003: | 4766 | * Patch by Tom Guilliams, 20 Jun 2003: |
4764 | added CONFIG_750FX support for IBM 750FX processors | 4767 | added CONFIG_750FX support for IBM 750FX processors |
4765 | 4768 | ||
4766 | * Patch by Devin Crumb, 02 Apr 2003: | 4769 | * Patch by Devin Crumb, 02 Apr 2003: |
4767 | Fix clock divider rounding problem in drivers/serial.c | 4770 | Fix clock divider rounding problem in drivers/serial.c |
4768 | 4771 | ||
4769 | * Patch by Richard Woodruff, 19 June 03: | 4772 | * Patch by Richard Woodruff, 19 June 03: |
4770 | - Fixed smc91c111 driver to sync with the u-boot environment | 4773 | - Fixed smc91c111 driver to sync with the u-boot environment |
4771 | (driver/smc91c111.c). | 4774 | (driver/smc91c111.c). |
4772 | - Added eth_init error return check in NetLoop (net/net.c). | 4775 | - Added eth_init error return check in NetLoop (net/net.c). |
4773 | 4776 | ||
4774 | * Patch by Ken Chou, 19 June 2003: | 4777 | * Patch by Ken Chou, 19 June 2003: |
4775 | Added support for A3000 SBC board (Artis Microsystems Inc.) | 4778 | Added support for A3000 SBC board (Artis Microsystems Inc.) |
4776 | 4779 | ||
4777 | * Patches by Murray Jensen, 17 Jun 2003: | 4780 | * Patches by Murray Jensen, 17 Jun 2003: |
4778 | - Hymod board database mods: add "who" field and new xilinx chip types | 4781 | - Hymod board database mods: add "who" field and new xilinx chip types |
4779 | - provide new "init_cmd_timeout()" function so code external to | 4782 | - provide new "init_cmd_timeout()" function so code external to |
4780 | "common/main.c" can use the "reset_cmd_timeout()" function before | 4783 | "common/main.c" can use the "reset_cmd_timeout()" function before |
4781 | entering the main loop | 4784 | entering the main loop |
4782 | - add DTT support for adm1021 (new file dtt/adm1021.c; config | 4785 | - add DTT support for adm1021 (new file dtt/adm1021.c; config |
4783 | slightly different. see include/configs/hymod.h for an example | 4786 | slightly different. see include/configs/hymod.h for an example |
4784 | (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and | 4787 | (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and |
4785 | CFG_DTT_ADM1021 defined) | 4788 | CFG_DTT_ADM1021 defined) |
4786 | - add new "eeprom_probe()" function which has similar args and | 4789 | - add new "eeprom_probe()" function which has similar args and |
4787 | behaves in a similar way to "eeprom_read()" etc. | 4790 | behaves in a similar way to "eeprom_read()" etc. |
4788 | - add 8260 FCC ethernet loopback code (new "eth_loopback_test()" | 4791 | - add 8260 FCC ethernet loopback code (new "eth_loopback_test()" |
4789 | function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST) | 4792 | function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST) |
4790 | - gdbtools copyright update | 4793 | - gdbtools copyright update |
4791 | - ensure that set_msr() executes the "sync" and "isync" instructions | 4794 | - ensure that set_msr() executes the "sync" and "isync" instructions |
4792 | after the "mtmsr" instruction in cpu/mpc8260/interrupts.c | 4795 | after the "mtmsr" instruction in cpu/mpc8260/interrupts.c |
4793 | - 8260 I/O ports fix: Open Drain should be set last when configuring | 4796 | - 8260 I/O ports fix: Open Drain should be set last when configuring |
4794 | - add SIU IRQ defines for 8260 | 4797 | - add SIU IRQ defines for 8260 |
4795 | - allow LDSCRIPT override and OBJCFLAGS initialization: change to | 4798 | - allow LDSCRIPT override and OBJCFLAGS initialization: change to |
4796 | config.mk to allow board configurations to override the GNU | 4799 | config.mk to allow board configurations to override the GNU |
4797 | linker script, selected via the LDSCRIPT, make variable, and to | 4800 | linker script, selected via the LDSCRIPT, make variable, and to |
4798 | give an initial value to the OBJCFLAGS make variable | 4801 | give an initial value to the OBJCFLAGS make variable |
4799 | - 8260 i2c enhancement: | 4802 | - 8260 i2c enhancement: |
4800 | o correctly extends the timeout depending on the size of all | 4803 | o correctly extends the timeout depending on the size of all |
4801 | queued messages for both transmit and receive | 4804 | queued messages for both transmit and receive |
4802 | o will not continue with receive if transmit times out | 4805 | o will not continue with receive if transmit times out |
4803 | o ensures that the error callback is done for all queued tx | 4806 | o ensures that the error callback is done for all queued tx |
4804 | and rx messages | 4807 | and rx messages |
4805 | o correctly detects both tx and rx timeouts, only delivers one to | 4808 | o correctly detects both tx and rx timeouts, only delivers one to |
4806 | the callback, and does not overwrite an earlier error | 4809 | the callback, and does not overwrite an earlier error |
4807 | o logic in i2c_probe now correct | 4810 | o logic in i2c_probe now correct |
4808 | - add "vprintf()" function so that "panic()" function can be | 4811 | - add "vprintf()" function so that "panic()" function can be |
4809 | technically correct | 4812 | technically correct |
4810 | - many Hymod board changes | 4813 | - many Hymod board changes |
4811 | 4814 | ||
4812 | * Patches by Robert Schwebel, 14 Jun 2003: | 4815 | * Patches by Robert Schwebel, 14 Jun 2003: |
4813 | - add support for Logotronic DL datalogger board | 4816 | - add support for Logotronic DL datalogger board |
4814 | - cleanup serial line after kermit binary download | 4817 | - cleanup serial line after kermit binary download |
4815 | - add debugX macro (debug level support) | 4818 | - add debugX macro (debug level support) |
4816 | - update mach-types.h to latest arm.linux.org.uk master list. | 4819 | - update mach-types.h to latest arm.linux.org.uk master list. |
4817 | 4820 | ||
4818 | * Patches by David Mรผller, 12 Jun 2003: | 4821 | * Patches by David Mรผller, 12 Jun 2003: |
4819 | - rewrite of the S3C24X0 register definitions stuff | 4822 | - rewrite of the S3C24X0 register definitions stuff |
4820 | - "driver" for the built-in S3C24X0 RTC | 4823 | - "driver" for the built-in S3C24X0 RTC |
4821 | 4824 | ||
4822 | * Patches by Yuli Barcohen, 12 Jun 2003: | 4825 | * Patches by Yuli Barcohen, 12 Jun 2003: |
4823 | - Add MII support and Ethernet PHY initialization for MPC8260ADS board | 4826 | - Add MII support and Ethernet PHY initialization for MPC8260ADS board |
4824 | - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset | 4827 | - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset |
4825 | configuration word supplied by FPGA on some MPC8260ADS boards | 4828 | configuration word supplied by FPGA on some MPC8260ADS boards |
4826 | 4829 | ||
4827 | * Patch by Pantelis Antoniou, 10 Jun 2003: | 4830 | * Patch by Pantelis Antoniou, 10 Jun 2003: |
4828 | Unify status LED interface | 4831 | Unify status LED interface |
4829 | 4832 | ||
4830 | * Add support for DS12887 RTC; add RTC support for ATC board | 4833 | * Add support for DS12887 RTC; add RTC support for ATC board |
4831 | 4834 | ||
4832 | * Patch by Nicolas Lacressonniere, 11 Jun 2003: | 4835 | * Patch by Nicolas Lacressonniere, 11 Jun 2003: |
4833 | Modifications for Atmel AT91RM9200DK ARM920T based development kit | 4836 | Modifications for Atmel AT91RM9200DK ARM920T based development kit |
4834 | - Add Atmel DataFlash support for reading and writing. | 4837 | - Add Atmel DataFlash support for reading and writing. |
4835 | - Add possibility to boot a Linux from DataFlash with BOOTM command. | 4838 | - Add possibility to boot a Linux from DataFlash with BOOTM command. |
4836 | - Add Flash detection on Atmel AT91RM9200DK | 4839 | - Add Flash detection on Atmel AT91RM9200DK |
4837 | (between Atmel AT49BV1614 and AT49BV1614A flashes) | 4840 | (between Atmel AT49BV1614 and AT49BV1614A flashes) |
4838 | - Replace old Ethernet PHY layer functions | 4841 | - Replace old Ethernet PHY layer functions |
4839 | - Change link address | 4842 | - Change link address |
4840 | 4843 | ||
4841 | * Patch by Frank Smith, 9 Jun 2003: | 4844 | * Patch by Frank Smith, 9 Jun 2003: |
4842 | use CRIT_EXCEPTION for machine check on 4xx | 4845 | use CRIT_EXCEPTION for machine check on 4xx |
4843 | 4846 | ||
4844 | * Patch by Detlev Zundel, 13 Jun 2003: | 4847 | * Patch by Detlev Zundel, 13 Jun 2003: |
4845 | added implementation of the "carinfo" command in cmd_immap.c | 4848 | added implementation of the "carinfo" command in cmd_immap.c |
4846 | 4849 | ||
4847 | * Fix CONFIG_NET_MULTI support in include/net.h | 4850 | * Fix CONFIG_NET_MULTI support in include/net.h |
4848 | 4851 | ||
4849 | * Patches by Kyle Harris, 13 Mar 2003: | 4852 | * Patches by Kyle Harris, 13 Mar 2003: |
4850 | - Add FAT partition support | 4853 | - Add FAT partition support |
4851 | - Add command support for FAT | 4854 | - Add command support for FAT |
4852 | - Add command support for MMC | 4855 | - Add command support for MMC |
4853 | ---- | 4856 | ---- |
4854 | - Add Intel PXA support for video | 4857 | - Add Intel PXA support for video |
4855 | - Add Intel PXA support for MMC | 4858 | - Add Intel PXA support for MMC |
4856 | ---- | 4859 | ---- |
4857 | - Enable MMC and FAT for lubbock board | 4860 | - Enable MMC and FAT for lubbock board |
4858 | - Other misc changes for lubbock board | 4861 | - Other misc changes for lubbock board |
4859 | 4862 | ||
4860 | * Patch by Robert Schwebel, April 02, 2003: | 4863 | * Patch by Robert Schwebel, April 02, 2003: |
4861 | fix for SMSC91111 driver | 4864 | fix for SMSC91111 driver |
4862 | 4865 | ||
4863 | * Patch by Vladimir Gurevich, 04 Jun 2003: | 4866 | * Patch by Vladimir Gurevich, 04 Jun 2003: |
4864 | make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option | 4867 | make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option |
4865 | 4868 | ||
4866 | * Patch by Stefan Roese, 05 Jun 2003: | 4869 | * Patch by Stefan Roese, 05 Jun 2003: |
4867 | - PPC4xx: Fix bug for initial stack in data cache as pointed out by | 4870 | - PPC4xx: Fix bug for initial stack in data cache as pointed out by |
4868 | Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in | 4871 | Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in |
4869 | data cache can be used even if the chip select is in use. | 4872 | data cache can be used even if the chip select is in use. |
4870 | - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count | 4873 | - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count |
4871 | (see README for further description). | 4874 | (see README for further description). |
4872 | - Changed config files of CONFIG_EEPRO100 boards to use the | 4875 | - Changed config files of CONFIG_EEPRO100 boards to use the |
4873 | CFG_RX_ETH_BUFFER define. | 4876 | CFG_RX_ETH_BUFFER define. |
4874 | 4877 | ||
4875 | * Add support for RMU board | 4878 | * Add support for RMU board |
4876 | 4879 | ||
4877 | * Add support for TQM862L at 100/50 MHz | 4880 | * Add support for TQM862L at 100/50 MHz |
4878 | 4881 | ||
4879 | * Patch by Pantelis Antoniou, 02 Jun 2003: | 4882 | * Patch by Pantelis Antoniou, 02 Jun 2003: |
4880 | major reconstruction of networking code; | 4883 | major reconstruction of networking code; |
4881 | add "ping" support (outgoing only!) | 4884 | add "ping" support (outgoing only!) |
4882 | 4885 | ||
4883 | * Patch by Denis Peter, 04 June 2003: | 4886 | * Patch by Denis Peter, 04 June 2003: |
4884 | add support for the MIP405T board | 4887 | add support for the MIP405T board |
4885 | 4888 | ||
4886 | * Patches by Udi Finkelstein, 2 June 2003: | 4889 | * Patches by Udi Finkelstein, 2 June 2003: |
4887 | - Added support for custom keyboards, initialized by defining a | 4890 | - Added support for custom keyboards, initialized by defining a |
4888 | board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD . | 4891 | board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD . |
4889 | - Added support for the RBC823 board. | 4892 | - Added support for the RBC823 board. |
4890 | - cpu/mpc8xx/lcd.c now automatically calculates the | 4893 | - cpu/mpc8xx/lcd.c now automatically calculates the |
4891 | Horizontal Pixel Count field. | 4894 | Horizontal Pixel Count field. |
4892 | 4895 | ||
4893 | * Fix alignment problem in BOOTP (dhcp_leasetime option) | 4896 | * Fix alignment problem in BOOTP (dhcp_leasetime option) |
4894 | [pointed out by Nicolas Lacressonniรจre, 2 Jun 2003] | 4897 | [pointed out by Nicolas Lacressonniรจre, 2 Jun 2003] |
4895 | 4898 | ||
4896 | * Patch by Mark Rakes, 14 May 2003: | 4899 | * Patch by Mark Rakes, 14 May 2003: |
4897 | add support for Intel e1000 gig cards. | 4900 | add support for Intel e1000 gig cards. |
4898 | 4901 | ||
4899 | * Patch by Nye Liu, 3 Jun 2003: | 4902 | * Patch by Nye Liu, 3 Jun 2003: |
4900 | fix critical typo in MAMR definition (include/mpc8xx.h) | 4903 | fix critical typo in MAMR definition (include/mpc8xx.h) |
4901 | 4904 | ||
4902 | * Fix requirement to align U-Boot image on 16 kB boundaries on PPC. | 4905 | * Fix requirement to align U-Boot image on 16 kB boundaries on PPC. |
4903 | 4906 | ||
4904 | * Patch by Klaus Heydeck, 2 Jun 2003 | 4907 | * Patch by Klaus Heydeck, 2 Jun 2003 |
4905 | Minor changes for KUP4K configuration | 4908 | Minor changes for KUP4K configuration |
4906 | 4909 | ||
4907 | * Patch by Marc Singer, 29 May 2003: | 4910 | * Patch by Marc Singer, 29 May 2003: |
4908 | Fixed rarp boot method for IA32 and other little-endian CPUs. | 4911 | Fixed rarp boot method for IA32 and other little-endian CPUs. |
4909 | 4912 | ||
4910 | * Patch by Marc Singer, 28 May 2003: | 4913 | * Patch by Marc Singer, 28 May 2003: |
4911 | Added port I/O commands. | 4914 | Added port I/O commands. |
4912 | 4915 | ||
4913 | * Patch by Matthew McClintock, 28 May 2003 | 4916 | * Patch by Matthew McClintock, 28 May 2003 |
4914 | - cpu/mpc824x/start.S: fix relocation code when booting from RAM | 4917 | - cpu/mpc824x/start.S: fix relocation code when booting from RAM |
4915 | - minor patches for utx8245 | 4918 | - minor patches for utx8245 |
4916 | 4919 | ||
4917 | * Patch by Daniel Engstrรถm, 28 May 2003: | 4920 | * Patch by Daniel Engstrรถm, 28 May 2003: |
4918 | x86 update | 4921 | x86 update |
4919 | 4922 | ||
4920 | * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: | 4923 | * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: |
4921 | add nand flash support to SXNI855T configuration | 4924 | add nand flash support to SXNI855T configuration |
4922 | fix/extend nand flash support: | 4925 | fix/extend nand flash support: |
4923 | - fix 'nand erase' command so does not erase bad blocks | 4926 | - fix 'nand erase' command so does not erase bad blocks |
4924 | - fix 'nand write' command so does not write to bad blocks | 4927 | - fix 'nand write' command so does not write to bad blocks |
4925 | - fix nand_probe() so handles no flash detected properly | 4928 | - fix nand_probe() so handles no flash detected properly |
4926 | - add doc/README.nand | 4929 | - add doc/README.nand |
4927 | - add .jffs2 and .oob options to nand read/write | 4930 | - add .jffs2 and .oob options to nand read/write |
4928 | - add 'nand bad' command to list bad blocks | 4931 | - add 'nand bad' command to list bad blocks |
4929 | - add 'clean' option to 'nand erase' to write JFFS2 clean markers | 4932 | - add 'clean' option to 'nand erase' to write JFFS2 clean markers |
4930 | - make NAND read/write faster | 4933 | - make NAND read/write faster |
4931 | 4934 | ||
4932 | * Patch by Rune Torgersen, 23 May 2003: | 4935 | * Patch by Rune Torgersen, 23 May 2003: |
4933 | Update for MPC8266ADS board | 4936 | Update for MPC8266ADS board |
4934 | 4937 | ||
4935 | * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length | 4938 | * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length |
4936 | instead CFG_MONITOR_LEN is now only used to determine _at_compile_ | 4939 | instead CFG_MONITOR_LEN is now only used to determine _at_compile_ |
4937 | _time_ (!) if the environment is embedded within the U-Boot image, | 4940 | _time_ (!) if the environment is embedded within the U-Boot image, |
4938 | or in a separate flash sector. | 4941 | or in a separate flash sector. |
4939 | 4942 | ||
4940 | * Cleanup CFG_DER #defines in config files (wd maintained only) | 4943 | * Cleanup CFG_DER #defines in config files (wd maintained only) |
4941 | 4944 | ||
4942 | * Fix data abort exception handling for arm920t CPU | 4945 | * Fix data abort exception handling for arm920t CPU |
4943 | 4946 | ||
4944 | * Fix alignment problems with flash driver for TRAB board | 4947 | * Fix alignment problems with flash driver for TRAB board |
4945 | 4948 | ||
4946 | * Patch by Donald White, 21 May 2003: | 4949 | * Patch by Donald White, 21 May 2003: |
4947 | fix calculation of base address in pci_hose_config_device() | 4950 | fix calculation of base address in pci_hose_config_device() |
4948 | 4951 | ||
4949 | * Fix bug in command line parsing: "cmd1;cmd2" is supposed to always | 4952 | * Fix bug in command line parsing: "cmd1;cmd2" is supposed to always |
4950 | execute "cmd2", even if "cmd1" fails. Note that this is different | 4953 | execute "cmd2", even if "cmd1" fails. Note that this is different |
4951 | to "run var1 var2" where the contents of "var2" will NOT be | 4954 | to "run var1 var2" where the contents of "var2" will NOT be |
4952 | executed when a command in "var1" fails. | 4955 | executed when a command in "var1" fails. |
4953 | 4956 | ||
4954 | * Add zero-copy ramdisk support (requires corresponding kernel support!) | 4957 | * Add zero-copy ramdisk support (requires corresponding kernel support!) |
4955 | 4958 | ||
4956 | * Patch by Kyle Harris, 20 May 2003: | 4959 | * Patch by Kyle Harris, 20 May 2003: |
4957 | In preparation for an ixp port, rename cpu/xscale and arch-xscale | 4960 | In preparation for an ixp port, rename cpu/xscale and arch-xscale |
4958 | into cpu/pxa and arch-pxa. | 4961 | into cpu/pxa and arch-pxa. |
4959 | 4962 | ||
4960 | * Patch by Stefan Roese, 23 May 2003: | 4963 | * Patch by Stefan Roese, 23 May 2003: |
4961 | - IBM PPC405EP port added. | 4964 | - IBM PPC405EP port added. |
4962 | - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not | 4965 | - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not |
4963 | UART0) is used as default U-Boot console. PPC4xx only! | 4966 | UART0) is used as default U-Boot console. PPC4xx only! |
4964 | - esd ASH405 board added (PPC405EP based). | 4967 | - esd ASH405 board added (PPC405EP based). |
4965 | - BUBINGA405EP board added (PPC405EP based - IBM Eval Board). | 4968 | - BUBINGA405EP board added (PPC405EP based - IBM Eval Board). |
4966 | - esd CPCI405AB board added. | 4969 | - esd CPCI405AB board added. |
4967 | - esd PMC405 board added. | 4970 | - esd PMC405 board added. |
4968 | - Update of some esd boards. | 4971 | - Update of some esd boards. |
4969 | 4972 | ||
4970 | * Patch by Denis Peter, 19 Mai 2003: | 4973 | * Patch by Denis Peter, 19 Mai 2003: |
4971 | add support for the MIP405-3 board | 4974 | add support for the MIP405-3 board |
4972 | 4975 | ||
4973 | * Patch by Dave Ellis, 22 May 2003: | 4976 | * Patch by Dave Ellis, 22 May 2003: |
4974 | Fix problem with only partially cleared .bss segment | 4977 | Fix problem with only partially cleared .bss segment |
4975 | 4978 | ||
4976 | * Patch by Rune Torgersen, 12 May 2003: | 4979 | * Patch by Rune Torgersen, 12 May 2003: |
4977 | get PCI to work on a MPC8266ADS board; incorporate change to | 4980 | get PCI to work on a MPC8266ADS board; incorporate change to |
4978 | cpu/mpc8260/pci.c to enable overrides of PCI memory parameters | 4981 | cpu/mpc8260/pci.c to enable overrides of PCI memory parameters |
4979 | 4982 | ||
4980 | * Patch by Nye Liu, 1 May 2003: | 4983 | * Patch by Nye Liu, 1 May 2003: |
4981 | minor patches for the FADS8xx | 4984 | minor patches for the FADS8xx |
4982 | 4985 | ||
4983 | * Patch by Thomas Schรคfer, 28 Apr 2003: | 4986 | * Patch by Thomas Schรคfer, 28 Apr 2003: |
4984 | Fix SPD handling for 256 ECC DIMM on Walnut | 4987 | Fix SPD handling for 256 ECC DIMM on Walnut |
4985 | 4988 | ||
4986 | * Add support for arbitrary bitmaps for TRAB's VFD command; | 4989 | * Add support for arbitrary bitmaps for TRAB's VFD command; |
4987 | allow to pass boot bitmap addresses in environment variables; | 4990 | allow to pass boot bitmap addresses in environment variables; |
4988 | allow for zero boot delay | 4991 | allow for zero boot delay |
4989 | 4992 | ||
4990 | * Patch by Christian Geiรinger, 19 May 2002: | 4993 | * Patch by Christian Geiรinger, 19 May 2002: |
4991 | On TRAB: wait until the dummy byte has been completely sent | 4994 | On TRAB: wait until the dummy byte has been completely sent |
4992 | 4995 | ||
4993 | * Patch by David Updegraff, 22 Apr 2003: | 4996 | * Patch by David Updegraff, 22 Apr 2003: |
4994 | update for CrayL1 board | 4997 | update for CrayL1 board |
4995 | 4998 | ||
4996 | * Patch by Pantelis Antoniou, 21 Apr 2003: | 4999 | * Patch by Pantelis Antoniou, 21 Apr 2003: |
4997 | add boot support for ARTOS (a proprietary OS) | 5000 | add boot support for ARTOS (a proprietary OS) |
4998 | 5001 | ||
4999 | * Patch by Steven Scholz, 11 Apr 2003: | 5002 | * Patch by Steven Scholz, 11 Apr 2003: |
5000 | Add support for RTC DS1338 | 5003 | Add support for RTC DS1338 |
5001 | 5004 | ||
5002 | * Patch by Rod Boyce, 24 Jan 2003: | 5005 | * Patch by Rod Boyce, 24 Jan 2003: |
5003 | Fix counting of extended partitions in diskboot command | 5006 | Fix counting of extended partitions in diskboot command |
5004 | 5007 | ||
5005 | * Patch by Christophe Lindheimer, 20 May 2003: | 5008 | * Patch by Christophe Lindheimer, 20 May 2003: |
5006 | allow the use of CFG_LOADS when CFG_NO_FLASH is set | 5009 | allow the use of CFG_LOADS when CFG_NO_FLASH is set |
5007 | 5010 | ||
5008 | * Fix SDRAM timing on Purple board | 5011 | * Fix SDRAM timing on Purple board |
5009 | 5012 | ||
5010 | * Add support for CompactFlash on ATC board | 5013 | * Add support for CompactFlash on ATC board |
5011 | (includes support for Intel 82365 and compatible PC Card controllers, | 5014 | (includes support for Intel 82365 and compatible PC Card controllers, |
5012 | and Yenta-compatible PCI-to-CardBus controllers) | 5015 | and Yenta-compatible PCI-to-CardBus controllers) |
5013 | 5016 | ||
5014 | * Patch by Mathijs Haarman, 08 May 2003: | 5017 | * Patch by Mathijs Haarman, 08 May 2003: |
5015 | Add lan91c96 driver (tested on Lubbock and custom PXA250 board only) | 5018 | Add lan91c96 driver (tested on Lubbock and custom PXA250 board only) |
5016 | 5019 | ||
5017 | * Fix problem with usage of "true" (undefined in current versions of bfd.h) | 5020 | * Fix problem with usage of "true" (undefined in current versions of bfd.h) |
5018 | 5021 | ||
5019 | * Add support for Promess ATC board | 5022 | * Add support for Promess ATC board |
5020 | 5023 | ||
5021 | * Patch by Keith Outwater, 28 Apr 2003: | 5024 | * Patch by Keith Outwater, 28 Apr 2003: |
5022 | - Miscellaneous corrections and additions to GEN860T board specific code. | 5025 | - Miscellaneous corrections and additions to GEN860T board specific code. |
5023 | - Added GEN860_SC variant to GEN860T. | 5026 | - Added GEN860_SC variant to GEN860T. |
5024 | - Miscellaneous corrections to GEN860T documentation. | 5027 | - Miscellaneous corrections to GEN860T documentation. |
5025 | - Correct duplicate entry in U-Boot CREDITS file. | 5028 | - Correct duplicate entry in U-Boot CREDITS file. |
5026 | - Add GEN860T_SC entry in MAINTAINERS file. | 5029 | - Add GEN860T_SC entry in MAINTAINERS file. |
5027 | - Update CREDITS file with GEN860T_SC info. | 5030 | - Update CREDITS file with GEN860T_SC info. |
5028 | 5031 | ||
5029 | * Update Smiths Aerospace addresses in MAINTAINERS file | 5032 | * Update Smiths Aerospace addresses in MAINTAINERS file |
5030 | 5033 | ||
5031 | * Fix error handling in hush's version of "run" command | 5034 | * Fix error handling in hush's version of "run" command |
5032 | 5035 | ||
5033 | * LWMON extensions: | 5036 | * LWMON extensions: |
5034 | - Splashscreen support | 5037 | - Splashscreen support |
5035 | - modem support | 5038 | - modem support |
5036 | - sysmon support | 5039 | - sysmon support |
5037 | - temperature dependend enabling of LCD | 5040 | - temperature dependend enabling of LCD |
5038 | 5041 | ||
5039 | * Allow booting from old "PPCBoot" disk partitions | 5042 | * Allow booting from old "PPCBoot" disk partitions |
5040 | 5043 | ||
5041 | * Add support for TQM8255 Board / MPC8255 CPU | 5044 | * Add support for TQM8255 Board / MPC8255 CPU |
5042 | 5045 | ||
5043 | ====================================================================== | 5046 | ====================================================================== |
5044 | Changes for U-Boot 0.3.1: | 5047 | Changes for U-Boot 0.3.1: |
5045 | ====================================================================== | 5048 | ====================================================================== |
5046 | 5049 | ||
5047 | * Make sure Block Lock Bits get cleared in R360MPI flash driver | 5050 | * Make sure Block Lock Bits get cleared in R360MPI flash driver |
5048 | 5051 | ||
5049 | * MPC823 LCD driver: Fill color map backwards, to allow for steady | 5052 | * MPC823 LCD driver: Fill color map backwards, to allow for steady |
5050 | display when Linux takes over | 5053 | display when Linux takes over |
5051 | 5054 | ||
5052 | * Patch by Erwin Rol, 27 Feb 2003: | 5055 | * Patch by Erwin Rol, 27 Feb 2003: |
5053 | Add support for RTEMS (this time for real). | 5056 | Add support for RTEMS (this time for real). |
5054 | 5057 | ||
5055 | * Add support for "bmp info" and "bmp display" commands to load | 5058 | * Add support for "bmp info" and "bmp display" commands to load |
5056 | bitmap images; this can be used (for example in a "preboot" | 5059 | bitmap images; this can be used (for example in a "preboot" |
5057 | command) to display a splash screen very quickly after poweron. | 5060 | command) to display a splash screen very quickly after poweron. |
5058 | 5061 | ||
5059 | * Add support for 133 MHz clock on INCA-IP board | 5062 | * Add support for 133 MHz clock on INCA-IP board |
5060 | 5063 | ||
5061 | * Patch by Lutz Dennig, 10 Apr 2003: | 5064 | * Patch by Lutz Dennig, 10 Apr 2003: |
5062 | Update for R360MPI board | 5065 | Update for R360MPI board |
5063 | 5066 | ||
5064 | * Add new meaning to "autostart" environment variable: | 5067 | * Add new meaning to "autostart" environment variable: |
5065 | If set to "no", a standalone image passed to the | 5068 | If set to "no", a standalone image passed to the |
5066 | "bootm" command will be copied to the load address | 5069 | "bootm" command will be copied to the load address |
5067 | (and eventually uncompressed), but NOT be started. | 5070 | (and eventually uncompressed), but NOT be started. |
5068 | This can be used to load and uncompress arbitrary | 5071 | This can be used to load and uncompress arbitrary |
5069 | data. | 5072 | data. |
5070 | 5073 | ||
5071 | * Patch by Stefan Roese, 10 Apr 2003: | 5074 | * Patch by Stefan Roese, 10 Apr 2003: |
5072 | Changed DHCP client to use IP address from server option field #54 | 5075 | Changed DHCP client to use IP address from server option field #54 |
5073 | from the OFFER packet in the server option field #54 in the REQUEST | 5076 | from the OFFER packet in the server option field #54 in the REQUEST |
5074 | packet. This fixes a problem using a Windows 2000 DHCP server, | 5077 | packet. This fixes a problem using a Windows 2000 DHCP server, |
5075 | where the DHCP-server is not the TFTP-server. | 5078 | where the DHCP-server is not the TFTP-server. |
5076 | 5079 | ||
5077 | * Set max brightness for MN11236 displays on TRAB board | 5080 | * Set max brightness for MN11236 displays on TRAB board |
5078 | 5081 | ||
5079 | * Add support for TQM862L modules | 5082 | * Add support for TQM862L modules |
5080 | 5083 | ||
5081 | ====================================================================== | 5084 | ====================================================================== |
5082 | Changes for U-Boot 0.3.0: | 5085 | Changes for U-Boot 0.3.0: |
5083 | ====================================================================== | 5086 | ====================================================================== |
5084 | 5087 | ||
5085 | * Patch by Arun Dharankar, 4 Apr 2003: | 5088 | * Patch by Arun Dharankar, 4 Apr 2003: |
5086 | Add IDMA example code (tested on 8260 only) | 5089 | Add IDMA example code (tested on 8260 only) |
5087 | 5090 | ||
5088 | * Add support for Purple Board (MIPS64 5Kc) | 5091 | * Add support for Purple Board (MIPS64 5Kc) |
5089 | 5092 | ||
5090 | * Add support for MIPS64 5Kc CPUs | 5093 | * Add support for MIPS64 5Kc CPUs |
5091 | 5094 | ||
5092 | * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS | 5095 | * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS |
5093 | 5096 | ||
5094 | * Patch by Denis Peter, 04 Apr 2003: | 5097 | * Patch by Denis Peter, 04 Apr 2003: |
5095 | - update MIP405-4 board | 5098 | - update MIP405-4 board |
5096 | 5099 | ||
5097 | * Patch by Stefan Roese, 4 Apr 2003: | 5100 | * Patch by Stefan Roese, 4 Apr 2003: |
5098 | - U-Boot version environment variable "ver" added | 5101 | - U-Boot version environment variable "ver" added |
5099 | (CONFIG_VERSION_VARIABLE). | 5102 | (CONFIG_VERSION_VARIABLE). |
5100 | - Changed PPC405GPr version from A to B. | 5103 | - Changed PPC405GPr version from A to B. |
5101 | - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. | 5104 | - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. |
5102 | 5105 | ||
5103 | * Patches by Denis Peter, 03 April 2003: | 5106 | * Patches by Denis Peter, 03 April 2003: |
5104 | - fix PCI IRQs on MPL boards | 5107 | - fix PCI IRQs on MPL boards |
5105 | - fix two more un-relocated pointer problems | 5108 | - fix two more un-relocated pointer problems |
5106 | 5109 | ||
5107 | * Fix behaviour of "run" command: | 5110 | * Fix behaviour of "run" command: |
5108 | - print error message iv variable does not exist | 5111 | - print error message iv variable does not exist |
5109 | - terminate processing of arguments in case of error | 5112 | - terminate processing of arguments in case of error |
5110 | 5113 | ||
5111 | * Patches by Peter Figuli, 10 Mar 2003 | 5114 | * Patches by Peter Figuli, 10 Mar 2003 |
5112 | - Add support for BTUART on PXA platform | 5115 | - Add support for BTUART on PXA platform |
5113 | - Add support for WEP EP250 (PXA) board | 5116 | - Add support for WEP EP250 (PXA) board |
5114 | 5117 | ||
5115 | * Fix flash problems on INCA-IP; add tool to allow bruning images to | 5118 | * Fix flash problems on INCA-IP; add tool to allow bruning images to |
5116 | flash using a BDI2000 | 5119 | flash using a BDI2000 |
5117 | 5120 | ||
5118 | * Implement fix for I2C Edge Conditions problem for all boards that | 5121 | * Implement fix for I2C Edge Conditions problem for all boards that |
5119 | use the bit-banging driver (common/soft_i2c.c) | 5122 | use the bit-banging driver (common/soft_i2c.c) |
5120 | 5123 | ||
5121 | * Patch by Martin Winistoerfer, 23 Mar 2003 | 5124 | * Patch by Martin Winistoerfer, 23 Mar 2003 |
5122 | - Add port to MPC555/556 microcontrollers | 5125 | - Add port to MPC555/556 microcontrollers |
5123 | - Add support for cmi customer board with | 5126 | - Add support for cmi customer board with |
5124 | Intel 28F128J3A, 28F320J3A or 28F640J3A flash. | 5127 | Intel 28F128J3A, 28F320J3A or 28F640J3A flash. |
5125 | 5128 | ||
5126 | * Patch by Rick Bronson, 28 Mar 2003: | 5129 | * Patch by Rick Bronson, 28 Mar 2003: |
5127 | - fix common/cmd_nand.c | 5130 | - fix common/cmd_nand.c |
5128 | 5131 | ||
5129 | * Patch by Arun Dharankar, 24 Mar 2003: | 5132 | * Patch by Arun Dharankar, 24 Mar 2003: |
5130 | - add threads / scheduler example code | 5133 | - add threads / scheduler example code |
5131 | 5134 | ||
5132 | * Add patches by Robert Schwebel, 31 Mar 2003: | 5135 | * Add patches by Robert Schwebel, 31 Mar 2003: |
5133 | - add ctrl-c support for kermit download | 5136 | - add ctrl-c support for kermit download |
5134 | - align bdinfo output on ARM | 5137 | - align bdinfo output on ARM |
5135 | - csb226 board: bring in sync with innokom/memsetup.S | 5138 | - csb226 board: bring in sync with innokom/memsetup.S |
5136 | - csb226 board: fix MDREFR handling | 5139 | - csb226 board: fix MDREFR handling |
5137 | - misc doc fixes / extensions | 5140 | - misc doc fixes / extensions |
5138 | - innokom board: cleanup, MDREFR fix in memsetup.S, config update | 5141 | - innokom board: cleanup, MDREFR fix in memsetup.S, config update |
5139 | - add BOOT_PROGRESS to armlinux.c | 5142 | - add BOOT_PROGRESS to armlinux.c |
5140 | 5143 | ||
5141 | * Add CPU ID, version, and clock speed for INCA-IP | 5144 | * Add CPU ID, version, and clock speed for INCA-IP |
5142 | 5145 | ||
5143 | * Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board: | 5146 | * Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board: |
5144 | - fix SRAM and SDRAM memory sizing | 5147 | - fix SRAM and SDRAM memory sizing |
5145 | - add status LED support | 5148 | - add status LED support |
5146 | - add MAC address for second (SCC1) ethernet port | 5149 | - add MAC address for second (SCC1) ethernet port |
5147 | 5150 | ||
5148 | * Update default environment for TQM8260 board | 5151 | * Update default environment for TQM8260 board |
5149 | 5152 | ||
5150 | * Patch by Rick Bronson, 16 Mar 2003: | 5153 | * Patch by Rick Bronson, 16 Mar 2003: |
5151 | - Add NAND flash support for reading, writing, and erasing NAND | 5154 | - Add NAND flash support for reading, writing, and erasing NAND |
5152 | flash (certain forms of which are called SmartMedia). | 5155 | flash (certain forms of which are called SmartMedia). |
5153 | - Add support for Atmel AT91RM9200DK ARM920T based development kit. | 5156 | - Add support for Atmel AT91RM9200DK ARM920T based development kit. |
5154 | 5157 | ||
5155 | * Patches by Robert Schwebel, 19 Mar 2003: | 5158 | * Patches by Robert Schwebel, 19 Mar 2003: |
5156 | - use arm-linux-gcc as default compiler for ARM | 5159 | - use arm-linux-gcc as default compiler for ARM |
5157 | - fix i2c fixup code | 5160 | - fix i2c fixup code |
5158 | - fix missing baudrate setting | 5161 | - fix missing baudrate setting |
5159 | - added $loadaddr / CFG_LOAD_ADDR support to loadb | 5162 | - added $loadaddr / CFG_LOAD_ADDR support to loadb |
5160 | - moved "ignoring trailing characters" _before_ u-boot wants to | 5163 | - moved "ignoring trailing characters" _before_ u-boot wants to |
5161 | print out diagnostics messages; removes bogus characters at the | 5164 | print out diagnostics messages; removes bogus characters at the |
5162 | end of transmission | 5165 | end of transmission |
5163 | 5166 | ||
5164 | * Patch by John Zhan, 18 Mar 2003: | 5167 | * Patch by John Zhan, 18 Mar 2003: |
5165 | Add support for SinoVee Microsystems SC8xx boards | 5168 | Add support for SinoVee Microsystems SC8xx boards |
5166 | 5169 | ||
5167 | * Patch by Rolf Offermanns, 21 Mar 2003: | 5170 | * Patch by Rolf Offermanns, 21 Mar 2003: |
5168 | ported the dnp1110 related changes from the current armboot cvs to | 5171 | ported the dnp1110 related changes from the current armboot cvs to |
5169 | current u-boot cvs. smc91111 does not work. problem marked in | 5172 | current u-boot cvs. smc91111 does not work. problem marked in |
5170 | smc91111.c, grep for "FIXME". | 5173 | smc91111.c, grep for "FIXME". |
5171 | 5174 | ||
5172 | * Patch by Brian Auld, 25 Mar 2003: | 5175 | * Patch by Brian Auld, 25 Mar 2003: |
5173 | Add support for STM flash chips on ebony board | 5176 | Add support for STM flash chips on ebony board |
5174 | 5177 | ||
5175 | * Add PCI support for MPC8250 Boards (PM825 module) | 5178 | * Add PCI support for MPC8250 Boards (PM825 module) |
5176 | 5179 | ||
5177 | * Patch by Stefan Roese, 25 Mar 2003: | 5180 | * Patch by Stefan Roese, 25 Mar 2003: |
5178 | - PCI405 update. | 5181 | - PCI405 update. |
5179 | 5182 | ||
5180 | * Patch by Stefan Roese, 20 Mar 2003: | 5183 | * Patch by Stefan Roese, 20 Mar 2003: |
5181 | - CPCI4052 update (support for revision 3). | 5184 | - CPCI4052 update (support for revision 3). |
5182 | - Set edge conditioning circuitry on PPC405GPr for compatibility | 5185 | - Set edge conditioning circuitry on PPC405GPr for compatibility |
5183 | to existing PPC405GP designs. | 5186 | to existing PPC405GP designs. |
5184 | - Clip udiv to 5 bits on PPC405 (serial.c). | 5187 | - Clip udiv to 5 bits on PPC405 (serial.c). |
5185 | 5188 | ||
5186 | * Extend INCAIP board support: | 5189 | * Extend INCAIP board support: |
5187 | - add automatic RAM size detection | 5190 | - add automatic RAM size detection |
5188 | - add "bdinfo" command | 5191 | - add "bdinfo" command |
5189 | - pass flash address and size to Linux kernel | 5192 | - pass flash address and size to Linux kernel |
5190 | - switch to 150 MHz clock | 5193 | - switch to 150 MHz clock |
5191 | 5194 | ||
5192 | * Avoid flicker on the TRAB's VFD by synchronizing the enable with | 5195 | * Avoid flicker on the TRAB's VFD by synchronizing the enable with |
5193 | the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 | 5196 | the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 |
5194 | boards, version 153 for Rev. 200 boards). | 5197 | boards, version 153 for Rev. 200 boards). |
5195 | 5198 | ||
5196 | * Patch by Vladimir Gurevich, 12 Mar 2003: | 5199 | * Patch by Vladimir Gurevich, 12 Mar 2003: |
5197 | Fix relocation problem of statically initialized string pointers | 5200 | Fix relocation problem of statically initialized string pointers |
5198 | in common/cmd_pci.c | 5201 | in common/cmd_pci.c |
5199 | 5202 | ||
5200 | * Patch by Kai-Uwe Blรถm, 12 Mar 2003: | 5203 | * Patch by Kai-Uwe Blรถm, 12 Mar 2003: |
5201 | Cleanup & bug fixes for JFFS2 code: | 5204 | Cleanup & bug fixes for JFFS2 code: |
5202 | - the memory mangement was broken. It caused havoc on malloc by | 5205 | - the memory mangement was broken. It caused havoc on malloc by |
5203 | writing beyond the block boundaries. | 5206 | writing beyond the block boundaries. |
5204 | - the length calculation for files was wrong, sometimes resulting | 5207 | - the length calculation for files was wrong, sometimes resulting |
5205 | in short file reads. | 5208 | in short file reads. |
5206 | - data copying now optionally takes fragment version numbers into | 5209 | - data copying now optionally takes fragment version numbers into |
5207 | account, to avoid copying from older data. | 5210 | account, to avoid copying from older data. |
5208 | See doc/README.JFFS2 for details. | 5211 | See doc/README.JFFS2 for details. |
5209 | 5212 | ||
5210 | * Patch by Josef Wagner, 12 Mar 2003: | 5213 | * Patch by Josef Wagner, 12 Mar 2003: |
5211 | - 16/32 MB and 50/80 MHz support with auto-detection for IP860 | 5214 | - 16/32 MB and 50/80 MHz support with auto-detection for IP860 |
5212 | - ETH05 and BEDBUG support for CU824 | 5215 | - ETH05 and BEDBUG support for CU824 |
5213 | - added support for MicroSys CPC45 | 5216 | - added support for MicroSys CPC45 |
5214 | - new BOOTROM/FLASH0 and DOC base for PM826 | 5217 | - new BOOTROM/FLASH0 and DOC base for PM826 |
5215 | 5218 | ||
5216 | * Patch by Robert Schwebel, 12 Mar 2003: | 5219 | * Patch by Robert Schwebel, 12 Mar 2003: |
5217 | Fix the chpart command on innokom board | 5220 | Fix the chpart command on innokom board |
5218 | 5221 | ||
5219 | * Name cleanup: | 5222 | * Name cleanup: |
5220 | mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h | 5223 | mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h |
5221 | s/PPCBoot/U-Boot/ in some files | 5224 | s/PPCBoot/U-Boot/ in some files |
5222 | s/pImage/uImage/ in some files | 5225 | s/pImage/uImage/ in some files |
5223 | 5226 | ||
5224 | * Patch by Detlev Zundel, 15 Jan 2003: | 5227 | * Patch by Detlev Zundel, 15 Jan 2003: |
5225 | Fix '' command line quoting | 5228 | Fix '' command line quoting |
5226 | 5229 | ||
5227 | * Patch by The LEOX team, 19 Jan 2003: | 5230 | * Patch by The LEOX team, 19 Jan 2003: |
5228 | - add support for the ELPT860 board | 5231 | - add support for the ELPT860 board |
5229 | - add support for Dallas ds164x RTC | 5232 | - add support for Dallas ds164x RTC |
5230 | 5233 | ||
5231 | * Patches by David Mรผller, 31 Jan 2003: | 5234 | * Patches by David Mรผller, 31 Jan 2003: |
5232 | - minimal setup for CardBus bridges | 5235 | - minimal setup for CardBus bridges |
5233 | - add EEPROM read/write support in the CS8900 driver | 5236 | - add EEPROM read/write support in the CS8900 driver |
5234 | - add support for the builtin I2C controller in the Samsung s3c24x0 chips | 5237 | - add support for the builtin I2C controller in the Samsung s3c24x0 chips |
5235 | - add support for MPL's VCMA9 (Samsung s3c2410 based) board | 5238 | - add support for MPL's VCMA9 (Samsung s3c2410 based) board |
5236 | 5239 | ||
5237 | * Patch by Steven Scholz, 04 Feb 2003: | 5240 | * Patch by Steven Scholz, 04 Feb 2003: |
5238 | add support for RTC DS1307 | 5241 | add support for RTC DS1307 |
5239 | 5242 | ||
5240 | * Patch by Reinhard Meyer, 5 Feb 2003: | 5243 | * Patch by Reinhard Meyer, 5 Feb 2003: |
5241 | fix PLPRCR/SCCR init sequence on 8xx to allow for | 5244 | fix PLPRCR/SCCR init sequence on 8xx to allow for |
5242 | changes of EBDF by software | 5245 | changes of EBDF by software |
5243 | 5246 | ||
5244 | * Patch by Vladimir Gurevich, 07 Feb 2003: | 5247 | * Patch by Vladimir Gurevich, 07 Feb 2003: |
5245 | "API-compatibility patch" for 4xx I2C driver | 5248 | "API-compatibility patch" for 4xx I2C driver |
5246 | 5249 | ||
5247 | * TRAB fixes / extensions: | 5250 | * TRAB fixes / extensions: |
5248 | - Restore VFD brightness as saved in environment | 5251 | - Restore VFD brightness as saved in environment |
5249 | - add support for Fujitsu flashes | 5252 | - add support for Fujitsu flashes |
5250 | - make sure both buzzers are turned off (drive low level) | 5253 | - make sure both buzzers are turned off (drive low level) |
5251 | 5254 | ||
5252 | * Patches by Robert Schwebel, 06 Mar 2003: | 5255 | * Patches by Robert Schwebel, 06 Mar 2003: |
5253 | - fix bug in BOOTP code (must use NetCopyIP) | 5256 | - fix bug in BOOTP code (must use NetCopyIP) |
5254 | - update of CSB226 port | 5257 | - update of CSB226 port |
5255 | - clear BSS segment on XScale | 5258 | - clear BSS segment on XScale |
5256 | - added support for i2c_init_board() function | 5259 | - added support for i2c_init_board() function |
5257 | - update to the Innokom plattform | 5260 | - update to the Innokom plattform |
5258 | 5261 | ||
5259 | * Extend support for redundand environments for configurations where | 5262 | * Extend support for redundand environments for configurations where |
5260 | environment size < sector size | 5263 | environment size < sector size |
5261 | 5264 | ||
5262 | * Patch by Rune Torgersen, 13 Feb 2003: | 5265 | * Patch by Rune Torgersen, 13 Feb 2003: |
5263 | Add support for Motorola MPC8266ADS board | 5266 | Add support for Motorola MPC8266ADS board |
5264 | 5267 | ||
5265 | * Patch by Kyle Harris, 19 Feb 2003: | 5268 | * Patch by Kyle Harris, 19 Feb 2003: |
5266 | patches for the Intel lubbock board: | 5269 | patches for the Intel lubbock board: |
5267 | memsetup.S - general cleanup (based on Robert's csb226 code) | 5270 | memsetup.S - general cleanup (based on Robert's csb226 code) |
5268 | flash.c - overhaul, actually works now | 5271 | flash.c - overhaul, actually works now |
5269 | lubbock.c - fix init funcs to return proper value | 5272 | lubbock.c - fix init funcs to return proper value |
5270 | 5273 | ||
5271 | * Patch by Kenneth Johansson, 26 Feb 2003: | 5274 | * Patch by Kenneth Johansson, 26 Feb 2003: |
5272 | - Fixed off by one in RFTA calculation. | 5275 | - Fixed off by one in RFTA calculation. |
5273 | - No need to abort when LDF is lower than we can program it's only | 5276 | - No need to abort when LDF is lower than we can program it's only |
5274 | minimum timing so clamp it to what we can do. | 5277 | minimum timing so clamp it to what we can do. |
5275 | - Takes function pointer to function for reading the spd_nvram. Usefull | 5278 | - Takes function pointer to function for reading the spd_nvram. Usefull |
5276 | for faking data or hardcode a module without the nvram. | 5279 | for faking data or hardcode a module without the nvram. |
5277 | - fix other user for above change | 5280 | - fix other user for above change |
5278 | - fix some comments. | 5281 | - fix some comments. |
5279 | 5282 | ||
5280 | * Patches by Brian Waite, 26 Feb 2003: | 5283 | * Patches by Brian Waite, 26 Feb 2003: |
5281 | - fix port for evb64260 board | 5284 | - fix port for evb64260 board |
5282 | - fix PCI for evb64260 board | 5285 | - fix PCI for evb64260 board |
5283 | - fix PCI scan | 5286 | - fix PCI scan |
5284 | 5287 | ||
5285 | * Patch by Reinhard Meyer, 1 Mar 2003: | 5288 | * Patch by Reinhard Meyer, 1 Mar 2003: |
5286 | Add support for EMK TOP860 Module | 5289 | Add support for EMK TOP860 Module |
5287 | 5290 | ||
5288 | * Patch by Yuli Barcohen, 02 Mar 2003: | 5291 | * Patch by Yuli Barcohen, 02 Mar 2003: |
5289 | Add SPD EEPROM support for MPC8260ADS board | 5292 | Add SPD EEPROM support for MPC8260ADS board |
5290 | 5293 | ||
5291 | * Patch by Robert Schwebel, 21 Jan 2003: | 5294 | * Patch by Robert Schwebel, 21 Jan 2003: |
5292 | - Add support for Innokom board | 5295 | - Add support for Innokom board |
5293 | - Don't complain if "install" fails | 5296 | - Don't complain if "install" fails |
5294 | - README cleanup (remove duplicated lines) | 5297 | - README cleanup (remove duplicated lines) |
5295 | - Update PXA header files | 5298 | - Update PXA header files |
5296 | 5299 | ||
5297 | * Add documentation for existing POST code (doc/README.POST) | 5300 | * Add documentation for existing POST code (doc/README.POST) |
5298 | 5301 | ||
5299 | * Patch by Laudney Ren, 15 Jan 2003: | 5302 | * Patch by Laudney Ren, 15 Jan 2003: |
5300 | Fix handling of redundand environment in "tools/envcrc.c" | 5303 | Fix handling of redundand environment in "tools/envcrc.c" |
5301 | 5304 | ||
5302 | * Patch by Detlev Zundel, 28 Feb 2003: | 5305 | * Patch by Detlev Zundel, 28 Feb 2003: |
5303 | Add bedbug support for 824x systems | 5306 | Add bedbug support for 824x systems |
5304 | 5307 | ||
5305 | * Add support for 16 MB flash configuration of TRAB board | 5308 | * Add support for 16 MB flash configuration of TRAB board |
5306 | 5309 | ||
5307 | * Patch by Erwin Rol, 27 Feb 2003: | 5310 | * Patch by Erwin Rol, 27 Feb 2003: |
5308 | Add support for RTEMS | 5311 | Add support for RTEMS |
5309 | 5312 | ||
5310 | * Add image information to README | 5313 | * Add image information to README |
5311 | 5314 | ||
5312 | * Patch by Stefan Roese, 18 Feb 2003: | 5315 | * Patch by Stefan Roese, 18 Feb 2003: |
5313 | CPCIISER4 configuration updated. | 5316 | CPCIISER4 configuration updated. |
5314 | 5317 | ||
5315 | * Patch by Stefan Roese, 17 Feb 2003: | 5318 | * Patch by Stefan Roese, 17 Feb 2003: |
5316 | Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port). | 5319 | Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port). |
5317 | 5320 | ||
5318 | * Patch by Stefan Roese, 13 Feb 2003: | 5321 | * Patch by Stefan Roese, 13 Feb 2003: |
5319 | Add "pcidelay" environment variable (in ms, enabled via | 5322 | Add "pcidelay" environment variable (in ms, enabled via |
5320 | CONFIG_PCI_BOOTDELAY). | 5323 | CONFIG_PCI_BOOTDELAY). |
5321 | PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after | 5324 | PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after |
5322 | RST# to respond to configuration cycles (33MHz -> 1s). | 5325 | RST# to respond to configuration cycles (33MHz -> 1s). |
5323 | 5326 | ||
5324 | * Fix dual PCMCIA slot support (when running with just one | 5327 | * Fix dual PCMCIA slot support (when running with just one |
5325 | slot populated) | 5328 | slot populated) |
5326 | 5329 | ||
5327 | * Add VFD type detection to trab board | 5330 | * Add VFD type detection to trab board |
5328 | 5331 | ||
5329 | * extend drivers/cs8900.c driver to synchronize ethaddr environment | 5332 | * extend drivers/cs8900.c driver to synchronize ethaddr environment |
5330 | variable with value in the EEPROM | 5333 | variable with value in the EEPROM |
5331 | 5334 | ||
5332 | * Patch by Stefan Roese, 10 Feb 2003: | 5335 | * Patch by Stefan Roese, 10 Feb 2003: |
5333 | Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) | 5336 | Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) |
5334 | 5337 | ||
5335 | * Add support for MIPS32 4Kc CPUs | 5338 | * Add support for MIPS32 4Kc CPUs |
5336 | 5339 | ||
5337 | * Add support for INCA-IP Board | 5340 | * Add support for INCA-IP Board |
5338 | 5341 | ||
5339 | ====================================================================== | 5342 | ====================================================================== |
5340 | Changes for U-Boot 0.2.2: | 5343 | Changes for U-Boot 0.2.2: |
5341 | ====================================================================== | 5344 | ====================================================================== |
5342 | 5345 | ||
5343 | * Add dual ethernet support on PM826 | 5346 | * Add dual ethernet support on PM826 |
5344 | 5347 | ||
5345 | * Add support for LXT971 PHY on PM826 | 5348 | * Add support for LXT971 PHY on PM826 |
5346 | 5349 | ||
5347 | * Patch by Tord Andersson, 16 Jan 2003: | 5350 | * Patch by Tord Andersson, 16 Jan 2003: |
5348 | Fix flash sector count for TQM8xxL | 5351 | Fix flash sector count for TQM8xxL |
5349 | 5352 | ||
5350 | * Fix I2C EEPROM problem on ICU862 board (would only write the first | 5353 | * Fix I2C EEPROM problem on ICU862 board (would only write the first |
5351 | 16 bytes out of each 32 byte block) | 5354 | 16 bytes out of each 32 byte block) |
5352 | 5355 | ||
5353 | ====================================================================== | 5356 | ====================================================================== |
5354 | Changes for U-Boot 0.2.1: | 5357 | Changes for U-Boot 0.2.1: |
5355 | ====================================================================== | 5358 | ====================================================================== |
5356 | 5359 | ||
5357 | * Add support for V37 board | 5360 | * Add support for V37 board |
5358 | (patch by Jรณn Benediktsson, 11 Dec 2002) | 5361 | (patch by Jรณn Benediktsson, 11 Dec 2002) |
5359 | 5362 | ||
5360 | * Update baudrate in bd_info when it gets changed | 5363 | * Update baudrate in bd_info when it gets changed |
5361 | 5364 | ||
5362 | * Add watchdog trigger points while waiting for serial port | 5365 | * Add watchdog trigger points while waiting for serial port |
5363 | (so far only 8xx -- needed on LWMON with 100ms watchdog) | 5366 | (so far only 8xx -- needed on LWMON with 100ms watchdog) |
5364 | 5367 | ||
5365 | * Improve command line tool to access the U-Boot's environment | 5368 | * Improve command line tool to access the U-Boot's environment |
5366 | (figuration of the utility, using a config file) | 5369 | (figuration of the utility, using a config file) |
5367 | 5370 | ||
5368 | * Add single quote support for (old) command line parser | 5371 | * Add single quote support for (old) command line parser |
5369 | 5372 | ||
5370 | * Switch LWMON board default config from FRAM to EEPROM; | 5373 | * Switch LWMON board default config from FRAM to EEPROM; |
5371 | in POST, EEPROM shows up on 8 addresses | 5374 | in POST, EEPROM shows up on 8 addresses |
5372 | 5375 | ||
5373 | ====================================================================== | 5376 | ====================================================================== |
5374 | Changes for U-Boot 0.2.0: | 5377 | Changes for U-Boot 0.2.0: |
5375 | ====================================================================== | 5378 | ====================================================================== |
5376 | 5379 | ||
5377 | * Use 1-byte-read instead of -write for iprobe() function | 5380 | * Use 1-byte-read instead of -write for iprobe() function |
5378 | Add i2c commands to PM826 config | 5381 | Add i2c commands to PM826 config |
5379 | 5382 | ||
5380 | * extend I2C POST code: check for list on known addresses | 5383 | * extend I2C POST code: check for list on known addresses |
5381 | 5384 | ||
5382 | * Improve log buffer code; use "loglevel" to decide which messages | 5385 | * Improve log buffer code; use "loglevel" to decide which messages |
5383 | to log on the console, too (like in Linux); get rid of "logstart" | 5386 | to log on the console, too (like in Linux); get rid of "logstart" |
5384 | 5387 | ||
5385 | * Add command line tool to access the U-Boot's environment | 5388 | * Add command line tool to access the U-Boot's environment |
5386 | (board-specific for TRAB now, to be fixed later) | 5389 | (board-specific for TRAB now, to be fixed later) |
5387 | 5390 | ||
5388 | * Patch by Hans-Joerg Frieden, 06 Dec 2002 | 5391 | * Patch by Hans-Joerg Frieden, 06 Dec 2002 |
5389 | Fix misc problems with AmigaOne support | 5392 | Fix misc problems with AmigaOne support |
5390 | 5393 | ||
5391 | * Patch by Chris Hallinan, 3 Dec 2002: | 5394 | * Patch by Chris Hallinan, 3 Dec 2002: |
5392 | minor cleanup to the MPC8245 EPIC driver | 5395 | minor cleanup to the MPC8245 EPIC driver |
5393 | 5396 | ||
5394 | * Patch by Pierre Aubert , 28 Nov 2002 | 5397 | * Patch by Pierre Aubert , 28 Nov 2002 |
5395 | Add support for external (SIU) interrupts on MPC8xx | 5398 | Add support for external (SIU) interrupts on MPC8xx |
5396 | 5399 | ||
5397 | * Patch by Pierre Aubert , 28 Nov 2002 | 5400 | * Patch by Pierre Aubert , 28 Nov 2002 |
5398 | Fix nested syscalls bug in standalone applications | 5401 | Fix nested syscalls bug in standalone applications |
5399 | 5402 | ||
5400 | * Patch by David Mรผller, 27 Nov 2002: | 5403 | * Patch by David Mรผller, 27 Nov 2002: |
5401 | fix output of "pciinfo" command for CardBus bridge devices. | 5404 | fix output of "pciinfo" command for CardBus bridge devices. |
5402 | 5405 | ||
5403 | * Fix bug in TQM8260 board detection - boards got stuck when board ID | 5406 | * Fix bug in TQM8260 board detection - boards got stuck when board ID |
5404 | was not readable | 5407 | was not readable |
5405 | 5408 | ||
5406 | * Add LED indication for IDE activity on KUP4K board | 5409 | * Add LED indication for IDE activity on KUP4K board |
5407 | 5410 | ||
5408 | * Fix startup problems with VFD display on TRAB | 5411 | * Fix startup problems with VFD display on TRAB |
5409 | 5412 | ||
5410 | * Patch by Pierre Aubert, 20 Nov 2002 | 5413 | * Patch by Pierre Aubert, 20 Nov 2002 |
5411 | Add driver for Epson SED13806 graphic controller. | 5414 | Add driver for Epson SED13806 graphic controller. |
5412 | Add support for BMP logos in cfb_console driver. | 5415 | Add support for BMP logos in cfb_console driver. |
5413 | 5416 | ||
5414 | * Added support for both PCMCIA slots (at the same time!) on MPC8xx | 5417 | * Added support for both PCMCIA slots (at the same time!) on MPC8xx |
5415 | 5418 | ||
5416 | * Patch by Rod Boyce, 21 Nov 2002: | 5419 | * Patch by Rod Boyce, 21 Nov 2002: |
5417 | fix PCMCIA on MBX8xx board | 5420 | fix PCMCIA on MBX8xx board |
5418 | 5421 | ||
5419 | * Patch by Pierre Aubert , 21 Nov 2002 | 5422 | * Patch by Pierre Aubert , 21 Nov 2002 |
5420 | Add CFG_CPM_POST_WORD_ADDR to make the offset of the | 5423 | Add CFG_CPM_POST_WORD_ADDR to make the offset of the |
5421 | bootmode word in DPRAM configurable | 5424 | bootmode word in DPRAM configurable |
5422 | 5425 | ||
5423 | * Patch by Daniel Engstrรถm, 18 Nov 2002: | 5426 | * Patch by Daniel Engstrรถm, 18 Nov 2002: |
5424 | Fixes for x86 port (mostly strings issues) | 5427 | Fixes for x86 port (mostly strings issues) |
5425 | 5428 | ||
5426 | * Patch by Ken Chou, 18 Nov 2002: | 5429 | * Patch by Ken Chou, 18 Nov 2002: |
5427 | Fix for natsemi NIC cards (DP83815) | 5430 | Fix for natsemi NIC cards (DP83815) |
5428 | 5431 | ||
5429 | * Patch by Pierre Aubert, 19 Nov 2002: | 5432 | * Patch by Pierre Aubert, 19 Nov 2002: |
5430 | fix a bug for the MII configuration, and some warnings | 5433 | fix a bug for the MII configuration, and some warnings |
5431 | 5434 | ||
5432 | * Patch by Thomas Frieden, 13 Nov 2002: | 5435 | * Patch by Thomas Frieden, 13 Nov 2002: |
5433 | Add code for AmigaOne board | 5436 | Add code for AmigaOne board |
5434 | (preliminary merge to U-Boot, still WIP) | 5437 | (preliminary merge to U-Boot, still WIP) |
5435 | 5438 | ||
5436 | * Patch by Jon Diekema, 12 Nov 2002: | 5439 | * Patch by Jon Diekema, 12 Nov 2002: |
5437 | - Adding URL for IEEE OUI lookup | 5440 | - Adding URL for IEEE OUI lookup |
5438 | - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED | 5441 | - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED |
5439 | being defined. | 5442 | being defined. |
5440 | - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and | 5443 | - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and |
5441 | root-on-nfs macros are designed to switch how the default boot | 5444 | root-on-nfs macros are designed to switch how the default boot |
5442 | method gets defined. | 5445 | method gets defined. |
5443 | 5446 | ||
5444 | * Patch by Daniel Engstrรถm, 13 Nov 2002: | 5447 | * Patch by Daniel Engstrรถm, 13 Nov 2002: |
5445 | Add support for i386 architecture and AMD SC520 board | 5448 | Add support for i386 architecture and AMD SC520 board |
5446 | 5449 | ||
5447 | * Patch by Pierre Aubert, 12 Nov 2002: | 5450 | * Patch by Pierre Aubert, 12 Nov 2002: |
5448 | Add support for DOS filesystem and booting from DOS floppy disk | 5451 | Add support for DOS filesystem and booting from DOS floppy disk |
5449 | 5452 | ||
5450 | * Patch by Jim Sandoz, 07 Nov 2002: | 5453 | * Patch by Jim Sandoz, 07 Nov 2002: |
5451 | Increase number of network RX buffers (PKTBUFSRX in | 5454 | Increase number of network RX buffers (PKTBUFSRX in |
5452 | "include/net.h") for EEPRO100 based boards (especially SP8240) | 5455 | "include/net.h") for EEPRO100 based boards (especially SP8240) |
5453 | which showed "Receiver is not ready" errors when U-Boot was | 5456 | which showed "Receiver is not ready" errors when U-Boot was |
5454 | processing the receive buffers slower than the network controller | 5457 | processing the receive buffers slower than the network controller |
5455 | was filling them. | 5458 | was filling them. |
5456 | 5459 | ||
5457 | * Patch by Andreas Oberritter, 09 Nov 2002: | 5460 | * Patch by Andreas Oberritter, 09 Nov 2002: |
5458 | Change behaviour of NetLoop(): return -1 for errors, filesize | 5461 | Change behaviour of NetLoop(): return -1 for errors, filesize |
5459 | otherwise; return code 0 is valid an means no file loaded - in this | 5462 | otherwise; return code 0 is valid an means no file loaded - in this |
5460 | case the environment still gets updated! | 5463 | case the environment still gets updated! |
5461 | 5464 | ||
5462 | * Patches by Jon Diekema, 9 Nov 2002: | 5465 | * Patches by Jon Diekema, 9 Nov 2002: |
5463 | - improve ADC/DAC clocking on the SACSng board to align | 5466 | - improve ADC/DAC clocking on the SACSng board to align |
5464 | the failing edges of LRCLK and SCLK | 5467 | the failing edges of LRCLK and SCLK |
5465 | - sbc8260 configuration tweaks | 5468 | - sbc8260 configuration tweaks |
5466 | - add status LED support for 82xx systems | 5469 | - add status LED support for 82xx systems |
5467 | - wire sspi/sspo commands into command handler; improved error | 5470 | - wire sspi/sspo commands into command handler; improved error |
5468 | handlering | 5471 | handlering |
5469 | - add timestamp support and alternate memory test to the | 5472 | - add timestamp support and alternate memory test to the |
5470 | SACSng configuration | 5473 | SACSng configuration |
5471 | 5474 | ||
5472 | * Patch by Vince Husovsky, 7 Nov 2002: | 5475 | * Patch by Vince Husovsky, 7 Nov 2002: |
5473 | Add "-n" to linker options to get rid of "Not enough room for | 5476 | Add "-n" to linker options to get rid of "Not enough room for |
5474 | program headers" problem | 5477 | program headers" problem |
5475 | 5478 | ||
5476 | * Patch by David Mรผller, 05 Nov 2002 | 5479 | * Patch by David Mรผller, 05 Nov 2002 |
5477 | Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ | 5480 | Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ |
5478 | so we can use an already existing name | 5481 | so we can use an already existing name |
5479 | 5482 | ||
5480 | * Patch by Pierre Aubert, 05 Nov 2002 | 5483 | * Patch by Pierre Aubert, 05 Nov 2002 |
5481 | Hardware relatied improvments in FDC boot code | 5484 | Hardware relatied improvments in FDC boot code |
5482 | 5485 | ||
5483 | * Patch by Holger Schurig, 5 Nov 2002: | 5486 | * Patch by Holger Schurig, 5 Nov 2002: |
5484 | Make the PXA really change it's frequency | 5487 | Make the PXA really change it's frequency |
5485 | 5488 | ||
5486 | * Patch by Pierre Aubert, 05 Nov 2002 | 5489 | * Patch by Pierre Aubert, 05 Nov 2002 |
5487 | Add support for slave serial Spartan 2 FPGAs | 5490 | Add support for slave serial Spartan 2 FPGAs |
5488 | 5491 | ||
5489 | * Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet | 5492 | * Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet |
5490 | drivers | 5493 | drivers |
5491 | 5494 | ||
5492 | * Add support for log buffer which can be passed to Linux kernel's | 5495 | * Add support for log buffer which can be passed to Linux kernel's |
5493 | syslog mechanism; used especially for POST results. | 5496 | syslog mechanism; used especially for POST results. |
5494 | 5497 | ||
5495 | * Patch by Klaus Heydeck, 31 Oct 2002: | 5498 | * Patch by Klaus Heydeck, 31 Oct 2002: |
5496 | Add initial support for kup4k board | 5499 | Add initial support for kup4k board |
5497 | 5500 | ||
5498 | * Patch by Robert Schwebel, 04 Nov 2002: | 5501 | * Patch by Robert Schwebel, 04 Nov 2002: |
5499 | - use watchdog to reset PXA250 systems | 5502 | - use watchdog to reset PXA250 systems |
5500 | - added progress callbacks to (some of the) ARM code | 5503 | - added progress callbacks to (some of the) ARM code |
5501 | - update for Cogent CSB226 board | 5504 | - update for Cogent CSB226 board |
5502 | 5505 | ||
5503 | * Add support for FPS860 board | 5506 | * Add support for FPS860 board |
5504 | 5507 | ||
5505 | * Patch by Guillaume Alexandre,, 04 Nov 2002: | 5508 | * Patch by Guillaume Alexandre,, 04 Nov 2002: |
5506 | Improve PCI access on 32-bits Compact PCI bus | 5509 | Improve PCI access on 32-bits Compact PCI bus |
5507 | 5510 | ||
5508 | * Fix mdelay() on TRAB - this was still the debugging version with | 5511 | * Fix mdelay() on TRAB - this was still the debugging version with |
5509 | seconds instead of ms. | 5512 | seconds instead of ms. |
5510 | 5513 | ||
5511 | * Patch by Robert Schwebel, 1 Nov 2002: | 5514 | * Patch by Robert Schwebel, 1 Nov 2002: |
5512 | XScale related cleanup (affects all ARM boards) | 5515 | XScale related cleanup (affects all ARM boards) |
5513 | 5516 | ||
5514 | * Cleanup of names and README. | 5517 | * Cleanup of names and README. |
5515 | 5518 | ||
5516 | ====================================================================== | 5519 | ====================================================================== |
5517 | Notes for U-Boot 0.1.0: | 5520 | Notes for U-Boot 0.1.0: |
5518 | ====================================================================== | 5521 | ====================================================================== |
5519 | 5522 | ||
5520 | This is the initial version of "Das U-Boot", the Universal Boot Loader. | 5523 | This is the initial version of "Das U-Boot", the Universal Boot Loader. |
5521 | 5524 | ||
5522 | It is based on version 2.0.0 (the "Halloween Release") of PPCBoot. | 5525 | It is based on version 2.0.0 (the "Halloween Release") of PPCBoot. |
5523 | For information about the history of the project please see the | 5526 | For information about the history of the project please see the |
5524 | PPCBoot project page at http://sourceforge.net/projects/ppcboot | 5527 | PPCBoot project page at http://sourceforge.net/projects/ppcboot |
5525 | 5528 | ||
5526 | ====================================================================== | 5529 | ====================================================================== |
5527 | 5530 |
include/ppc440.h
1 | /*----------------------------------------------------------------------------+ | 1 | /*----------------------------------------------------------------------------+ |
2 | | | 2 | | |
3 | | This source code has been made available to you by IBM on an AS-IS | 3 | | This source code has been made available to you by IBM on an AS-IS |
4 | | basis. Anyone receiving this source is licensed under IBM | 4 | | basis. Anyone receiving this source is licensed under IBM |
5 | | copyrights to use it in any way he or she deems fit, including | 5 | | copyrights to use it in any way he or she deems fit, including |
6 | | copying it, modifying it, compiling it, and redistributing it either | 6 | | copying it, modifying it, compiling it, and redistributing it either |
7 | | with or without modifications. No license under IBM patents or | 7 | | with or without modifications. No license under IBM patents or |
8 | | patent applications is to be implied by the copyright license. | 8 | | patent applications is to be implied by the copyright license. |
9 | | | 9 | | |
10 | | Any user of this software should understand that IBM cannot provide | 10 | | Any user of this software should understand that IBM cannot provide |
11 | | technical support for this software and will not be responsible for | 11 | | technical support for this software and will not be responsible for |
12 | | any consequences resulting from the use of this software. | 12 | | any consequences resulting from the use of this software. |
13 | | | 13 | | |
14 | | Any person who transfers this source code or any derivative work | 14 | | Any person who transfers this source code or any derivative work |
15 | | must include the IBM copyright notice, this paragraph, and the | 15 | | must include the IBM copyright notice, this paragraph, and the |
16 | | preceding two paragraphs in the transferred software. | 16 | | preceding two paragraphs in the transferred software. |
17 | | | 17 | | |
18 | | COPYRIGHT I B M CORPORATION 1999 | 18 | | COPYRIGHT I B M CORPORATION 1999 |
19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
20 | +----------------------------------------------------------------------------*/ | 20 | +----------------------------------------------------------------------------*/ |
21 | 21 | ||
22 | #ifndef __PPC440_H__ | 22 | #ifndef __PPC440_H__ |
23 | #define __PPC440_H__ | 23 | #define __PPC440_H__ |
24 | 24 | ||
25 | /*--------------------------------------------------------------------- */ | 25 | /*--------------------------------------------------------------------- */ |
26 | /* Special Purpose Registers */ | 26 | /* Special Purpose Registers */ |
27 | /*--------------------------------------------------------------------- */ | 27 | /*--------------------------------------------------------------------- */ |
28 | #define xer_reg 0x001 | 28 | #define xer_reg 0x001 |
29 | #define lr_reg 0x008 | 29 | #define lr_reg 0x008 |
30 | #define dec 0x016 /* decrementer */ | 30 | #define dec 0x016 /* decrementer */ |
31 | #define srr0 0x01a /* save/restore register 0 */ | 31 | #define srr0 0x01a /* save/restore register 0 */ |
32 | #define srr1 0x01b /* save/restore register 1 */ | 32 | #define srr1 0x01b /* save/restore register 1 */ |
33 | #define pid 0x030 /* process id */ | 33 | #define pid 0x030 /* process id */ |
34 | #define decar 0x036 /* decrementer auto-reload */ | 34 | #define decar 0x036 /* decrementer auto-reload */ |
35 | #define csrr0 0x03a /* critical save/restore register 0 */ | 35 | #define csrr0 0x03a /* critical save/restore register 0 */ |
36 | #define csrr1 0x03b /* critical save/restore register 1 */ | 36 | #define csrr1 0x03b /* critical save/restore register 1 */ |
37 | #define dear 0x03d /* data exception address register */ | 37 | #define dear 0x03d /* data exception address register */ |
38 | #define esr 0x03e /* exception syndrome register */ | 38 | #define esr 0x03e /* exception syndrome register */ |
39 | #define ivpr 0x03f /* interrupt prefix register */ | 39 | #define ivpr 0x03f /* interrupt prefix register */ |
40 | #define usprg0 0x100 /* user special purpose register general 0 */ | 40 | #define usprg0 0x100 /* user special purpose register general 0 */ |
41 | #define usprg1 0x110 /* user special purpose register general 1 */ | 41 | #define usprg1 0x110 /* user special purpose register general 1 */ |
42 | #define tblr 0x10c /* time base lower, read only */ | 42 | #define tblr 0x10c /* time base lower, read only */ |
43 | #define tbur 0x10d /* time base upper, read only */ | 43 | #define tbur 0x10d /* time base upper, read only */ |
44 | #define sprg1 0x111 /* special purpose register general 1 */ | 44 | #define sprg1 0x111 /* special purpose register general 1 */ |
45 | #define sprg2 0x112 /* special purpose register general 2 */ | 45 | #define sprg2 0x112 /* special purpose register general 2 */ |
46 | #define sprg3 0x113 /* special purpose register general 3 */ | 46 | #define sprg3 0x113 /* special purpose register general 3 */ |
47 | #define sprg4 0x114 /* special purpose register general 4 */ | 47 | #define sprg4 0x114 /* special purpose register general 4 */ |
48 | #define sprg5 0x115 /* special purpose register general 5 */ | 48 | #define sprg5 0x115 /* special purpose register general 5 */ |
49 | #define sprg6 0x116 /* special purpose register general 6 */ | 49 | #define sprg6 0x116 /* special purpose register general 6 */ |
50 | #define sprg7 0x117 /* special purpose register general 7 */ | 50 | #define sprg7 0x117 /* special purpose register general 7 */ |
51 | #define tbl 0x11c /* time base lower (supervisor)*/ | 51 | #define tbl 0x11c /* time base lower (supervisor)*/ |
52 | #define tbu 0x11d /* time base upper (supervisor)*/ | 52 | #define tbu 0x11d /* time base upper (supervisor)*/ |
53 | #define pir 0x11e /* processor id register */ | 53 | #define pir 0x11e /* processor id register */ |
54 | /*#define pvr 0x11f processor version register */ | 54 | /*#define pvr 0x11f processor version register */ |
55 | #define dbsr 0x130 /* debug status register */ | 55 | #define dbsr 0x130 /* debug status register */ |
56 | #define dbcr0 0x134 /* debug control register 0 */ | 56 | #define dbcr0 0x134 /* debug control register 0 */ |
57 | #define dbcr1 0x135 /* debug control register 1 */ | 57 | #define dbcr1 0x135 /* debug control register 1 */ |
58 | #define dbcr2 0x136 /* debug control register 2 */ | 58 | #define dbcr2 0x136 /* debug control register 2 */ |
59 | #define iac1 0x138 /* instruction address compare 1 */ | 59 | #define iac1 0x138 /* instruction address compare 1 */ |
60 | #define iac2 0x139 /* instruction address compare 2 */ | 60 | #define iac2 0x139 /* instruction address compare 2 */ |
61 | #define iac3 0x13a /* instruction address compare 3 */ | 61 | #define iac3 0x13a /* instruction address compare 3 */ |
62 | #define iac4 0x13b /* instruction address compare 4 */ | 62 | #define iac4 0x13b /* instruction address compare 4 */ |
63 | #define dac1 0x13c /* data address compare 1 */ | 63 | #define dac1 0x13c /* data address compare 1 */ |
64 | #define dac2 0x13d /* data address compare 2 */ | 64 | #define dac2 0x13d /* data address compare 2 */ |
65 | #define dvc1 0x13e /* data value compare 1 */ | 65 | #define dvc1 0x13e /* data value compare 1 */ |
66 | #define dvc2 0x13f /* data value compare 2 */ | 66 | #define dvc2 0x13f /* data value compare 2 */ |
67 | #define tsr 0x150 /* timer status register */ | 67 | #define tsr 0x150 /* timer status register */ |
68 | #define tcr 0x154 /* timer control register */ | 68 | #define tcr 0x154 /* timer control register */ |
69 | #define ivor0 0x190 /* interrupt vector offset register 0 */ | 69 | #define ivor0 0x190 /* interrupt vector offset register 0 */ |
70 | #define ivor1 0x191 /* interrupt vector offset register 1 */ | 70 | #define ivor1 0x191 /* interrupt vector offset register 1 */ |
71 | #define ivor2 0x192 /* interrupt vector offset register 2 */ | 71 | #define ivor2 0x192 /* interrupt vector offset register 2 */ |
72 | #define ivor3 0x193 /* interrupt vector offset register 3 */ | 72 | #define ivor3 0x193 /* interrupt vector offset register 3 */ |
73 | #define ivor4 0x194 /* interrupt vector offset register 4 */ | 73 | #define ivor4 0x194 /* interrupt vector offset register 4 */ |
74 | #define ivor5 0x195 /* interrupt vector offset register 5 */ | 74 | #define ivor5 0x195 /* interrupt vector offset register 5 */ |
75 | #define ivor6 0x196 /* interrupt vector offset register 6 */ | 75 | #define ivor6 0x196 /* interrupt vector offset register 6 */ |
76 | #define ivor7 0x197 /* interrupt vector offset register 7 */ | 76 | #define ivor7 0x197 /* interrupt vector offset register 7 */ |
77 | #define ivor8 0x198 /* interrupt vector offset register 8 */ | 77 | #define ivor8 0x198 /* interrupt vector offset register 8 */ |
78 | #define ivor9 0x199 /* interrupt vector offset register 9 */ | 78 | #define ivor9 0x199 /* interrupt vector offset register 9 */ |
79 | #define ivor10 0x19a /* interrupt vector offset register 10 */ | 79 | #define ivor10 0x19a /* interrupt vector offset register 10 */ |
80 | #define ivor11 0x19b /* interrupt vector offset register 11 */ | 80 | #define ivor11 0x19b /* interrupt vector offset register 11 */ |
81 | #define ivor12 0x19c /* interrupt vector offset register 12 */ | 81 | #define ivor12 0x19c /* interrupt vector offset register 12 */ |
82 | #define ivor13 0x19d /* interrupt vector offset register 13 */ | 82 | #define ivor13 0x19d /* interrupt vector offset register 13 */ |
83 | #define ivor14 0x19e /* interrupt vector offset register 14 */ | 83 | #define ivor14 0x19e /* interrupt vector offset register 14 */ |
84 | #define ivor15 0x19f /* interrupt vector offset register 15 */ | 84 | #define ivor15 0x19f /* interrupt vector offset register 15 */ |
85 | #if defined(CONFIG_440GX) || \ | 85 | #if defined(CONFIG_440GX) || \ |
86 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | 86 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
87 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | 87 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
88 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | 88 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
89 | #define mcsrr0 0x23a /* machine check save/restore register 0 */ | 89 | #define mcsrr0 0x23a /* machine check save/restore register 0 */ |
90 | #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ | 90 | #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ |
91 | #define mcsr 0x23c /* machine check status register */ | 91 | #define mcsr 0x23c /* machine check status register */ |
92 | #endif | 92 | #endif |
93 | #define inv0 0x370 /* instruction cache normal victim 0 */ | 93 | #define inv0 0x370 /* instruction cache normal victim 0 */ |
94 | #define inv1 0x371 /* instruction cache normal victim 1 */ | 94 | #define inv1 0x371 /* instruction cache normal victim 1 */ |
95 | #define inv2 0x372 /* instruction cache normal victim 2 */ | 95 | #define inv2 0x372 /* instruction cache normal victim 2 */ |
96 | #define inv3 0x373 /* instruction cache normal victim 3 */ | 96 | #define inv3 0x373 /* instruction cache normal victim 3 */ |
97 | #define itv0 0x374 /* instruction cache transient victim 0 */ | 97 | #define itv0 0x374 /* instruction cache transient victim 0 */ |
98 | #define itv1 0x375 /* instruction cache transient victim 1 */ | 98 | #define itv1 0x375 /* instruction cache transient victim 1 */ |
99 | #define itv2 0x376 /* instruction cache transient victim 2 */ | 99 | #define itv2 0x376 /* instruction cache transient victim 2 */ |
100 | #define itv3 0x377 /* instruction cache transient victim 3 */ | 100 | #define itv3 0x377 /* instruction cache transient victim 3 */ |
101 | #define dnv0 0x390 /* data cache normal victim 0 */ | 101 | #define dnv0 0x390 /* data cache normal victim 0 */ |
102 | #define dnv1 0x391 /* data cache normal victim 1 */ | 102 | #define dnv1 0x391 /* data cache normal victim 1 */ |
103 | #define dnv2 0x392 /* data cache normal victim 2 */ | 103 | #define dnv2 0x392 /* data cache normal victim 2 */ |
104 | #define dnv3 0x393 /* data cache normal victim 3 */ | 104 | #define dnv3 0x393 /* data cache normal victim 3 */ |
105 | #define dtv0 0x394 /* data cache transient victim 0 */ | 105 | #define dtv0 0x394 /* data cache transient victim 0 */ |
106 | #define dtv1 0x395 /* data cache transient victim 1 */ | 106 | #define dtv1 0x395 /* data cache transient victim 1 */ |
107 | #define dtv2 0x396 /* data cache transient victim 2 */ | 107 | #define dtv2 0x396 /* data cache transient victim 2 */ |
108 | #define dtv3 0x397 /* data cache transient victim 3 */ | 108 | #define dtv3 0x397 /* data cache transient victim 3 */ |
109 | #define dvlim 0x398 /* data cache victim limit */ | 109 | #define dvlim 0x398 /* data cache victim limit */ |
110 | #define ivlim 0x399 /* instruction cache victim limit */ | 110 | #define ivlim 0x399 /* instruction cache victim limit */ |
111 | #define rstcfg 0x39b /* reset configuration */ | 111 | #define rstcfg 0x39b /* reset configuration */ |
112 | #define dcdbtrl 0x39c /* data cache debug tag register low */ | 112 | #define dcdbtrl 0x39c /* data cache debug tag register low */ |
113 | #define dcdbtrh 0x39d /* data cache debug tag register high */ | 113 | #define dcdbtrh 0x39d /* data cache debug tag register high */ |
114 | #define icdbtrl 0x39e /* instruction cache debug tag register low */ | 114 | #define icdbtrl 0x39e /* instruction cache debug tag register low */ |
115 | #define icdbtrh 0x39f /* instruction cache debug tag register high */ | 115 | #define icdbtrh 0x39f /* instruction cache debug tag register high */ |
116 | #define mmucr 0x3b2 /* mmu control register */ | 116 | #define mmucr 0x3b2 /* mmu control register */ |
117 | #define ccr0 0x3b3 /* core configuration register 0 */ | 117 | #define ccr0 0x3b3 /* core configuration register 0 */ |
118 | #define ccr1 0x378 /* core configuration for 440x5 only */ | 118 | #define ccr1 0x378 /* core configuration for 440x5 only */ |
119 | #define icdbdr 0x3d3 /* instruction cache debug data register */ | 119 | #define icdbdr 0x3d3 /* instruction cache debug data register */ |
120 | #define dbdr 0x3f3 /* debug data register */ | 120 | #define dbdr 0x3f3 /* debug data register */ |
121 | 121 | ||
122 | /****************************************************************************** | 122 | /****************************************************************************** |
123 | * DCRs & Related | 123 | * DCRs & Related |
124 | ******************************************************************************/ | 124 | ******************************************************************************/ |
125 | 125 | ||
126 | /*----------------------------------------------------------------------------- | 126 | /*----------------------------------------------------------------------------- |
127 | | Clocking Controller | 127 | | Clocking Controller |
128 | +----------------------------------------------------------------------------*/ | 128 | +----------------------------------------------------------------------------*/ |
129 | #define CLOCKING_DCR_BASE 0x0c | 129 | #define CLOCKING_DCR_BASE 0x0c |
130 | #define clkcfga (CLOCKING_DCR_BASE+0x0) | 130 | #define clkcfga (CLOCKING_DCR_BASE+0x0) |
131 | #define clkcfgd (CLOCKING_DCR_BASE+0x1) | 131 | #define clkcfgd (CLOCKING_DCR_BASE+0x1) |
132 | 132 | ||
133 | /* values for clkcfga register - indirect addressing of these regs */ | 133 | /* values for clkcfga register - indirect addressing of these regs */ |
134 | #define clk_clkukpd 0x0020 | 134 | #define clk_clkukpd 0x0020 |
135 | #define clk_pllc 0x0040 | 135 | #define clk_pllc 0x0040 |
136 | #define clk_plld 0x0060 | 136 | #define clk_plld 0x0060 |
137 | #define clk_primad 0x0080 | 137 | #define clk_primad 0x0080 |
138 | #define clk_primbd 0x00a0 | 138 | #define clk_primbd 0x00a0 |
139 | #define clk_opbd 0x00c0 | 139 | #define clk_opbd 0x00c0 |
140 | #define clk_perd 0x00e0 | 140 | #define clk_perd 0x00e0 |
141 | #define clk_mald 0x0100 | 141 | #define clk_mald 0x0100 |
142 | #define clk_spcid 0x0120 | 142 | #define clk_spcid 0x0120 |
143 | #define clk_icfg 0x0140 | 143 | #define clk_icfg 0x0140 |
144 | 144 | ||
145 | /* 440gx sdr register definations */ | 145 | /* 440gx sdr register definations */ |
146 | #define SDR_DCR_BASE 0x0e | 146 | #define SDR_DCR_BASE 0x0e |
147 | #define sdrcfga (SDR_DCR_BASE+0x0) | 147 | #define sdrcfga (SDR_DCR_BASE+0x0) |
148 | #define sdrcfgd (SDR_DCR_BASE+0x1) | 148 | #define sdrcfgd (SDR_DCR_BASE+0x1) |
149 | #define sdr_sdstp0 0x0020 /* */ | 149 | #define sdr_sdstp0 0x0020 /* */ |
150 | #define sdr_sdstp1 0x0021 /* */ | 150 | #define sdr_sdstp1 0x0021 /* */ |
151 | #define sdr_pinstp 0x0040 | 151 | #define sdr_pinstp 0x0040 |
152 | #define sdr_sdcs 0x0060 | 152 | #define sdr_sdcs 0x0060 |
153 | #define sdr_ecid0 0x0080 | 153 | #define sdr_ecid0 0x0080 |
154 | #define sdr_ecid1 0x0081 | 154 | #define sdr_ecid1 0x0081 |
155 | #define sdr_ecid2 0x0082 | 155 | #define sdr_ecid2 0x0082 |
156 | #define sdr_jtag 0x00c0 | 156 | #define sdr_jtag 0x00c0 |
157 | #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) | 157 | #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) |
158 | #define sdr_ddrdl 0x00e0 | 158 | #define sdr_ddrdl 0x00e0 |
159 | #else | 159 | #else |
160 | #define sdr_cfg 0x00e0 | 160 | #define sdr_cfg 0x00e0 |
161 | #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ | 161 | #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ |
162 | #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ | 162 | #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ |
163 | #define SDR_CFG_32BITS 0x00000000 /* 32 bits */ | 163 | #define SDR_CFG_32BITS 0x00000000 /* 32 bits */ |
164 | #define SDR_CFG_64BITS 0x01000000 /* 64 bits */ | 164 | #define SDR_CFG_64BITS 0x01000000 /* 64 bits */ |
165 | #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ | 165 | #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ |
166 | #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ | 166 | #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ |
167 | #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ | 167 | #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ |
168 | #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ | 168 | #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ |
169 | #define sdr_ebc 0x0100 | 169 | #define sdr_ebc 0x0100 |
170 | #define sdr_uart0 0x0120 /* UART0 Config */ | 170 | #define sdr_uart0 0x0120 /* UART0 Config */ |
171 | #define sdr_uart1 0x0121 /* UART1 Config */ | 171 | #define sdr_uart1 0x0121 /* UART1 Config */ |
172 | #define sdr_uart2 0x0122 /* UART2 Config */ | 172 | #define sdr_uart2 0x0122 /* UART2 Config */ |
173 | #define sdr_uart3 0x0123 /* UART3 Config */ | 173 | #define sdr_uart3 0x0123 /* UART3 Config */ |
174 | #define sdr_cp440 0x0180 | 174 | #define sdr_cp440 0x0180 |
175 | #define sdr_xcr 0x01c0 | 175 | #define sdr_xcr 0x01c0 |
176 | #define sdr_xpllc 0x01c1 | 176 | #define sdr_xpllc 0x01c1 |
177 | #define sdr_xplld 0x01c2 | 177 | #define sdr_xplld 0x01c2 |
178 | #define sdr_srst 0x0200 | 178 | #define sdr_srst 0x0200 |
179 | #define sdr_slpipe 0x0220 | 179 | #define sdr_slpipe 0x0220 |
180 | #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ | 180 | #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ |
181 | #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ | 181 | #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ |
182 | #define sdr_mirq0 0x0260 | 182 | #define sdr_mirq0 0x0260 |
183 | #define sdr_mirq1 0x0261 | 183 | #define sdr_mirq1 0x0261 |
184 | #define sdr_maltbl 0x0280 | 184 | #define sdr_maltbl 0x0280 |
185 | #define sdr_malrbl 0x02a0 | 185 | #define sdr_malrbl 0x02a0 |
186 | #define sdr_maltbs 0x02c0 | 186 | #define sdr_maltbs 0x02c0 |
187 | #define sdr_malrbs 0x02e0 | 187 | #define sdr_malrbs 0x02e0 |
188 | #define sdr_pci0 0x0300 | 188 | #define sdr_pci0 0x0300 |
189 | #define sdr_usb0 0x0320 | 189 | #define sdr_usb0 0x0320 |
190 | #define sdr_cust0 0x4000 | 190 | #define sdr_cust0 0x4000 |
191 | #define sdr_cust1 0x4002 | 191 | #define sdr_cust1 0x4002 |
192 | #define sdr_pfc0 0x4100 /* Pin Function 0 */ | 192 | #define sdr_pfc0 0x4100 /* Pin Function 0 */ |
193 | #define sdr_pfc1 0x4101 /* Pin Function 1 */ | 193 | #define sdr_pfc1 0x4101 /* Pin Function 1 */ |
194 | #define sdr_plbtr 0x4200 | 194 | #define sdr_plbtr 0x4200 |
195 | #define sdr_mfr 0x4300 /* SDR0_MFR reg */ | 195 | #define sdr_mfr 0x4300 /* SDR0_MFR reg */ |
196 | 196 | ||
197 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */ | 197 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */ |
198 | #define DDR0_00 0x00 | 198 | #define DDR0_00 0x00 |
199 | #define DDR0_01 0x01 | 199 | #define DDR0_01 0x01 |
200 | #define DDR0_02 0x02 | 200 | #define DDR0_02 0x02 |
201 | #define DDR0_03 0x03 | 201 | #define DDR0_03 0x03 |
202 | #define DDR0_04 0x04 | 202 | #define DDR0_04 0x04 |
203 | #define DDR0_05 0x05 | 203 | #define DDR0_05 0x05 |
204 | #define DDR0_06 0x06 | 204 | #define DDR0_06 0x06 |
205 | #define DDR0_07 0x07 | 205 | #define DDR0_07 0x07 |
206 | #define DDR0_08 0x08 | 206 | #define DDR0_08 0x08 |
207 | #define DDR0_09 0x09 | 207 | #define DDR0_09 0x09 |
208 | #define DDR0_10 0x0A | 208 | #define DDR0_10 0x0A |
209 | #define DDR0_11 0x0B | 209 | #define DDR0_11 0x0B |
210 | #define DDR0_12 0x0C | 210 | #define DDR0_12 0x0C |
211 | #define DDR0_13 0x0D | 211 | #define DDR0_13 0x0D |
212 | #define DDR0_14 0x0E | 212 | #define DDR0_14 0x0E |
213 | #define DDR0_15 0x0F | 213 | #define DDR0_15 0x0F |
214 | #define DDR0_16 0x10 | 214 | #define DDR0_16 0x10 |
215 | #define DDR0_17 0x11 | 215 | #define DDR0_17 0x11 |
216 | #define DDR0_18 0x12 | 216 | #define DDR0_18 0x12 |
217 | #define DDR0_19 0x13 | 217 | #define DDR0_19 0x13 |
218 | #define DDR0_20 0x14 | 218 | #define DDR0_20 0x14 |
219 | #define DDR0_21 0x15 | 219 | #define DDR0_21 0x15 |
220 | #define DDR0_22 0x16 | 220 | #define DDR0_22 0x16 |
221 | #define DDR0_23 0x17 | 221 | #define DDR0_23 0x17 |
222 | #define DDR0_24 0x18 | 222 | #define DDR0_24 0x18 |
223 | #define DDR0_25 0x19 | 223 | #define DDR0_25 0x19 |
224 | #define DDR0_26 0x1A | 224 | #define DDR0_26 0x1A |
225 | #define DDR0_27 0x1B | 225 | #define DDR0_27 0x1B |
226 | #define DDR0_28 0x1C | 226 | #define DDR0_28 0x1C |
227 | #define DDR0_29 0x1D | 227 | #define DDR0_29 0x1D |
228 | #define DDR0_30 0x1E | 228 | #define DDR0_30 0x1E |
229 | #define DDR0_31 0x1F | 229 | #define DDR0_31 0x1F |
230 | #define DDR0_32 0x20 | 230 | #define DDR0_32 0x20 |
231 | #define DDR0_33 0x21 | 231 | #define DDR0_33 0x21 |
232 | #define DDR0_34 0x22 | 232 | #define DDR0_34 0x22 |
233 | #define DDR0_35 0x23 | 233 | #define DDR0_35 0x23 |
234 | #define DDR0_36 0x24 | 234 | #define DDR0_36 0x24 |
235 | #define DDR0_37 0x25 | 235 | #define DDR0_37 0x25 |
236 | #define DDR0_38 0x26 | 236 | #define DDR0_38 0x26 |
237 | #define DDR0_39 0x27 | 237 | #define DDR0_39 0x27 |
238 | #define DDR0_40 0x28 | 238 | #define DDR0_40 0x28 |
239 | #define DDR0_41 0x29 | 239 | #define DDR0_41 0x29 |
240 | #define DDR0_42 0x2A | 240 | #define DDR0_42 0x2A |
241 | #define DDR0_43 0x2B | 241 | #define DDR0_43 0x2B |
242 | #define DDR0_44 0x2C | 242 | #define DDR0_44 0x2C |
243 | #endif /*CONFIG_440EPX*/ | 243 | #endif /*CONFIG_440EPX*/ |
244 | 244 | ||
245 | /*----------------------------------------------------------------------------- | 245 | /*----------------------------------------------------------------------------- |
246 | | SDRAM Controller | 246 | | SDRAM Controller |
247 | +----------------------------------------------------------------------------*/ | 247 | +----------------------------------------------------------------------------*/ |
248 | #define SDRAM_DCR_BASE 0x10 | 248 | #define SDRAM_DCR_BASE 0x10 |
249 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ | 249 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ |
250 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ | 250 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ |
251 | 251 | ||
252 | /* values for memcfga register - indirect addressing of these regs */ | 252 | /* values for memcfga register - indirect addressing of these regs */ |
253 | #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ | 253 | #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ |
254 | #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ | 254 | #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ |
255 | #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ | 255 | #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ |
256 | #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ | 256 | #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ |
257 | #define mem_bear 0x0010 /* bus error address reg */ | 257 | #define mem_bear 0x0010 /* bus error address reg */ |
258 | #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ | 258 | #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ |
259 | #define mem_mirq_set 0x0012 /* bus master interrupt (set) */ | 259 | #define mem_mirq_set 0x0012 /* bus master interrupt (set) */ |
260 | #define mem_slio 0x0018 /* ddr sdram slave interface options */ | 260 | #define mem_slio 0x0018 /* ddr sdram slave interface options */ |
261 | #define mem_cfg0 0x0020 /* ddr sdram options 0 */ | 261 | #define mem_cfg0 0x0020 /* ddr sdram options 0 */ |
262 | #define mem_cfg1 0x0021 /* ddr sdram options 1 */ | 262 | #define mem_cfg1 0x0021 /* ddr sdram options 1 */ |
263 | #define mem_devopt 0x0022 /* ddr sdram device options */ | 263 | #define mem_devopt 0x0022 /* ddr sdram device options */ |
264 | #define mem_mcsts 0x0024 /* memory controller status */ | 264 | #define mem_mcsts 0x0024 /* memory controller status */ |
265 | #define mem_rtr 0x0030 /* refresh timer register */ | 265 | #define mem_rtr 0x0030 /* refresh timer register */ |
266 | #define mem_pmit 0x0034 /* power management idle timer */ | 266 | #define mem_pmit 0x0034 /* power management idle timer */ |
267 | #define mem_uabba 0x0038 /* plb UABus base address */ | 267 | #define mem_uabba 0x0038 /* plb UABus base address */ |
268 | #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ | 268 | #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ |
269 | #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ | 269 | #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ |
270 | #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ | 270 | #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ |
271 | #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ | 271 | #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ |
272 | #define mem_tr0 0x0080 /* sdram timing register 0 */ | 272 | #define mem_tr0 0x0080 /* sdram timing register 0 */ |
273 | #define mem_tr1 0x0081 /* sdram timing register 1 */ | 273 | #define mem_tr1 0x0081 /* sdram timing register 1 */ |
274 | #define mem_clktr 0x0082 /* ddr clock timing register */ | 274 | #define mem_clktr 0x0082 /* ddr clock timing register */ |
275 | #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ | 275 | #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ |
276 | #define mem_dlycal 0x0084 /* delay line calibration register */ | 276 | #define mem_dlycal 0x0084 /* delay line calibration register */ |
277 | #define mem_eccesr 0x0098 /* ECC error status */ | 277 | #define mem_eccesr 0x0098 /* ECC error status */ |
278 | 278 | ||
279 | #ifdef CONFIG_440GX | 279 | #ifdef CONFIG_440GX |
280 | #define sdr_amp 0x0240 | 280 | #define sdr_amp 0x0240 |
281 | #define sdr_xpllc 0x01c1 | 281 | #define sdr_xpllc 0x01c1 |
282 | #define sdr_xplld 0x01c2 | 282 | #define sdr_xplld 0x01c2 |
283 | #define sdr_xcr 0x01c0 | 283 | #define sdr_xcr 0x01c0 |
284 | #define sdr_sdstp2 0x4001 | 284 | #define sdr_sdstp2 0x4001 |
285 | #define sdr_sdstp3 0x4003 | 285 | #define sdr_sdstp3 0x4003 |
286 | #endif /* CONFIG_440GX */ | 286 | #endif /* CONFIG_440GX */ |
287 | 287 | ||
288 | #ifdef CONFIG_440SPE | 288 | #ifdef CONFIG_440SPE |
289 | #undef sdr_sdstp2 | 289 | #undef sdr_sdstp2 |
290 | #define sdr_sdstp2 0x0022 | 290 | #define sdr_sdstp2 0x0022 |
291 | #undef sdr_sdstp3 | 291 | #undef sdr_sdstp3 |
292 | #define sdr_sdstp3 0x0023 | 292 | #define sdr_sdstp3 0x0023 |
293 | #define sdr_ddr0 0x00E1 | 293 | #define sdr_ddr0 0x00E1 |
294 | #define sdr_uart2 0x0122 | 294 | #define sdr_uart2 0x0122 |
295 | #define sdr_xcr0 0x01c0 | 295 | #define sdr_xcr0 0x01c0 |
296 | /* #define sdr_xcr1 0x01c3 only one PCIX - SG */ | 296 | /* #define sdr_xcr1 0x01c3 only one PCIX - SG */ |
297 | /* #define sdr_xcr2 0x01c6 only one PCIX - SG */ | 297 | /* #define sdr_xcr2 0x01c6 only one PCIX - SG */ |
298 | #define sdr_xpllc0 0x01c1 | 298 | #define sdr_xpllc0 0x01c1 |
299 | #define sdr_xplld0 0x01c2 | 299 | #define sdr_xplld0 0x01c2 |
300 | #define sdr_xpllc1 0x01c4 /*notRCW - SG */ | 300 | #define sdr_xpllc1 0x01c4 /*notRCW - SG */ |
301 | #define sdr_xplld1 0x01c5 /*notRCW - SG */ | 301 | #define sdr_xplld1 0x01c5 /*notRCW - SG */ |
302 | #define sdr_xpllc2 0x01c7 /*notRCW - SG */ | 302 | #define sdr_xpllc2 0x01c7 /*notRCW - SG */ |
303 | #define sdr_xplld2 0x01c8 /*notRCW - SG */ | 303 | #define sdr_xplld2 0x01c8 /*notRCW - SG */ |
304 | #define sdr_amp0 0x0240 | 304 | #define sdr_amp0 0x0240 |
305 | #define sdr_amp1 0x0241 | 305 | #define sdr_amp1 0x0241 |
306 | #define sdr_cust2 0x4004 | 306 | #define sdr_cust2 0x4004 |
307 | #define sdr_cust3 0x4006 | 307 | #define sdr_cust3 0x4006 |
308 | #define sdr_sdstp4 0x4001 | 308 | #define sdr_sdstp4 0x4001 |
309 | #define sdr_sdstp5 0x4003 | 309 | #define sdr_sdstp5 0x4003 |
310 | #define sdr_sdstp6 0x4005 | 310 | #define sdr_sdstp6 0x4005 |
311 | #define sdr_sdstp7 0x4007 | 311 | #define sdr_sdstp7 0x4007 |
312 | 312 | ||
313 | /*----------------------------------------------------------------------------+ | 313 | /*----------------------------------------------------------------------------+ |
314 | | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). | 314 | | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). |
315 | +----------------------------------------------------------------------------*/ | 315 | +----------------------------------------------------------------------------*/ |
316 | #define CCR0_PRE 0x40000000 | 316 | #define CCR0_PRE 0x40000000 |
317 | #define CCR0_CRPE 0x08000000 | 317 | #define CCR0_CRPE 0x08000000 |
318 | #define CCR0_DSTG 0x00200000 | 318 | #define CCR0_DSTG 0x00200000 |
319 | #define CCR0_DAPUIB 0x00100000 | 319 | #define CCR0_DAPUIB 0x00100000 |
320 | #define CCR0_DTB 0x00008000 | 320 | #define CCR0_DTB 0x00008000 |
321 | #define CCR0_GICBT 0x00004000 | 321 | #define CCR0_GICBT 0x00004000 |
322 | #define CCR0_GDCBT 0x00002000 | 322 | #define CCR0_GDCBT 0x00002000 |
323 | #define CCR0_FLSTA 0x00000100 | 323 | #define CCR0_FLSTA 0x00000100 |
324 | #define CCR0_ICSLC_MASK 0x0000000C | 324 | #define CCR0_ICSLC_MASK 0x0000000C |
325 | #define CCR0_ICSLT_MASK 0x00000003 | 325 | #define CCR0_ICSLT_MASK 0x00000003 |
326 | #define CCR1_TCS_MASK 0x00000080 | 326 | #define CCR1_TCS_MASK 0x00000080 |
327 | #define CCR1_TCS_INTCLK 0x00000000 | 327 | #define CCR1_TCS_INTCLK 0x00000000 |
328 | #define CCR1_TCS_EXTCLK 0x00000080 | 328 | #define CCR1_TCS_EXTCLK 0x00000080 |
329 | #define MMUCR_SEOA 0x01000000 | 329 | #define MMUCR_SEOA 0x01000000 |
330 | #define MMUCR_U1TE 0x00400000 | 330 | #define MMUCR_U1TE 0x00400000 |
331 | #define MMUCR_U2SWOAE 0x00200000 | 331 | #define MMUCR_U2SWOAE 0x00200000 |
332 | #define MMUCR_DULXE 0x00800000 | 332 | #define MMUCR_DULXE 0x00800000 |
333 | #define MMUCR_IULXE 0x00400000 | 333 | #define MMUCR_IULXE 0x00400000 |
334 | #define MMUCR_STS 0x00100000 | 334 | #define MMUCR_STS 0x00100000 |
335 | #define MMUCR_STID_MASK 0x000000FF | 335 | #define MMUCR_STID_MASK 0x000000FF |
336 | 336 | ||
337 | #define SDR0_CFGADDR 0x00E | 337 | #define SDR0_CFGADDR 0x00E |
338 | #define SDR0_CFGDATA 0x00F | 338 | #define SDR0_CFGDATA 0x00F |
339 | 339 | ||
340 | /****************************************************************************** | 340 | /****************************************************************************** |
341 | * PCI express defines | 341 | * PCI express defines |
342 | ******************************************************************************/ | 342 | ******************************************************************************/ |
343 | #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */ | 343 | #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */ |
344 | #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */ | 344 | #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */ |
345 | #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */ | 345 | #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */ |
346 | #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */ | 346 | #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */ |
347 | #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */ | 347 | #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */ |
348 | #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */ | 348 | #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */ |
349 | #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */ | 349 | #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */ |
350 | #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */ | 350 | #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */ |
351 | #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */ | 351 | #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */ |
352 | #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */ | 352 | #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */ |
353 | #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */ | 353 | #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */ |
354 | #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */ | 354 | #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */ |
355 | #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */ | 355 | #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */ |
356 | #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */ | 356 | #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */ |
357 | #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */ | 357 | #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */ |
358 | #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */ | 358 | #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */ |
359 | #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */ | 359 | #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */ |
360 | #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */ | 360 | #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */ |
361 | #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */ | 361 | #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */ |
362 | #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */ | 362 | #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */ |
363 | #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */ | 363 | #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */ |
364 | #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */ | 364 | #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */ |
365 | #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */ | 365 | #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */ |
366 | #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */ | 366 | #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */ |
367 | #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */ | 367 | #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */ |
368 | #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */ | 368 | #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */ |
369 | #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */ | 369 | #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */ |
370 | #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */ | 370 | #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */ |
371 | #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */ | 371 | #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */ |
372 | #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */ | 372 | #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */ |
373 | #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */ | 373 | #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */ |
374 | #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */ | 374 | #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */ |
375 | #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */ | 375 | #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */ |
376 | 376 | ||
377 | #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */ | 377 | #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */ |
378 | #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */ | 378 | #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */ |
379 | #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */ | 379 | #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */ |
380 | #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */ | 380 | #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */ |
381 | #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */ | 381 | #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */ |
382 | #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */ | 382 | #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */ |
383 | #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */ | 383 | #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */ |
384 | #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */ | 384 | #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */ |
385 | #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */ | 385 | #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */ |
386 | #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */ | 386 | #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */ |
387 | #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */ | 387 | #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */ |
388 | #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */ | 388 | #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */ |
389 | #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */ | 389 | #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */ |
390 | #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */ | 390 | #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */ |
391 | #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */ | 391 | #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */ |
392 | #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */ | 392 | #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */ |
393 | #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */ | 393 | #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */ |
394 | #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */ | 394 | #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */ |
395 | #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */ | 395 | #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */ |
396 | #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */ | 396 | #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */ |
397 | #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */ | 397 | #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */ |
398 | #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */ | 398 | #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */ |
399 | #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */ | 399 | #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */ |
400 | #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */ | 400 | #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */ |
401 | #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */ | 401 | #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */ |
402 | #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */ | 402 | #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */ |
403 | #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */ | 403 | #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */ |
404 | #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */ | 404 | #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */ |
405 | #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */ | 405 | #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */ |
406 | #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */ | 406 | #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */ |
407 | #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */ | 407 | #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */ |
408 | #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */ | 408 | #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */ |
409 | #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */ | 409 | #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */ |
410 | #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */ | 410 | #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */ |
411 | #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */ | 411 | #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */ |
412 | #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */ | 412 | #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */ |
413 | #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */ | 413 | #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */ |
414 | #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */ | 414 | #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */ |
415 | #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */ | 415 | #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */ |
416 | #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */ | 416 | #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */ |
417 | #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ | 417 | #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ |
418 | #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ | 418 | #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ |
419 | #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ | 419 | #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ |
420 | 420 | ||
421 | /*----------------------------------------------------------------------------+ | 421 | /*----------------------------------------------------------------------------+ |
422 | | SDRAM Controller | 422 | | SDRAM Controller |
423 | +----------------------------------------------------------------------------*/ | 423 | +----------------------------------------------------------------------------*/ |
424 | /*-----------------------------------------------------------------------------+ | 424 | /*-----------------------------------------------------------------------------+ |
425 | | SDRAM DLYCAL Options | 425 | | SDRAM DLYCAL Options |
426 | +-----------------------------------------------------------------------------*/ | 426 | +-----------------------------------------------------------------------------*/ |
427 | #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC | 427 | #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC |
428 | #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) | 428 | #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) |
429 | #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) | 429 | #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) |
430 | 430 | ||
431 | /*----------------------------------------------------------------------------+ | 431 | /*----------------------------------------------------------------------------+ |
432 | | Memory queue defines | 432 | | Memory queue defines |
433 | +----------------------------------------------------------------------------*/ | 433 | +----------------------------------------------------------------------------*/ |
434 | /* A REVOIR versus RWC - SG*/ | 434 | /* A REVOIR versus RWC - SG*/ |
435 | #define SDRAMQ_DCR_BASE 0x040 | 435 | #define SDRAMQ_DCR_BASE 0x040 |
436 | 436 | ||
437 | #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ | 437 | #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ |
438 | #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ | 438 | #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ |
439 | #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ | 439 | #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ |
440 | #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ | 440 | #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ |
441 | #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ | 441 | #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ |
442 | #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ | 442 | #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ |
443 | #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ | 443 | #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ |
444 | #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ | 444 | #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ |
445 | #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ | 445 | #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ |
446 | #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ | 446 | #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ |
447 | #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ | 447 | #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ |
448 | #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ | 448 | #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ |
449 | #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ | 449 | #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ |
450 | #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ | 450 | #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ |
451 | #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ | 451 | #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ |
452 | 452 | ||
453 | /*-----------------------------------------------------------------------------+ | 453 | /*-----------------------------------------------------------------------------+ |
454 | | Memory Bank 0-7 configuration | 454 | | Memory Bank 0-7 configuration |
455 | +-----------------------------------------------------------------------------*/ | 455 | +-----------------------------------------------------------------------------*/ |
456 | #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ | 456 | #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ |
457 | #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) | 457 | #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) |
458 | #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) | 458 | #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) |
459 | #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ | 459 | #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ |
460 | #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) | 460 | #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) |
461 | #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) | 461 | #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) |
462 | #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ | 462 | #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ |
463 | #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ | 463 | #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ |
464 | #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ | 464 | #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ |
465 | #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ | 465 | #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ |
466 | #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ | 466 | #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ |
467 | #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ | 467 | #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ |
468 | #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ | 468 | #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ |
469 | #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ | 469 | #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ |
470 | #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ | 470 | #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ |
471 | #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ | 471 | #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ |
472 | #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ | 472 | #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ |
473 | 473 | ||
474 | /*----------------------------------------------------------------------------+ | 474 | /*----------------------------------------------------------------------------+ |
475 | | Memory controller defines | 475 | | Memory controller defines |
476 | +----------------------------------------------------------------------------*/ | 476 | +----------------------------------------------------------------------------*/ |
477 | #define SDRAMC_DCR_BASE 0x010 | 477 | #define SDRAMC_DCR_BASE 0x010 |
478 | #define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ | 478 | #define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ |
479 | #define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ | 479 | #define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ |
480 | 480 | ||
481 | /* A REVOIR versus specs 4 bank - SG*/ | 481 | /* A REVOIR versus specs 4 bank - SG*/ |
482 | #define SDRAM_MCSTAT 0x14 /* memory controller status */ | 482 | #define SDRAM_MCSTAT 0x14 /* memory controller status */ |
483 | #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ | 483 | #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ |
484 | #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ | 484 | #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ |
485 | #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ | 485 | #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ |
486 | #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ | 486 | #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ |
487 | #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ | 487 | #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ |
488 | #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ | 488 | #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ |
489 | #define SDRAM_CODT 0x26 /* on die termination for controller */ | 489 | #define SDRAM_CODT 0x26 /* on die termination for controller */ |
490 | #define SDRAM_VVPR 0x27 /* variable VRef programmming */ | 490 | #define SDRAM_VVPR 0x27 /* variable VRef programmming */ |
491 | #define SDRAM_OPARS 0x28 /* on chip driver control setup */ | 491 | #define SDRAM_OPARS 0x28 /* on chip driver control setup */ |
492 | #define SDRAM_OPART 0x29 /* on chip driver control trigger */ | 492 | #define SDRAM_OPART 0x29 /* on chip driver control trigger */ |
493 | #define SDRAM_RTR 0x30 /* refresh timer */ | 493 | #define SDRAM_RTR 0x30 /* refresh timer */ |
494 | #define SDRAM_PMIT 0x34 /* power management idle timer */ | 494 | #define SDRAM_PMIT 0x34 /* power management idle timer */ |
495 | #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ | 495 | #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ |
496 | #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ | 496 | #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ |
497 | #define SDRAM_MB2CF 0x48 | 497 | #define SDRAM_MB2CF 0x48 |
498 | #define SDRAM_MB3CF 0x4C | 498 | #define SDRAM_MB3CF 0x4C |
499 | #define SDRAM_INITPLR0 0x50 /* manual initialization control */ | 499 | #define SDRAM_INITPLR0 0x50 /* manual initialization control */ |
500 | #define SDRAM_INITPLR1 0x51 /* manual initialization control */ | 500 | #define SDRAM_INITPLR1 0x51 /* manual initialization control */ |
501 | #define SDRAM_INITPLR2 0x52 /* manual initialization control */ | 501 | #define SDRAM_INITPLR2 0x52 /* manual initialization control */ |
502 | #define SDRAM_INITPLR3 0x53 /* manual initialization control */ | 502 | #define SDRAM_INITPLR3 0x53 /* manual initialization control */ |
503 | #define SDRAM_INITPLR4 0x54 /* manual initialization control */ | 503 | #define SDRAM_INITPLR4 0x54 /* manual initialization control */ |
504 | #define SDRAM_INITPLR5 0x55 /* manual initialization control */ | 504 | #define SDRAM_INITPLR5 0x55 /* manual initialization control */ |
505 | #define SDRAM_INITPLR6 0x56 /* manual initialization control */ | 505 | #define SDRAM_INITPLR6 0x56 /* manual initialization control */ |
506 | #define SDRAM_INITPLR7 0x57 /* manual initialization control */ | 506 | #define SDRAM_INITPLR7 0x57 /* manual initialization control */ |
507 | #define SDRAM_INITPLR8 0x58 /* manual initialization control */ | 507 | #define SDRAM_INITPLR8 0x58 /* manual initialization control */ |
508 | #define SDRAM_INITPLR9 0x59 /* manual initialization control */ | 508 | #define SDRAM_INITPLR9 0x59 /* manual initialization control */ |
509 | #define SDRAM_INITPLR10 0x5a /* manual initialization control */ | 509 | #define SDRAM_INITPLR10 0x5a /* manual initialization control */ |
510 | #define SDRAM_INITPLR11 0x5b /* manual initialization control */ | 510 | #define SDRAM_INITPLR11 0x5b /* manual initialization control */ |
511 | #define SDRAM_INITPLR12 0x5c /* manual initialization control */ | 511 | #define SDRAM_INITPLR12 0x5c /* manual initialization control */ |
512 | #define SDRAM_INITPLR13 0x5d /* manual initialization control */ | 512 | #define SDRAM_INITPLR13 0x5d /* manual initialization control */ |
513 | #define SDRAM_INITPLR14 0x5e /* manual initialization control */ | 513 | #define SDRAM_INITPLR14 0x5e /* manual initialization control */ |
514 | #define SDRAM_INITPLR15 0x5f /* manual initialization control */ | 514 | #define SDRAM_INITPLR15 0x5f /* manual initialization control */ |
515 | #define SDRAM_RQDC 0x70 /* read DQS delay control */ | 515 | #define SDRAM_RQDC 0x70 /* read DQS delay control */ |
516 | #define SDRAM_RFDC 0x74 /* read feedback delay control */ | 516 | #define SDRAM_RFDC 0x74 /* read feedback delay control */ |
517 | #define SDRAM_RDCC 0x78 /* read data capture control */ | 517 | #define SDRAM_RDCC 0x78 /* read data capture control */ |
518 | #define SDRAM_DLCR 0x7A /* delay line calibration */ | 518 | #define SDRAM_DLCR 0x7A /* delay line calibration */ |
519 | #define SDRAM_CLKTR 0x80 /* DDR clock timing */ | 519 | #define SDRAM_CLKTR 0x80 /* DDR clock timing */ |
520 | #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ | 520 | #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ |
521 | #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ | 521 | #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ |
522 | #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ | 522 | #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ |
523 | #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ | 523 | #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ |
524 | #define SDRAM_MMODE 0x88 /* memory mode */ | 524 | #define SDRAM_MMODE 0x88 /* memory mode */ |
525 | #define SDRAM_MEMODE 0x89 /* memory extended mode */ | 525 | #define SDRAM_MEMODE 0x89 /* memory extended mode */ |
526 | #define SDRAM_ECCCR 0x98 /* ECC error status */ | 526 | #define SDRAM_ECCCR 0x98 /* ECC error status */ |
527 | #define SDRAM_CID 0xA4 /* core ID */ | 527 | #define SDRAM_CID 0xA4 /* core ID */ |
528 | #define SDRAM_RID 0xA8 /* revision ID */ | 528 | #define SDRAM_RID 0xA8 /* revision ID */ |
529 | 529 | ||
530 | /*-----------------------------------------------------------------------------+ | 530 | /*-----------------------------------------------------------------------------+ |
531 | | Memory Controller Status | 531 | | Memory Controller Status |
532 | +-----------------------------------------------------------------------------*/ | 532 | +-----------------------------------------------------------------------------*/ |
533 | #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ | 533 | #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ |
534 | #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ | 534 | #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ |
535 | #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ | 535 | #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ |
536 | #define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ | 536 | #define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ |
537 | #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ | 537 | #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ |
538 | #define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ | 538 | #define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ |
539 | 539 | ||
540 | /*-----------------------------------------------------------------------------+ | 540 | /*-----------------------------------------------------------------------------+ |
541 | | Memory Controller Options 1 | 541 | | Memory Controller Options 1 |
542 | +-----------------------------------------------------------------------------*/ | 542 | +-----------------------------------------------------------------------------*/ |
543 | #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ | 543 | #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ |
544 | #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ | 544 | #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ |
545 | #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ | 545 | #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ |
546 | #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ | 546 | #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ |
547 | #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ | 547 | #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ |
548 | #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) | 548 | #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) |
549 | #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ | 549 | #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ |
550 | #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ | 550 | #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ |
551 | #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ | 551 | #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ |
552 | #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ | 552 | #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ |
553 | #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ | 553 | #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ |
554 | #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ | 554 | #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ |
555 | #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ | 555 | #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ |
556 | #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ | 556 | #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ |
557 | #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ | 557 | #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ |
558 | #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ | 558 | #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ |
559 | #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ | 559 | #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ |
560 | #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ | 560 | #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ |
561 | #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ | 561 | #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ |
562 | #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ | 562 | #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ |
563 | #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ | 563 | #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ |
564 | #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ | 564 | #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ |
565 | #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ | 565 | #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ |
566 | #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ | 566 | #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ |
567 | #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ | 567 | #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ |
568 | #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ | 568 | #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ |
569 | #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ | 569 | #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ |
570 | #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ | 570 | #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ |
571 | #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ | 571 | #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ |
572 | #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ | 572 | #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ |
573 | #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ | 573 | #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ |
574 | #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ | 574 | #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ |
575 | #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ | 575 | #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ |
576 | #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ | 576 | #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ |
577 | #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ | 577 | #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ |
578 | 578 | ||
579 | /*-----------------------------------------------------------------------------+ | 579 | /*-----------------------------------------------------------------------------+ |
580 | | Memory Controller Options 2 | 580 | | Memory Controller Options 2 |
581 | +-----------------------------------------------------------------------------*/ | 581 | +-----------------------------------------------------------------------------*/ |
582 | #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ | 582 | #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ |
583 | #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ | 583 | #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ |
584 | #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ | 584 | #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ |
585 | #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ | 585 | #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ |
586 | #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ | 586 | #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ |
587 | #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ | 587 | #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ |
588 | #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ | 588 | #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ |
589 | #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ | 589 | #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ |
590 | #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ | 590 | #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ |
591 | #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ | 591 | #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ |
592 | #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ | 592 | #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ |
593 | #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ | 593 | #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ |
594 | #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ | 594 | #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ |
595 | #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ | 595 | #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ |
596 | #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ | 596 | #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ |
597 | #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ | 597 | #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ |
598 | #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ | 598 | #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ |
599 | #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ | 599 | #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ |
600 | 600 | ||
601 | /*-----------------------------------------------------------------------------+ | 601 | /*-----------------------------------------------------------------------------+ |
602 | | SDRAM Refresh Timer Register | 602 | | SDRAM Refresh Timer Register |
603 | +-----------------------------------------------------------------------------*/ | 603 | +-----------------------------------------------------------------------------*/ |
604 | #define SDRAM_RTR_RINT_MASK 0xFFF80000 | 604 | #define SDRAM_RTR_RINT_MASK 0xFFF80000 |
605 | #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) | 605 | #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) |
606 | #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) | 606 | #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) |
607 | 607 | ||
608 | /*-----------------------------------------------------------------------------+ | 608 | /*-----------------------------------------------------------------------------+ |
609 | | SDRAM Read DQS Delay Control Register | 609 | | SDRAM Read DQS Delay Control Register |
610 | +-----------------------------------------------------------------------------*/ | 610 | +-----------------------------------------------------------------------------*/ |
611 | #define SDRAM_RQDC_RQDE_MASK 0x80000000 | 611 | #define SDRAM_RQDC_RQDE_MASK 0x80000000 |
612 | #define SDRAM_RQDC_RQDE_DISABLE 0x00000000 | 612 | #define SDRAM_RQDC_RQDE_DISABLE 0x00000000 |
613 | #define SDRAM_RQDC_RQDE_ENABLE 0x80000000 | 613 | #define SDRAM_RQDC_RQDE_ENABLE 0x80000000 |
614 | #define SDRAM_RQDC_RQFD_MASK 0x000001FF | 614 | #define SDRAM_RQDC_RQFD_MASK 0x000001FF |
615 | #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) | 615 | #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) |
616 | 616 | ||
617 | #define SDRAM_RQDC_RQFD_MAX 0x1FF | 617 | #define SDRAM_RQDC_RQFD_MAX 0x1FF |
618 | 618 | ||
619 | /*-----------------------------------------------------------------------------+ | 619 | /*-----------------------------------------------------------------------------+ |
620 | | SDRAM Read Data Capture Control Register | 620 | | SDRAM Read Data Capture Control Register |
621 | +-----------------------------------------------------------------------------*/ | 621 | +-----------------------------------------------------------------------------*/ |
622 | #define SDRAM_RDCC_RDSS_MASK 0xC0000000 | 622 | #define SDRAM_RDCC_RDSS_MASK 0xC0000000 |
623 | #define SDRAM_RDCC_RDSS_T1 0x00000000 | 623 | #define SDRAM_RDCC_RDSS_T1 0x00000000 |
624 | #define SDRAM_RDCC_RDSS_T2 0x40000000 | 624 | #define SDRAM_RDCC_RDSS_T2 0x40000000 |
625 | #define SDRAM_RDCC_RDSS_T3 0x80000000 | 625 | #define SDRAM_RDCC_RDSS_T3 0x80000000 |
626 | #define SDRAM_RDCC_RDSS_T4 0xC0000000 | 626 | #define SDRAM_RDCC_RDSS_T4 0xC0000000 |
627 | #define SDRAM_RDCC_RSAE_MASK 0x00000001 | 627 | #define SDRAM_RDCC_RSAE_MASK 0x00000001 |
628 | #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 | 628 | #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 |
629 | #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 | 629 | #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 |
630 | 630 | ||
631 | /*-----------------------------------------------------------------------------+ | 631 | /*-----------------------------------------------------------------------------+ |
632 | | SDRAM Read Feedback Delay Control Register | 632 | | SDRAM Read Feedback Delay Control Register |
633 | +-----------------------------------------------------------------------------*/ | 633 | +-----------------------------------------------------------------------------*/ |
634 | #define SDRAM_RFDC_ARSE_MASK 0x80000000 | 634 | #define SDRAM_RFDC_ARSE_MASK 0x80000000 |
635 | #define SDRAM_RFDC_ARSE_DISABLE 0x80000000 | 635 | #define SDRAM_RFDC_ARSE_DISABLE 0x80000000 |
636 | #define SDRAM_RFDC_ARSE_ENABLE 0x00000000 | 636 | #define SDRAM_RFDC_ARSE_ENABLE 0x00000000 |
637 | #define SDRAM_RFDC_RFOS_MASK 0x007F0000 | 637 | #define SDRAM_RFDC_RFOS_MASK 0x007F0000 |
638 | #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) | 638 | #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) |
639 | #define SDRAM_RFDC_RFFD_MASK 0x000003FF | 639 | #define SDRAM_RFDC_RFFD_MASK 0x000003FF |
640 | #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) | 640 | #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) |
641 | 641 | ||
642 | #define SDRAM_RFDC_RFFD_MAX 0x7FF | 642 | #define SDRAM_RFDC_RFFD_MAX 0x7FF |
643 | 643 | ||
644 | /*-----------------------------------------------------------------------------+ | 644 | /*-----------------------------------------------------------------------------+ |
645 | | SDRAM Delay Line Calibration Register | 645 | | SDRAM Delay Line Calibration Register |
646 | +-----------------------------------------------------------------------------*/ | 646 | +-----------------------------------------------------------------------------*/ |
647 | #define SDRAM_DLCR_DCLM_MASK 0x80000000 | 647 | #define SDRAM_DLCR_DCLM_MASK 0x80000000 |
648 | #define SDRAM_DLCR_DCLM_MANUEL 0x80000000 | 648 | #define SDRAM_DLCR_DCLM_MANUEL 0x80000000 |
649 | #define SDRAM_DLCR_DCLM_AUTO 0x00000000 | 649 | #define SDRAM_DLCR_DCLM_AUTO 0x00000000 |
650 | #define SDRAM_DLCR_DLCR_MASK 0x08000000 | 650 | #define SDRAM_DLCR_DLCR_MASK 0x08000000 |
651 | #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 | 651 | #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 |
652 | #define SDRAM_DLCR_DLCR_IDLE 0x00000000 | 652 | #define SDRAM_DLCR_DLCR_IDLE 0x00000000 |
653 | #define SDRAM_DLCR_DLCS_MASK 0x07000000 | 653 | #define SDRAM_DLCR_DLCS_MASK 0x07000000 |
654 | #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 | 654 | #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 |
655 | #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 | 655 | #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 |
656 | #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 | 656 | #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 |
657 | #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 | 657 | #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 |
658 | #define SDRAM_DLCR_DLCS_ERROR 0x04000000 | 658 | #define SDRAM_DLCR_DLCS_ERROR 0x04000000 |
659 | #define SDRAM_DLCR_DLCV_MASK 0x000001FF | 659 | #define SDRAM_DLCR_DLCV_MASK 0x000001FF |
660 | #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) | 660 | #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) |
661 | #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) | 661 | #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) |
662 | 662 | ||
663 | /*-----------------------------------------------------------------------------+ | 663 | /*-----------------------------------------------------------------------------+ |
664 | | SDRAM Controller On Die Termination Register | 664 | | SDRAM Controller On Die Termination Register |
665 | +-----------------------------------------------------------------------------*/ | 665 | +-----------------------------------------------------------------------------*/ |
666 | #define SDRAM_CODT_ODT_ON 0x80000000 | 666 | #define SDRAM_CODT_ODT_ON 0x80000000 |
667 | #define SDRAM_CODT_ODT_OFF 0x00000000 | 667 | #define SDRAM_CODT_ODT_OFF 0x00000000 |
668 | #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 | 668 | #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 |
669 | #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 | 669 | #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 |
670 | #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 | 670 | #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 |
671 | #define SDRAM_CODT_DQS_MASK 0x00000010 | 671 | #define SDRAM_CODT_DQS_MASK 0x00000010 |
672 | #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 | 672 | #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 |
673 | #define SDRAM_CODT_DQS_SINGLE_END 0x00000010 | 673 | #define SDRAM_CODT_DQS_SINGLE_END 0x00000010 |
674 | #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 | 674 | #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 |
675 | #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 | 675 | #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 |
676 | #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 | 676 | #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 |
677 | #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 | 677 | #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 |
678 | #define SDRAM_CODT_IO_HIZ 0x00000000 | 678 | #define SDRAM_CODT_IO_HIZ 0x00000000 |
679 | #define SDRAM_CODT_IO_NMODE 0x00000001 | 679 | #define SDRAM_CODT_IO_NMODE 0x00000001 |
680 | 680 | ||
681 | /*-----------------------------------------------------------------------------+ | 681 | /*-----------------------------------------------------------------------------+ |
682 | | SDRAM Mode Register | 682 | | SDRAM Mode Register |
683 | +-----------------------------------------------------------------------------*/ | 683 | +-----------------------------------------------------------------------------*/ |
684 | #define SDRAM_MMODE_WR_MASK 0x00000E00 | 684 | #define SDRAM_MMODE_WR_MASK 0x00000E00 |
685 | #define SDRAM_MMODE_WR_DDR1 0x00000000 | 685 | #define SDRAM_MMODE_WR_DDR1 0x00000000 |
686 | #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 | 686 | #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 |
687 | #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 | 687 | #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 |
688 | #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 | 688 | #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 |
689 | #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 | 689 | #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 |
690 | #define SDRAM_MMODE_DCL_MASK 0x00000070 | 690 | #define SDRAM_MMODE_DCL_MASK 0x00000070 |
691 | #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 | 691 | #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 |
692 | #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 | 692 | #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 |
693 | #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 | 693 | #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 |
694 | #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 | 694 | #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 |
695 | #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 | 695 | #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 |
696 | #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 | 696 | #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 |
697 | #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 | 697 | #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 |
698 | #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 | 698 | #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 |
699 | #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 | 699 | #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 |
700 | 700 | ||
701 | /*-----------------------------------------------------------------------------+ | 701 | /*-----------------------------------------------------------------------------+ |
702 | | SDRAM Extended Mode Register | 702 | | SDRAM Extended Mode Register |
703 | +-----------------------------------------------------------------------------*/ | 703 | +-----------------------------------------------------------------------------*/ |
704 | #define SDRAM_MEMODE_DIC_MASK 0x00000002 | 704 | #define SDRAM_MEMODE_DIC_MASK 0x00000002 |
705 | #define SDRAM_MEMODE_DIC_NORMAL 0x00000000 | 705 | #define SDRAM_MEMODE_DIC_NORMAL 0x00000000 |
706 | #define SDRAM_MEMODE_DIC_WEAK 0x00000002 | 706 | #define SDRAM_MEMODE_DIC_WEAK 0x00000002 |
707 | #define SDRAM_MEMODE_DLL_MASK 0x00000001 | 707 | #define SDRAM_MEMODE_DLL_MASK 0x00000001 |
708 | #define SDRAM_MEMODE_DLL_DISABLE 0x00000001 | 708 | #define SDRAM_MEMODE_DLL_DISABLE 0x00000001 |
709 | #define SDRAM_MEMODE_DLL_ENABLE 0x00000000 | 709 | #define SDRAM_MEMODE_DLL_ENABLE 0x00000000 |
710 | #define SDRAM_MEMODE_RTT_MASK 0x00000044 | 710 | #define SDRAM_MEMODE_RTT_MASK 0x00000044 |
711 | #define SDRAM_MEMODE_RTT_DISABLED 0x00000000 | 711 | #define SDRAM_MEMODE_RTT_DISABLED 0x00000000 |
712 | #define SDRAM_MEMODE_RTT_75OHM 0x00000004 | 712 | #define SDRAM_MEMODE_RTT_75OHM 0x00000004 |
713 | #define SDRAM_MEMODE_RTT_150OHM 0x00000040 | 713 | #define SDRAM_MEMODE_RTT_150OHM 0x00000040 |
714 | #define SDRAM_MEMODE_DQS_MASK 0x00000400 | 714 | #define SDRAM_MEMODE_DQS_MASK 0x00000400 |
715 | #define SDRAM_MEMODE_DQS_DISABLE 0x00000400 | 715 | #define SDRAM_MEMODE_DQS_DISABLE 0x00000400 |
716 | #define SDRAM_MEMODE_DQS_ENABLE 0x00000000 | 716 | #define SDRAM_MEMODE_DQS_ENABLE 0x00000000 |
717 | 717 | ||
718 | /*-----------------------------------------------------------------------------+ | 718 | /*-----------------------------------------------------------------------------+ |
719 | | SDRAM Clock Timing Register | 719 | | SDRAM Clock Timing Register |
720 | +-----------------------------------------------------------------------------*/ | 720 | +-----------------------------------------------------------------------------*/ |
721 | #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 | 721 | #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 |
722 | #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 | 722 | #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 |
723 | #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 | 723 | #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 |
724 | 724 | ||
725 | /*-----------------------------------------------------------------------------+ | 725 | /*-----------------------------------------------------------------------------+ |
726 | | SDRAM Write Timing Register | 726 | | SDRAM Write Timing Register |
727 | +-----------------------------------------------------------------------------*/ | 727 | +-----------------------------------------------------------------------------*/ |
728 | #define SDRAM_WRDTR_LLWP_MASK 0x10000000 | 728 | #define SDRAM_WRDTR_LLWP_MASK 0x10000000 |
729 | #define SDRAM_WRDTR_LLWP_DIS 0x10000000 | 729 | #define SDRAM_WRDTR_LLWP_DIS 0x10000000 |
730 | #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 | 730 | #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 |
731 | #define SDRAM_WRDTR_WTR_MASK 0x0E000000 | 731 | #define SDRAM_WRDTR_WTR_MASK 0x0E000000 |
732 | #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 | 732 | #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 |
733 | #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 | 733 | #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 |
734 | #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 | 734 | #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 |
735 | 735 | ||
736 | /*-----------------------------------------------------------------------------+ | 736 | /*-----------------------------------------------------------------------------+ |
737 | | SDRAM SDTR1 Options | 737 | | SDRAM SDTR1 Options |
738 | +-----------------------------------------------------------------------------*/ | 738 | +-----------------------------------------------------------------------------*/ |
739 | #define SDRAM_SDTR1_LDOF_MASK 0x80000000 | 739 | #define SDRAM_SDTR1_LDOF_MASK 0x80000000 |
740 | #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 | 740 | #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 |
741 | #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 | 741 | #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 |
742 | #define SDRAM_SDTR1_RTW_MASK 0x00F00000 | 742 | #define SDRAM_SDTR1_RTW_MASK 0x00F00000 |
743 | #define SDRAM_SDTR1_RTW_2_CLK 0x00200000 | 743 | #define SDRAM_SDTR1_RTW_2_CLK 0x00200000 |
744 | #define SDRAM_SDTR1_RTW_3_CLK 0x00300000 | 744 | #define SDRAM_SDTR1_RTW_3_CLK 0x00300000 |
745 | #define SDRAM_SDTR1_WTWO_MASK 0x000F0000 | 745 | #define SDRAM_SDTR1_WTWO_MASK 0x000F0000 |
746 | #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 | 746 | #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 |
747 | #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 | 747 | #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 |
748 | #define SDRAM_SDTR1_RTRO_MASK 0x0000F000 | 748 | #define SDRAM_SDTR1_RTRO_MASK 0x0000F000 |
749 | #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 | 749 | #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 |
750 | #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 | 750 | #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 |
751 | 751 | ||
752 | /*-----------------------------------------------------------------------------+ | 752 | /*-----------------------------------------------------------------------------+ |
753 | | SDRAM SDTR2 Options | 753 | | SDRAM SDTR2 Options |
754 | +-----------------------------------------------------------------------------*/ | 754 | +-----------------------------------------------------------------------------*/ |
755 | #define SDRAM_SDTR2_RCD_MASK 0xF0000000 | 755 | #define SDRAM_SDTR2_RCD_MASK 0xF0000000 |
756 | #define SDRAM_SDTR2_RCD_1_CLK 0x10000000 | 756 | #define SDRAM_SDTR2_RCD_1_CLK 0x10000000 |
757 | #define SDRAM_SDTR2_RCD_2_CLK 0x20000000 | 757 | #define SDRAM_SDTR2_RCD_2_CLK 0x20000000 |
758 | #define SDRAM_SDTR2_RCD_3_CLK 0x30000000 | 758 | #define SDRAM_SDTR2_RCD_3_CLK 0x30000000 |
759 | #define SDRAM_SDTR2_RCD_4_CLK 0x40000000 | 759 | #define SDRAM_SDTR2_RCD_4_CLK 0x40000000 |
760 | #define SDRAM_SDTR2_RCD_5_CLK 0x50000000 | 760 | #define SDRAM_SDTR2_RCD_5_CLK 0x50000000 |
761 | #define SDRAM_SDTR2_WTR_MASK 0x0F000000 | 761 | #define SDRAM_SDTR2_WTR_MASK 0x0F000000 |
762 | #define SDRAM_SDTR2_WTR_1_CLK 0x01000000 | 762 | #define SDRAM_SDTR2_WTR_1_CLK 0x01000000 |
763 | #define SDRAM_SDTR2_WTR_2_CLK 0x02000000 | 763 | #define SDRAM_SDTR2_WTR_2_CLK 0x02000000 |
764 | #define SDRAM_SDTR2_WTR_3_CLK 0x03000000 | 764 | #define SDRAM_SDTR2_WTR_3_CLK 0x03000000 |
765 | #define SDRAM_SDTR2_WTR_4_CLK 0x04000000 | 765 | #define SDRAM_SDTR2_WTR_4_CLK 0x04000000 |
766 | #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | 766 | #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) |
767 | #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 | 767 | #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 |
768 | #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 | 768 | #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 |
769 | #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 | 769 | #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 |
770 | #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 | 770 | #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 |
771 | #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 | 771 | #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 |
772 | #define SDRAM_SDTR2_WPC_MASK 0x0000F000 | 772 | #define SDRAM_SDTR2_WPC_MASK 0x0000F000 |
773 | #define SDRAM_SDTR2_WPC_2_CLK 0x00002000 | 773 | #define SDRAM_SDTR2_WPC_2_CLK 0x00002000 |
774 | #define SDRAM_SDTR2_WPC_3_CLK 0x00003000 | 774 | #define SDRAM_SDTR2_WPC_3_CLK 0x00003000 |
775 | #define SDRAM_SDTR2_WPC_4_CLK 0x00004000 | 775 | #define SDRAM_SDTR2_WPC_4_CLK 0x00004000 |
776 | #define SDRAM_SDTR2_WPC_5_CLK 0x00005000 | 776 | #define SDRAM_SDTR2_WPC_5_CLK 0x00005000 |
777 | #define SDRAM_SDTR2_WPC_6_CLK 0x00006000 | 777 | #define SDRAM_SDTR2_WPC_6_CLK 0x00006000 |
778 | #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) | 778 | #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) |
779 | #define SDRAM_SDTR2_RPC_MASK 0x00000F00 | 779 | #define SDRAM_SDTR2_RPC_MASK 0x00000F00 |
780 | #define SDRAM_SDTR2_RPC_2_CLK 0x00000200 | 780 | #define SDRAM_SDTR2_RPC_2_CLK 0x00000200 |
781 | #define SDRAM_SDTR2_RPC_3_CLK 0x00000300 | 781 | #define SDRAM_SDTR2_RPC_3_CLK 0x00000300 |
782 | #define SDRAM_SDTR2_RPC_4_CLK 0x00000400 | 782 | #define SDRAM_SDTR2_RPC_4_CLK 0x00000400 |
783 | #define SDRAM_SDTR2_RP_MASK 0x000000F0 | 783 | #define SDRAM_SDTR2_RP_MASK 0x000000F0 |
784 | #define SDRAM_SDTR2_RP_3_CLK 0x00000030 | 784 | #define SDRAM_SDTR2_RP_3_CLK 0x00000030 |
785 | #define SDRAM_SDTR2_RP_4_CLK 0x00000040 | 785 | #define SDRAM_SDTR2_RP_4_CLK 0x00000040 |
786 | #define SDRAM_SDTR2_RP_5_CLK 0x00000050 | 786 | #define SDRAM_SDTR2_RP_5_CLK 0x00000050 |
787 | #define SDRAM_SDTR2_RP_6_CLK 0x00000060 | 787 | #define SDRAM_SDTR2_RP_6_CLK 0x00000060 |
788 | #define SDRAM_SDTR2_RP_7_CLK 0x00000070 | 788 | #define SDRAM_SDTR2_RP_7_CLK 0x00000070 |
789 | #define SDRAM_SDTR2_RRD_MASK 0x0000000F | 789 | #define SDRAM_SDTR2_RRD_MASK 0x0000000F |
790 | #define SDRAM_SDTR2_RRD_2_CLK 0x00000002 | 790 | #define SDRAM_SDTR2_RRD_2_CLK 0x00000002 |
791 | #define SDRAM_SDTR2_RRD_3_CLK 0x00000003 | 791 | #define SDRAM_SDTR2_RRD_3_CLK 0x00000003 |
792 | 792 | ||
793 | /*-----------------------------------------------------------------------------+ | 793 | /*-----------------------------------------------------------------------------+ |
794 | | SDRAM SDTR3 Options | 794 | | SDRAM SDTR3 Options |
795 | +-----------------------------------------------------------------------------*/ | 795 | +-----------------------------------------------------------------------------*/ |
796 | #define SDRAM_SDTR3_RAS_MASK 0x1F000000 | 796 | #define SDRAM_SDTR3_RAS_MASK 0x1F000000 |
797 | #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) | 797 | #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) |
798 | #define SDRAM_SDTR3_RC_MASK 0x001F0000 | 798 | #define SDRAM_SDTR3_RC_MASK 0x001F0000 |
799 | #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) | 799 | #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) |
800 | #define SDRAM_SDTR3_XCS_MASK 0x00001F00 | 800 | #define SDRAM_SDTR3_XCS_MASK 0x00001F00 |
801 | #define SDRAM_SDTR3_XCS 0x00000D00 | 801 | #define SDRAM_SDTR3_XCS 0x00000D00 |
802 | #define SDRAM_SDTR3_RFC_MASK 0x0000003F | 802 | #define SDRAM_SDTR3_RFC_MASK 0x0000003F |
803 | #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) | 803 | #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) |
804 | 804 | ||
805 | /*-----------------------------------------------------------------------------+ | 805 | /*-----------------------------------------------------------------------------+ |
806 | | Memory Bank 0-1 configuration | 806 | | Memory Bank 0-1 configuration |
807 | +-----------------------------------------------------------------------------*/ | 807 | +-----------------------------------------------------------------------------*/ |
808 | #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ | 808 | #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ |
809 | #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ | 809 | #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ |
810 | #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ | 810 | #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ |
811 | #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ | 811 | #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ |
812 | #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ | 812 | #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ |
813 | #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ | 813 | #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ |
814 | #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ | 814 | #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ |
815 | #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ | 815 | #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ |
816 | #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ | 816 | #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ |
817 | #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ | 817 | #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ |
818 | #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ | 818 | #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ |
819 | #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ | 819 | #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ |
820 | #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ | 820 | #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ |
821 | #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ | 821 | #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ |
822 | #endif /* CONFIG_440SPE */ | 822 | #endif /* CONFIG_440SPE */ |
823 | 823 | ||
824 | /*----------------------------------------------------------------------------- | 824 | /*----------------------------------------------------------------------------- |
825 | | External Bus Controller | 825 | | External Bus Controller |
826 | +----------------------------------------------------------------------------*/ | 826 | +----------------------------------------------------------------------------*/ |
827 | #define EBC_DCR_BASE 0x12 | 827 | #define EBC_DCR_BASE 0x12 |
828 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ | 828 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ |
829 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ | 829 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ |
830 | /* values for ebccfga register - indirect addressing of these regs */ | 830 | /* values for ebccfga register - indirect addressing of these regs */ |
831 | #define pb0cr 0x00 /* periph bank 0 config reg */ | 831 | #define pb0cr 0x00 /* periph bank 0 config reg */ |
832 | #define pb1cr 0x01 /* periph bank 1 config reg */ | 832 | #define pb1cr 0x01 /* periph bank 1 config reg */ |
833 | #define pb2cr 0x02 /* periph bank 2 config reg */ | 833 | #define pb2cr 0x02 /* periph bank 2 config reg */ |
834 | #define pb3cr 0x03 /* periph bank 3 config reg */ | 834 | #define pb3cr 0x03 /* periph bank 3 config reg */ |
835 | #define pb4cr 0x04 /* periph bank 4 config reg */ | 835 | #define pb4cr 0x04 /* periph bank 4 config reg */ |
836 | #define pb5cr 0x05 /* periph bank 5 config reg */ | 836 | #define pb5cr 0x05 /* periph bank 5 config reg */ |
837 | #define pb6cr 0x06 /* periph bank 6 config reg */ | 837 | #define pb6cr 0x06 /* periph bank 6 config reg */ |
838 | #define pb7cr 0x07 /* periph bank 7 config reg */ | 838 | #define pb7cr 0x07 /* periph bank 7 config reg */ |
839 | #define pb0ap 0x10 /* periph bank 0 access parameters */ | 839 | #define pb0ap 0x10 /* periph bank 0 access parameters */ |
840 | #define pb1ap 0x11 /* periph bank 1 access parameters */ | 840 | #define pb1ap 0x11 /* periph bank 1 access parameters */ |
841 | #define pb2ap 0x12 /* periph bank 2 access parameters */ | 841 | #define pb2ap 0x12 /* periph bank 2 access parameters */ |
842 | #define pb3ap 0x13 /* periph bank 3 access parameters */ | 842 | #define pb3ap 0x13 /* periph bank 3 access parameters */ |
843 | #define pb4ap 0x14 /* periph bank 4 access parameters */ | 843 | #define pb4ap 0x14 /* periph bank 4 access parameters */ |
844 | #define pb5ap 0x15 /* periph bank 5 access parameters */ | 844 | #define pb5ap 0x15 /* periph bank 5 access parameters */ |
845 | #define pb6ap 0x16 /* periph bank 6 access parameters */ | 845 | #define pb6ap 0x16 /* periph bank 6 access parameters */ |
846 | #define pb7ap 0x17 /* periph bank 7 access parameters */ | 846 | #define pb7ap 0x17 /* periph bank 7 access parameters */ |
847 | #define pbear 0x20 /* periph bus error addr reg */ | 847 | #define pbear 0x20 /* periph bus error addr reg */ |
848 | #define pbesr 0x21 /* periph bus error status reg */ | 848 | #define pbesr 0x21 /* periph bus error status reg */ |
849 | #define xbcfg 0x23 /* external bus configuration reg */ | 849 | #define xbcfg 0x23 /* external bus configuration reg */ |
850 | #define xbcid 0x24 /* external bus core id reg */ | 850 | #define xbcid 0x24 /* external bus core id reg */ |
851 | 851 | ||
852 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | 852 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
853 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 853 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
854 | 854 | ||
855 | /* PLB4 to PLB3 Bridge OUT */ | 855 | /* PLB4 to PLB3 Bridge OUT */ |
856 | #define P4P3_DCR_BASE 0x020 | 856 | #define P4P3_DCR_BASE 0x020 |
857 | #define p4p3_esr0_read (P4P3_DCR_BASE+0x0) | 857 | #define p4p3_esr0_read (P4P3_DCR_BASE+0x0) |
858 | #define p4p3_esr0_write (P4P3_DCR_BASE+0x1) | 858 | #define p4p3_esr0_write (P4P3_DCR_BASE+0x1) |
859 | #define p4p3_eadr (P4P3_DCR_BASE+0x2) | 859 | #define p4p3_eadr (P4P3_DCR_BASE+0x2) |
860 | #define p4p3_euadr (P4P3_DCR_BASE+0x3) | 860 | #define p4p3_euadr (P4P3_DCR_BASE+0x3) |
861 | #define p4p3_esr1_read (P4P3_DCR_BASE+0x4) | 861 | #define p4p3_esr1_read (P4P3_DCR_BASE+0x4) |
862 | #define p4p3_esr1_write (P4P3_DCR_BASE+0x5) | 862 | #define p4p3_esr1_write (P4P3_DCR_BASE+0x5) |
863 | #define p4p3_confg (P4P3_DCR_BASE+0x6) | 863 | #define p4p3_confg (P4P3_DCR_BASE+0x6) |
864 | #define p4p3_pic (P4P3_DCR_BASE+0x7) | 864 | #define p4p3_pic (P4P3_DCR_BASE+0x7) |
865 | #define p4p3_peir (P4P3_DCR_BASE+0x8) | 865 | #define p4p3_peir (P4P3_DCR_BASE+0x8) |
866 | #define p4p3_rev (P4P3_DCR_BASE+0xA) | 866 | #define p4p3_rev (P4P3_DCR_BASE+0xA) |
867 | 867 | ||
868 | /* PLB3 to PLB4 Bridge IN */ | 868 | /* PLB3 to PLB4 Bridge IN */ |
869 | #define P3P4_DCR_BASE 0x030 | 869 | #define P3P4_DCR_BASE 0x030 |
870 | #define p3p4_esr0_read (P3P4_DCR_BASE+0x0) | 870 | #define p3p4_esr0_read (P3P4_DCR_BASE+0x0) |
871 | #define p3p4_esr0_write (P3P4_DCR_BASE+0x1) | 871 | #define p3p4_esr0_write (P3P4_DCR_BASE+0x1) |
872 | #define p3p4_eadr (P3P4_DCR_BASE+0x2) | 872 | #define p3p4_eadr (P3P4_DCR_BASE+0x2) |
873 | #define p3p4_euadr (P3P4_DCR_BASE+0x3) | 873 | #define p3p4_euadr (P3P4_DCR_BASE+0x3) |
874 | #define p3p4_esr1_read (P3P4_DCR_BASE+0x4) | 874 | #define p3p4_esr1_read (P3P4_DCR_BASE+0x4) |
875 | #define p3p4_esr1_write (P3P4_DCR_BASE+0x5) | 875 | #define p3p4_esr1_write (P3P4_DCR_BASE+0x5) |
876 | #define p3p4_confg (P3P4_DCR_BASE+0x6) | 876 | #define p3p4_confg (P3P4_DCR_BASE+0x6) |
877 | #define p3p4_pic (P3P4_DCR_BASE+0x7) | 877 | #define p3p4_pic (P3P4_DCR_BASE+0x7) |
878 | #define p3p4_peir (P3P4_DCR_BASE+0x8) | 878 | #define p3p4_peir (P3P4_DCR_BASE+0x8) |
879 | #define p3p4_rev (P3P4_DCR_BASE+0xA) | 879 | #define p3p4_rev (P3P4_DCR_BASE+0xA) |
880 | 880 | ||
881 | /* PLB3 Arbiter */ | 881 | /* PLB3 Arbiter */ |
882 | #define PLB3_DCR_BASE 0x070 | 882 | #define PLB3_DCR_BASE 0x070 |
883 | #define plb3_revid (PLB3_DCR_BASE+0x2) | 883 | #define plb3_revid (PLB3_DCR_BASE+0x2) |
884 | #define plb3_besr (PLB3_DCR_BASE+0x3) | 884 | #define plb3_besr (PLB3_DCR_BASE+0x3) |
885 | #define plb3_bear (PLB3_DCR_BASE+0x6) | 885 | #define plb3_bear (PLB3_DCR_BASE+0x6) |
886 | #define plb3_acr (PLB3_DCR_BASE+0x7) | 886 | #define plb3_acr (PLB3_DCR_BASE+0x7) |
887 | 887 | ||
888 | /* PLB4 Arbiter - PowerPC440EP Pass1 */ | 888 | /* PLB4 Arbiter - PowerPC440EP Pass1 */ |
889 | #define PLB4_DCR_BASE 0x080 | 889 | #define PLB4_DCR_BASE 0x080 |
890 | #define plb4_revid (PLB4_DCR_BASE+0x2) | 890 | #define plb4_revid (PLB4_DCR_BASE+0x2) |
891 | #define plb4_acr (PLB4_DCR_BASE+0x3) | 891 | #define plb4_acr (PLB4_DCR_BASE+0x3) |
892 | #define plb4_besr (PLB4_DCR_BASE+0x4) | 892 | #define plb4_besr (PLB4_DCR_BASE+0x4) |
893 | #define plb4_bearl (PLB4_DCR_BASE+0x6) | 893 | #define plb4_bearl (PLB4_DCR_BASE+0x6) |
894 | #define plb4_bearh (PLB4_DCR_BASE+0x7) | 894 | #define plb4_bearh (PLB4_DCR_BASE+0x7) |
895 | 895 | ||
896 | /* Nebula PLB4 Arbiter - PowerPC440EP */ | 896 | /* Nebula PLB4 Arbiter - PowerPC440EP */ |
897 | #define PLB_ARBITER_BASE 0x80 | 897 | #define PLB_ARBITER_BASE 0x80 |
898 | 898 | ||
899 | #define plb0_revid (PLB_ARBITER_BASE+ 0x00) | 899 | #define plb0_revid (PLB_ARBITER_BASE+ 0x00) |
900 | #define plb0_acr (PLB_ARBITER_BASE+ 0x01) | 900 | #define plb0_acr (PLB_ARBITER_BASE+ 0x01) |
901 | #define plb0_acr_ppm_mask 0xF0000000 | 901 | #define plb0_acr_ppm_mask 0xF0000000 |
902 | #define plb0_acr_ppm_fixed 0x00000000 | 902 | #define plb0_acr_ppm_fixed 0x00000000 |
903 | #define plb0_acr_ppm_fair 0xD0000000 | 903 | #define plb0_acr_ppm_fair 0xD0000000 |
904 | #define plb0_acr_hbu_mask 0x08000000 | 904 | #define plb0_acr_hbu_mask 0x08000000 |
905 | #define plb0_acr_hbu_disabled 0x00000000 | 905 | #define plb0_acr_hbu_disabled 0x00000000 |
906 | #define plb0_acr_hbu_enabled 0x08000000 | 906 | #define plb0_acr_hbu_enabled 0x08000000 |
907 | #define plb0_acr_rdp_mask 0x06000000 | 907 | #define plb0_acr_rdp_mask 0x06000000 |
908 | #define plb0_acr_rdp_disabled 0x00000000 | 908 | #define plb0_acr_rdp_disabled 0x00000000 |
909 | #define plb0_acr_rdp_2deep 0x02000000 | 909 | #define plb0_acr_rdp_2deep 0x02000000 |
910 | #define plb0_acr_rdp_3deep 0x04000000 | 910 | #define plb0_acr_rdp_3deep 0x04000000 |
911 | #define plb0_acr_rdp_4deep 0x06000000 | 911 | #define plb0_acr_rdp_4deep 0x06000000 |
912 | #define plb0_acr_wrp_mask 0x01000000 | 912 | #define plb0_acr_wrp_mask 0x01000000 |
913 | #define plb0_acr_wrp_disabled 0x00000000 | 913 | #define plb0_acr_wrp_disabled 0x00000000 |
914 | #define plb0_acr_wrp_2deep 0x01000000 | 914 | #define plb0_acr_wrp_2deep 0x01000000 |
915 | 915 | ||
916 | #define plb0_besrl (PLB_ARBITER_BASE+ 0x02) | 916 | #define plb0_besrl (PLB_ARBITER_BASE+ 0x02) |
917 | #define plb0_besrh (PLB_ARBITER_BASE+ 0x03) | 917 | #define plb0_besrh (PLB_ARBITER_BASE+ 0x03) |
918 | #define plb0_bearl (PLB_ARBITER_BASE+ 0x04) | 918 | #define plb0_bearl (PLB_ARBITER_BASE+ 0x04) |
919 | #define plb0_bearh (PLB_ARBITER_BASE+ 0x05) | 919 | #define plb0_bearh (PLB_ARBITER_BASE+ 0x05) |
920 | #define plb0_ccr (PLB_ARBITER_BASE+ 0x08) | 920 | #define plb0_ccr (PLB_ARBITER_BASE+ 0x08) |
921 | 921 | ||
922 | #define plb1_acr (PLB_ARBITER_BASE+ 0x09) | 922 | #define plb1_acr (PLB_ARBITER_BASE+ 0x09) |
923 | #define plb1_acr_ppm_mask 0xF0000000 | 923 | #define plb1_acr_ppm_mask 0xF0000000 |
924 | #define plb1_acr_ppm_fixed 0x00000000 | 924 | #define plb1_acr_ppm_fixed 0x00000000 |
925 | #define plb1_acr_ppm_fair 0xD0000000 | 925 | #define plb1_acr_ppm_fair 0xD0000000 |
926 | #define plb1_acr_hbu_mask 0x08000000 | 926 | #define plb1_acr_hbu_mask 0x08000000 |
927 | #define plb1_acr_hbu_disabled 0x00000000 | 927 | #define plb1_acr_hbu_disabled 0x00000000 |
928 | #define plb1_acr_hbu_enabled 0x08000000 | 928 | #define plb1_acr_hbu_enabled 0x08000000 |
929 | #define plb1_acr_rdp_mask 0x06000000 | 929 | #define plb1_acr_rdp_mask 0x06000000 |
930 | #define plb1_acr_rdp_disabled 0x00000000 | 930 | #define plb1_acr_rdp_disabled 0x00000000 |
931 | #define plb1_acr_rdp_2deep 0x02000000 | 931 | #define plb1_acr_rdp_2deep 0x02000000 |
932 | #define plb1_acr_rdp_3deep 0x04000000 | 932 | #define plb1_acr_rdp_3deep 0x04000000 |
933 | #define plb1_acr_rdp_4deep 0x06000000 | 933 | #define plb1_acr_rdp_4deep 0x06000000 |
934 | #define plb1_acr_wrp_mask 0x01000000 | 934 | #define plb1_acr_wrp_mask 0x01000000 |
935 | #define plb1_acr_wrp_disabled 0x00000000 | 935 | #define plb1_acr_wrp_disabled 0x00000000 |
936 | #define plb1_acr_wrp_2deep 0x01000000 | 936 | #define plb1_acr_wrp_2deep 0x01000000 |
937 | 937 | ||
938 | #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) | 938 | #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) |
939 | #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) | 939 | #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) |
940 | #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) | 940 | #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) |
941 | #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) | 941 | #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) |
942 | 942 | ||
943 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) | 943 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
944 | /* Pin Function Control Register 1 */ | 944 | /* Pin Function Control Register 1 */ |
945 | #define SDR0_PFC1 0x4101 | 945 | #define SDR0_PFC1 0x4101 |
946 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | 946 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ |
947 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | 947 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ |
948 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | 948 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ |
949 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | 949 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ |
950 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | 950 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ |
951 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | 951 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ |
952 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | 952 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ |
953 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | 953 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ |
954 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | 954 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ |
955 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | 955 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ |
956 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | 956 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ |
957 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | 957 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ |
958 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | 958 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ |
959 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | 959 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ |
960 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | 960 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ |
961 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | 961 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ |
962 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | 962 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ |
963 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | 963 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ |
964 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | 964 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ |
965 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | 965 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ |
966 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | 966 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ |
967 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | 967 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ |
968 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | 968 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ |
969 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | 969 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ |
970 | 970 | ||
971 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | 971 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ |
972 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | 972 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ |
973 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | 973 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ |
974 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | 974 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ |
975 | 975 | ||
976 | /* USB Control Register */ | 976 | /* USB Control Register */ |
977 | #define SDR0_USB0 0x0320 | 977 | #define SDR0_USB0 0x0320 |
978 | #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ | 978 | #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ |
979 | #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | 979 | #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ |
980 | #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | 980 | #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ |
981 | #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ | 981 | #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ |
982 | #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | 982 | #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ |
983 | #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | 983 | #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ |
984 | 984 | ||
985 | /* Miscealleneaous Function Reg. */ | 985 | /* Miscealleneaous Function Reg. */ |
986 | #define SDR0_MFR 0x4300 | 986 | #define SDR0_MFR 0x4300 |
987 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | 987 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ |
988 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | 988 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 |
989 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | 989 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ |
990 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | 990 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 |
991 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | 991 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ |
992 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | 992 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ |
993 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | 993 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ |
994 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | 994 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ |
995 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | 995 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ |
996 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | 996 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ |
997 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | 997 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ |
998 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | 998 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) |
999 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | 999 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) |
1000 | 1000 | ||
1001 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | 1001 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 |
1002 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | 1002 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 |
1003 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | 1003 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ |
1004 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | 1004 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ |
1005 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | 1005 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ |
1006 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | 1006 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ |
1007 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | 1007 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ |
1008 | 1008 | ||
1009 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ | 1009 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ |
1010 | 1010 | ||
1011 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 1011 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1012 | #define SDR_USB2D0CR 0x0320 | 1012 | #define SDR_USB2D0CR 0x0320 |
1013 | #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ | 1013 | #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ |
1014 | #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ | 1014 | #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ |
1015 | #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ | 1015 | #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ |
1016 | 1016 | ||
1017 | #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */ | 1017 | #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */ |
1018 | #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | 1018 | #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ |
1019 | #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | 1019 | #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ |
1020 | 1020 | ||
1021 | #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ | 1021 | #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ |
1022 | #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | 1022 | #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ |
1023 | #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | 1023 | #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ |
1024 | 1024 | ||
1025 | /* USB2 Host Control Register */ | 1025 | /* USB2 Host Control Register */ |
1026 | #define SDR0_USB2H0CR 0x0340 | 1026 | #define SDR0_USB2H0CR 0x0340 |
1027 | #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */ | 1027 | #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */ |
1028 | #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ | 1028 | #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ |
1029 | #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ | 1029 | #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ |
1030 | #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */ | 1030 | #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */ |
1031 | 1031 | ||
1032 | /* Pin Function Control Register 1 */ | 1032 | /* Pin Function Control Register 1 */ |
1033 | #define SDR0_PFC1 0x4101 | 1033 | #define SDR0_PFC1 0x4101 |
1034 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | 1034 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ |
1035 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | 1035 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ |
1036 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | 1036 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ |
1037 | 1037 | ||
1038 | #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */ | 1038 | #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */ |
1039 | #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */ | 1039 | #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */ |
1040 | #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | 1040 | #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ |
1041 | #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */ | 1041 | #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */ |
1042 | #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */ | 1042 | #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */ |
1043 | #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */ | 1043 | #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */ |
1044 | #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */ | 1044 | #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */ |
1045 | #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */ | 1045 | #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */ |
1046 | 1046 | ||
1047 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | 1047 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ |
1048 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | 1048 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ |
1049 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | 1049 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ |
1050 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | 1050 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ |
1051 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | 1051 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ |
1052 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | 1052 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ |
1053 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | 1053 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ |
1054 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | 1054 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ |
1055 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | 1055 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ |
1056 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | 1056 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ |
1057 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | 1057 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ |
1058 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | 1058 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ |
1059 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | 1059 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ |
1060 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | 1060 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ |
1061 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | 1061 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ |
1062 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | 1062 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ |
1063 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | 1063 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ |
1064 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | 1064 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ |
1065 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | 1065 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ |
1066 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | 1066 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ |
1067 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | 1067 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ |
1068 | 1068 | ||
1069 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | 1069 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ |
1070 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | 1070 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ |
1071 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | 1071 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ |
1072 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | 1072 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ |
1073 | 1073 | ||
1074 | /* Ethernet PLL Configuration Register */ | 1074 | /* Ethernet PLL Configuration Register */ |
1075 | #define SDR0_PFC2 0x4102 | 1075 | #define SDR0_PFC2 0x4102 |
1076 | #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ | 1076 | #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ |
1077 | #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */ | 1077 | #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */ |
1078 | #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ | 1078 | #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ |
1079 | #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ | 1079 | #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ |
1080 | 1080 | ||
1081 | #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ | 1081 | #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ |
1082 | #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ | 1082 | #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ |
1083 | #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | 1083 | #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ |
1084 | #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ | 1084 | #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ |
1085 | #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ | 1085 | #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ |
1086 | #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ | 1086 | #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ |
1087 | #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ | 1087 | #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ |
1088 | #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ | 1088 | #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ |
1089 | 1089 | ||
1090 | /* USB2PHY0 Control Register */ | 1090 | /* USB2PHY0 Control Register */ |
1091 | #define SDR0_USB2PHY0CR 0x4103 | 1091 | #define SDR0_USB2PHY0CR 0x4103 |
1092 | #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ | 1092 | #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ |
1093 | #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ | 1093 | #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ |
1094 | #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ | 1094 | #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ |
1095 | 1095 | ||
1096 | #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ | 1096 | #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ |
1097 | #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ | 1097 | #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ |
1098 | #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ | 1098 | #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ |
1099 | 1099 | ||
1100 | #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */ | 1100 | #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */ |
1101 | #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */ | 1101 | #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */ |
1102 | #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */ | 1102 | #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */ |
1103 | 1103 | ||
1104 | #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */ | 1104 | #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */ |
1105 | #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ | 1105 | #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ |
1106 | #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ | 1106 | #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ |
1107 | 1107 | ||
1108 | #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ | 1108 | #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ |
1109 | #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ | 1109 | #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ |
1110 | #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */ | 1110 | #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */ |
1111 | 1111 | ||
1112 | #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */ | 1112 | #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */ |
1113 | #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ | 1113 | #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ |
1114 | #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */ | 1114 | #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */ |
1115 | 1115 | ||
1116 | #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ | 1116 | #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ |
1117 | #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ | 1117 | #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ |
1118 | #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */ | 1118 | #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */ |
1119 | 1119 | ||
1120 | #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */ | 1120 | #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */ |
1121 | #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */ | 1121 | #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */ |
1122 | #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */ | 1122 | #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */ |
1123 | 1123 | ||
1124 | #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */ | 1124 | #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */ |
1125 | #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */ | 1125 | #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */ |
1126 | #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */ | 1126 | #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */ |
1127 | 1127 | ||
1128 | #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ | 1128 | #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ |
1129 | #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/ | 1129 | #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/ |
1130 | #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/ | 1130 | #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/ |
1131 | #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/ | 1131 | #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/ |
1132 | 1132 | ||
1133 | /* Miscealleneaous Function Reg. */ | 1133 | /* Miscealleneaous Function Reg. */ |
1134 | #define SDR0_MFR 0x4300 | 1134 | #define SDR0_MFR 0x4300 |
1135 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | 1135 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ |
1136 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | 1136 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 |
1137 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | 1137 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ |
1138 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | 1138 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 |
1139 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | 1139 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ |
1140 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | 1140 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ |
1141 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | 1141 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ |
1142 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | 1142 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ |
1143 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | 1143 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ |
1144 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | 1144 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) |
1145 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | 1145 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) |
1146 | 1146 | ||
1147 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | 1147 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 |
1148 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | 1148 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 |
1149 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | 1149 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ |
1150 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | 1150 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ |
1151 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | 1151 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ |
1152 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | 1152 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ |
1153 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | 1153 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ |
1154 | 1154 | ||
1155 | #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ | 1155 | #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ |
1156 | 1156 | ||
1157 | /* CUST0 Customer Configuration Register0 */ | 1157 | /* CUST0 Customer Configuration Register0 */ |
1158 | #define SDR0_CUST0 0x4000 | 1158 | #define SDR0_CUST0 0x4000 |
1159 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | 1159 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ |
1160 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | 1160 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ |
1161 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | 1161 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ |
1162 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | 1162 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ |
1163 | 1163 | ||
1164 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | 1164 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ |
1165 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | 1165 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ |
1166 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | 1166 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ |
1167 | 1167 | ||
1168 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | 1168 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ |
1169 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | 1169 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ |
1170 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | 1170 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ |
1171 | 1171 | ||
1172 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | 1172 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ |
1173 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | 1173 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) |
1174 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | 1174 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) |
1175 | 1175 | ||
1176 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | 1176 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ |
1177 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) | 1177 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) |
1178 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | 1178 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) |
1179 | 1179 | ||
1180 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | 1180 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ |
1181 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | 1181 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ |
1182 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | 1182 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ |
1183 | 1183 | ||
1184 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | 1184 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ |
1185 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | 1185 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ |
1186 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | 1186 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ |
1187 | 1187 | ||
1188 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | 1188 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ |
1189 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) | 1189 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) |
1190 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) | 1190 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) |
1191 | 1191 | ||
1192 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | 1192 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ |
1193 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | 1193 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ |
1194 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ | 1194 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ |
1195 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | 1195 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ |
1196 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | 1196 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ |
1197 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | 1197 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ |
1198 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | 1198 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ |
1199 | 1199 | ||
1200 | /* CUST1 Customer Configuration Register1 */ | 1200 | /* CUST1 Customer Configuration Register1 */ |
1201 | #define SDR0_CUST1 0x4002 | 1201 | #define SDR0_CUST1 0x4002 |
1202 | #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ | 1202 | #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ |
1203 | #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) | 1203 | #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) |
1204 | #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) | 1204 | #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) |
1205 | 1205 | ||
1206 | /* Pin Function Control Register 0 */ | 1206 | /* Pin Function Control Register 0 */ |
1207 | #define SDR0_PFC0 0x4100 | 1207 | #define SDR0_PFC0 0x4100 |
1208 | #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ | 1208 | #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ |
1209 | #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ | 1209 | #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ |
1210 | #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ | 1210 | #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ |
1211 | #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | 1211 | #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) |
1212 | #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | 1212 | #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) |
1213 | 1213 | ||
1214 | /* Pin Function Control Register 1 */ | 1214 | /* Pin Function Control Register 1 */ |
1215 | #define SDR0_PFC1 0x4101 | 1215 | #define SDR0_PFC1 0x4101 |
1216 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | 1216 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ |
1217 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | 1217 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ |
1218 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | 1218 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ |
1219 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | 1219 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ |
1220 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | 1220 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ |
1221 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | 1221 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ |
1222 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | 1222 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ |
1223 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | 1223 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ |
1224 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | 1224 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ |
1225 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | 1225 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ |
1226 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | 1226 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ |
1227 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | 1227 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ |
1228 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | 1228 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ |
1229 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | 1229 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ |
1230 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | 1230 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ |
1231 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | 1231 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ |
1232 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | 1232 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ |
1233 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | 1233 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ |
1234 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | 1234 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ |
1235 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | 1235 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ |
1236 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | 1236 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ |
1237 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | 1237 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ |
1238 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | 1238 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ |
1239 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | 1239 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ |
1240 | 1240 | ||
1241 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | 1241 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ |
1242 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | 1242 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ |
1243 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | 1243 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ |
1244 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | 1244 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ |
1245 | 1245 | ||
1246 | /*----------------------------------------------------------------------------- | 1246 | /*----------------------------------------------------------------------------- |
1247 | | Internal SRAM | 1247 | | Internal SRAM |
1248 | +----------------------------------------------------------------------------*/ | 1248 | +----------------------------------------------------------------------------*/ |
1249 | #define ISRAM0_DCR_BASE 0x380 | 1249 | #define ISRAM0_DCR_BASE 0x380 |
1250 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ | 1250 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ |
1251 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ | 1251 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ |
1252 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ | 1252 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ |
1253 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ | 1253 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ |
1254 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ | 1254 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ |
1255 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ | 1255 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ |
1256 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ | 1256 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ |
1257 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ | 1257 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ |
1258 | 1258 | ||
1259 | #else | 1259 | #else |
1260 | 1260 | ||
1261 | /*----------------------------------------------------------------------------- | 1261 | /*----------------------------------------------------------------------------- |
1262 | | Internal SRAM | 1262 | | Internal SRAM |
1263 | +----------------------------------------------------------------------------*/ | 1263 | +----------------------------------------------------------------------------*/ |
1264 | #define ISRAM0_DCR_BASE 0x020 | 1264 | #define ISRAM0_DCR_BASE 0x020 |
1265 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ | 1265 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ |
1266 | #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ | 1266 | #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ |
1267 | #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ | 1267 | #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ |
1268 | #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ | 1268 | #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ |
1269 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ | 1269 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ |
1270 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ | 1270 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ |
1271 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ | 1271 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ |
1272 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ | 1272 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ |
1273 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ | 1273 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ |
1274 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ | 1274 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ |
1275 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ | 1275 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ |
1276 | 1276 | ||
1277 | /*----------------------------------------------------------------------------- | 1277 | /*----------------------------------------------------------------------------- |
1278 | | L2 Cache | 1278 | | L2 Cache |
1279 | +----------------------------------------------------------------------------*/ | 1279 | +----------------------------------------------------------------------------*/ |
1280 | #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) | 1280 | #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
1281 | #define L2_CACHE_BASE 0x030 | 1281 | #define L2_CACHE_BASE 0x030 |
1282 | #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ | 1282 | #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ |
1283 | #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ | 1283 | #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ |
1284 | #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ | 1284 | #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ |
1285 | #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ | 1285 | #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ |
1286 | #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ | 1286 | #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ |
1287 | #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ | 1287 | #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ |
1288 | #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ | 1288 | #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ |
1289 | #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ | 1289 | #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ |
1290 | 1290 | ||
1291 | #endif /* CONFIG_440GX */ | 1291 | #endif /* CONFIG_440GX */ |
1292 | #endif /* !CONFIG_440EP !CONFIG_440GR*/ | 1292 | #endif /* !CONFIG_440EP !CONFIG_440GR*/ |
1293 | 1293 | ||
1294 | /*----------------------------------------------------------------------------- | 1294 | /*----------------------------------------------------------------------------- |
1295 | | On-Chip Buses | 1295 | | On-Chip Buses |
1296 | +----------------------------------------------------------------------------*/ | 1296 | +----------------------------------------------------------------------------*/ |
1297 | /* TODO: as needed */ | 1297 | /* TODO: as needed */ |
1298 | 1298 | ||
1299 | /*----------------------------------------------------------------------------- | 1299 | /*----------------------------------------------------------------------------- |
1300 | | Clocking, Power Management and Chip Control | 1300 | | Clocking, Power Management and Chip Control |
1301 | +----------------------------------------------------------------------------*/ | 1301 | +----------------------------------------------------------------------------*/ |
1302 | #define CNTRL_DCR_BASE 0x0b0 | 1302 | #define CNTRL_DCR_BASE 0x0b0 |
1303 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) | 1303 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
1304 | #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ | 1304 | #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ |
1305 | #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ | 1305 | #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ |
1306 | #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ | 1306 | #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ |
1307 | #else | 1307 | #else |
1308 | #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ | 1308 | #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ |
1309 | #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ | 1309 | #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ |
1310 | #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ | 1310 | #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ |
1311 | #endif | 1311 | #endif |
1312 | 1312 | ||
1313 | #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ | 1313 | #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ |
1314 | #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ | 1314 | #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ |
1315 | #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ | 1315 | #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ |
1316 | #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ | 1316 | #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ |
1317 | 1317 | ||
1318 | #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ | 1318 | #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ |
1319 | #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ | 1319 | #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ |
1320 | #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ | 1320 | #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ |
1321 | #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ | 1321 | #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ |
1322 | 1322 | ||
1323 | #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ | 1323 | #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ |
1324 | 1324 | ||
1325 | #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ | 1325 | #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ |
1326 | #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ | 1326 | #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ |
1327 | 1327 | ||
1328 | /*----------------------------------------------------------------------------- | 1328 | /*----------------------------------------------------------------------------- |
1329 | | Universal interrupt controller | 1329 | | Universal interrupt controller |
1330 | +----------------------------------------------------------------------------*/ | 1330 | +----------------------------------------------------------------------------*/ |
1331 | #define UIC0_DCR_BASE 0xc0 | 1331 | #define UIC0_DCR_BASE 0xc0 |
1332 | #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ | 1332 | #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ |
1333 | #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ | 1333 | #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ |
1334 | #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ | 1334 | #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ |
1335 | #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ | 1335 | #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ |
1336 | #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ | 1336 | #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ |
1337 | #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ | 1337 | #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ |
1338 | #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ | 1338 | #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ |
1339 | #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ | 1339 | #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ |
1340 | 1340 | ||
1341 | #define UIC1_DCR_BASE 0xd0 | 1341 | #define UIC1_DCR_BASE 0xd0 |
1342 | #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ | 1342 | #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ |
1343 | #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ | 1343 | #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ |
1344 | #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ | 1344 | #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ |
1345 | #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ | 1345 | #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ |
1346 | #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ | 1346 | #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ |
1347 | #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ | 1347 | #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ |
1348 | #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ | 1348 | #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ |
1349 | #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ | 1349 | #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ |
1350 | 1350 | ||
1351 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 1351 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1352 | #define UIC2_DCR_BASE 0xe0 | 1352 | #define UIC2_DCR_BASE 0xe0 |
1353 | #define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ | 1353 | #define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ |
1354 | #define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ | 1354 | #define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ |
1355 | #define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */ | 1355 | #define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */ |
1356 | #define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */ | 1356 | #define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */ |
1357 | #define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */ | 1357 | #define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */ |
1358 | #define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */ | 1358 | #define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */ |
1359 | #define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */ | 1359 | #define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */ |
1360 | #define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */ | 1360 | #define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */ |
1361 | #define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */ | 1361 | #define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */ |
1362 | 1362 | ||
1363 | #define UIC3_DCR_BASE 0xf0 | 1363 | #define UIC3_DCR_BASE 0xf0 |
1364 | #define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */ | 1364 | #define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */ |
1365 | #define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */ | 1365 | #define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */ |
1366 | #define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */ | 1366 | #define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */ |
1367 | #define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */ | 1367 | #define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */ |
1368 | #define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */ | 1368 | #define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */ |
1369 | #define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */ | 1369 | #define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */ |
1370 | #define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */ | 1370 | #define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */ |
1371 | #define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */ | 1371 | #define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */ |
1372 | #define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */ | 1372 | #define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */ |
1373 | #endif /* CONFIG_440SPE */ | 1373 | #endif /* CONFIG_440SPE */ |
1374 | 1374 | ||
1375 | #if defined(CONFIG_440GX) | 1375 | #if defined(CONFIG_440GX) |
1376 | #define UIC2_DCR_BASE 0x210 | 1376 | #define UIC2_DCR_BASE 0x210 |
1377 | #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ | 1377 | #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ |
1378 | #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ | 1378 | #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ |
1379 | #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ | 1379 | #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ |
1380 | #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ | 1380 | #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ |
1381 | #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ | 1381 | #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ |
1382 | #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ | 1382 | #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ |
1383 | #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ | 1383 | #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ |
1384 | #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ | 1384 | #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ |
1385 | 1385 | ||
1386 | 1386 | ||
1387 | #define UIC_DCR_BASE 0x200 | 1387 | #define UIC_DCR_BASE 0x200 |
1388 | #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ | 1388 | #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ |
1389 | #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ | 1389 | #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ |
1390 | #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ | 1390 | #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ |
1391 | #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ | 1391 | #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ |
1392 | #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ | 1392 | #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ |
1393 | #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ | 1393 | #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ |
1394 | #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ | 1394 | #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ |
1395 | #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ | 1395 | #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ |
1396 | #endif /* CONFIG_440GX */ | 1396 | #endif /* CONFIG_440GX */ |
1397 | 1397 | ||
1398 | /* The following is for compatibility with 405 code */ | 1398 | /* The following is for compatibility with 405 code */ |
1399 | #define uicsr uic0sr | 1399 | #define uicsr uic0sr |
1400 | #define uicer uic0er | 1400 | #define uicer uic0er |
1401 | #define uiccr uic0cr | 1401 | #define uiccr uic0cr |
1402 | #define uicpr uic0pr | 1402 | #define uicpr uic0pr |
1403 | #define uictr uic0tr | 1403 | #define uictr uic0tr |
1404 | #define uicmsr uic0msr | 1404 | #define uicmsr uic0msr |
1405 | #define uicvr uic0vr | 1405 | #define uicvr uic0vr |
1406 | #define uicvcr uic0vcr | 1406 | #define uicvcr uic0vcr |
1407 | 1407 | ||
1408 | #if defined(CONFIG_440SPE) | 1408 | #if defined(CONFIG_440SPE) |
1409 | /*----------------------------------------------------------------------------+ | 1409 | /*----------------------------------------------------------------------------+ |
1410 | | Clock / Power-on-reset DCR's. | 1410 | | Clock / Power-on-reset DCR's. |
1411 | +----------------------------------------------------------------------------*/ | 1411 | +----------------------------------------------------------------------------*/ |
1412 | #define CPR0_CFGADDR 0x00C | 1412 | #define CPR0_CFGADDR 0x00C |
1413 | #define CPR0_CFGDATA 0x00D | 1413 | #define CPR0_CFGDATA 0x00D |
1414 | 1414 | ||
1415 | #define CPR0_CLKUPD 0x20 | 1415 | #define CPR0_CLKUPD 0x20 |
1416 | #define CPR0_CLKUPD_BSY_MASK 0x80000000 | 1416 | #define CPR0_CLKUPD_BSY_MASK 0x80000000 |
1417 | #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 | 1417 | #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 |
1418 | #define CPR0_CLKUPD_BSY_BUSY 0x80000000 | 1418 | #define CPR0_CLKUPD_BSY_BUSY 0x80000000 |
1419 | #define CPR0_CLKUPD_CUI_MASK 0x80000000 | 1419 | #define CPR0_CLKUPD_CUI_MASK 0x80000000 |
1420 | #define CPR0_CLKUPD_CUI_DISABLE 0x00000000 | 1420 | #define CPR0_CLKUPD_CUI_DISABLE 0x00000000 |
1421 | #define CPR0_CLKUPD_CUI_ENABLE 0x80000000 | 1421 | #define CPR0_CLKUPD_CUI_ENABLE 0x80000000 |
1422 | #define CPR0_CLKUPD_CUD_MASK 0x40000000 | 1422 | #define CPR0_CLKUPD_CUD_MASK 0x40000000 |
1423 | #define CPR0_CLKUPD_CUD_DISABLE 0x00000000 | 1423 | #define CPR0_CLKUPD_CUD_DISABLE 0x00000000 |
1424 | #define CPR0_CLKUPD_CUD_ENABLE 0x40000000 | 1424 | #define CPR0_CLKUPD_CUD_ENABLE 0x40000000 |
1425 | 1425 | ||
1426 | #define CPR0_PLLC 0x40 | 1426 | #define CPR0_PLLC 0x40 |
1427 | #define CPR0_PLLC_RST_MASK 0x80000000 | 1427 | #define CPR0_PLLC_RST_MASK 0x80000000 |
1428 | #define CPR0_PLLC_RST_PLLLOCKED 0x00000000 | 1428 | #define CPR0_PLLC_RST_PLLLOCKED 0x00000000 |
1429 | #define CPR0_PLLC_RST_PLLRESET 0x80000000 | 1429 | #define CPR0_PLLC_RST_PLLRESET 0x80000000 |
1430 | #define CPR0_PLLC_ENG_MASK 0x40000000 | 1430 | #define CPR0_PLLC_ENG_MASK 0x40000000 |
1431 | #define CPR0_PLLC_ENG_DISABLE 0x00000000 | 1431 | #define CPR0_PLLC_ENG_DISABLE 0x00000000 |
1432 | #define CPR0_PLLC_ENG_ENABLE 0x40000000 | 1432 | #define CPR0_PLLC_ENG_ENABLE 0x40000000 |
1433 | #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 1433 | #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
1434 | #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 1434 | #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
1435 | #define CPR0_PLLC_SRC_MASK 0x20000000 | 1435 | #define CPR0_PLLC_SRC_MASK 0x20000000 |
1436 | #define CPR0_PLLC_SRC_PLLOUTA 0x00000000 | 1436 | #define CPR0_PLLC_SRC_PLLOUTA 0x00000000 |
1437 | #define CPR0_PLLC_SRC_PLLOUTB 0x20000000 | 1437 | #define CPR0_PLLC_SRC_PLLOUTB 0x20000000 |
1438 | #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | 1438 | #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) |
1439 | #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | 1439 | #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) |
1440 | #define CPR0_PLLC_SEL_MASK 0x07000000 | 1440 | #define CPR0_PLLC_SEL_MASK 0x07000000 |
1441 | #define CPR0_PLLC_SEL_PLLOUT 0x00000000 | 1441 | #define CPR0_PLLC_SEL_PLLOUT 0x00000000 |
1442 | #define CPR0_PLLC_SEL_CPU 0x01000000 | 1442 | #define CPR0_PLLC_SEL_CPU 0x01000000 |
1443 | #define CPR0_PLLC_SEL_EBC 0x05000000 | 1443 | #define CPR0_PLLC_SEL_EBC 0x05000000 |
1444 | #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 1444 | #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
1445 | #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) | 1445 | #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) |
1446 | #define CPR0_PLLC_TUNE_MASK 0x000003FF | 1446 | #define CPR0_PLLC_TUNE_MASK 0x000003FF |
1447 | #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) | 1447 | #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) |
1448 | #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) | 1448 | #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) |
1449 | 1449 | ||
1450 | #define CPR0_PLLD 0x60 | 1450 | #define CPR0_PLLD 0x60 |
1451 | #define CPR0_PLLD_FBDV_MASK 0x1F000000 | 1451 | #define CPR0_PLLD_FBDV_MASK 0x1F000000 |
1452 | #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) | 1452 | #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) |
1453 | #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) | 1453 | #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) |
1454 | #define CPR0_PLLD_FWDVA_MASK 0x000F0000 | 1454 | #define CPR0_PLLD_FWDVA_MASK 0x000F0000 |
1455 | #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) | 1455 | #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) |
1456 | #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) | 1456 | #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) |
1457 | #define CPR0_PLLD_FWDVB_MASK 0x00000700 | 1457 | #define CPR0_PLLD_FWDVB_MASK 0x00000700 |
1458 | #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) | 1458 | #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) |
1459 | #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) | 1459 | #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) |
1460 | #define CPR0_PLLD_LFBDV_MASK 0x0000003F | 1460 | #define CPR0_PLLD_LFBDV_MASK 0x0000003F |
1461 | #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) | 1461 | #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) |
1462 | #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) | 1462 | #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) |
1463 | 1463 | ||
1464 | #define CPR0_PRIMAD 0x80 | 1464 | #define CPR0_PRIMAD 0x80 |
1465 | #define CPR0_PRIMAD_PRADV0_MASK 0x07000000 | 1465 | #define CPR0_PRIMAD_PRADV0_MASK 0x07000000 |
1466 | #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 1466 | #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
1467 | #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) | 1467 | #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) |
1468 | 1468 | ||
1469 | #define CPR0_PRIMBD 0xA0 | 1469 | #define CPR0_PRIMBD 0xA0 |
1470 | #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 | 1470 | #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 |
1471 | #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 1471 | #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
1472 | #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) | 1472 | #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) |
1473 | 1473 | ||
1474 | #define CPR0_OPBD 0xC0 | 1474 | #define CPR0_OPBD 0xC0 |
1475 | #define CPR0_OPBD_OPBDV0_MASK 0x03000000 | 1475 | #define CPR0_OPBD_OPBDV0_MASK 0x03000000 |
1476 | #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 1476 | #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
1477 | #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 1477 | #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
1478 | 1478 | ||
1479 | #define CPR0_PERD 0xE0 | 1479 | #define CPR0_PERD 0xE0 |
1480 | #define CPR0_PERD_PERDV0_MASK 0x03000000 | 1480 | #define CPR0_PERD_PERDV0_MASK 0x03000000 |
1481 | #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 1481 | #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
1482 | #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 1482 | #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
1483 | 1483 | ||
1484 | #define CPR0_MALD 0x100 | 1484 | #define CPR0_MALD 0x100 |
1485 | #define CPR0_MALD_MALDV0_MASK 0x03000000 | 1485 | #define CPR0_MALD_MALDV0_MASK 0x03000000 |
1486 | #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 1486 | #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
1487 | #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 1487 | #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
1488 | 1488 | ||
1489 | #define CPR0_ICFG 0x140 | 1489 | #define CPR0_ICFG 0x140 |
1490 | #define CPR0_ICFG_RLI_MASK 0x80000000 | 1490 | #define CPR0_ICFG_RLI_MASK 0x80000000 |
1491 | #define CPR0_ICFG_RLI_RESETCPR 0x00000000 | 1491 | #define CPR0_ICFG_RLI_RESETCPR 0x00000000 |
1492 | #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 | 1492 | #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 |
1493 | #define CPR0_ICFG_ICS_MASK 0x00000007 | 1493 | #define CPR0_ICFG_ICS_MASK 0x00000007 |
1494 | #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) | 1494 | #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) |
1495 | #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) | 1495 | #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) |
1496 | 1496 | ||
1497 | /************************/ | 1497 | /************************/ |
1498 | /* IIC defines */ | 1498 | /* IIC defines */ |
1499 | /************************/ | 1499 | /************************/ |
1500 | #define IIC0_MMIO_BASE 0xA0000400 | 1500 | #define IIC0_MMIO_BASE 0xA0000400 |
1501 | #define IIC1_MMIO_BASE 0xA0000500 | 1501 | #define IIC1_MMIO_BASE 0xA0000500 |
1502 | 1502 | ||
1503 | #endif /* CONFIG_440SP */ | 1503 | #endif /* CONFIG_440SP */ |
1504 | 1504 | ||
1505 | /*----------------------------------------------------------------------------- | 1505 | /*----------------------------------------------------------------------------- |
1506 | | DMA | 1506 | | DMA |
1507 | +----------------------------------------------------------------------------*/ | 1507 | +----------------------------------------------------------------------------*/ |
1508 | #define DMA_DCR_BASE 0x100 | 1508 | #define DMA_DCR_BASE 0x100 |
1509 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ | 1509 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
1510 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | 1510 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ |
1511 | #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ | 1511 | #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ |
1512 | #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ | 1512 | #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ |
1513 | #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ | 1513 | #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ |
1514 | #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ | 1514 | #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ |
1515 | #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ | 1515 | #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ |
1516 | #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ | 1516 | #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ |
1517 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ | 1517 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ |
1518 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | 1518 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ |
1519 | #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ | 1519 | #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ |
1520 | #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ | 1520 | #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ |
1521 | #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ | 1521 | #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ |
1522 | #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ | 1522 | #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ |
1523 | #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ | 1523 | #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ |
1524 | #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ | 1524 | #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ |
1525 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ | 1525 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ |
1526 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | 1526 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ |
1527 | #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ | 1527 | #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ |
1528 | #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ | 1528 | #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ |
1529 | #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ | 1529 | #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ |
1530 | #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ | 1530 | #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ |
1531 | #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ | 1531 | #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ |
1532 | #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ | 1532 | #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ |
1533 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ | 1533 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ |
1534 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ | 1534 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ |
1535 | #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ | 1535 | #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ |
1536 | #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ | 1536 | #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ |
1537 | #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ | 1537 | #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ |
1538 | #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ | 1538 | #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ |
1539 | #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ | 1539 | #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ |
1540 | #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ | 1540 | #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ |
1541 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ | 1541 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ |
1542 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | 1542 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ |
1543 | #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ | 1543 | #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ |
1544 | #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ | 1544 | #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ |
1545 | 1545 | ||
1546 | /*----------------------------------------------------------------------------- | 1546 | /*----------------------------------------------------------------------------- |
1547 | | Memory Access Layer | 1547 | | Memory Access Layer |
1548 | +----------------------------------------------------------------------------*/ | 1548 | +----------------------------------------------------------------------------*/ |
1549 | #define MAL_DCR_BASE 0x180 | 1549 | #define MAL_DCR_BASE 0x180 |
1550 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ | 1550 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ |
1551 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ | 1551 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ |
1552 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | 1552 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ |
1553 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | 1553 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ |
1554 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ | 1554 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ |
1555 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ | 1555 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ |
1556 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | 1556 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ |
1557 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ | 1557 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ |
1558 | #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ | 1558 | #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ |
1559 | #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ | 1559 | #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ |
1560 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ | 1560 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ |
1561 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ | 1561 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ |
1562 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | 1562 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ |
1563 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ | 1563 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ |
1564 | #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ | 1564 | #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ |
1565 | #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ | 1565 | #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ |
1566 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ | 1566 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ |
1567 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ | 1567 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ |
1568 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ | 1568 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ |
1569 | #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ | 1569 | #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ |
1570 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ | 1570 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
1571 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ | 1571 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ |
1572 | #if defined(CONFIG_440GX) | 1572 | #if defined(CONFIG_440GX) |
1573 | #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ | 1573 | #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ |
1574 | #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ | 1574 | #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ |
1575 | #endif /* CONFIG_440GX */ | 1575 | #endif /* CONFIG_440GX */ |
1576 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ | 1576 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
1577 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ | 1577 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ |
1578 | #if defined(CONFIG_440GX) | 1578 | #if defined(CONFIG_440GX) |
1579 | #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ | 1579 | #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ |
1580 | #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ | 1580 | #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ |
1581 | #endif /* CONFIG_440GX */ | 1581 | #endif /* CONFIG_440GX */ |
1582 | 1582 | ||
1583 | 1583 | ||
1584 | /*---------------------------------------------------------------------------+ | 1584 | /*---------------------------------------------------------------------------+ |
1585 | | Universal interrupt controller 0 interrupts (UIC0) | 1585 | | Universal interrupt controller 0 interrupts (UIC0) |
1586 | +---------------------------------------------------------------------------*/ | 1586 | +---------------------------------------------------------------------------*/ |
1587 | #if defined(CONFIG_440SP) | 1587 | #if defined(CONFIG_440SP) |
1588 | #define UIC_U0 0x80000000 /* UART 0 */ | 1588 | #define UIC_U0 0x80000000 /* UART 0 */ |
1589 | #define UIC_U1 0x40000000 /* UART 1 */ | 1589 | #define UIC_U1 0x40000000 /* UART 1 */ |
1590 | #define UIC_IIC0 0x20000000 /* IIC */ | 1590 | #define UIC_IIC0 0x20000000 /* IIC */ |
1591 | #define UIC_IIC1 0x10000000 /* IIC */ | 1591 | #define UIC_IIC1 0x10000000 /* IIC */ |
1592 | #define UIC_PIM 0x08000000 /* PCI0 inbound message */ | 1592 | #define UIC_PIM 0x08000000 /* PCI0 inbound message */ |
1593 | #define UIC_PCRW 0x04000000 /* PCI0 command write register */ | 1593 | #define UIC_PCRW 0x04000000 /* PCI0 command write register */ |
1594 | #define UIC_PPM 0x02000000 /* PCI0 power management */ | 1594 | #define UIC_PPM 0x02000000 /* PCI0 power management */ |
1595 | #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ | 1595 | #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ |
1596 | #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ | 1596 | #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ |
1597 | #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ | 1597 | #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ |
1598 | #define UIC_P1CRW 0x00200000 /* PCI1 command write register */ | 1598 | #define UIC_P1CRW 0x00200000 /* PCI1 command write register */ |
1599 | #define UIC_P1PM 0x00100000 /* PCI1 power management */ | 1599 | #define UIC_P1PM 0x00100000 /* PCI1 power management */ |
1600 | #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ | 1600 | #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ |
1601 | #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ | 1601 | #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ |
1602 | #define UIC_P2IM 0x00020000 /* PCI2 inbound message */ | 1602 | #define UIC_P2IM 0x00020000 /* PCI2 inbound message */ |
1603 | #define UIC_P2CRW 0x00010000 /* PCI2 command register write */ | 1603 | #define UIC_P2CRW 0x00010000 /* PCI2 command register write */ |
1604 | #define UIC_P2PM 0x00008000 /* PCI2 power management */ | 1604 | #define UIC_P2PM 0x00008000 /* PCI2 power management */ |
1605 | #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ | 1605 | #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ |
1606 | #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ | 1606 | #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ |
1607 | #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ | 1607 | #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ |
1608 | #define UIC_D0CSF 0x00000800 /* DMA0 command status */ | 1608 | #define UIC_D0CSF 0x00000800 /* DMA0 command status */ |
1609 | #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ | 1609 | #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ |
1610 | #define UIC_D1CSF 0x00000200 /* DMA1 command status */ | 1610 | #define UIC_D1CSF 0x00000200 /* DMA1 command status */ |
1611 | #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ | 1611 | #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ |
1612 | #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ | 1612 | #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ |
1613 | #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ | 1613 | #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ |
1614 | #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ | 1614 | #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ |
1615 | #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ | 1615 | #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ |
1616 | #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ | 1616 | #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ |
1617 | #define UIC_GPTCT 0x00000004 /* GPT count timer */ | 1617 | #define UIC_GPTCT 0x00000004 /* GPT count timer */ |
1618 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ | 1618 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ |
1619 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ | 1619 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ |
1620 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) | 1620 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) |
1621 | #define UIC_U0 0x80000000 /* UART 0 */ | 1621 | #define UIC_U0 0x80000000 /* UART 0 */ |
1622 | #define UIC_U1 0x40000000 /* UART 1 */ | 1622 | #define UIC_U1 0x40000000 /* UART 1 */ |
1623 | #define UIC_IIC0 0x20000000 /* IIC */ | 1623 | #define UIC_IIC0 0x20000000 /* IIC */ |
1624 | #define UIC_IIC1 0x10000000 /* IIC */ | 1624 | #define UIC_IIC1 0x10000000 /* IIC */ |
1625 | #define UIC_PIM 0x08000000 /* PCI inbound message */ | 1625 | #define UIC_PIM 0x08000000 /* PCI inbound message */ |
1626 | #define UIC_PCRW 0x04000000 /* PCI command register write */ | 1626 | #define UIC_PCRW 0x04000000 /* PCI command register write */ |
1627 | #define UIC_PPM 0x02000000 /* PCI power management */ | 1627 | #define UIC_PPM 0x02000000 /* PCI power management */ |
1628 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ | 1628 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ |
1629 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ | 1629 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ |
1630 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ | 1630 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ |
1631 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ | 1631 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ |
1632 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ | 1632 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ |
1633 | #define UIC_D0 0x00080000 /* DMA channel 0 */ | 1633 | #define UIC_D0 0x00080000 /* DMA channel 0 */ |
1634 | #define UIC_D1 0x00040000 /* DMA channel 1 */ | 1634 | #define UIC_D1 0x00040000 /* DMA channel 1 */ |
1635 | #define UIC_D2 0x00020000 /* DMA channel 2 */ | 1635 | #define UIC_D2 0x00020000 /* DMA channel 2 */ |
1636 | #define UIC_D3 0x00010000 /* DMA channel 3 */ | 1636 | #define UIC_D3 0x00010000 /* DMA channel 3 */ |
1637 | #define UIC_RSVD0 0x00008000 /* Reserved */ | 1637 | #define UIC_RSVD0 0x00008000 /* Reserved */ |
1638 | #define UIC_RSVD1 0x00004000 /* Reserved */ | 1638 | #define UIC_RSVD1 0x00004000 /* Reserved */ |
1639 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ | 1639 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ |
1640 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ | 1640 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ |
1641 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ | 1641 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ |
1642 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ | 1642 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ |
1643 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ | 1643 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ |
1644 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ | 1644 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ |
1645 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ | 1645 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ |
1646 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ | 1646 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ |
1647 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ | 1647 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ |
1648 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ | 1648 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ |
1649 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ | 1649 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ |
1650 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ | 1650 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ |
1651 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ | 1651 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ |
1652 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ | 1652 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ |
1653 | 1653 | ||
1654 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 1654 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1655 | 1655 | ||
1656 | #define UIC_U0 0x80000000 /* UART 0 */ | 1656 | #define UIC_U0 0x80000000 /* UART 0 */ |
1657 | #define UIC_U1 0x40000000 /* UART 1 */ | 1657 | #define UIC_U1 0x40000000 /* UART 1 */ |
1658 | #define UIC_IIC0 0x20000000 /* IIC */ | 1658 | #define UIC_IIC0 0x20000000 /* IIC */ |
1659 | #define UIC_KRD 0x10000000 /* Kasumi Ready for data */ | 1659 | #define UIC_KRD 0x10000000 /* Kasumi Ready for data */ |
1660 | #define UIC_KDA 0x08000000 /* Kasumi Data Available */ | 1660 | #define UIC_KDA 0x08000000 /* Kasumi Data Available */ |
1661 | #define UIC_PCRW 0x04000000 /* PCI command register write */ | 1661 | #define UIC_PCRW 0x04000000 /* PCI command register write */ |
1662 | #define UIC_PPM 0x02000000 /* PCI power management */ | 1662 | #define UIC_PPM 0x02000000 /* PCI power management */ |
1663 | #define UIC_IIC1 0x01000000 /* IIC */ | 1663 | #define UIC_IIC1 0x01000000 /* IIC */ |
1664 | #define UIC_SPI 0x00800000 /* SPI */ | 1664 | #define UIC_SPI 0x00800000 /* SPI */ |
1665 | #define UIC_EPCISER 0x00400000 /* External PCI SERR */ | 1665 | #define UIC_EPCISER 0x00400000 /* External PCI SERR */ |
1666 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ | 1666 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ |
1667 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ | 1667 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ |
1668 | #define UIC_D0 0x00080000 /* DMA channel 0 */ | 1668 | #define UIC_D0 0x00080000 /* DMA channel 0 */ |
1669 | #define UIC_D1 0x00040000 /* DMA channel 1 */ | 1669 | #define UIC_D1 0x00040000 /* DMA channel 1 */ |
1670 | #define UIC_D2 0x00020000 /* DMA channel 2 */ | 1670 | #define UIC_D2 0x00020000 /* DMA channel 2 */ |
1671 | #define UIC_D3 0x00010000 /* DMA channel 3 */ | 1671 | #define UIC_D3 0x00010000 /* DMA channel 3 */ |
1672 | #define UIC_UD0 0x00008000 /* UDMA irq 0 */ | 1672 | #define UIC_UD0 0x00008000 /* UDMA irq 0 */ |
1673 | #define UIC_UD1 0x00004000 /* UDMA irq 1 */ | 1673 | #define UIC_UD1 0x00004000 /* UDMA irq 1 */ |
1674 | #define UIC_UD2 0x00002000 /* UDMA irq 2 */ | 1674 | #define UIC_UD2 0x00002000 /* UDMA irq 2 */ |
1675 | #define UIC_UD3 0x00001000 /* UDMA irq 3 */ | 1675 | #define UIC_UD3 0x00001000 /* UDMA irq 3 */ |
1676 | #define UIC_HSB2D 0x00000800 /* USB2.0 Device */ | 1676 | #define UIC_HSB2D 0x00000800 /* USB2.0 Device */ |
1677 | #define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ | 1677 | #define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ |
1678 | #define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ | 1678 | #define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ |
1679 | #define UIC_EIP94 0x00000100 /* Security EIP94 */ | 1679 | #define UIC_EIP94 0x00000100 /* Security EIP94 */ |
1680 | #define UIC_ETH0 0x00000080 /* Emac 0 */ | 1680 | #define UIC_ETH0 0x00000080 /* Emac 0 */ |
1681 | #define UIC_ETH1 0x00000040 /* Emac 1 */ | 1681 | #define UIC_ETH1 0x00000040 /* Emac 1 */ |
1682 | #define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ | 1682 | #define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ |
1683 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ | 1683 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ |
1684 | #define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ | 1684 | #define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ |
1685 | #define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ | 1685 | #define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ |
1686 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ | 1686 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ |
1687 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ | 1687 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ |
1688 | 1688 | ||
1689 | /* For compatibility with 405 code */ | 1689 | /* For compatibility with 405 code */ |
1690 | #define UIC_MAL_TXEOB UIC_MTE | 1690 | #define UIC_MAL_TXEOB UIC_MTE |
1691 | #define UIC_MAL_RXEOB UIC_MRE | 1691 | #define UIC_MAL_RXEOB UIC_MRE |
1692 | 1692 | ||
1693 | #elif !defined(CONFIG_440SPE) | 1693 | #elif !defined(CONFIG_440SPE) |
1694 | #define UIC_U0 0x80000000 /* UART 0 */ | 1694 | #define UIC_U0 0x80000000 /* UART 0 */ |
1695 | #define UIC_U1 0x40000000 /* UART 1 */ | 1695 | #define UIC_U1 0x40000000 /* UART 1 */ |
1696 | #define UIC_IIC0 0x20000000 /* IIC */ | 1696 | #define UIC_IIC0 0x20000000 /* IIC */ |
1697 | #define UIC_IIC1 0x10000000 /* IIC */ | 1697 | #define UIC_IIC1 0x10000000 /* IIC */ |
1698 | #define UIC_PIM 0x08000000 /* PCI inbound message */ | 1698 | #define UIC_PIM 0x08000000 /* PCI inbound message */ |
1699 | #define UIC_PCRW 0x04000000 /* PCI command register write */ | 1699 | #define UIC_PCRW 0x04000000 /* PCI command register write */ |
1700 | #define UIC_PPM 0x02000000 /* PCI power management */ | 1700 | #define UIC_PPM 0x02000000 /* PCI power management */ |
1701 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ | 1701 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ |
1702 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ | 1702 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ |
1703 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ | 1703 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ |
1704 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ | 1704 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ |
1705 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ | 1705 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ |
1706 | #define UIC_D0 0x00080000 /* DMA channel 0 */ | 1706 | #define UIC_D0 0x00080000 /* DMA channel 0 */ |
1707 | #define UIC_D1 0x00040000 /* DMA channel 1 */ | 1707 | #define UIC_D1 0x00040000 /* DMA channel 1 */ |
1708 | #define UIC_D2 0x00020000 /* DMA channel 2 */ | 1708 | #define UIC_D2 0x00020000 /* DMA channel 2 */ |
1709 | #define UIC_D3 0x00010000 /* DMA channel 3 */ | 1709 | #define UIC_D3 0x00010000 /* DMA channel 3 */ |
1710 | #define UIC_RSVD0 0x00008000 /* Reserved */ | 1710 | #define UIC_RSVD0 0x00008000 /* Reserved */ |
1711 | #define UIC_RSVD1 0x00004000 /* Reserved */ | 1711 | #define UIC_RSVD1 0x00004000 /* Reserved */ |
1712 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ | 1712 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ |
1713 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ | 1713 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ |
1714 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ | 1714 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ |
1715 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ | 1715 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ |
1716 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ | 1716 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ |
1717 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ | 1717 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ |
1718 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ | 1718 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ |
1719 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ | 1719 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ |
1720 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ | 1720 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ |
1721 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ | 1721 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ |
1722 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ | 1722 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ |
1723 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ | 1723 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ |
1724 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ | 1724 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ |
1725 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ | 1725 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ |
1726 | #endif /* CONFIG_440GX */ | 1726 | #endif /* CONFIG_440GX */ |
1727 | 1727 | ||
1728 | /* For compatibility with 405 code */ | 1728 | /* For compatibility with 405 code */ |
1729 | #define UIC_MAL_TXEOB UIC_MTE | 1729 | #define UIC_MAL_TXEOB UIC_MTE |
1730 | #define UIC_MAL_RXEOB UIC_MRE | 1730 | #define UIC_MAL_RXEOB UIC_MRE |
1731 | 1731 | ||
1732 | /*---------------------------------------------------------------------------+ | 1732 | /*---------------------------------------------------------------------------+ |
1733 | | Universal interrupt controller 1 interrupts (UIC1) | 1733 | | Universal interrupt controller 1 interrupts (UIC1) |
1734 | +---------------------------------------------------------------------------*/ | 1734 | +---------------------------------------------------------------------------*/ |
1735 | #if defined(CONFIG_440SP) | 1735 | #if defined(CONFIG_440SP) |
1736 | #define UIC_EIR0 0x80000000 /* External interrupt 0 */ | 1736 | #define UIC_EIR0 0x80000000 /* External interrupt 0 */ |
1737 | #define UIC_MS 0x40000000 /* MAL SERR */ | 1737 | #define UIC_MS 0x40000000 /* MAL SERR */ |
1738 | #define UIC_MTDE 0x20000000 /* MAL TXDE */ | 1738 | #define UIC_MTDE 0x20000000 /* MAL TXDE */ |
1739 | #define UIC_MRDE 0x10000000 /* MAL RXDE */ | 1739 | #define UIC_MRDE 0x10000000 /* MAL RXDE */ |
1740 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ | 1740 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ |
1741 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | 1741 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
1742 | #define UIC_MTE 0x02000000 /* MAL TXEOB */ | 1742 | #define UIC_MTE 0x02000000 /* MAL TXEOB */ |
1743 | #define UIC_MRE 0x01000000 /* MAL RXEOB */ | 1743 | #define UIC_MRE 0x01000000 /* MAL RXEOB */ |
1744 | #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ | 1744 | #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ |
1745 | #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ | 1745 | #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ |
1746 | #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ | 1746 | #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ |
1747 | #define UIC_L2C 0x00100000 /* L2 cache */ | 1747 | #define UIC_L2C 0x00100000 /* L2 cache */ |
1748 | #define UIC_CT0 0x00080000 /* GPT compare timer 0 */ | 1748 | #define UIC_CT0 0x00080000 /* GPT compare timer 0 */ |
1749 | #define UIC_CT1 0x00040000 /* GPT compare timer 1 */ | 1749 | #define UIC_CT1 0x00040000 /* GPT compare timer 1 */ |
1750 | #define UIC_CT2 0x00020000 /* GPT compare timer 2 */ | 1750 | #define UIC_CT2 0x00020000 /* GPT compare timer 2 */ |
1751 | #define UIC_CT3 0x00010000 /* GPT compare timer 3 */ | 1751 | #define UIC_CT3 0x00010000 /* GPT compare timer 3 */ |
1752 | #define UIC_CT4 0x00008000 /* GPT compare timer 4 */ | 1752 | #define UIC_CT4 0x00008000 /* GPT compare timer 4 */ |
1753 | #define UIC_EIR1 0x00004000 /* External interrupt 1 */ | 1753 | #define UIC_EIR1 0x00004000 /* External interrupt 1 */ |
1754 | #define UIC_EIR2 0x00002000 /* External interrupt 2 */ | 1754 | #define UIC_EIR2 0x00002000 /* External interrupt 2 */ |
1755 | #define UIC_EIR3 0x00001000 /* External interrupt 3 */ | 1755 | #define UIC_EIR3 0x00001000 /* External interrupt 3 */ |
1756 | #define UIC_EIR4 0x00000800 /* External interrupt 4 */ | 1756 | #define UIC_EIR4 0x00000800 /* External interrupt 4 */ |
1757 | #define UIC_EIR5 0x00000400 /* External interrupt 5 */ | 1757 | #define UIC_EIR5 0x00000400 /* External interrupt 5 */ |
1758 | #define UIC_DMAE 0x00000200 /* DMA error */ | 1758 | #define UIC_DMAE 0x00000200 /* DMA error */ |
1759 | #define UIC_I2OE 0x00000100 /* I2O error */ | 1759 | #define UIC_I2OE 0x00000100 /* I2O error */ |
1760 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | 1760 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
1761 | #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ | 1761 | #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ |
1762 | #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ | 1762 | #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ |
1763 | #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ | 1763 | #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ |
1764 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ | 1764 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ |
1765 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | 1765 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
1766 | #define UIC_ETH1 0x00000002 /* Reserved */ | 1766 | #define UIC_ETH1 0x00000002 /* Reserved */ |
1767 | #define UIC_XOR 0x00000001 /* XOR */ | 1767 | #define UIC_XOR 0x00000001 /* XOR */ |
1768 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) | 1768 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) |
1769 | #define UIC_MS 0x80000000 /* MAL SERR */ | 1769 | #define UIC_MS 0x80000000 /* MAL SERR */ |
1770 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ | 1770 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ |
1771 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ | 1771 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ |
1772 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ | 1772 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ |
1773 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ | 1773 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ |
1774 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | 1774 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
1775 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ | 1775 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ |
1776 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ | 1776 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ |
1777 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ | 1777 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ |
1778 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ | 1778 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ |
1779 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ | 1779 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ |
1780 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ | 1780 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ |
1781 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ | 1781 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ |
1782 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ | 1782 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ |
1783 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ | 1783 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ |
1784 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ | 1784 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ |
1785 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ | 1785 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ |
1786 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ | 1786 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ |
1787 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ | 1787 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ |
1788 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ | 1788 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ |
1789 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ | 1789 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ |
1790 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ | 1790 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ |
1791 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ | 1791 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ |
1792 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ | 1792 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ |
1793 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | 1793 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
1794 | #define UIC_RSVD2 0x00000040 /* Reserved */ | 1794 | #define UIC_RSVD2 0x00000040 /* Reserved */ |
1795 | #define UIC_RSVD3 0x00000020 /* Reserved */ | 1795 | #define UIC_RSVD3 0x00000020 /* Reserved */ |
1796 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ | 1796 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ |
1797 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ | 1797 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ |
1798 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | 1798 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
1799 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ | 1799 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ |
1800 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ | 1800 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ |
1801 | 1801 | ||
1802 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 1802 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1803 | 1803 | ||
1804 | #define UIC_MS 0x80000000 /* MAL SERR */ | 1804 | #define UIC_MS 0x80000000 /* MAL SERR */ |
1805 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ | 1805 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ |
1806 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ | 1806 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ |
1807 | #define UIC_U2 0x10000000 /* UART 2 */ | 1807 | #define UIC_U2 0x10000000 /* UART 2 */ |
1808 | #define UIC_U3 0x08000000 /* UART 3 */ | 1808 | #define UIC_U3 0x08000000 /* UART 3 */ |
1809 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | 1809 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
1810 | #define UIC_NDFC 0x02000000 /* NDFC */ | 1810 | #define UIC_NDFC 0x02000000 /* NDFC */ |
1811 | #define UIC_KSLE 0x01000000 /* KASUMI slave error */ | 1811 | #define UIC_KSLE 0x01000000 /* KASUMI slave error */ |
1812 | #define UIC_CT5 0x00800000 /* GPT compare timer 5 */ | 1812 | #define UIC_CT5 0x00800000 /* GPT compare timer 5 */ |
1813 | #define UIC_CT6 0x00400000 /* GPT compare timer 6 */ | 1813 | #define UIC_CT6 0x00400000 /* GPT compare timer 6 */ |
1814 | #define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ | 1814 | #define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ |
1815 | #define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ | 1815 | #define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ |
1816 | #define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ | 1816 | #define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ |
1817 | #define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ | 1817 | #define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ |
1818 | #define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ | 1818 | #define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ |
1819 | #define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ | 1819 | #define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ |
1820 | #define UIC_CT0 0x00008000 /* GPT compare timer 0 */ | 1820 | #define UIC_CT0 0x00008000 /* GPT compare timer 0 */ |
1821 | #define UIC_CT1 0x00004000 /* GPT compare timer 1 */ | 1821 | #define UIC_CT1 0x00004000 /* GPT compare timer 1 */ |
1822 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ | 1822 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ |
1823 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ | 1823 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ |
1824 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ | 1824 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ |
1825 | #define UIC_CT2 0x00000400 /* GPT compare timer 2 */ | 1825 | #define UIC_CT2 0x00000400 /* GPT compare timer 2 */ |
1826 | #define UIC_CT3 0x00000200 /* GPT compare timer 3 */ | 1826 | #define UIC_CT3 0x00000200 /* GPT compare timer 3 */ |
1827 | #define UIC_CT4 0x00000100 /* GPT compare timer 4 */ | 1827 | #define UIC_CT4 0x00000100 /* GPT compare timer 4 */ |
1828 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | 1828 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
1829 | #define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ | 1829 | #define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ |
1830 | #define UIC_RSVD0 0x00000020 /* Reserved */ | 1830 | #define UIC_RSVD0 0x00000020 /* Reserved */ |
1831 | #define UIC_EPCIPER 0x00000010 /* External PCI PERR */ | 1831 | #define UIC_EPCIPER 0x00000010 /* External PCI PERR */ |
1832 | #define UIC_EIR0 0x00000008 /* External interrupt 0 */ | 1832 | #define UIC_EIR0 0x00000008 /* External interrupt 0 */ |
1833 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | 1833 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
1834 | #define UIC_EIR1 0x00000002 /* External interrupt 1 */ | 1834 | #define UIC_EIR1 0x00000002 /* External interrupt 1 */ |
1835 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ | 1835 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ |
1836 | 1836 | ||
1837 | /* For compatibility with 405 code */ | 1837 | /* For compatibility with 405 code */ |
1838 | #define UIC_MAL_SERR UIC_MS | 1838 | #define UIC_MAL_SERR UIC_MS |
1839 | #define UIC_MAL_TXDE UIC_MTDE | 1839 | #define UIC_MAL_TXDE UIC_MTDE |
1840 | #define UIC_MAL_RXDE UIC_MRDE | 1840 | #define UIC_MAL_RXDE UIC_MRDE |
1841 | #define UIC_ENET UIC_ETH0 | 1841 | #define UIC_ENET UIC_ETH0 |
1842 | 1842 | ||
1843 | #elif !defined(CONFIG_440SPE) | 1843 | #elif !defined(CONFIG_440SPE) |
1844 | #define UIC_MS 0x80000000 /* MAL SERR */ | 1844 | #define UIC_MS 0x80000000 /* MAL SERR */ |
1845 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ | 1845 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ |
1846 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ | 1846 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ |
1847 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ | 1847 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ |
1848 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ | 1848 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ |
1849 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | 1849 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
1850 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ | 1850 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ |
1851 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ | 1851 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ |
1852 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ | 1852 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ |
1853 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ | 1853 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ |
1854 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ | 1854 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ |
1855 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ | 1855 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ |
1856 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ | 1856 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ |
1857 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ | 1857 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ |
1858 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ | 1858 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ |
1859 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ | 1859 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ |
1860 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ | 1860 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ |
1861 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ | 1861 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ |
1862 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ | 1862 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ |
1863 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ | 1863 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ |
1864 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ | 1864 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ |
1865 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ | 1865 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ |
1866 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ | 1866 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ |
1867 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ | 1867 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ |
1868 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | 1868 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
1869 | #define UIC_RSVD2 0x00000040 /* Reserved */ | 1869 | #define UIC_RSVD2 0x00000040 /* Reserved */ |
1870 | #define UIC_RSVD3 0x00000020 /* Reserved */ | 1870 | #define UIC_RSVD3 0x00000020 /* Reserved */ |
1871 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ | 1871 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ |
1872 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ | 1872 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ |
1873 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | 1873 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
1874 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ | 1874 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ |
1875 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ | 1875 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ |
1876 | #endif /* CONFIG_440SP */ | 1876 | #endif /* CONFIG_440SP */ |
1877 | 1877 | ||
1878 | /* For compatibility with 405 code */ | 1878 | /* For compatibility with 405 code */ |
1879 | #define UIC_MAL_SERR UIC_MS | 1879 | #define UIC_MAL_SERR UIC_MS |
1880 | #define UIC_MAL_TXDE UIC_MTDE | 1880 | #define UIC_MAL_TXDE UIC_MTDE |
1881 | #define UIC_MAL_RXDE UIC_MRDE | 1881 | #define UIC_MAL_RXDE UIC_MRDE |
1882 | #define UIC_ENET UIC_ETH0 | 1882 | #define UIC_ENET UIC_ETH0 |
1883 | 1883 | ||
1884 | /*---------------------------------------------------------------------------+ | 1884 | /*---------------------------------------------------------------------------+ |
1885 | | Universal interrupt controller 2 interrupts (UIC2) | 1885 | | Universal interrupt controller 2 interrupts (UIC2) |
1886 | +---------------------------------------------------------------------------*/ | 1886 | +---------------------------------------------------------------------------*/ |
1887 | #if defined(CONFIG_440GX) | 1887 | #if defined(CONFIG_440GX) |
1888 | #define UIC_ETH2 0x80000000 /* Ethernet 2 */ | 1888 | #define UIC_ETH2 0x80000000 /* Ethernet 2 */ |
1889 | #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ | 1889 | #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ |
1890 | #define UIC_ETH3 0x20000000 /* Ethernet 3 */ | 1890 | #define UIC_ETH3 0x20000000 /* Ethernet 3 */ |
1891 | #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ | 1891 | #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ |
1892 | #define UIC_TAH0 0x08000000 /* TAH 0 */ | 1892 | #define UIC_TAH0 0x08000000 /* TAH 0 */ |
1893 | #define UIC_TAH1 0x04000000 /* TAH 1 */ | 1893 | #define UIC_TAH1 0x04000000 /* TAH 1 */ |
1894 | #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ | 1894 | #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ |
1895 | #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ | 1895 | #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ |
1896 | #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ | 1896 | #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ |
1897 | #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ | 1897 | #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ |
1898 | #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ | 1898 | #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ |
1899 | #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ | 1899 | #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ |
1900 | #define UIC_IMUTO 0x00080000 /* IMU timeout */ | 1900 | #define UIC_IMUTO 0x00080000 /* IMU timeout */ |
1901 | #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ | 1901 | #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ |
1902 | #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ | 1902 | #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ |
1903 | #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ | 1903 | #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ |
1904 | #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ | 1904 | #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ |
1905 | #define UIC_EIR13 0x00004000 /* External interrupt 13 */ | 1905 | #define UIC_EIR13 0x00004000 /* External interrupt 13 */ |
1906 | #define UIC_EIR14 0x00002000 /* External interrupt 14 */ | 1906 | #define UIC_EIR14 0x00002000 /* External interrupt 14 */ |
1907 | #define UIC_EIR15 0x00001000 /* External interrupt 15 */ | 1907 | #define UIC_EIR15 0x00001000 /* External interrupt 15 */ |
1908 | #define UIC_EIR16 0x00000800 /* External interrupt 16 */ | 1908 | #define UIC_EIR16 0x00000800 /* External interrupt 16 */ |
1909 | #define UIC_EIR17 0x00000400 /* External interrupt 17 */ | 1909 | #define UIC_EIR17 0x00000400 /* External interrupt 17 */ |
1910 | #define UIC_PCIVPD 0x00000200 /* PCI VPD */ | 1910 | #define UIC_PCIVPD 0x00000200 /* PCI VPD */ |
1911 | #define UIC_L2C 0x00000100 /* L2 Cache */ | 1911 | #define UIC_L2C 0x00000100 /* L2 Cache */ |
1912 | #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ | 1912 | #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ |
1913 | #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ | 1913 | #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ |
1914 | #define UIC_RSVD26 0x00000020 /* Reserved */ | 1914 | #define UIC_RSVD26 0x00000020 /* Reserved */ |
1915 | #define UIC_RSVD27 0x00000010 /* Reserved */ | 1915 | #define UIC_RSVD27 0x00000010 /* Reserved */ |
1916 | #define UIC_RSVD28 0x00000008 /* Reserved */ | 1916 | #define UIC_RSVD28 0x00000008 /* Reserved */ |
1917 | #define UIC_RSVD29 0x00000004 /* Reserved */ | 1917 | #define UIC_RSVD29 0x00000004 /* Reserved */ |
1918 | #define UIC_RSVD30 0x00000002 /* Reserved */ | 1918 | #define UIC_RSVD30 0x00000002 /* Reserved */ |
1919 | #define UIC_RSVD31 0x00000001 /* Reserved */ | 1919 | #define UIC_RSVD31 0x00000001 /* Reserved */ |
1920 | 1920 | ||
1921 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ | 1921 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ |
1922 | 1922 | ||
1923 | #define UIC_EIR5 0x80000000 /* External interrupt 5 */ | 1923 | #define UIC_EIR5 0x80000000 /* External interrupt 5 */ |
1924 | #define UIC_EIR6 0x40000000 /* External interrupt 6 */ | 1924 | #define UIC_EIR6 0x40000000 /* External interrupt 6 */ |
1925 | #define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ | 1925 | #define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ |
1926 | #define UIC_EIR2 0x10000000 /* External interrupt 2 */ | 1926 | #define UIC_EIR2 0x10000000 /* External interrupt 2 */ |
1927 | #define UIC_EIR3 0x08000000 /* External interrupt 3 */ | 1927 | #define UIC_EIR3 0x08000000 /* External interrupt 3 */ |
1928 | #define UIC_DDR2 0x04000000 /* DDR2 sdram */ | 1928 | #define UIC_DDR2 0x04000000 /* DDR2 sdram */ |
1929 | #define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ | 1929 | #define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ |
1930 | #define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ | 1930 | #define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ |
1931 | #define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ | 1931 | #define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ |
1932 | #define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ | 1932 | #define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ |
1933 | 1933 | ||
1934 | #endif /* CONFIG_440GX */ | 1934 | #endif /* CONFIG_440GX */ |
1935 | 1935 | ||
1936 | /*---------------------------------------------------------------------------+ | 1936 | /*---------------------------------------------------------------------------+ |
1937 | | Universal interrupt controller Base 0 interrupts (UICB0) | 1937 | | Universal interrupt controller Base 0 interrupts (UICB0) |
1938 | +---------------------------------------------------------------------------*/ | 1938 | +---------------------------------------------------------------------------*/ |
1939 | #if defined(CONFIG_440GX) | 1939 | #if defined(CONFIG_440GX) |
1940 | #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ | 1940 | #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ |
1941 | #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ | 1941 | #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ |
1942 | #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ | 1942 | #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ |
1943 | #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ | 1943 | #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ |
1944 | #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ | 1944 | #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ |
1945 | #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ | 1945 | #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ |
1946 | 1946 | ||
1947 | #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ | 1947 | #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ |
1948 | UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) | 1948 | UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) |
1949 | 1949 | ||
1950 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 1950 | #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1951 | 1951 | ||
1952 | #define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */ | 1952 | #define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */ |
1953 | #define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */ | 1953 | #define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */ |
1954 | #define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */ | 1954 | #define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */ |
1955 | #define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */ | 1955 | #define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */ |
1956 | 1956 | ||
1957 | #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ | 1957 | #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ |
1958 | UICB0_UIC1CI | UICB0_UIC2NCI) | 1958 | UICB0_UIC1CI | UICB0_UIC2NCI) |
1959 | 1959 | ||
1960 | #endif /* CONFIG_440GX */ | 1960 | #endif /* CONFIG_440GX */ |
1961 | /*---------------------------------------------------------------------------+ | 1961 | /*---------------------------------------------------------------------------+ |
1962 | | Universal interrupt controller interrupts | 1962 | | Universal interrupt controller interrupts |
1963 | +---------------------------------------------------------------------------*/ | 1963 | +---------------------------------------------------------------------------*/ |
1964 | #if defined(CONFIG_440SPE) | 1964 | #if defined(CONFIG_440SPE) |
1965 | /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ | 1965 | /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ |
1966 | /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ | 1966 | /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ |
1967 | #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ | 1967 | #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ |
1968 | #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ | 1968 | #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ |
1969 | #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ | 1969 | #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ |
1970 | #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ | 1970 | #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ |
1971 | #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ | 1971 | #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ |
1972 | #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ | 1972 | #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ |
1973 | 1973 | ||
1974 | #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ | 1974 | #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ |
1975 | UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) | 1975 | UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) |
1976 | /*---------------------------------------------------------------------------+ | 1976 | /*---------------------------------------------------------------------------+ |
1977 | | Universal interrupt controller 0 interrupts (UIC0) | 1977 | | Universal interrupt controller 0 interrupts (UIC0) |
1978 | +---------------------------------------------------------------------------*/ | 1978 | +---------------------------------------------------------------------------*/ |
1979 | #define UIC_U0 0x80000000 /* UART 0 */ | 1979 | #define UIC_U0 0x80000000 /* UART 0 */ |
1980 | #define UIC_U1 0x40000000 /* UART 1 */ | 1980 | #define UIC_U1 0x40000000 /* UART 1 */ |
1981 | #define UIC_IIC0 0x20000000 /* IIC */ | 1981 | #define UIC_IIC0 0x20000000 /* IIC */ |
1982 | #define UIC_IIC1 0x10000000 /* IIC */ | 1982 | #define UIC_IIC1 0x10000000 /* IIC */ |
1983 | #define UIC_PIM 0x08000000 /* PCI inbound message */ | 1983 | #define UIC_PIM 0x08000000 /* PCI inbound message */ |
1984 | #define UIC_PCRW 0x04000000 /* PCI command register write */ | 1984 | #define UIC_PCRW 0x04000000 /* PCI command register write */ |
1985 | #define UIC_PPM 0x02000000 /* PCI power management */ | 1985 | #define UIC_PPM 0x02000000 /* PCI power management */ |
1986 | #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ | 1986 | #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ |
1987 | #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ | 1987 | #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ |
1988 | #define UIC_EIR15 0x00400000 /* External intp 15 */ | 1988 | #define UIC_EIR15 0x00400000 /* External intp 15 */ |
1989 | #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ | 1989 | #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ |
1990 | #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ | 1990 | #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ |
1991 | #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ | 1991 | #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ |
1992 | #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ | 1992 | #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ |
1993 | #define UIC_EIR14 0x00002000 /* External interrupt 14 */ | 1993 | #define UIC_EIR14 0x00002000 /* External interrupt 14 */ |
1994 | #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ | 1994 | #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ |
1995 | #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ | 1995 | #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ |
1996 | #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ | 1996 | #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ |
1997 | #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ | 1997 | #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ |
1998 | #define UIC_I2OID 0x00000100 /* I2O inbound door bell */ | 1998 | #define UIC_I2OID 0x00000100 /* I2O inbound door bell */ |
1999 | #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ | 1999 | #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ |
2000 | #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ | 2000 | #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ |
2001 | #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ | 2001 | #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ |
2002 | #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ | 2002 | #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ |
2003 | #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ | 2003 | #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ |
2004 | #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ | 2004 | #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ |
2005 | /*---------------------------------------------------------------------------+ | 2005 | /*---------------------------------------------------------------------------+ |
2006 | | Universal interrupt controller 1 interrupts (UIC1) | 2006 | | Universal interrupt controller 1 interrupts (UIC1) |
2007 | +---------------------------------------------------------------------------*/ | 2007 | +---------------------------------------------------------------------------*/ |
2008 | #define UIC_EIR13 0x80000000 /* externei intp 13 */ | 2008 | #define UIC_EIR13 0x80000000 /* externei intp 13 */ |
2009 | #define UIC_MS 0x40000000 /* MAL SERR */ | 2009 | #define UIC_MS 0x40000000 /* MAL SERR */ |
2010 | #define UIC_MTDE 0x20000000 /* MAL TXDE */ | 2010 | #define UIC_MTDE 0x20000000 /* MAL TXDE */ |
2011 | #define UIC_MRDE 0x10000000 /* MAL RXDE */ | 2011 | #define UIC_MRDE 0x10000000 /* MAL RXDE */ |
2012 | #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ | 2012 | #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ |
2013 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | 2013 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ |
2014 | #define UIC_MTE 0x02000000 /* MAL TXEOB */ | 2014 | #define UIC_MTE 0x02000000 /* MAL TXEOB */ |
2015 | #define UIC_MRE 0x01000000 /* MAL RXEOB */ | 2015 | #define UIC_MRE 0x01000000 /* MAL RXEOB */ |
2016 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ | 2016 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ |
2017 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ | 2017 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ |
2018 | #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ | 2018 | #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ |
2019 | #define UIC_L2C 0x00100000 /* L2 cache */ | 2019 | #define UIC_L2C 0x00100000 /* L2 cache */ |
2020 | #define UIC_CT0 0x00080000 /* GPT compare timer 0 */ | 2020 | #define UIC_CT0 0x00080000 /* GPT compare timer 0 */ |
2021 | #define UIC_CT1 0x00040000 /* GPT compare timer 1 */ | 2021 | #define UIC_CT1 0x00040000 /* GPT compare timer 1 */ |
2022 | #define UIC_CT2 0x00020000 /* GPT compare timer 2 */ | 2022 | #define UIC_CT2 0x00020000 /* GPT compare timer 2 */ |
2023 | #define UIC_CT3 0x00010000 /* GPT compare timer 3 */ | 2023 | #define UIC_CT3 0x00010000 /* GPT compare timer 3 */ |
2024 | #define UIC_CT4 0x00008000 /* GPT compare timer 4 */ | 2024 | #define UIC_CT4 0x00008000 /* GPT compare timer 4 */ |
2025 | #define UIC_EIR12 0x00004000 /* External interrupt 12 */ | 2025 | #define UIC_EIR12 0x00004000 /* External interrupt 12 */ |
2026 | #define UIC_EIR11 0x00002000 /* External interrupt 11 */ | 2026 | #define UIC_EIR11 0x00002000 /* External interrupt 11 */ |
2027 | #define UIC_EIR10 0x00001000 /* External interrupt 10 */ | 2027 | #define UIC_EIR10 0x00001000 /* External interrupt 10 */ |
2028 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ | 2028 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ |
2029 | #define UIC_EIR8 0x00000400 /* External interrupt 8 */ | 2029 | #define UIC_EIR8 0x00000400 /* External interrupt 8 */ |
2030 | #define UIC_DMAE 0x00000200 /* dma error */ | 2030 | #define UIC_DMAE 0x00000200 /* dma error */ |
2031 | #define UIC_I2OE 0x00000100 /* i2o error */ | 2031 | #define UIC_I2OE 0x00000100 /* i2o error */ |
2032 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | 2032 | #define UIC_SRE 0x00000080 /* Serial ROM error */ |
2033 | #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ | 2033 | #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ |
2034 | #define UIC_EIR7 0x00000020 /* External interrupt 7 */ | 2034 | #define UIC_EIR7 0x00000020 /* External interrupt 7 */ |
2035 | #define UIC_EIR6 0x00000010 /* External interrupt 6 */ | 2035 | #define UIC_EIR6 0x00000010 /* External interrupt 6 */ |
2036 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ | 2036 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ |
2037 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | 2037 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ |
2038 | #define UIC_ETH1 0x00000002 /* reserved */ | 2038 | #define UIC_ETH1 0x00000002 /* reserved */ |
2039 | #define UIC_XOR 0x00000001 /* xor */ | 2039 | #define UIC_XOR 0x00000001 /* xor */ |
2040 | 2040 | ||
2041 | /*---------------------------------------------------------------------------+ | 2041 | /*---------------------------------------------------------------------------+ |
2042 | | Universal interrupt controller 2 interrupts (UIC2) | 2042 | | Universal interrupt controller 2 interrupts (UIC2) |
2043 | +---------------------------------------------------------------------------*/ | 2043 | +---------------------------------------------------------------------------*/ |
2044 | #define UIC_PEOAL 0x80000000 /* PE0 AL */ | 2044 | #define UIC_PEOAL 0x80000000 /* PE0 AL */ |
2045 | #define UIC_PEOVA 0x40000000 /* PE0 VPD access */ | 2045 | #define UIC_PEOVA 0x40000000 /* PE0 VPD access */ |
2046 | #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ | 2046 | #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ |
2047 | #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ | 2047 | #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ |
2048 | #define UIC_PE0TCR 0x08000000 /* PE0 TCR */ | 2048 | #define UIC_PE0TCR 0x08000000 /* PE0 TCR */ |
2049 | #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ | 2049 | #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ |
2050 | #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ | 2050 | #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ |
2051 | #define UIC_PE1AL 0x00800000 /* PE1 AL */ | 2051 | #define UIC_PE1AL 0x00800000 /* PE1 AL */ |
2052 | #define UIC_PE1VA 0x00400000 /* PE1 VPD access */ | 2052 | #define UIC_PE1VA 0x00400000 /* PE1 VPD access */ |
2053 | #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ | 2053 | #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ |
2054 | #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ | 2054 | #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ |
2055 | #define UIC_PE1TCR 0x00080000 /* PE1 TCR */ | 2055 | #define UIC_PE1TCR 0x00080000 /* PE1 TCR */ |
2056 | #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ | 2056 | #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ |
2057 | #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ | 2057 | #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ |
2058 | #define UIC_PE2AL 0x00008000 /* PE2 AL */ | 2058 | #define UIC_PE2AL 0x00008000 /* PE2 AL */ |
2059 | #define UIC_PE2VA 0x00004000 /* PE2 VPD access */ | 2059 | #define UIC_PE2VA 0x00004000 /* PE2 VPD access */ |
2060 | #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ | 2060 | #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ |
2061 | #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ | 2061 | #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ |
2062 | #define UIC_PE2TCR 0x00000800 /* PE2 TCR */ | 2062 | #define UIC_PE2TCR 0x00000800 /* PE2 TCR */ |
2063 | #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ | 2063 | #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ |
2064 | #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ | 2064 | #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ |
2065 | #define UIC_EIR5 0x00000080 /* External interrupt 5 */ | 2065 | #define UIC_EIR5 0x00000080 /* External interrupt 5 */ |
2066 | #define UIC_EIR4 0x00000040 /* External interrupt 4 */ | 2066 | #define UIC_EIR4 0x00000040 /* External interrupt 4 */ |
2067 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ | 2067 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ |
2068 | #define UIC_EIR2 0x00000010 /* External interrupt 2 */ | 2068 | #define UIC_EIR2 0x00000010 /* External interrupt 2 */ |
2069 | #define UIC_EIR1 0x00000008 /* External interrupt 1 */ | 2069 | #define UIC_EIR1 0x00000008 /* External interrupt 1 */ |
2070 | #define UIC_EIR0 0x00000004 /* External interrupt 0 */ | 2070 | #define UIC_EIR0 0x00000004 /* External interrupt 0 */ |
2071 | #endif /* CONFIG_440SPE */ | 2071 | #endif /* CONFIG_440SPE */ |
2072 | 2072 | ||
2073 | /*-----------------------------------------------------------------------------+ | 2073 | /*-----------------------------------------------------------------------------+ |
2074 | | External Bus Controller Bit Settings | 2074 | | External Bus Controller Bit Settings |
2075 | +-----------------------------------------------------------------------------*/ | 2075 | +-----------------------------------------------------------------------------*/ |
2076 | #define EBC_CFGADDR_MASK 0x0000003F | 2076 | #define EBC_CFGADDR_MASK 0x0000003F |
2077 | 2077 | ||
2078 | #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) | 2078 | #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) |
2079 | #define EBC_BXCR_BS_MASK 0x000E0000 | 2079 | #define EBC_BXCR_BS_MASK 0x000E0000 |
2080 | #define EBC_BXCR_BS_1MB 0x00000000 | 2080 | #define EBC_BXCR_BS_1MB 0x00000000 |
2081 | #define EBC_BXCR_BS_2MB 0x00020000 | 2081 | #define EBC_BXCR_BS_2MB 0x00020000 |
2082 | #define EBC_BXCR_BS_4MB 0x00040000 | 2082 | #define EBC_BXCR_BS_4MB 0x00040000 |
2083 | #define EBC_BXCR_BS_8MB 0x00060000 | 2083 | #define EBC_BXCR_BS_8MB 0x00060000 |
2084 | #define EBC_BXCR_BS_16MB 0x00080000 | 2084 | #define EBC_BXCR_BS_16MB 0x00080000 |
2085 | #define EBC_BXCR_BS_32MB 0x000A0000 | 2085 | #define EBC_BXCR_BS_32MB 0x000A0000 |
2086 | #define EBC_BXCR_BS_64MB 0x000C0000 | 2086 | #define EBC_BXCR_BS_64MB 0x000C0000 |
2087 | #define EBC_BXCR_BS_128MB 0x000E0000 | 2087 | #define EBC_BXCR_BS_128MB 0x000E0000 |
2088 | #define EBC_BXCR_BU_MASK 0x00018000 | 2088 | #define EBC_BXCR_BU_MASK 0x00018000 |
2089 | #define EBC_BXCR_BU_R 0x00008000 | 2089 | #define EBC_BXCR_BU_R 0x00008000 |
2090 | #define EBC_BXCR_BU_W 0x00010000 | 2090 | #define EBC_BXCR_BU_W 0x00010000 |
2091 | #define EBC_BXCR_BU_RW 0x00018000 | 2091 | #define EBC_BXCR_BU_RW 0x00018000 |
2092 | #define EBC_BXCR_BW_MASK 0x00006000 | 2092 | #define EBC_BXCR_BW_MASK 0x00006000 |
2093 | #define EBC_BXCR_BW_8BIT 0x00000000 | 2093 | #define EBC_BXCR_BW_8BIT 0x00000000 |
2094 | #define EBC_BXCR_BW_16BIT 0x00002000 | 2094 | #define EBC_BXCR_BW_16BIT 0x00002000 |
2095 | #define EBC_BXCR_BW_32BIT 0x00006000 | 2095 | #define EBC_BXCR_BW_32BIT 0x00006000 |
2096 | #define EBC_BXAP_BME_ENABLED 0x80000000 | 2096 | #define EBC_BXAP_BME_ENABLED 0x80000000 |
2097 | #define EBC_BXAP_BME_DISABLED 0x00000000 | 2097 | #define EBC_BXAP_BME_DISABLED 0x00000000 |
2098 | #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) | 2098 | #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) |
2099 | #define EBC_BXAP_BCE_DISABLE 0x00000000 | 2099 | #define EBC_BXAP_BCE_DISABLE 0x00000000 |
2100 | #define EBC_BXAP_BCE_ENABLE 0x00400000 | 2100 | #define EBC_BXAP_BCE_ENABLE 0x00400000 |
2101 | #define EBC_BXAP_BCT_MASK 0x00300000 | 2101 | #define EBC_BXAP_BCT_MASK 0x00300000 |
2102 | #define EBC_BXAP_BCT_2TRANS 0x00000000 | 2102 | #define EBC_BXAP_BCT_2TRANS 0x00000000 |
2103 | #define EBC_BXAP_BCT_4TRANS 0x00100000 | 2103 | #define EBC_BXAP_BCT_4TRANS 0x00100000 |
2104 | #define EBC_BXAP_BCT_8TRANS 0x00200000 | 2104 | #define EBC_BXAP_BCT_8TRANS 0x00200000 |
2105 | #define EBC_BXAP_BCT_16TRANS 0x00300000 | 2105 | #define EBC_BXAP_BCT_16TRANS 0x00300000 |
2106 | #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) | 2106 | #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) |
2107 | #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) | 2107 | #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) |
2108 | #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) | 2108 | #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) |
2109 | #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) | 2109 | #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) |
2110 | #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) | 2110 | #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) |
2111 | #define EBC_BXAP_RE_ENABLED 0x00000100 | 2111 | #define EBC_BXAP_RE_ENABLED 0x00000100 |
2112 | #define EBC_BXAP_RE_DISABLED 0x00000000 | 2112 | #define EBC_BXAP_RE_DISABLED 0x00000000 |
2113 | #define EBC_BXAP_SOR_DELAYED 0x00000000 | 2113 | #define EBC_BXAP_SOR_DELAYED 0x00000000 |
2114 | #define EBC_BXAP_SOR_NONDELAYED 0x00000080 | 2114 | #define EBC_BXAP_SOR_NONDELAYED 0x00000080 |
2115 | #define EBC_BXAP_BEM_WRITEONLY 0x00000000 | 2115 | #define EBC_BXAP_BEM_WRITEONLY 0x00000000 |
2116 | #define EBC_BXAP_BEM_RW 0x00000040 | 2116 | #define EBC_BXAP_BEM_RW 0x00000040 |
2117 | #define EBC_BXAP_PEN_DISABLED 0x00000000 | 2117 | #define EBC_BXAP_PEN_DISABLED 0x00000000 |
2118 | 2118 | ||
2119 | #define EBC_CFG_LE_MASK 0x80000000 | 2119 | #define EBC_CFG_LE_MASK 0x80000000 |
2120 | #define EBC_CFG_LE_UNLOCK 0x00000000 | 2120 | #define EBC_CFG_LE_UNLOCK 0x00000000 |
2121 | #define EBC_CFG_LE_LOCK 0x80000000 | 2121 | #define EBC_CFG_LE_LOCK 0x80000000 |
2122 | #define EBC_CFG_PTD_MASK 0x40000000 | 2122 | #define EBC_CFG_PTD_MASK 0x40000000 |
2123 | #define EBC_CFG_PTD_ENABLE 0x00000000 | 2123 | #define EBC_CFG_PTD_ENABLE 0x00000000 |
2124 | #define EBC_CFG_PTD_DISABLE 0x40000000 | 2124 | #define EBC_CFG_PTD_DISABLE 0x40000000 |
2125 | #define EBC_CFG_RTC_MASK 0x38000000 | 2125 | #define EBC_CFG_RTC_MASK 0x38000000 |
2126 | #define EBC_CFG_RTC_16PERCLK 0x00000000 | 2126 | #define EBC_CFG_RTC_16PERCLK 0x00000000 |
2127 | #define EBC_CFG_RTC_32PERCLK 0x08000000 | 2127 | #define EBC_CFG_RTC_32PERCLK 0x08000000 |
2128 | #define EBC_CFG_RTC_64PERCLK 0x10000000 | 2128 | #define EBC_CFG_RTC_64PERCLK 0x10000000 |
2129 | #define EBC_CFG_RTC_128PERCLK 0x18000000 | 2129 | #define EBC_CFG_RTC_128PERCLK 0x18000000 |
2130 | #define EBC_CFG_RTC_256PERCLK 0x20000000 | 2130 | #define EBC_CFG_RTC_256PERCLK 0x20000000 |
2131 | #define EBC_CFG_RTC_512PERCLK 0x28000000 | 2131 | #define EBC_CFG_RTC_512PERCLK 0x28000000 |
2132 | #define EBC_CFG_RTC_1024PERCLK 0x30000000 | 2132 | #define EBC_CFG_RTC_1024PERCLK 0x30000000 |
2133 | #define EBC_CFG_RTC_2048PERCLK 0x38000000 | 2133 | #define EBC_CFG_RTC_2048PERCLK 0x38000000 |
2134 | #define EBC_CFG_ATC_MASK 0x04000000 | 2134 | #define EBC_CFG_ATC_MASK 0x04000000 |
2135 | #define EBC_CFG_ATC_HI 0x00000000 | 2135 | #define EBC_CFG_ATC_HI 0x00000000 |
2136 | #define EBC_CFG_ATC_PREVIOUS 0x04000000 | 2136 | #define EBC_CFG_ATC_PREVIOUS 0x04000000 |
2137 | #define EBC_CFG_DTC_MASK 0x02000000 | 2137 | #define EBC_CFG_DTC_MASK 0x02000000 |
2138 | #define EBC_CFG_DTC_HI 0x00000000 | 2138 | #define EBC_CFG_DTC_HI 0x00000000 |
2139 | #define EBC_CFG_DTC_PREVIOUS 0x02000000 | 2139 | #define EBC_CFG_DTC_PREVIOUS 0x02000000 |
2140 | #define EBC_CFG_CTC_MASK 0x01000000 | 2140 | #define EBC_CFG_CTC_MASK 0x01000000 |
2141 | #define EBC_CFG_CTC_HI 0x00000000 | 2141 | #define EBC_CFG_CTC_HI 0x00000000 |
2142 | #define EBC_CFG_CTC_PREVIOUS 0x01000000 | 2142 | #define EBC_CFG_CTC_PREVIOUS 0x01000000 |
2143 | #define EBC_CFG_OEO_MASK 0x00800000 | 2143 | #define EBC_CFG_OEO_MASK 0x00800000 |
2144 | #define EBC_CFG_OEO_HI 0x00000000 | 2144 | #define EBC_CFG_OEO_HI 0x00000000 |
2145 | #define EBC_CFG_OEO_PREVIOUS 0x00800000 | 2145 | #define EBC_CFG_OEO_PREVIOUS 0x00800000 |
2146 | #define EBC_CFG_EMC_MASK 0x00400000 | 2146 | #define EBC_CFG_EMC_MASK 0x00400000 |
2147 | #define EBC_CFG_EMC_NONDEFAULT 0x00000000 | 2147 | #define EBC_CFG_EMC_NONDEFAULT 0x00000000 |
2148 | #define EBC_CFG_EMC_DEFAULT 0x00400000 | 2148 | #define EBC_CFG_EMC_DEFAULT 0x00400000 |
2149 | #define EBC_CFG_PME_MASK 0x00200000 | 2149 | #define EBC_CFG_PME_MASK 0x00200000 |
2150 | #define EBC_CFG_PME_DISABLE 0x00000000 | 2150 | #define EBC_CFG_PME_DISABLE 0x00000000 |
2151 | #define EBC_CFG_PME_ENABLE 0x00200000 | 2151 | #define EBC_CFG_PME_ENABLE 0x00200000 |
2152 | #define EBC_CFG_PMT_MASK 0x001F0000 | 2152 | #define EBC_CFG_PMT_MASK 0x001F0000 |
2153 | #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | 2153 | #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) |
2154 | #define EBC_CFG_PR_MASK 0x0000C000 | 2154 | #define EBC_CFG_PR_MASK 0x0000C000 |
2155 | #define EBC_CFG_PR_16 0x00000000 | 2155 | #define EBC_CFG_PR_16 0x00000000 |
2156 | #define EBC_CFG_PR_32 0x00004000 | 2156 | #define EBC_CFG_PR_32 0x00004000 |
2157 | #define EBC_CFG_PR_64 0x00008000 | 2157 | #define EBC_CFG_PR_64 0x00008000 |
2158 | #define EBC_CFG_PR_128 0x0000C000 | 2158 | #define EBC_CFG_PR_128 0x0000C000 |
2159 | 2159 | ||
2160 | /*-----------------------------------------------------------------------------+ | 2160 | /*-----------------------------------------------------------------------------+ |
2161 | | SDR0 Bit Settings | 2161 | | SDR0 Bit Settings |
2162 | +-----------------------------------------------------------------------------*/ | 2162 | +-----------------------------------------------------------------------------*/ |
2163 | #if defined(CONFIG_440SPE) | 2163 | #if defined(CONFIG_440SPE) |
2164 | #define SDR0_CP440 0x0180 | 2164 | #define SDR0_CP440 0x0180 |
2165 | #define SDR0_CP440_ERPN_MASK 0x30000000 | 2165 | #define SDR0_CP440_ERPN_MASK 0x30000000 |
2166 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 | 2166 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 |
2167 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 | 2167 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 |
2168 | #define SDR0_CP440_ERPN_EBC 0x10000000 | 2168 | #define SDR0_CP440_ERPN_EBC 0x10000000 |
2169 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 | 2169 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 |
2170 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 | 2170 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 |
2171 | #define SDR0_CP440_ERPN_PCI 0x20000000 | 2171 | #define SDR0_CP440_ERPN_PCI 0x20000000 |
2172 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 | 2172 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 |
2173 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 | 2173 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 |
2174 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | 2174 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) |
2175 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | 2175 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) |
2176 | #define SDR0_CP440_NTO1_MASK 0x00000002 | 2176 | #define SDR0_CP440_NTO1_MASK 0x00000002 |
2177 | #define SDR0_CP440_NTO1_NTOP 0x00000000 | 2177 | #define SDR0_CP440_NTO1_NTOP 0x00000000 |
2178 | #define SDR0_CP440_NTO1_NTO1 0x00000002 | 2178 | #define SDR0_CP440_NTO1_NTO1 0x00000002 |
2179 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | 2179 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) |
2180 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | 2180 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) |
2181 | #define SDR0_CFGADDR 0x00E /*already defined line 277 */ | 2181 | #define SDR0_CFGADDR 0x00E /*already defined line 277 */ |
2182 | #define SDR0_CFGDATA 0x00F | 2182 | #define SDR0_CFGDATA 0x00F |
2183 | 2183 | ||
2184 | 2184 | ||
2185 | #define SDR0_SDSTP0 0x0020 | 2185 | #define SDR0_SDSTP0 0x0020 |
2186 | #define SDR0_SDSTP0_ENG_MASK 0x80000000 | 2186 | #define SDR0_SDSTP0_ENG_MASK 0x80000000 |
2187 | #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 | 2187 | #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 |
2188 | #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 | 2188 | #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 |
2189 | #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | 2189 | #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) |
2190 | #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | 2190 | #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) |
2191 | #define SDR0_SDSTP0_SRC_MASK 0x40000000 | 2191 | #define SDR0_SDSTP0_SRC_MASK 0x40000000 |
2192 | #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 | 2192 | #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 |
2193 | #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 | 2193 | #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 |
2194 | #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 2194 | #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
2195 | #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 2195 | #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
2196 | #define SDR0_SDSTP0_SEL_MASK 0x38000000 | 2196 | #define SDR0_SDSTP0_SEL_MASK 0x38000000 |
2197 | #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 | 2197 | #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 |
2198 | #define SDR0_SDSTP0_SEL_CPU 0x08000000 | 2198 | #define SDR0_SDSTP0_SEL_CPU 0x08000000 |
2199 | #define SDR0_SDSTP0_SEL_EBC 0x28000000 | 2199 | #define SDR0_SDSTP0_SEL_EBC 0x28000000 |
2200 | #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) | 2200 | #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) |
2201 | #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) | 2201 | #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) |
2202 | #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 | 2202 | #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 |
2203 | #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) | 2203 | #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) |
2204 | #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) | 2204 | #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) |
2205 | #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 | 2205 | #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 |
2206 | #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | 2206 | #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) |
2207 | #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) | 2207 | #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) |
2208 | #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 | 2208 | #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 |
2209 | #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) | 2209 | #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) |
2210 | #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) | 2210 | #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) |
2211 | #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 | 2211 | #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 |
2212 | #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) | 2212 | #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) |
2213 | #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) | 2213 | #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) |
2214 | #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C | 2214 | #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C |
2215 | #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) | 2215 | #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) |
2216 | #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) | 2216 | #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) |
2217 | #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 | 2217 | #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 |
2218 | #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) | 2218 | #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) |
2219 | #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) | 2219 | #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) |
2220 | 2220 | ||
2221 | 2221 | ||
2222 | #define SDR0_SDSTP1 0x0021 | 2222 | #define SDR0_SDSTP1 0x0021 |
2223 | #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 | 2223 | #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 |
2224 | #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) | 2224 | #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) |
2225 | #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) | 2225 | #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) |
2226 | #define SDR0_SDSTP1_PERDV0_MASK 0x03000000 | 2226 | #define SDR0_SDSTP1_PERDV0_MASK 0x03000000 |
2227 | #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 2227 | #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
2228 | #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) | 2228 | #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) |
2229 | #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 | 2229 | #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 |
2230 | #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) | 2230 | #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) |
2231 | #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | 2231 | #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) |
2232 | #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 | 2232 | #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 |
2233 | #define SDR0_SDSTP1_DDR1_MODE 0x00100000 | 2233 | #define SDR0_SDSTP1_DDR1_MODE 0x00100000 |
2234 | #define SDR0_SDSTP1_DDR2_MODE 0x00200000 | 2234 | #define SDR0_SDSTP1_DDR2_MODE 0x00200000 |
2235 | #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) | 2235 | #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) |
2236 | #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) | 2236 | #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) |
2237 | #define SDR0_SDSTP1_ERPN_MASK 0x00080000 | 2237 | #define SDR0_SDSTP1_ERPN_MASK 0x00080000 |
2238 | #define SDR0_SDSTP1_ERPN_EBC 0x00000000 | 2238 | #define SDR0_SDSTP1_ERPN_EBC 0x00000000 |
2239 | #define SDR0_SDSTP1_ERPN_PCI 0x00080000 | 2239 | #define SDR0_SDSTP1_ERPN_PCI 0x00080000 |
2240 | #define SDR0_SDSTP1_PAE_MASK 0x00040000 | 2240 | #define SDR0_SDSTP1_PAE_MASK 0x00040000 |
2241 | #define SDR0_SDSTP1_PAE_DISABLE 0x00000000 | 2241 | #define SDR0_SDSTP1_PAE_DISABLE 0x00000000 |
2242 | #define SDR0_SDSTP1_PAE_ENABLE 0x00040000 | 2242 | #define SDR0_SDSTP1_PAE_ENABLE 0x00040000 |
2243 | #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | 2243 | #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) |
2244 | #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | 2244 | #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) |
2245 | #define SDR0_SDSTP1_PHCE_MASK 0x00020000 | 2245 | #define SDR0_SDSTP1_PHCE_MASK 0x00020000 |
2246 | #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 | 2246 | #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 |
2247 | #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 | 2247 | #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 |
2248 | #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | 2248 | #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) |
2249 | #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | 2249 | #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) |
2250 | #define SDR0_SDSTP1_PISE_MASK 0x00010000 | 2250 | #define SDR0_SDSTP1_PISE_MASK 0x00010000 |
2251 | #define SDR0_SDSTP1_PISE_DISABLE 0x00000000 | 2251 | #define SDR0_SDSTP1_PISE_DISABLE 0x00000000 |
2252 | #define SDR0_SDSTP1_PISE_ENABLE 0x00001000 | 2252 | #define SDR0_SDSTP1_PISE_ENABLE 0x00001000 |
2253 | #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | 2253 | #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) |
2254 | #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | 2254 | #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) |
2255 | #define SDR0_SDSTP1_PCWE_MASK 0x00008000 | 2255 | #define SDR0_SDSTP1_PCWE_MASK 0x00008000 |
2256 | #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 | 2256 | #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 |
2257 | #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 | 2257 | #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 |
2258 | #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | 2258 | #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) |
2259 | #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | 2259 | #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) |
2260 | #define SDR0_SDSTP1_PPIM_MASK 0x00007800 | 2260 | #define SDR0_SDSTP1_PPIM_MASK 0x00007800 |
2261 | #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | 2261 | #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) |
2262 | #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | 2262 | #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) |
2263 | #define SDR0_SDSTP1_PR64E_MASK 0x00000400 | 2263 | #define SDR0_SDSTP1_PR64E_MASK 0x00000400 |
2264 | #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 | 2264 | #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 |
2265 | #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 | 2265 | #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 |
2266 | #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) | 2266 | #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) |
2267 | #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) | 2267 | #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) |
2268 | #define SDR0_SDSTP1_PXFS_MASK 0x00000300 | 2268 | #define SDR0_SDSTP1_PXFS_MASK 0x00000300 |
2269 | #define SDR0_SDSTP1_PXFS_100_133 0x00000000 | 2269 | #define SDR0_SDSTP1_PXFS_100_133 0x00000000 |
2270 | #define SDR0_SDSTP1_PXFS_66_100 0x00000100 | 2270 | #define SDR0_SDSTP1_PXFS_66_100 0x00000100 |
2271 | #define SDR0_SDSTP1_PXFS_50_66 0x00000200 | 2271 | #define SDR0_SDSTP1_PXFS_50_66 0x00000200 |
2272 | #define SDR0_SDSTP1_PXFS_0_50 0x00000300 | 2272 | #define SDR0_SDSTP1_PXFS_0_50 0x00000300 |
2273 | #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | 2273 | #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) |
2274 | #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | 2274 | #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) |
2275 | #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ | 2275 | #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ |
2276 | #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ | 2276 | #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ |
2277 | #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ | 2277 | #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ |
2278 | #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ | 2278 | #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ |
2279 | #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 | 2279 | #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 |
2280 | #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 | 2280 | #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 |
2281 | #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ | 2281 | #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ |
2282 | #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ | 2282 | #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ |
2283 | #define SDR0_SDSTP1_ETH_MASK 0x00000004 | 2283 | #define SDR0_SDSTP1_ETH_MASK 0x00000004 |
2284 | #define SDR0_SDSTP1_ETH_10_100 0x00000000 | 2284 | #define SDR0_SDSTP1_ETH_10_100 0x00000000 |
2285 | #define SDR0_SDSTP1_ETH_GIGA 0x00000004 | 2285 | #define SDR0_SDSTP1_ETH_GIGA 0x00000004 |
2286 | #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) | 2286 | #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) |
2287 | #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) | 2287 | #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) |
2288 | #define SDR0_SDSTP1_NTO1_MASK 0x00000001 | 2288 | #define SDR0_SDSTP1_NTO1_MASK 0x00000001 |
2289 | #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 | 2289 | #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 |
2290 | #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 | 2290 | #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 |
2291 | #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) | 2291 | #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) |
2292 | #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) | 2292 | #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) |
2293 | 2293 | ||
2294 | #define SDR0_SDSTP2 0x0022 | 2294 | #define SDR0_SDSTP2 0x0022 |
2295 | #define SDR0_SDSTP2_P1AE_MASK 0x80000000 | 2295 | #define SDR0_SDSTP2_P1AE_MASK 0x80000000 |
2296 | #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 | 2296 | #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 |
2297 | #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 | 2297 | #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 |
2298 | #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | 2298 | #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) |
2299 | #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | 2299 | #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) |
2300 | #define SDR0_SDSTP2_P1HCE_MASK 0x40000000 | 2300 | #define SDR0_SDSTP2_P1HCE_MASK 0x40000000 |
2301 | #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 | 2301 | #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 |
2302 | #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 | 2302 | #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 |
2303 | #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 2303 | #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
2304 | #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 2304 | #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
2305 | #define SDR0_SDSTP2_P1ISE_MASK 0x20000000 | 2305 | #define SDR0_SDSTP2_P1ISE_MASK 0x20000000 |
2306 | #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 | 2306 | #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 |
2307 | #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 | 2307 | #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 |
2308 | #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | 2308 | #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) |
2309 | #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | 2309 | #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) |
2310 | #define SDR0_SDSTP2_P1CWE_MASK 0x10000000 | 2310 | #define SDR0_SDSTP2_P1CWE_MASK 0x10000000 |
2311 | #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 | 2311 | #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 |
2312 | #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 | 2312 | #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 |
2313 | #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | 2313 | #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) |
2314 | #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | 2314 | #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) |
2315 | #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 | 2315 | #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 |
2316 | #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | 2316 | #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) |
2317 | #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | 2317 | #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) |
2318 | #define SDR0_SDSTP2_P1R64E_MASK 0x00800000 | 2318 | #define SDR0_SDSTP2_P1R64E_MASK 0x00800000 |
2319 | #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 | 2319 | #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 |
2320 | #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 | 2320 | #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 |
2321 | #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | 2321 | #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) |
2322 | #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | 2322 | #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) |
2323 | #define SDR0_SDSTP2_P1XFS_MASK 0x00600000 | 2323 | #define SDR0_SDSTP2_P1XFS_MASK 0x00600000 |
2324 | #define SDR0_SDSTP2_P1XFS_100_133 0x00000000 | 2324 | #define SDR0_SDSTP2_P1XFS_100_133 0x00000000 |
2325 | #define SDR0_SDSTP2_P1XFS_66_100 0x00200000 | 2325 | #define SDR0_SDSTP2_P1XFS_66_100 0x00200000 |
2326 | #define SDR0_SDSTP2_P1XFS_50_66 0x00400000 | 2326 | #define SDR0_SDSTP2_P1XFS_50_66 0x00400000 |
2327 | #define SDR0_SDSTP2_P1XFS_0_50 0x00600000 | 2327 | #define SDR0_SDSTP2_P1XFS_0_50 0x00600000 |
2328 | #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | 2328 | #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) |
2329 | #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | 2329 | #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) |
2330 | #define SDR0_SDSTP2_P2AE_MASK 0x00040000 | 2330 | #define SDR0_SDSTP2_P2AE_MASK 0x00040000 |
2331 | #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 | 2331 | #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 |
2332 | #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 | 2332 | #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 |
2333 | #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | 2333 | #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) |
2334 | #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | 2334 | #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) |
2335 | #define SDR0_SDSTP2_P2HCE_MASK 0x00020000 | 2335 | #define SDR0_SDSTP2_P2HCE_MASK 0x00020000 |
2336 | #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 | 2336 | #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 |
2337 | #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 | 2337 | #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 |
2338 | #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | 2338 | #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) |
2339 | #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | 2339 | #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) |
2340 | #define SDR0_SDSTP2_P2ISE_MASK 0x00010000 | 2340 | #define SDR0_SDSTP2_P2ISE_MASK 0x00010000 |
2341 | #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 | 2341 | #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 |
2342 | #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 | 2342 | #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 |
2343 | #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | 2343 | #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) |
2344 | #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | 2344 | #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) |
2345 | #define SDR0_SDSTP2_P2CWE_MASK 0x00008000 | 2345 | #define SDR0_SDSTP2_P2CWE_MASK 0x00008000 |
2346 | #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 | 2346 | #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 |
2347 | #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 | 2347 | #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 |
2348 | #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | 2348 | #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) |
2349 | #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | 2349 | #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) |
2350 | #define SDR0_SDSTP2_P2PIM_MASK 0x00007800 | 2350 | #define SDR0_SDSTP2_P2PIM_MASK 0x00007800 |
2351 | #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | 2351 | #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) |
2352 | #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | 2352 | #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) |
2353 | #define SDR0_SDSTP2_P2XFS_MASK 0x00000300 | 2353 | #define SDR0_SDSTP2_P2XFS_MASK 0x00000300 |
2354 | #define SDR0_SDSTP2_P2XFS_100_133 0x00000000 | 2354 | #define SDR0_SDSTP2_P2XFS_100_133 0x00000000 |
2355 | #define SDR0_SDSTP2_P2XFS_66_100 0x00000100 | 2355 | #define SDR0_SDSTP2_P2XFS_66_100 0x00000100 |
2356 | #define SDR0_SDSTP2_P2XFS_50_66 0x00000200 | 2356 | #define SDR0_SDSTP2_P2XFS_50_66 0x00000200 |
2357 | #define SDR0_SDSTP2_P2XFS_0_50 0x00000100 | 2357 | #define SDR0_SDSTP2_P2XFS_0_50 0x00000100 |
2358 | #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | 2358 | #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) |
2359 | #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | 2359 | #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) |
2360 | 2360 | ||
2361 | #define SDR0_SDSTP3 0x0023 | 2361 | #define SDR0_SDSTP3 0x0023 |
2362 | 2362 | ||
2363 | #define SDR0_PINSTP 0x0040 | 2363 | #define SDR0_PINSTP 0x0040 |
2364 | #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ | 2364 | #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ |
2365 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */ | 2365 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */ |
2366 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */ | 2366 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */ |
2367 | #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */ | 2367 | #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */ |
2368 | #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */ | 2368 | #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */ |
2369 | #define SDR0_SDCS 0x0060 | 2369 | #define SDR0_SDCS 0x0060 |
2370 | #define SDR0_ECID0 0x0080 | 2370 | #define SDR0_ECID0 0x0080 |
2371 | #define SDR0_ECID1 0x0081 | 2371 | #define SDR0_ECID1 0x0081 |
2372 | #define SDR0_ECID2 0x0082 | 2372 | #define SDR0_ECID2 0x0082 |
2373 | #define SDR0_JTAG 0x00C0 | 2373 | #define SDR0_JTAG 0x00C0 |
2374 | 2374 | ||
2375 | #define SDR0_DDR0 0x00E1 | 2375 | #define SDR0_DDR0 0x00E1 |
2376 | #define SDR0_DDR0_DPLLRST 0x80000000 | 2376 | #define SDR0_DDR0_DPLLRST 0x80000000 |
2377 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | 2377 | #define SDR0_DDR0_DDRM_MASK 0x60000000 |
2378 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | 2378 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 |
2379 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | 2379 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 |
2380 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | 2380 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) |
2381 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | 2381 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) |
2382 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | 2382 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) |
2383 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | 2383 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) |
2384 | 2384 | ||
2385 | #define SDR0_UART0 0x0120 | 2385 | #define SDR0_UART0 0x0120 |
2386 | #define SDR0_UART1 0x0121 | 2386 | #define SDR0_UART1 0x0121 |
2387 | #define SDR0_UART2 0x0122 | 2387 | #define SDR0_UART2 0x0122 |
2388 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | 2388 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 |
2389 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | 2389 | #define SDR0_UARTX_UXICS_PLB 0x20000000 |
2390 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | 2390 | #define SDR0_UARTX_UXEC_MASK 0x00800000 |
2391 | #define SDR0_UARTX_UXEC_INT 0x00000000 | 2391 | #define SDR0_UARTX_UXEC_INT 0x00000000 |
2392 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | 2392 | #define SDR0_UARTX_UXEC_EXT 0x00800000 |
2393 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | 2393 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF |
2394 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | 2394 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) |
2395 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | 2395 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) |
2396 | 2396 | ||
2397 | #define SDR0_CP440 0x0180 | 2397 | #define SDR0_CP440 0x0180 |
2398 | #define SDR0_CP440_ERPN_MASK 0x30000000 | 2398 | #define SDR0_CP440_ERPN_MASK 0x30000000 |
2399 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 | 2399 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 |
2400 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 | 2400 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 |
2401 | #define SDR0_CP440_ERPN_EBC 0x10000000 | 2401 | #define SDR0_CP440_ERPN_EBC 0x10000000 |
2402 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 | 2402 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 |
2403 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 | 2403 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 |
2404 | #define SDR0_CP440_ERPN_PCI 0x20000000 | 2404 | #define SDR0_CP440_ERPN_PCI 0x20000000 |
2405 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 | 2405 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 |
2406 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 | 2406 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 |
2407 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | 2407 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) |
2408 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | 2408 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) |
2409 | #define SDR0_CP440_NTO1_MASK 0x00000002 | 2409 | #define SDR0_CP440_NTO1_MASK 0x00000002 |
2410 | #define SDR0_CP440_NTO1_NTOP 0x00000000 | 2410 | #define SDR0_CP440_NTO1_NTOP 0x00000000 |
2411 | #define SDR0_CP440_NTO1_NTO1 0x00000002 | 2411 | #define SDR0_CP440_NTO1_NTO1 0x00000002 |
2412 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | 2412 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) |
2413 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | 2413 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) |
2414 | 2414 | ||
2415 | #define SDR0_XCR0 0x01C0 | 2415 | #define SDR0_XCR0 0x01C0 |
2416 | #define SDR0_XCR1 0x01C3 | 2416 | #define SDR0_XCR1 0x01C3 |
2417 | #define SDR0_XCR2 0x01C6 | 2417 | #define SDR0_XCR2 0x01C6 |
2418 | #define SDR0_XCRn_PAE_MASK 0x80000000 | 2418 | #define SDR0_XCRn_PAE_MASK 0x80000000 |
2419 | #define SDR0_XCRn_PAE_DISABLE 0x00000000 | 2419 | #define SDR0_XCRn_PAE_DISABLE 0x00000000 |
2420 | #define SDR0_XCRn_PAE_ENABLE 0x80000000 | 2420 | #define SDR0_XCRn_PAE_ENABLE 0x80000000 |
2421 | #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | 2421 | #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) |
2422 | #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | 2422 | #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) |
2423 | #define SDR0_XCRn_PHCE_MASK 0x40000000 | 2423 | #define SDR0_XCRn_PHCE_MASK 0x40000000 |
2424 | #define SDR0_XCRn_PHCE_DISABLE 0x00000000 | 2424 | #define SDR0_XCRn_PHCE_DISABLE 0x00000000 |
2425 | #define SDR0_XCRn_PHCE_ENABLE 0x40000000 | 2425 | #define SDR0_XCRn_PHCE_ENABLE 0x40000000 |
2426 | #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 2426 | #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
2427 | #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 2427 | #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
2428 | #define SDR0_XCRn_PISE_MASK 0x20000000 | 2428 | #define SDR0_XCRn_PISE_MASK 0x20000000 |
2429 | #define SDR0_XCRn_PISE_DISABLE 0x00000000 | 2429 | #define SDR0_XCRn_PISE_DISABLE 0x00000000 |
2430 | #define SDR0_XCRn_PISE_ENABLE 0x20000000 | 2430 | #define SDR0_XCRn_PISE_ENABLE 0x20000000 |
2431 | #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | 2431 | #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) |
2432 | #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | 2432 | #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) |
2433 | #define SDR0_XCRn_PCWE_MASK 0x10000000 | 2433 | #define SDR0_XCRn_PCWE_MASK 0x10000000 |
2434 | #define SDR0_XCRn_PCWE_DISABLE 0x00000000 | 2434 | #define SDR0_XCRn_PCWE_DISABLE 0x00000000 |
2435 | #define SDR0_XCRn_PCWE_ENABLE 0x10000000 | 2435 | #define SDR0_XCRn_PCWE_ENABLE 0x10000000 |
2436 | #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | 2436 | #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) |
2437 | #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | 2437 | #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) |
2438 | #define SDR0_XCRn_PPIM_MASK 0x0F000000 | 2438 | #define SDR0_XCRn_PPIM_MASK 0x0F000000 |
2439 | #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | 2439 | #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) |
2440 | #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | 2440 | #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) |
2441 | #define SDR0_XCRn_PR64E_MASK 0x00800000 | 2441 | #define SDR0_XCRn_PR64E_MASK 0x00800000 |
2442 | #define SDR0_XCRn_PR64E_DISABLE 0x00000000 | 2442 | #define SDR0_XCRn_PR64E_DISABLE 0x00000000 |
2443 | #define SDR0_XCRn_PR64E_ENABLE 0x00800000 | 2443 | #define SDR0_XCRn_PR64E_ENABLE 0x00800000 |
2444 | #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | 2444 | #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) |
2445 | #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | 2445 | #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) |
2446 | #define SDR0_XCRn_PXFS_MASK 0x00600000 | 2446 | #define SDR0_XCRn_PXFS_MASK 0x00600000 |
2447 | #define SDR0_XCRn_PXFS_100_133 0x00000000 | 2447 | #define SDR0_XCRn_PXFS_100_133 0x00000000 |
2448 | #define SDR0_XCRn_PXFS_66_100 0x00200000 | 2448 | #define SDR0_XCRn_PXFS_66_100 0x00200000 |
2449 | #define SDR0_XCRn_PXFS_50_66 0x00400000 | 2449 | #define SDR0_XCRn_PXFS_50_66 0x00400000 |
2450 | #define SDR0_XCRn_PXFS_0_33 0x00600000 | 2450 | #define SDR0_XCRn_PXFS_0_33 0x00600000 |
2451 | #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | 2451 | #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) |
2452 | #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | 2452 | #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) |
2453 | 2453 | ||
2454 | #define SDR0_XPLLC0 0x01C1 | 2454 | #define SDR0_XPLLC0 0x01C1 |
2455 | #define SDR0_XPLLD0 0x01C2 | 2455 | #define SDR0_XPLLD0 0x01C2 |
2456 | #define SDR0_XPLLC1 0x01C4 | 2456 | #define SDR0_XPLLC1 0x01C4 |
2457 | #define SDR0_XPLLD1 0x01C5 | 2457 | #define SDR0_XPLLD1 0x01C5 |
2458 | #define SDR0_XPLLC2 0x01C7 | 2458 | #define SDR0_XPLLC2 0x01C7 |
2459 | #define SDR0_XPLLD2 0x01C8 | 2459 | #define SDR0_XPLLD2 0x01C8 |
2460 | #define SDR0_SRST 0x0200 | 2460 | #define SDR0_SRST 0x0200 |
2461 | #define SDR0_SLPIPE 0x0220 | 2461 | #define SDR0_SLPIPE 0x0220 |
2462 | 2462 | ||
2463 | #define SDR0_AMP0 0x0240 | 2463 | #define SDR0_AMP0 0x0240 |
2464 | #define SDR0_AMP0_PRIORITY 0xFFFF0000 | 2464 | #define SDR0_AMP0_PRIORITY 0xFFFF0000 |
2465 | #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 | 2465 | #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 |
2466 | #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF | 2466 | #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF |
2467 | 2467 | ||
2468 | #define SDR0_AMP1 0x0241 | 2468 | #define SDR0_AMP1 0x0241 |
2469 | #define SDR0_AMP1_PRIORITY 0xFC000000 | 2469 | #define SDR0_AMP1_PRIORITY 0xFC000000 |
2470 | #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 | 2470 | #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 |
2471 | #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF | 2471 | #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF |
2472 | 2472 | ||
2473 | #define SDR0_MIRQ0 0x0260 | 2473 | #define SDR0_MIRQ0 0x0260 |
2474 | #define SDR0_MIRQ1 0x0261 | 2474 | #define SDR0_MIRQ1 0x0261 |
2475 | #define SDR0_MALTBL 0x0280 | 2475 | #define SDR0_MALTBL 0x0280 |
2476 | #define SDR0_MALRBL 0x02A0 | 2476 | #define SDR0_MALRBL 0x02A0 |
2477 | #define SDR0_MALTBS 0x02C0 | 2477 | #define SDR0_MALTBS 0x02C0 |
2478 | #define SDR0_MALRBS 0x02E0 | 2478 | #define SDR0_MALRBS 0x02E0 |
2479 | 2479 | ||
2480 | /* Reserved for Customer Use */ | 2480 | /* Reserved for Customer Use */ |
2481 | #define SDR0_CUST0 0x4000 | 2481 | #define SDR0_CUST0 0x4000 |
2482 | #define SDR0_CUST0_AUTONEG_MASK 0x8000000 | 2482 | #define SDR0_CUST0_AUTONEG_MASK 0x8000000 |
2483 | #define SDR0_CUST0_NO_AUTONEG 0x0000000 | 2483 | #define SDR0_CUST0_NO_AUTONEG 0x0000000 |
2484 | #define SDR0_CUST0_AUTONEG 0x8000000 | 2484 | #define SDR0_CUST0_AUTONEG 0x8000000 |
2485 | #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 | 2485 | #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 |
2486 | #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 | 2486 | #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 |
2487 | #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 | 2487 | #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 |
2488 | #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 | 2488 | #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 |
2489 | #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 | 2489 | #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 |
2490 | #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 | 2490 | #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 |
2491 | #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 | 2491 | #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 |
2492 | 2492 | ||
2493 | #define SDR0_SDSTP4 0x4001 | 2493 | #define SDR0_SDSTP4 0x4001 |
2494 | #define SDR0_CUST1 0x4002 | 2494 | #define SDR0_CUST1 0x4002 |
2495 | #define SDR0_SDSTP5 0x4003 | 2495 | #define SDR0_SDSTP5 0x4003 |
2496 | #define SDR0_CUST2 0x4004 | 2496 | #define SDR0_CUST2 0x4004 |
2497 | #define SDR0_SDSTP6 0x4005 | 2497 | #define SDR0_SDSTP6 0x4005 |
2498 | #define SDR0_CUST3 0x4006 | 2498 | #define SDR0_CUST3 0x4006 |
2499 | #define SDR0_SDSTP7 0x4007 | 2499 | #define SDR0_SDSTP7 0x4007 |
2500 | 2500 | ||
2501 | #define SDR0_PFC0 0x4100 | 2501 | #define SDR0_PFC0 0x4100 |
2502 | #define SDR0_PFC0_GPIO_0 0x80000000 | 2502 | #define SDR0_PFC0_GPIO_0 0x80000000 |
2503 | #define SDR0_PFC0_PCIX0REQ2_N 0x00000000 | 2503 | #define SDR0_PFC0_PCIX0REQ2_N 0x00000000 |
2504 | #define SDR0_PFC0_GPIO_1 0x40000000 | 2504 | #define SDR0_PFC0_GPIO_1 0x40000000 |
2505 | #define SDR0_PFC0_PCIX0REQ3_N 0x00000000 | 2505 | #define SDR0_PFC0_PCIX0REQ3_N 0x00000000 |
2506 | #define SDR0_PFC0_GPIO_2 0x20000000 | 2506 | #define SDR0_PFC0_GPIO_2 0x20000000 |
2507 | #define SDR0_PFC0_PCIX0GNT2_N 0x00000000 | 2507 | #define SDR0_PFC0_PCIX0GNT2_N 0x00000000 |
2508 | #define SDR0_PFC0_GPIO_3 0x10000000 | 2508 | #define SDR0_PFC0_GPIO_3 0x10000000 |
2509 | #define SDR0_PFC0_PCIX0GNT3_N 0x00000000 | 2509 | #define SDR0_PFC0_PCIX0GNT3_N 0x00000000 |
2510 | #define SDR0_PFC0_GPIO_4 0x08000000 | 2510 | #define SDR0_PFC0_GPIO_4 0x08000000 |
2511 | #define SDR0_PFC0_PCIX1REQ2_N 0x00000000 | 2511 | #define SDR0_PFC0_PCIX1REQ2_N 0x00000000 |
2512 | #define SDR0_PFC0_GPIO_5 0x04000000 | 2512 | #define SDR0_PFC0_GPIO_5 0x04000000 |
2513 | #define SDR0_PFC0_PCIX1REQ3_N 0x00000000 | 2513 | #define SDR0_PFC0_PCIX1REQ3_N 0x00000000 |
2514 | #define SDR0_PFC0_GPIO_6 0x02000000 | 2514 | #define SDR0_PFC0_GPIO_6 0x02000000 |
2515 | #define SDR0_PFC0_PCIX1GNT2_N 0x00000000 | 2515 | #define SDR0_PFC0_PCIX1GNT2_N 0x00000000 |
2516 | #define SDR0_PFC0_GPIO_7 0x01000000 | 2516 | #define SDR0_PFC0_GPIO_7 0x01000000 |
2517 | #define SDR0_PFC0_PCIX1GNT3_N 0x00000000 | 2517 | #define SDR0_PFC0_PCIX1GNT3_N 0x00000000 |
2518 | #define SDR0_PFC0_GPIO_8 0x00800000 | 2518 | #define SDR0_PFC0_GPIO_8 0x00800000 |
2519 | #define SDR0_PFC0_PERREADY 0x00000000 | 2519 | #define SDR0_PFC0_PERREADY 0x00000000 |
2520 | #define SDR0_PFC0_GPIO_9 0x00400000 | 2520 | #define SDR0_PFC0_GPIO_9 0x00400000 |
2521 | #define SDR0_PFC0_PERCS1_N 0x00000000 | 2521 | #define SDR0_PFC0_PERCS1_N 0x00000000 |
2522 | #define SDR0_PFC0_GPIO_10 0x00200000 | 2522 | #define SDR0_PFC0_GPIO_10 0x00200000 |
2523 | #define SDR0_PFC0_PERCS2_N 0x00000000 | 2523 | #define SDR0_PFC0_PERCS2_N 0x00000000 |
2524 | #define SDR0_PFC0_GPIO_11 0x00100000 | 2524 | #define SDR0_PFC0_GPIO_11 0x00100000 |
2525 | #define SDR0_PFC0_IRQ0 0x00000000 | 2525 | #define SDR0_PFC0_IRQ0 0x00000000 |
2526 | #define SDR0_PFC0_GPIO_12 0x00080000 | 2526 | #define SDR0_PFC0_GPIO_12 0x00080000 |
2527 | #define SDR0_PFC0_IRQ1 0x00000000 | 2527 | #define SDR0_PFC0_IRQ1 0x00000000 |
2528 | #define SDR0_PFC0_GPIO_13 0x00040000 | 2528 | #define SDR0_PFC0_GPIO_13 0x00040000 |
2529 | #define SDR0_PFC0_IRQ2 0x00000000 | 2529 | #define SDR0_PFC0_IRQ2 0x00000000 |
2530 | #define SDR0_PFC0_GPIO_14 0x00020000 | 2530 | #define SDR0_PFC0_GPIO_14 0x00020000 |
2531 | #define SDR0_PFC0_IRQ3 0x00000000 | 2531 | #define SDR0_PFC0_IRQ3 0x00000000 |
2532 | #define SDR0_PFC0_GPIO_15 0x00010000 | 2532 | #define SDR0_PFC0_GPIO_15 0x00010000 |
2533 | #define SDR0_PFC0_IRQ4 0x00000000 | 2533 | #define SDR0_PFC0_IRQ4 0x00000000 |
2534 | #define SDR0_PFC0_GPIO_16 0x00008000 | 2534 | #define SDR0_PFC0_GPIO_16 0x00008000 |
2535 | #define SDR0_PFC0_IRQ5 0x00000000 | 2535 | #define SDR0_PFC0_IRQ5 0x00000000 |
2536 | #define SDR0_PFC0_GPIO_17 0x00004000 | 2536 | #define SDR0_PFC0_GPIO_17 0x00004000 |
2537 | #define SDR0_PFC0_PERBE0_N 0x00000000 | 2537 | #define SDR0_PFC0_PERBE0_N 0x00000000 |
2538 | #define SDR0_PFC0_GPIO_18 0x00002000 | 2538 | #define SDR0_PFC0_GPIO_18 0x00002000 |
2539 | #define SDR0_PFC0_PCI0GNT0_N 0x00000000 | 2539 | #define SDR0_PFC0_PCI0GNT0_N 0x00000000 |
2540 | #define SDR0_PFC0_GPIO_19 0x00001000 | 2540 | #define SDR0_PFC0_GPIO_19 0x00001000 |
2541 | #define SDR0_PFC0_PCI0GNT1_N 0x00000000 | 2541 | #define SDR0_PFC0_PCI0GNT1_N 0x00000000 |
2542 | #define SDR0_PFC0_GPIO_20 0x00000800 | 2542 | #define SDR0_PFC0_GPIO_20 0x00000800 |
2543 | #define SDR0_PFC0_PCI0REQ0_N 0x00000000 | 2543 | #define SDR0_PFC0_PCI0REQ0_N 0x00000000 |
2544 | #define SDR0_PFC0_GPIO_21 0x00000400 | 2544 | #define SDR0_PFC0_GPIO_21 0x00000400 |
2545 | #define SDR0_PFC0_PCI0REQ1_N 0x00000000 | 2545 | #define SDR0_PFC0_PCI0REQ1_N 0x00000000 |
2546 | #define SDR0_PFC0_GPIO_22 0x00000200 | 2546 | #define SDR0_PFC0_GPIO_22 0x00000200 |
2547 | #define SDR0_PFC0_PCI1GNT0_N 0x00000000 | 2547 | #define SDR0_PFC0_PCI1GNT0_N 0x00000000 |
2548 | #define SDR0_PFC0_GPIO_23 0x00000100 | 2548 | #define SDR0_PFC0_GPIO_23 0x00000100 |
2549 | #define SDR0_PFC0_PCI1GNT1_N 0x00000000 | 2549 | #define SDR0_PFC0_PCI1GNT1_N 0x00000000 |
2550 | #define SDR0_PFC0_GPIO_24 0x00000080 | 2550 | #define SDR0_PFC0_GPIO_24 0x00000080 |
2551 | #define SDR0_PFC0_PCI1REQ0_N 0x00000000 | 2551 | #define SDR0_PFC0_PCI1REQ0_N 0x00000000 |
2552 | #define SDR0_PFC0_GPIO_25 0x00000040 | 2552 | #define SDR0_PFC0_GPIO_25 0x00000040 |
2553 | #define SDR0_PFC0_PCI1REQ1_N 0x00000000 | 2553 | #define SDR0_PFC0_PCI1REQ1_N 0x00000000 |
2554 | #define SDR0_PFC0_GPIO_26 0x00000020 | 2554 | #define SDR0_PFC0_GPIO_26 0x00000020 |
2555 | #define SDR0_PFC0_PCI2GNT0_N 0x00000000 | 2555 | #define SDR0_PFC0_PCI2GNT0_N 0x00000000 |
2556 | #define SDR0_PFC0_GPIO_27 0x00000010 | 2556 | #define SDR0_PFC0_GPIO_27 0x00000010 |
2557 | #define SDR0_PFC0_PCI2GNT1_N 0x00000000 | 2557 | #define SDR0_PFC0_PCI2GNT1_N 0x00000000 |
2558 | #define SDR0_PFC0_GPIO_28 0x00000008 | 2558 | #define SDR0_PFC0_GPIO_28 0x00000008 |
2559 | #define SDR0_PFC0_PCI2REQ0_N 0x00000000 | 2559 | #define SDR0_PFC0_PCI2REQ0_N 0x00000000 |
2560 | #define SDR0_PFC0_GPIO_29 0x00000004 | 2560 | #define SDR0_PFC0_GPIO_29 0x00000004 |
2561 | #define SDR0_PFC0_PCI2REQ1_N 0x00000000 | 2561 | #define SDR0_PFC0_PCI2REQ1_N 0x00000000 |
2562 | #define SDR0_PFC0_GPIO_30 0x00000002 | 2562 | #define SDR0_PFC0_GPIO_30 0x00000002 |
2563 | #define SDR0_PFC0_UART1RX 0x00000000 | 2563 | #define SDR0_PFC0_UART1RX 0x00000000 |
2564 | #define SDR0_PFC0_GPIO_31 0x00000001 | 2564 | #define SDR0_PFC0_GPIO_31 0x00000001 |
2565 | #define SDR0_PFC0_UART1TX 0x00000000 | 2565 | #define SDR0_PFC0_UART1TX 0x00000000 |
2566 | 2566 | ||
2567 | #define SDR0_PFC1 0x4101 | 2567 | #define SDR0_PFC1 0x4101 |
2568 | #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 | 2568 | #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 |
2569 | #define SDR0_PFC1_UART1_DSR_DTR 0x00000000 | 2569 | #define SDR0_PFC1_UART1_DSR_DTR 0x00000000 |
2570 | #define SDR0_PFC1_UART1_CTS_RTS 0x02000000 | 2570 | #define SDR0_PFC1_UART1_CTS_RTS 0x02000000 |
2571 | #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 | 2571 | #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 |
2572 | #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 | 2572 | #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 |
2573 | #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 | 2573 | #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 |
2574 | #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 | 2574 | #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 |
2575 | #define SDR0_PFC1_ETH_10_100 0x00000000 | 2575 | #define SDR0_PFC1_ETH_10_100 0x00000000 |
2576 | #define SDR0_PFC1_ETH_GIGA 0x00200000 | 2576 | #define SDR0_PFC1_ETH_GIGA 0x00200000 |
2577 | #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) | 2577 | #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) |
2578 | #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | 2578 | #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) |
2579 | #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ | 2579 | #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ |
2580 | #define SDR0_PFC1_CPU_NO_TRACE 0x00000000 | 2580 | #define SDR0_PFC1_CPU_NO_TRACE 0x00000000 |
2581 | #define SDR0_PFC1_CPU_TRACE 0x00080000 | 2581 | #define SDR0_PFC1_CPU_TRACE 0x00080000 |
2582 | #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */ | 2582 | #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */ |
2583 | #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */ | 2583 | #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */ |
2584 | 2584 | ||
2585 | #define SDR0_MFR 0x4300 | 2585 | #define SDR0_MFR 0x4300 |
2586 | #endif /* CONFIG_440SPE */ | 2586 | #endif /* CONFIG_440SPE */ |
2587 | 2587 | ||
2588 | 2588 | ||
2589 | #define SDR0_SDCS_SDD (0x80000000 >> 31) | 2589 | #define SDR0_SDCS_SDD (0x80000000 >> 31) |
2590 | 2590 | ||
2591 | #if defined(CONFIG_440GP) | 2591 | #if defined(CONFIG_440GP) |
2592 | #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) | 2592 | #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) |
2593 | #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) | 2593 | #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) |
2594 | #endif /* defined(CONFIG_440GP) */ | 2594 | #endif /* defined(CONFIG_440GP) */ |
2595 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) | 2595 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
2596 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) | 2596 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) |
2597 | #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) | 2597 | #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) |
2598 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ | 2598 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
2599 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | 2599 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
2600 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 2600 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
2601 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) | 2601 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) |
2602 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) | 2602 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) |
2603 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ | 2603 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ |
2604 | 2604 | ||
2605 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | 2605 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 |
2606 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | 2606 | #define SDR0_UARTX_UXICS_PLB 0x20000000 |
2607 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | 2607 | #define SDR0_UARTX_UXEC_MASK 0x00800000 |
2608 | #define SDR0_UARTX_UXEC_INT 0x00000000 | 2608 | #define SDR0_UARTX_UXEC_INT 0x00000000 |
2609 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | 2609 | #define SDR0_UARTX_UXEC_EXT 0x00800000 |
2610 | #define SDR0_UARTX_UXDTE_MASK 0x00400000 | 2610 | #define SDR0_UARTX_UXDTE_MASK 0x00400000 |
2611 | #define SDR0_UARTX_UXDTE_DISABLE 0x00000000 | 2611 | #define SDR0_UARTX_UXDTE_DISABLE 0x00000000 |
2612 | #define SDR0_UARTX_UXDTE_ENABLE 0x00400000 | 2612 | #define SDR0_UARTX_UXDTE_ENABLE 0x00400000 |
2613 | #define SDR0_UARTX_UXDRE_MASK 0x00200000 | 2613 | #define SDR0_UARTX_UXDRE_MASK 0x00200000 |
2614 | #define SDR0_UARTX_UXDRE_DISABLE 0x00000000 | 2614 | #define SDR0_UARTX_UXDRE_DISABLE 0x00000000 |
2615 | #define SDR0_UARTX_UXDRE_ENABLE 0x00200000 | 2615 | #define SDR0_UARTX_UXDRE_ENABLE 0x00200000 |
2616 | #define SDR0_UARTX_UXDC_MASK 0x00100000 | 2616 | #define SDR0_UARTX_UXDC_MASK 0x00100000 |
2617 | #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 | 2617 | #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 |
2618 | #define SDR0_UARTX_UXDC_CLEARED 0x00100000 | 2618 | #define SDR0_UARTX_UXDC_CLEARED 0x00100000 |
2619 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | 2619 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF |
2620 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | 2620 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) |
2621 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | 2621 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) |
2622 | 2622 | ||
2623 | #define SDR0_CPU440_EARV_MASK 0x30000000 | 2623 | #define SDR0_CPU440_EARV_MASK 0x30000000 |
2624 | #define SDR0_CPU440_EARV_EBC 0x10000000 | 2624 | #define SDR0_CPU440_EARV_EBC 0x10000000 |
2625 | #define SDR0_CPU440_EARV_PCI 0x20000000 | 2625 | #define SDR0_CPU440_EARV_PCI 0x20000000 |
2626 | #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | 2626 | #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) |
2627 | #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | 2627 | #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) |
2628 | #define SDR0_CPU440_NTO1_MASK 0x00000002 | 2628 | #define SDR0_CPU440_NTO1_MASK 0x00000002 |
2629 | #define SDR0_CPU440_NTO1_NTOP 0x00000000 | 2629 | #define SDR0_CPU440_NTO1_NTOP 0x00000000 |
2630 | #define SDR0_CPU440_NTO1_NTO1 0x00000002 | 2630 | #define SDR0_CPU440_NTO1_NTO1 0x00000002 |
2631 | #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | 2631 | #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) |
2632 | #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | 2632 | #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) |
2633 | 2633 | ||
2634 | #define SDR0_XCR_PAE_MASK 0x80000000 | 2634 | #define SDR0_XCR_PAE_MASK 0x80000000 |
2635 | #define SDR0_XCR_PAE_DISABLE 0x00000000 | 2635 | #define SDR0_XCR_PAE_DISABLE 0x00000000 |
2636 | #define SDR0_XCR_PAE_ENABLE 0x80000000 | 2636 | #define SDR0_XCR_PAE_ENABLE 0x80000000 |
2637 | #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | 2637 | #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) |
2638 | #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | 2638 | #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) |
2639 | #define SDR0_XCR_PHCE_MASK 0x40000000 | 2639 | #define SDR0_XCR_PHCE_MASK 0x40000000 |
2640 | #define SDR0_XCR_PHCE_DISABLE 0x00000000 | 2640 | #define SDR0_XCR_PHCE_DISABLE 0x00000000 |
2641 | #define SDR0_XCR_PHCE_ENABLE 0x40000000 | 2641 | #define SDR0_XCR_PHCE_ENABLE 0x40000000 |
2642 | #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 2642 | #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
2643 | #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 2643 | #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
2644 | #define SDR0_XCR_PISE_MASK 0x20000000 | 2644 | #define SDR0_XCR_PISE_MASK 0x20000000 |
2645 | #define SDR0_XCR_PISE_DISABLE 0x00000000 | 2645 | #define SDR0_XCR_PISE_DISABLE 0x00000000 |
2646 | #define SDR0_XCR_PISE_ENABLE 0x20000000 | 2646 | #define SDR0_XCR_PISE_ENABLE 0x20000000 |
2647 | #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | 2647 | #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) |
2648 | #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | 2648 | #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) |
2649 | #define SDR0_XCR_PCWE_MASK 0x10000000 | 2649 | #define SDR0_XCR_PCWE_MASK 0x10000000 |
2650 | #define SDR0_XCR_PCWE_DISABLE 0x00000000 | 2650 | #define SDR0_XCR_PCWE_DISABLE 0x00000000 |
2651 | #define SDR0_XCR_PCWE_ENABLE 0x10000000 | 2651 | #define SDR0_XCR_PCWE_ENABLE 0x10000000 |
2652 | #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | 2652 | #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) |
2653 | #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | 2653 | #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) |
2654 | #define SDR0_XCR_PPIM_MASK 0x0F000000 | 2654 | #define SDR0_XCR_PPIM_MASK 0x0F000000 |
2655 | #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | 2655 | #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) |
2656 | #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | 2656 | #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) |
2657 | #define SDR0_XCR_PR64E_MASK 0x00800000 | 2657 | #define SDR0_XCR_PR64E_MASK 0x00800000 |
2658 | #define SDR0_XCR_PR64E_DISABLE 0x00000000 | 2658 | #define SDR0_XCR_PR64E_DISABLE 0x00000000 |
2659 | #define SDR0_XCR_PR64E_ENABLE 0x00800000 | 2659 | #define SDR0_XCR_PR64E_ENABLE 0x00800000 |
2660 | #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | 2660 | #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) |
2661 | #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | 2661 | #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) |
2662 | #define SDR0_XCR_PXFS_MASK 0x00600000 | 2662 | #define SDR0_XCR_PXFS_MASK 0x00600000 |
2663 | #define SDR0_XCR_PXFS_HIGH 0x00000000 | 2663 | #define SDR0_XCR_PXFS_HIGH 0x00000000 |
2664 | #define SDR0_XCR_PXFS_MED 0x00200000 | 2664 | #define SDR0_XCR_PXFS_MED 0x00200000 |
2665 | #define SDR0_XCR_PXFS_LOW 0x00400000 | 2665 | #define SDR0_XCR_PXFS_LOW 0x00400000 |
2666 | #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | 2666 | #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) |
2667 | #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | 2667 | #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) |
2668 | #define SDR0_XCR_PDM_MASK 0x00000040 | 2668 | #define SDR0_XCR_PDM_MASK 0x00000040 |
2669 | #define SDR0_XCR_PDM_MULTIPOINT 0x00000000 | 2669 | #define SDR0_XCR_PDM_MULTIPOINT 0x00000000 |
2670 | #define SDR0_XCR_PDM_P2P 0x00000040 | 2670 | #define SDR0_XCR_PDM_P2P 0x00000040 |
2671 | #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) | 2671 | #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) |
2672 | #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) | 2672 | #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) |
2673 | 2673 | ||
2674 | #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 | 2674 | #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 |
2675 | #define SDR0_PFC0_GEIE_MASK 0x00003E00 | 2675 | #define SDR0_PFC0_GEIE_MASK 0x00003E00 |
2676 | #define SDR0_PFC0_GEIE_TRE 0x00003E00 | 2676 | #define SDR0_PFC0_GEIE_TRE 0x00003E00 |
2677 | #define SDR0_PFC0_GEIE_NOTRE 0x00000000 | 2677 | #define SDR0_PFC0_GEIE_NOTRE 0x00000000 |
2678 | #define SDR0_PFC0_TRE_MASK 0x00000100 | 2678 | #define SDR0_PFC0_TRE_MASK 0x00000100 |
2679 | #define SDR0_PFC0_TRE_DISABLE 0x00000000 | 2679 | #define SDR0_PFC0_TRE_DISABLE 0x00000000 |
2680 | #define SDR0_PFC0_TRE_ENABLE 0x00000100 | 2680 | #define SDR0_PFC0_TRE_ENABLE 0x00000100 |
2681 | #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | 2681 | #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) |
2682 | #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | 2682 | #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) |
2683 | 2683 | ||
2684 | #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 | 2684 | #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 |
2685 | #define SDR0_PFC1_EPS_MASK 0x01C00000 | 2685 | #define SDR0_PFC1_EPS_MASK 0x01C00000 |
2686 | #define SDR0_PFC1_EPS_GROUP0 0x00000000 | 2686 | #define SDR0_PFC1_EPS_GROUP0 0x00000000 |
2687 | #define SDR0_PFC1_EPS_GROUP1 0x00400000 | 2687 | #define SDR0_PFC1_EPS_GROUP1 0x00400000 |
2688 | #define SDR0_PFC1_EPS_GROUP2 0x00800000 | 2688 | #define SDR0_PFC1_EPS_GROUP2 0x00800000 |
2689 | #define SDR0_PFC1_EPS_GROUP3 0x00C00000 | 2689 | #define SDR0_PFC1_EPS_GROUP3 0x00C00000 |
2690 | #define SDR0_PFC1_EPS_GROUP4 0x01000000 | 2690 | #define SDR0_PFC1_EPS_GROUP4 0x01000000 |
2691 | #define SDR0_PFC1_EPS_GROUP5 0x01400000 | 2691 | #define SDR0_PFC1_EPS_GROUP5 0x01400000 |
2692 | #define SDR0_PFC1_EPS_GROUP6 0x01800000 | 2692 | #define SDR0_PFC1_EPS_GROUP6 0x01800000 |
2693 | #define SDR0_PFC1_EPS_GROUP7 0x01C00000 | 2693 | #define SDR0_PFC1_EPS_GROUP7 0x01C00000 |
2694 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | 2694 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) |
2695 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | 2695 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) |
2696 | #define SDR0_PFC1_RMII_MASK 0x00200000 | 2696 | #define SDR0_PFC1_RMII_MASK 0x00200000 |
2697 | #define SDR0_PFC1_RMII_100MBIT 0x00000000 | 2697 | #define SDR0_PFC1_RMII_100MBIT 0x00000000 |
2698 | #define SDR0_PFC1_RMII_10MBIT 0x00200000 | 2698 | #define SDR0_PFC1_RMII_10MBIT 0x00200000 |
2699 | #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) | 2699 | #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) |
2700 | #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | 2700 | #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) |
2701 | #define SDR0_PFC1_CTEMS_MASK 0x00100000 | 2701 | #define SDR0_PFC1_CTEMS_MASK 0x00100000 |
2702 | #define SDR0_PFC1_CTEMS_EMS 0x00000000 | 2702 | #define SDR0_PFC1_CTEMS_EMS 0x00000000 |
2703 | #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 | 2703 | #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 |
2704 | 2704 | ||
2705 | #define SDR0_MFR_TAH0_MASK 0x80000000 | 2705 | #define SDR0_MFR_TAH0_MASK 0x80000000 |
2706 | #define SDR0_MFR_TAH0_ENABLE 0x00000000 | 2706 | #define SDR0_MFR_TAH0_ENABLE 0x00000000 |
2707 | #define SDR0_MFR_TAH0_DISABLE 0x80000000 | 2707 | #define SDR0_MFR_TAH0_DISABLE 0x80000000 |
2708 | #define SDR0_MFR_TAH1_MASK 0x40000000 | 2708 | #define SDR0_MFR_TAH1_MASK 0x40000000 |
2709 | #define SDR0_MFR_TAH1_ENABLE 0x00000000 | 2709 | #define SDR0_MFR_TAH1_ENABLE 0x00000000 |
2710 | #define SDR0_MFR_TAH1_DISABLE 0x40000000 | 2710 | #define SDR0_MFR_TAH1_DISABLE 0x40000000 |
2711 | #define SDR0_MFR_PCM_MASK 0x20000000 | 2711 | #define SDR0_MFR_PCM_MASK 0x20000000 |
2712 | #define SDR0_MFR_PCM_PPC440GX 0x00000000 | 2712 | #define SDR0_MFR_PCM_PPC440GX 0x00000000 |
2713 | #define SDR0_MFR_PCM_PPC440GP 0x20000000 | 2713 | #define SDR0_MFR_PCM_PPC440GP 0x20000000 |
2714 | #define SDR0_MFR_ECS_MASK 0x10000000 | 2714 | #define SDR0_MFR_ECS_MASK 0x10000000 |
2715 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | 2715 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 |
2716 | 2716 | ||
2717 | #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ | 2717 | #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ |
2718 | #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ | 2718 | #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ |
2719 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | 2719 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ |
2720 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | 2720 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ |
2721 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | 2721 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ |
2722 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | 2722 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ |
2723 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | 2723 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ |
2724 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | 2724 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ |
2725 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | 2725 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ |
2726 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | 2726 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 |
2727 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | 2727 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 |
2728 | #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ | 2728 | #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ |
2729 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ | 2729 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ |
2730 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | 2730 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ |
2731 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ | 2731 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ |
2732 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ | 2732 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ |
2733 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ | 2733 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ |
2734 | #endif | 2734 | #endif |
2735 | 2735 | ||
2736 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 2736 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
2737 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | 2737 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) |
2738 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | 2738 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) |
2739 | #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) | 2739 | #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) |
2740 | #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) | 2740 | #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) |
2741 | #endif | 2741 | #endif |
2742 | 2742 | ||
2743 | #define SDR0_MFR_ECS_MASK 0x10000000 | 2743 | #define SDR0_MFR_ECS_MASK 0x10000000 |
2744 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | 2744 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 |
2745 | 2745 | ||
2746 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 2746 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
2747 | #define SDR0_SRST0 0x200 | 2747 | #define SDR0_SRST0 0x200 |
2748 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ | 2748 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ |
2749 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | 2749 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ |
2750 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | 2750 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ |
2751 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | 2751 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ |
2752 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ | 2752 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ |
2753 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ | 2753 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ |
2754 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ | 2754 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ |
2755 | #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ | 2755 | #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ |
2756 | #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ | 2756 | #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ |
2757 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | 2757 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ |
2758 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | 2758 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ |
2759 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | 2759 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ |
2760 | #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ | 2760 | #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ |
2761 | #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ | 2761 | #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ |
2762 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | 2762 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ |
2763 | #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ | 2763 | #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ |
2764 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ | 2764 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ |
2765 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ | 2765 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ |
2766 | #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ | 2766 | #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ |
2767 | #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ | 2767 | #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ |
2768 | #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ | 2768 | #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ |
2769 | #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ | 2769 | #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ |
2770 | #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ | 2770 | #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ |
2771 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ | 2771 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ |
2772 | #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ | 2772 | #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ |
2773 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | 2773 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ |
2774 | #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ | 2774 | #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ |
2775 | #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ | 2775 | #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ |
2776 | #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ | 2776 | #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ |
2777 | #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */ | 2777 | #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */ |
2778 | #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */ | 2778 | #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */ |
2779 | 2779 | ||
2780 | #define SDR0_SRST1 0x201 | 2780 | #define SDR0_SRST1 0x201 |
2781 | #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ | 2781 | #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ |
2782 | #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ | 2782 | #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ |
2783 | #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ | 2783 | #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ |
2784 | #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 | 2784 | #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 |
2785 | #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ | 2785 | #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ |
2786 | #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ | 2786 | #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ |
2787 | #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */ | 2787 | #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */ |
2788 | #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */ | 2788 | #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */ |
2789 | #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */ | 2789 | #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */ |
2790 | #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ | 2790 | #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ |
2791 | #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */ | 2791 | #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */ |
2792 | #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ | 2792 | #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ |
2793 | #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ | 2793 | #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ |
2794 | #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ | 2794 | #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ |
2795 | #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ | 2795 | #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ |
2796 | #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ | 2796 | #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ |
2797 | #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ | 2797 | #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ |
2798 | #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ | 2798 | #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ |
2799 | #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ | 2799 | #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ |
2800 | #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ | 2800 | #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ |
2801 | 2801 | ||
2802 | #else | 2802 | #else |
2803 | 2803 | ||
2804 | #define SDR0_SRST_BGO 0x80000000 | 2804 | #define SDR0_SRST_BGO 0x80000000 |
2805 | #define SDR0_SRST_PLB 0x40000000 | 2805 | #define SDR0_SRST_PLB 0x40000000 |
2806 | #define SDR0_SRST_EBC 0x20000000 | 2806 | #define SDR0_SRST_EBC 0x20000000 |
2807 | #define SDR0_SRST_OPB 0x10000000 | 2807 | #define SDR0_SRST_OPB 0x10000000 |
2808 | #define SDR0_SRST_UART0 0x08000000 | 2808 | #define SDR0_SRST_UART0 0x08000000 |
2809 | #define SDR0_SRST_UART1 0x04000000 | 2809 | #define SDR0_SRST_UART1 0x04000000 |
2810 | #define SDR0_SRST_IIC0 0x02000000 | 2810 | #define SDR0_SRST_IIC0 0x02000000 |
2811 | #define SDR0_SRST_IIC1 0x01000000 | 2811 | #define SDR0_SRST_IIC1 0x01000000 |
2812 | #define SDR0_SRST_GPIO 0x00800000 | 2812 | #define SDR0_SRST_GPIO 0x00800000 |
2813 | #define SDR0_SRST_GPT 0x00400000 | 2813 | #define SDR0_SRST_GPT 0x00400000 |
2814 | #define SDR0_SRST_DMC 0x00200000 | 2814 | #define SDR0_SRST_DMC 0x00200000 |
2815 | #define SDR0_SRST_PCI 0x00100000 | 2815 | #define SDR0_SRST_PCI 0x00100000 |
2816 | #define SDR0_SRST_EMAC0 0x00080000 | 2816 | #define SDR0_SRST_EMAC0 0x00080000 |
2817 | #define SDR0_SRST_EMAC1 0x00040000 | 2817 | #define SDR0_SRST_EMAC1 0x00040000 |
2818 | #define SDR0_SRST_CPM 0x00020000 | 2818 | #define SDR0_SRST_CPM 0x00020000 |
2819 | #define SDR0_SRST_IMU 0x00010000 | 2819 | #define SDR0_SRST_IMU 0x00010000 |
2820 | #define SDR0_SRST_UIC01 0x00008000 | 2820 | #define SDR0_SRST_UIC01 0x00008000 |
2821 | #define SDR0_SRST_UICB2 0x00004000 | 2821 | #define SDR0_SRST_UICB2 0x00004000 |
2822 | #define SDR0_SRST_SRAM 0x00002000 | 2822 | #define SDR0_SRST_SRAM 0x00002000 |
2823 | #define SDR0_SRST_EBM 0x00001000 | 2823 | #define SDR0_SRST_EBM 0x00001000 |
2824 | #define SDR0_SRST_BGI 0x00000800 | 2824 | #define SDR0_SRST_BGI 0x00000800 |
2825 | #define SDR0_SRST_DMA 0x00000400 | 2825 | #define SDR0_SRST_DMA 0x00000400 |
2826 | #define SDR0_SRST_DMAC 0x00000200 | 2826 | #define SDR0_SRST_DMAC 0x00000200 |
2827 | #define SDR0_SRST_MAL 0x00000100 | 2827 | #define SDR0_SRST_MAL 0x00000100 |
2828 | #define SDR0_SRST_ZMII 0x00000080 | 2828 | #define SDR0_SRST_ZMII 0x00000080 |
2829 | #define SDR0_SRST_GPTR 0x00000040 | 2829 | #define SDR0_SRST_GPTR 0x00000040 |
2830 | #define SDR0_SRST_PPM 0x00000020 | 2830 | #define SDR0_SRST_PPM 0x00000020 |
2831 | #define SDR0_SRST_EMAC2 0x00000010 | 2831 | #define SDR0_SRST_EMAC2 0x00000010 |
2832 | #define SDR0_SRST_EMAC3 0x00000008 | 2832 | #define SDR0_SRST_EMAC3 0x00000008 |
2833 | #define SDR0_SRST_RGMII 0x00000001 | 2833 | #define SDR0_SRST_RGMII 0x00000001 |
2834 | 2834 | ||
2835 | #endif | 2835 | #endif |
2836 | 2836 | ||
2837 | /*-----------------------------------------------------------------------------+ | 2837 | /*-----------------------------------------------------------------------------+ |
2838 | | Clocking | 2838 | | Clocking |
2839 | +-----------------------------------------------------------------------------*/ | 2839 | +-----------------------------------------------------------------------------*/ |
2840 | #if !defined (CONFIG_440GX) && \ | 2840 | #if !defined (CONFIG_440GX) && \ |
2841 | !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ | 2841 | !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ |
2842 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | 2842 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ |
2843 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) | 2843 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
2844 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ | 2844 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ |
2845 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ | 2845 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ |
2846 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ | 2846 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ |
2847 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ | 2847 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ |
2848 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ | 2848 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ |
2849 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ | 2849 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ |
2850 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ | 2850 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ |
2851 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ | 2851 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ |
2852 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ | 2852 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ |
2853 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ | 2853 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ |
2854 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ | 2854 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ |
2855 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | 2855 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ |
2856 | 2856 | ||
2857 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ | 2857 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
2858 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | 2858 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ |
2859 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | 2859 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ |
2860 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | 2860 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ |
2861 | #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ | 2861 | #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ |
2862 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ | 2862 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ |
2863 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | 2863 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ |
2864 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ | 2864 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ |
2865 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ | 2865 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ |
2866 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | 2866 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ |
2867 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | 2867 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ |
2868 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | 2868 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ |
2869 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | 2869 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ |
2870 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | 2870 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ |
2871 | 2871 | ||
2872 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ | 2872 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ |
2873 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ | 2873 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ |
2874 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | 2874 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ |
2875 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | 2875 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ |
2876 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | 2876 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ |
2877 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | 2877 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ |
2878 | 2878 | ||
2879 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | 2879 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ |
2880 | #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ | 2880 | #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ |
2881 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ | 2881 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ |
2882 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | 2882 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ |
2883 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | 2883 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ |
2884 | 2884 | ||
2885 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ | 2885 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
2886 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | 2886 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ |
2887 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | 2887 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ |
2888 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | 2888 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ |
2889 | 2889 | ||
2890 | /* Strap 1 Register */ | 2890 | /* Strap 1 Register */ |
2891 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | 2891 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ |
2892 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | 2892 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
2893 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | 2893 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ |
2894 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | 2894 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ |
2895 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ | 2895 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ |
2896 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ | 2896 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ |
2897 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | 2897 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ |
2898 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | 2898 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ |
2899 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | 2899 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ |
2900 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | 2900 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ |
2901 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | 2901 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ |
2902 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | 2902 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ |
2903 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | 2903 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ |
2904 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | 2904 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ |
2905 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | 2905 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ |
2906 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | 2906 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ |
2907 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | 2907 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ |
2908 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | 2908 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ |
2909 | #endif /* CONFIG_440GX */ | 2909 | #endif /* CONFIG_440GX */ |
2910 | 2910 | ||
2911 | #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) | 2911 | #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) |
2912 | /*--------------------------------------*/ | 2912 | /*--------------------------------------*/ |
2913 | #define CPR0_PLLC 0x40 | 2913 | #define CPR0_PLLC 0x40 |
2914 | #define CPR0_PLLC_RST_MASK 0x80000000 | 2914 | #define CPR0_PLLC_RST_MASK 0x80000000 |
2915 | #define CPR0_PLLC_RST_PLLLOCKED 0x00000000 | 2915 | #define CPR0_PLLC_RST_PLLLOCKED 0x00000000 |
2916 | #define CPR0_PLLC_RST_PLLRESET 0x80000000 | 2916 | #define CPR0_PLLC_RST_PLLRESET 0x80000000 |
2917 | #define CPR0_PLLC_ENG_MASK 0x40000000 | 2917 | #define CPR0_PLLC_ENG_MASK 0x40000000 |
2918 | #define CPR0_PLLC_ENG_DISABLE 0x00000000 | 2918 | #define CPR0_PLLC_ENG_DISABLE 0x00000000 |
2919 | #define CPR0_PLLC_ENG_ENABLE 0x40000000 | 2919 | #define CPR0_PLLC_ENG_ENABLE 0x40000000 |
2920 | #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | 2920 | #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) |
2921 | #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | 2921 | #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) |
2922 | #define CPR0_PLLC_SRC_MASK 0x20000000 | 2922 | #define CPR0_PLLC_SRC_MASK 0x20000000 |
2923 | #define CPR0_PLLC_SRC_PLLOUTA 0x00000000 | 2923 | #define CPR0_PLLC_SRC_PLLOUTA 0x00000000 |
2924 | #define CPR0_PLLC_SRC_PLLOUTB 0x20000000 | 2924 | #define CPR0_PLLC_SRC_PLLOUTB 0x20000000 |
2925 | #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | 2925 | #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) |
2926 | #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | 2926 | #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) |
2927 | #define CPR0_PLLC_SEL_MASK 0x07000000 | 2927 | #define CPR0_PLLC_SEL_MASK 0x07000000 |
2928 | #define CPR0_PLLC_SEL_PLL 0x00000000 | 2928 | #define CPR0_PLLC_SEL_PLL 0x00000000 |
2929 | #define CPR0_PLLC_SEL_CPU 0x01000000 | 2929 | #define CPR0_PLLC_SEL_CPU 0x01000000 |
2930 | #define CPR0_PLLC_SEL_PER 0x05000000 | 2930 | #define CPR0_PLLC_SEL_PER 0x05000000 |
2931 | #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 2931 | #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
2932 | #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) | 2932 | #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) |
2933 | #define CPR0_PLLC_TUNE_MASK 0x000003FF | 2933 | #define CPR0_PLLC_TUNE_MASK 0x000003FF |
2934 | #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) | 2934 | #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) |
2935 | #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) | 2935 | #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) |
2936 | /*--------------------------------------*/ | 2936 | /*--------------------------------------*/ |
2937 | #define CPR0_PLLD 0x60 | 2937 | #define CPR0_PLLD 0x60 |
2938 | #define CPR0_PLLD_FBDV_MASK 0x1F000000 | 2938 | #define CPR0_PLLD_FBDV_MASK 0x1F000000 |
2939 | #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) | 2939 | #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) |
2940 | #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) | 2940 | #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) |
2941 | #define CPR0_PLLD_FWDVA_MASK 0x000F0000 | 2941 | #define CPR0_PLLD_FWDVA_MASK 0x000F0000 |
2942 | #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) | 2942 | #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) |
2943 | #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) | 2943 | #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) |
2944 | #define CPR0_PLLD_FWDVB_MASK 0x00000700 | 2944 | #define CPR0_PLLD_FWDVB_MASK 0x00000700 |
2945 | #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) | 2945 | #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) |
2946 | #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) | 2946 | #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) |
2947 | #define CPR0_PLLD_LFBDV_MASK 0x0000003F | 2947 | #define CPR0_PLLD_LFBDV_MASK 0x0000003F |
2948 | #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) | 2948 | #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) |
2949 | #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) | 2949 | #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) |
2950 | /*--------------------------------------*/ | 2950 | /*--------------------------------------*/ |
2951 | #define CPR0_PRIMAD 0x80 | 2951 | #define CPR0_PRIMAD 0x80 |
2952 | #define CPR0_PRIMAD_PRADV0_MASK 0x07000000 | 2952 | #define CPR0_PRIMAD_PRADV0_MASK 0x07000000 |
2953 | #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 2953 | #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
2954 | #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) | 2954 | #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) |
2955 | /*--------------------------------------*/ | 2955 | /*--------------------------------------*/ |
2956 | #define CPR0_PRIMBD 0xA0 | 2956 | #define CPR0_PRIMBD 0xA0 |
2957 | #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 | 2957 | #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 |
2958 | #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 2958 | #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
2959 | #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) | 2959 | #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) |
2960 | /*--------------------------------------*/ | 2960 | /*--------------------------------------*/ |
2961 | #if 0 | 2961 | #if 0 |
2962 | #define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */ | 2962 | #define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */ |
2963 | #define CPR0_CPM0_FR 0xB1 /* CPM Force Register */ | 2963 | #define CPR0_CPM0_FR 0xB1 /* CPM Force Register */ |
2964 | #define CPR0_CPM0_SR 0xB2 /* CPM Status Register */ | 2964 | #define CPR0_CPM0_SR 0xB2 /* CPM Status Register */ |
2965 | #define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */ | 2965 | #define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */ |
2966 | #define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */ | 2966 | #define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */ |
2967 | #define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */ | 2967 | #define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */ |
2968 | #define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */ | 2968 | #define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */ |
2969 | #define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */ | 2969 | #define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */ |
2970 | #define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */ | 2970 | #define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */ |
2971 | #define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */ | 2971 | #define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */ |
2972 | #define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */ | 2972 | #define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */ |
2973 | #define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */ | 2973 | #define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */ |
2974 | #define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */ | 2974 | #define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */ |
2975 | #define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */ | 2975 | #define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */ |
2976 | #define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ | 2976 | #define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ |
2977 | #define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ | 2977 | #define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ |
2978 | #define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */ | 2978 | #define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */ |
2979 | #define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */ | 2979 | #define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */ |
2980 | #define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */ | 2980 | #define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */ |
2981 | #define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */ | 2981 | #define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */ |
2982 | #define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */ | 2982 | #define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */ |
2983 | #define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */ | 2983 | #define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */ |
2984 | #define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */ | 2984 | #define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */ |
2985 | #define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */ | 2985 | #define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */ |
2986 | #define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */ | 2986 | #define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */ |
2987 | #define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */ | 2987 | #define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */ |
2988 | #define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */ | 2988 | #define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */ |
2989 | #define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */ | 2989 | #define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */ |
2990 | #define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */ | 2990 | #define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */ |
2991 | #define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */ | 2991 | #define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */ |
2992 | #define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */ | 2992 | #define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */ |
2993 | #define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */ | 2993 | #define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */ |
2994 | #define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */ | 2994 | #define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */ |
2995 | #define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */ | 2995 | #define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */ |
2996 | #endif | 2996 | #endif |
2997 | /*--------------------------------------*/ | 2997 | /*--------------------------------------*/ |
2998 | #define CPR0_OPBD 0xC0 | 2998 | #define CPR0_OPBD 0xC0 |
2999 | #define CPR0_OPBD_OPBDV0_MASK 0x03000000 | 2999 | #define CPR0_OPBD_OPBDV0_MASK 0x03000000 |
3000 | #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 3000 | #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
3001 | #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 3001 | #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
3002 | /*--------------------------------------*/ | 3002 | /*--------------------------------------*/ |
3003 | #define CPR0_PERD 0xE0 | 3003 | #define CPR0_PERD 0xE0 |
3004 | #define CPR0_PERD_PERDV0_MASK 0x07000000 | 3004 | #define CPR0_PERD_PERDV0_MASK 0x07000000 |
3005 | #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) | 3005 | #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) |
3006 | #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) | 3006 | #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) |
3007 | /*--------------------------------------*/ | 3007 | /*--------------------------------------*/ |
3008 | #define CPR0_MALD 0x100 | 3008 | #define CPR0_MALD 0x100 |
3009 | #define CPR0_MALD_MALDV0_MASK 0x03000000 | 3009 | #define CPR0_MALD_MALDV0_MASK 0x03000000 |
3010 | #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 3010 | #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
3011 | #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 3011 | #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
3012 | /*--------------------------------------*/ | 3012 | /*--------------------------------------*/ |
3013 | #define CPR0_SPCID 0x120 | 3013 | #define CPR0_SPCID 0x120 |
3014 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 | 3014 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 |
3015 | #define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | 3015 | #define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) |
3016 | #define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) | 3016 | #define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) |
3017 | /*--------------------------------------*/ | 3017 | /*--------------------------------------*/ |
3018 | #define CPR0_ICFG 0x140 | 3018 | #define CPR0_ICFG 0x140 |
3019 | #define CPR0_ICFG_RLI_MASK 0x80000000 | 3019 | #define CPR0_ICFG_RLI_MASK 0x80000000 |
3020 | #define CPR0_ICFG_RLI_RESETCPR 0x00000000 | 3020 | #define CPR0_ICFG_RLI_RESETCPR 0x00000000 |
3021 | #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 | 3021 | #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 |
3022 | #define CPR0_ICFG_ICS_MASK 0x00000007 | 3022 | #define CPR0_ICFG_ICS_MASK 0x00000007 |
3023 | #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */ | 3023 | #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */ |
3024 | 3024 | ||
3025 | /*----------------------------------------------------------------------------- | 3025 | /*----------------------------------------------------------------------------- |
3026 | | IIC Register Offsets | 3026 | | IIC Register Offsets |
3027 | '----------------------------------------------------------------------------*/ | 3027 | '----------------------------------------------------------------------------*/ |
3028 | #define IICMDBUF 0x00 | 3028 | #define IICMDBUF 0x00 |
3029 | #define IICSDBUF 0x02 | 3029 | #define IICSDBUF 0x02 |
3030 | #define IICLMADR 0x04 | 3030 | #define IICLMADR 0x04 |
3031 | #define IICHMADR 0x05 | 3031 | #define IICHMADR 0x05 |
3032 | #define IICCNTL 0x06 | 3032 | #define IICCNTL 0x06 |
3033 | #define IICMDCNTL 0x07 | 3033 | #define IICMDCNTL 0x07 |
3034 | #define IICSTS 0x08 | 3034 | #define IICSTS 0x08 |
3035 | #define IICEXTSTS 0x09 | 3035 | #define IICEXTSTS 0x09 |
3036 | #define IICLSADR 0x0A | 3036 | #define IICLSADR 0x0A |
3037 | #define IICHSADR 0x0B | 3037 | #define IICHSADR 0x0B |
3038 | #define IICCLKDIV 0x0C | 3038 | #define IICCLKDIV 0x0C |
3039 | #define IICINTRMSK 0x0D | 3039 | #define IICINTRMSK 0x0D |
3040 | #define IICXFRCNT 0x0E | 3040 | #define IICXFRCNT 0x0E |
3041 | #define IICXTCNTLSS 0x0F | 3041 | #define IICXTCNTLSS 0x0F |
3042 | #define IICDIRECTCNTL 0x10 | 3042 | #define IICDIRECTCNTL 0x10 |
3043 | 3043 | ||
3044 | /*----------------------------------------------------------------------------- | 3044 | /*----------------------------------------------------------------------------- |
3045 | | UART Register Offsets | 3045 | | UART Register Offsets |
3046 | '----------------------------------------------------------------------------*/ | 3046 | '----------------------------------------------------------------------------*/ |
3047 | #define DATA_REG 0x00 | 3047 | #define DATA_REG 0x00 |
3048 | #define DL_LSB 0x00 | 3048 | #define DL_LSB 0x00 |
3049 | #define DL_MSB 0x01 | 3049 | #define DL_MSB 0x01 |
3050 | #define INT_ENABLE 0x01 | 3050 | #define INT_ENABLE 0x01 |
3051 | #define FIFO_CONTROL 0x02 | 3051 | #define FIFO_CONTROL 0x02 |
3052 | #define LINE_CONTROL 0x03 | 3052 | #define LINE_CONTROL 0x03 |
3053 | #define MODEM_CONTROL 0x04 | 3053 | #define MODEM_CONTROL 0x04 |
3054 | #define LINE_STATUS 0x05 | 3054 | #define LINE_STATUS 0x05 |
3055 | #define MODEM_STATUS 0x06 | 3055 | #define MODEM_STATUS 0x06 |
3056 | #define SCRATCH 0x07 | 3056 | #define SCRATCH 0x07 |
3057 | 3057 | ||
3058 | /*----------------------------------------------------------------------------- | 3058 | /*----------------------------------------------------------------------------- |
3059 | | PCI Internal Registers et. al. (accessed via plb) | 3059 | | PCI Internal Registers et. al. (accessed via plb) |
3060 | +----------------------------------------------------------------------------*/ | 3060 | +----------------------------------------------------------------------------*/ |
3061 | #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) | 3061 | #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) |
3062 | #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) | 3062 | #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) |
3063 | #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) | 3063 | #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) |
3064 | #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) | 3064 | #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) |
3065 | 3065 | ||
3066 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | 3066 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
3067 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 3067 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
3068 | 3068 | ||
3069 | /* PCI Local Configuration Registers | 3069 | /* PCI Local Configuration Registers |
3070 | --------------------------------- */ | 3070 | --------------------------------- */ |
3071 | #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ | 3071 | #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ |
3072 | 3072 | ||
3073 | /* PCI Master Local Configuration Registers */ | 3073 | /* PCI Master Local Configuration Registers */ |
3074 | #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ | 3074 | #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ |
3075 | #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | 3075 | #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ |
3076 | #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | 3076 | #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ |
3077 | #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | 3077 | #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ |
3078 | #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | 3078 | #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ |
3079 | #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | 3079 | #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ |
3080 | #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | 3080 | #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ |
3081 | #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | 3081 | #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ |
3082 | #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | 3082 | #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ |
3083 | #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | 3083 | #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ |
3084 | #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | 3084 | #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ |
3085 | #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | 3085 | #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ |
3086 | 3086 | ||
3087 | /* PCI Target Local Configuration Registers */ | 3087 | /* PCI Target Local Configuration Registers */ |
3088 | #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ | 3088 | #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ |
3089 | #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | 3089 | #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ |
3090 | #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ | 3090 | #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ |
3091 | #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | 3091 | #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ |
3092 | 3092 | ||
3093 | #else | 3093 | #else |
3094 | 3094 | ||
3095 | #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) | 3095 | #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) |
3096 | #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) | 3096 | #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) |
3097 | #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) | 3097 | #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) |
3098 | #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) | 3098 | #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) |
3099 | #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) | 3099 | #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) |
3100 | #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) | 3100 | #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) |
3101 | #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) | 3101 | #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) |
3102 | #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) | 3102 | #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) |
3103 | #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) | 3103 | #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) |
3104 | #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) | 3104 | #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) |
3105 | #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) | 3105 | #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) |
3106 | #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) | 3106 | #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) |
3107 | #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) | 3107 | #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) |
3108 | #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) | 3108 | #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) |
3109 | #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) | 3109 | #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) |
3110 | #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) | 3110 | #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) |
3111 | #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) | 3111 | #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) |
3112 | #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) | 3112 | #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) |
3113 | #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) | 3113 | #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) |
3114 | #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) | 3114 | #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) |
3115 | #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) | 3115 | #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) |
3116 | #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) | 3116 | #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) |
3117 | #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) | 3117 | #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) |
3118 | #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) | 3118 | #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) |
3119 | #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) | 3119 | #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) |
3120 | #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) | 3120 | #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) |
3121 | #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) | 3121 | #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) |
3122 | #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) | 3122 | #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) |
3123 | 3123 | ||
3124 | #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) | 3124 | #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) |
3125 | #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) | 3125 | #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) |
3126 | 3126 | ||
3127 | #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) | 3127 | #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) |
3128 | #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) | 3128 | #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) |
3129 | #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) | 3129 | #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) |
3130 | #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) | 3130 | #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) |
3131 | #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) | 3131 | #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) |
3132 | #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) | 3132 | #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) |
3133 | #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) | 3133 | #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) |
3134 | #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) | 3134 | #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) |
3135 | #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) | 3135 | #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) |
3136 | #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) | 3136 | #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) |
3137 | #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) | 3137 | #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) |
3138 | 3138 | ||
3139 | #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) | 3139 | #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) |
3140 | #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) | 3140 | #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) |
3141 | #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) | 3141 | #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) |
3142 | #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) | 3142 | #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) |
3143 | #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) | 3143 | #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) |
3144 | #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) | 3144 | #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) |
3145 | #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) | 3145 | #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) |
3146 | #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) | 3146 | #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) |
3147 | #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) | 3147 | #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) |
3148 | 3148 | ||
3149 | #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) | 3149 | #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) |
3150 | 3150 | ||
3151 | #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ | 3151 | #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ |
3152 | 3152 | ||
3153 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 3153 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
3154 | 3154 | ||
3155 | /* USB2.0 Device */ | 3155 | /* USB2.0 Device */ |
3156 | #define USB2D0_BASE CFG_USB2D0_BASE | 3156 | #define USB2D0_BASE CFG_USB2D0_BASE |
3157 | 3157 | ||
3158 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) | 3158 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) |
3159 | 3159 | ||
3160 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */ | 3160 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */ |
3161 | #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */ | 3161 | #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */ |
3162 | #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */ | 3162 | #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */ |
3163 | #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */ | 3163 | #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */ |
3164 | #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */ | 3164 | #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */ |
3165 | #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */ | 3165 | #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */ |
3166 | #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */ | 3166 | #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */ |
3167 | #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */ | 3167 | #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */ |
3168 | #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */ | 3168 | #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */ |
3169 | #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */ | 3169 | #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */ |
3170 | #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ | 3170 | #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ |
3171 | #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */ | 3171 | #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */ |
3172 | #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */ | 3172 | #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */ |
3173 | #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */ | 3173 | #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */ |
3174 | #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */ | 3174 | #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */ |
3175 | #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */ | 3175 | #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */ |
3176 | #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ | 3176 | #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ |
3177 | #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ | 3177 | #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ |
3178 | #endif | 3178 | #endif |
3179 | 3179 | ||
3180 | /****************************************************************************** | 3180 | /****************************************************************************** |
3181 | * GPIO macro register defines | 3181 | * GPIO macro register defines |
3182 | ******************************************************************************/ | 3182 | ******************************************************************************/ |
3183 | #define GPIO0 0 | 3183 | #define GPIO0 0 |
3184 | #define GPIO1 1 | 3184 | #define GPIO1 1 |
3185 | 3185 | ||
3186 | #if defined(CONFIG_440GP) | 3186 | #if defined(CONFIG_440GP) |
3187 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) | 3187 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) |
3188 | 3188 | ||
3189 | #define GPIO0_OR (GPIO0_BASE+0x0) | 3189 | #define GPIO0_OR (GPIO0_BASE+0x0) |
3190 | #define GPIO0_TCR (GPIO0_BASE+0x4) | 3190 | #define GPIO0_TCR (GPIO0_BASE+0x4) |
3191 | #define GPIO0_ODR (GPIO0_BASE+0x18) | 3191 | #define GPIO0_ODR (GPIO0_BASE+0x18) |
3192 | #define GPIO0_IR (GPIO0_BASE+0x1C) | 3192 | #define GPIO0_IR (GPIO0_BASE+0x1C) |
3193 | #endif /* CONFIG_440GP */ | 3193 | #endif /* CONFIG_440GP */ |
3194 | 3194 | ||
3195 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | 3195 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
3196 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | 3196 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
3197 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) | 3197 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) |
3198 | #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) | 3198 | #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) |
3199 | 3199 | ||
3200 | /* Offsets */ | 3200 | /* Offsets */ |
3201 | #define GPIOx_OR 0x00 /* GPIO Output Register */ | 3201 | #define GPIOx_OR 0x00 /* GPIO Output Register */ |
3202 | #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ | 3202 | #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ |
3203 | #define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ | 3203 | #define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ |
3204 | #define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ | 3204 | #define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ |
3205 | #define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ | 3205 | #define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ |
3206 | #define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ | 3206 | #define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ |
3207 | #define GPIOx_ODR 0x18 /* GPIO Open drain Register */ | 3207 | #define GPIOx_ODR 0x18 /* GPIO Open drain Register */ |
3208 | #define GPIOx_IR 0x1C /* GPIO Input Register */ | 3208 | #define GPIOx_IR 0x1C /* GPIO Input Register */ |
3209 | #define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ | 3209 | #define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ |
3210 | #define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ | 3210 | #define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ |
3211 | #define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ | 3211 | #define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ |
3212 | #define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ | 3212 | #define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ |
3213 | #define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ | 3213 | #define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ |
3214 | #define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ | 3214 | #define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ |
3215 | #define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ | 3215 | #define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ |
3216 | #define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ | 3216 | #define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ |
3217 | #define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ | 3217 | #define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ |
3218 | 3218 | ||
3219 | #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ | 3219 | #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ |
3220 | #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ | 3220 | #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ |
3221 | #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ | 3221 | #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ |
3222 | #define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ | 3222 | #define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ |
3223 | #define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ | 3223 | #define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ |
3224 | 3224 | ||
3225 | #define GPIO0_OR (GPIO0_BASE+0x0) | 3225 | #define GPIO0_OR (GPIO0_BASE+0x0) |
3226 | #define GPIO0_TCR (GPIO0_BASE+0x4) | 3226 | #define GPIO0_TCR (GPIO0_BASE+0x4) |
3227 | #define GPIO0_OSRL (GPIO0_BASE+0x8) | 3227 | #define GPIO0_OSRL (GPIO0_BASE+0x8) |
3228 | #define GPIO0_OSRH (GPIO0_BASE+0xC) | 3228 | #define GPIO0_OSRH (GPIO0_BASE+0xC) |
3229 | #define GPIO0_TSRL (GPIO0_BASE+0x10) | 3229 | #define GPIO0_TSRL (GPIO0_BASE+0x10) |
3230 | #define GPIO0_TSRH (GPIO0_BASE+0x14) | 3230 | #define GPIO0_TSRH (GPIO0_BASE+0x14) |
3231 | #define GPIO0_ODR (GPIO0_BASE+0x18) | 3231 | #define GPIO0_ODR (GPIO0_BASE+0x18) |
3232 | #define GPIO0_IR (GPIO0_BASE+0x1C) | 3232 | #define GPIO0_IR (GPIO0_BASE+0x1C) |
3233 | #define GPIO0_RR1 (GPIO0_BASE+0x20) | 3233 | #define GPIO0_RR1 (GPIO0_BASE+0x20) |
3234 | #define GPIO0_RR2 (GPIO0_BASE+0x24) | 3234 | #define GPIO0_RR2 (GPIO0_BASE+0x24) |
3235 | #define GPIO0_RR3 (GPIO0_BASE+0x28) | 3235 | #define GPIO0_RR3 (GPIO0_BASE+0x28) |
3236 | #define GPIO0_ISR1L (GPIO0_BASE+0x30) | 3236 | #define GPIO0_ISR1L (GPIO0_BASE+0x30) |
3237 | #define GPIO0_ISR1H (GPIO0_BASE+0x34) | 3237 | #define GPIO0_ISR1H (GPIO0_BASE+0x34) |
3238 | #define GPIO0_ISR2L (GPIO0_BASE+0x38) | 3238 | #define GPIO0_ISR2L (GPIO0_BASE+0x38) |
3239 | #define GPIO0_ISR2H (GPIO0_BASE+0x3C) | 3239 | #define GPIO0_ISR2H (GPIO0_BASE+0x3C) |
3240 | #define GPIO0_ISR3L (GPIO0_BASE+0x40) | 3240 | #define GPIO0_ISR3L (GPIO0_BASE+0x40) |
3241 | #define GPIO0_ISR3H (GPIO0_BASE+0x44) | 3241 | #define GPIO0_ISR3H (GPIO0_BASE+0x44) |
3242 | 3242 | ||
3243 | #define GPIO1_OR (GPIO1_BASE+0x0) | 3243 | #define GPIO1_OR (GPIO1_BASE+0x0) |
3244 | #define GPIO1_TCR (GPIO1_BASE+0x4) | 3244 | #define GPIO1_TCR (GPIO1_BASE+0x4) |
3245 | #define GPIO1_OSRL (GPIO1_BASE+0x8) | 3245 | #define GPIO1_OSRL (GPIO1_BASE+0x8) |
3246 | #define GPIO1_OSRH (GPIO1_BASE+0xC) | 3246 | #define GPIO1_OSRH (GPIO1_BASE+0xC) |
3247 | #define GPIO1_TSRL (GPIO1_BASE+0x10) | 3247 | #define GPIO1_TSRL (GPIO1_BASE+0x10) |
3248 | #define GPIO1_TSRH (GPIO1_BASE+0x14) | 3248 | #define GPIO1_TSRH (GPIO1_BASE+0x14) |
3249 | #define GPIO1_ODR (GPIO1_BASE+0x18) | 3249 | #define GPIO1_ODR (GPIO1_BASE+0x18) |
3250 | #define GPIO1_IR (GPIO1_BASE+0x1C) | 3250 | #define GPIO1_IR (GPIO1_BASE+0x1C) |
3251 | #define GPIO1_RR1 (GPIO1_BASE+0x20) | 3251 | #define GPIO1_RR1 (GPIO1_BASE+0x20) |
3252 | #define GPIO1_RR2 (GPIO1_BASE+0x24) | 3252 | #define GPIO1_RR2 (GPIO1_BASE+0x24) |
3253 | #define GPIO1_RR3 (GPIO1_BASE+0x28) | 3253 | #define GPIO1_RR3 (GPIO1_BASE+0x28) |
3254 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) | 3254 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) |
3255 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) | 3255 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) |
3256 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) | 3256 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) |
3257 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) | 3257 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) |
3258 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) | 3258 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) |
3259 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) | 3259 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) |
3260 | #endif | 3260 | #endif |
3261 | 3261 | ||
3262 | #define GPIO_GROUP_MAX 2 | 3262 | #define GPIO_GROUP_MAX 2 |
3263 | #define GPIO_MAX 32 | 3263 | #define GPIO_MAX 32 |
3264 | #define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ | 3264 | #define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ |
3265 | #define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ | 3265 | #define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ |
3266 | #define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ | 3266 | #define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ |
3267 | #define GPIO_MASK 0xC0000000 /* GPIO_MASK */ | 3267 | #define GPIO_MASK 0xC0000000 /* GPIO_MASK */ |
3268 | #define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ | 3268 | #define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ |
3269 | /* For the other GPIO number, you must shift */ | 3269 | /* For the other GPIO number, you must shift */ |
3270 | 3270 | ||
3271 | #ifndef __ASSEMBLY__ | 3271 | #ifndef __ASSEMBLY__ |
3272 | 3272 | ||
3273 | typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; | 3273 | typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; |
3274 | typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; | 3274 | typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; |
3275 | 3275 | ||
3276 | typedef struct { unsigned long add; /* gpio core base address */ | 3276 | typedef struct { unsigned long add; /* gpio core base address */ |
3277 | gpio_driver_t in_out; /* Driver Setting */ | 3277 | gpio_driver_t in_out; /* Driver Setting */ |
3278 | gpio_select_t alt_nb; /* Selected Alternate */ | 3278 | gpio_select_t alt_nb; /* Selected Alternate */ |
3279 | } gpio_param_s; | 3279 | } gpio_param_s; |
3280 | 3280 | ||
3281 | 3281 | ||
3282 | #endif /* __ASSEMBLY__ */ | 3282 | #endif /* __ASSEMBLY__ */ |
3283 | 3283 | ||
3284 | /* | 3284 | /* |
3285 | * Macros for accessing the indirect EBC registers | 3285 | * Macros for accessing the indirect EBC registers |
3286 | */ | 3286 | */ |
3287 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) | 3287 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) |
3288 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) | 3288 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) |
3289 | 3289 | ||
3290 | /* | 3290 | /* |
3291 | * Macros for accessing the indirect SDRAM controller registers | 3291 | * Macros for accessing the indirect SDRAM controller registers |
3292 | */ | 3292 | */ |
3293 | #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) | 3293 | #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
3294 | #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) | 3294 | #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) |
3295 | 3295 | ||
3296 | /* | 3296 | /* |
3297 | * Macros for accessing the indirect clocking controller registers | 3297 | * Macros for accessing the indirect clocking controller registers |
3298 | */ | 3298 | */ |
3299 | #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) | 3299 | #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) |
3300 | #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) | 3300 | #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) |
3301 | 3301 | ||
3302 | /* | 3302 | /* |
3303 | * Macros for accessing the sdr controller registers | 3303 | * Macros for accessing the sdr controller registers |
3304 | */ | 3304 | */ |
3305 | #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) | 3305 | #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) |
3306 | #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) | 3306 | #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) |
3307 | 3307 | ||
3308 | 3308 | ||
3309 | #ifndef __ASSEMBLY__ | 3309 | #ifndef __ASSEMBLY__ |
3310 | 3310 | ||
3311 | typedef struct { | 3311 | typedef struct { |
3312 | unsigned long pllFwdDivA; | 3312 | unsigned long pllFwdDivA; |
3313 | unsigned long pllFwdDivB; | 3313 | unsigned long pllFwdDivB; |
3314 | unsigned long pllFbkDiv; | 3314 | unsigned long pllFbkDiv; |
3315 | unsigned long pllOpbDiv; | 3315 | unsigned long pllOpbDiv; |
3316 | unsigned long pllPciDiv; | 3316 | unsigned long pllPciDiv; |
3317 | unsigned long pllExtBusDiv; | 3317 | unsigned long pllExtBusDiv; |
3318 | unsigned long freqVCOMhz; /* in MHz */ | 3318 | unsigned long freqVCOMhz; /* in MHz */ |
3319 | unsigned long freqProcessor; | 3319 | unsigned long freqProcessor; |
3320 | unsigned long freqTmrClk; | 3320 | unsigned long freqTmrClk; |
3321 | unsigned long freqPLB; | 3321 | unsigned long freqPLB; |
3322 | unsigned long freqOPB; | 3322 | unsigned long freqOPB; |
3323 | unsigned long freqEPB; | 3323 | unsigned long freqEPB; |
3324 | unsigned long freqPCI; | 3324 | unsigned long freqPCI; |
3325 | #ifdef CONFIG_440SPE | 3325 | #ifdef CONFIG_440SPE |
3326 | unsigned long freqDDR; | 3326 | unsigned long freqDDR; |
3327 | #endif | 3327 | #endif |
3328 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ | 3328 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ |
3329 | unsigned long pciClkSync; /* PCI clock is synchronous */ | 3329 | unsigned long pciClkSync; /* PCI clock is synchronous */ |
3330 | } PPC440_SYS_INFO; | 3330 | } PPC440_SYS_INFO; |
3331 | 3331 | ||
3332 | #endif /* _ASMLANGUAGE */ | 3332 | #endif /* _ASMLANGUAGE */ |
3333 | 3333 | ||
3334 | #define RESET_VECTOR 0xfffffffc | 3334 | #define RESET_VECTOR 0xfffffffc |
3335 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ | 3335 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ |
3336 | /* cache line aligned data. */ | 3336 | /* cache line aligned data. */ |
3337 | 3337 | ||
3338 | #endif /* __PPC440_H__ */ | 3338 | #endif /* __PPC440_H__ */ |
3339 | 3339 |