Commit 9444b8818f1de25dfa322cbe3a283c758a3d20e3
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CHANGELOG
| ... | ... | @@ -2,6 +2,9 @@ |
| 2 | 2 | Changes since U-Boot 1.1.4: |
| 3 | 3 | ====================================================================== |
| 4 | 4 | |
| 5 | +* Fix comments in include/ppc440.h | |
| 6 | + Patch by Martin Hicks, 16 Jun 2006 | |
| 7 | + | |
| 5 | 8 | * Update for CAM5200 board: |
| 6 | 9 | - Map in a additional chip selects CS4 and CS5. |
| 7 | 10 | - Modify the port configration, configure six UARTs and no PCI, |
include/ppc440.h
| ... | ... | @@ -1570,8 +1570,8 @@ |
| 1570 | 1570 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| 1571 | 1571 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ |
| 1572 | 1572 | #if defined(CONFIG_440GX) |
| 1573 | -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ | |
| 1574 | -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ | |
| 1573 | +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ | |
| 1574 | +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ | |
| 1575 | 1575 | #endif /* CONFIG_440GX */ |
| 1576 | 1576 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| 1577 | 1577 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ |