Commit 948b8bbd5fc4722ec10e0ffde29d31d982f6a6e4
Committed by
Tom Rini
Tom Rini
1 parent
84295f2a20
Exists in
v2017.01-smarct4x
and in
25 other branches
spi: ti_qspi: Fix baudrate divider calculation
Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Showing 1 changed file with 7 additions and 9 deletions Side-by-side Diff
drivers/spi/ti_qspi.c
| ... | ... | @@ -16,6 +16,7 @@ |
| 16 | 16 | #include <asm/omap_gpio.h> |
| 17 | 17 | #include <asm/omap_common.h> |
| 18 | 18 | #include <asm/ti-common/ti-edma3.h> |
| 19 | +#include <linux/kernel.h> | |
| 19 | 20 | |
| 20 | 21 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | 22 | |
| 22 | 23 | |
| 23 | 24 | |
| ... | ... | @@ -118,21 +119,18 @@ |
| 118 | 119 | if (!hz) |
| 119 | 120 | clk_div = 0; |
| 120 | 121 | else |
| 121 | - clk_div = (priv->fclk / hz) - 1; | |
| 122 | + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; | |
| 122 | 123 | |
| 124 | + /* truncate clk_div value to QSPI_CLK_DIV_MAX */ | |
| 125 | + if (clk_div > QSPI_CLK_DIV_MAX) | |
| 126 | + clk_div = QSPI_CLK_DIV_MAX; | |
| 127 | + | |
| 123 | 128 | debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); |
| 124 | 129 | |
| 125 | 130 | /* disable SCLK */ |
| 126 | 131 | writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, |
| 127 | 132 | &priv->base->clk_ctrl); |
| 128 | - | |
| 129 | - /* assign clk_div values */ | |
| 130 | - if (clk_div < 0) | |
| 131 | - clk_div = 0; | |
| 132 | - else if (clk_div > QSPI_CLK_DIV_MAX) | |
| 133 | - clk_div = QSPI_CLK_DIV_MAX; | |
| 134 | - | |
| 135 | - /* enable SCLK */ | |
| 133 | + /* enable SCLK and program the clk divider */ | |
| 136 | 134 | writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); |
| 137 | 135 | } |
| 138 | 136 |