powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support

Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support
Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Scott Wood
1 parent c97cd1ba48
Showing 5 changed files with 160 additions and 5 deletions Side-by-side Diff
README
board/freescale/p1_p2_rdb_pc/Makefile
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
board/freescale/p1_p2_rdb_pc/spl_minimal.c
board/freescale/p1_p2_rdb_pc/tlb.c
@@ -2653,6 +2653,10 @@
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
  
+		CONFIG_SPL_RELOC_TEXT_BASE
+		Address to relocate to.  If unspecified, this is equal to
+		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.
  
@@ -2661,6 +2665,11 @@
  
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
+
+		CONFIG_SPL_RELOC_STACK
+		Adress of the start of the stack SPL will use after
+		relocation.  If unspecified, this is equal to
+		CONFIG_SPL_STACK.
  
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.
@@ -24,10 +24,26 @@
  
 LIB    = $(obj)lib$(BOARD).o
  
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
+
+endif
  
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
@@ -177,7 +177,7 @@
 	 */
  
 	setbits_be32(&pgpio->gpdir, 0x02130000);
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 	/* init DDR3 reset signal */
 	setbits_be32(&pgpio->gpdir, 0x00200000);
 	setbits_be32(&pgpio->gpodr, 0x00200000);
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+void sdram_init(void)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
+
+	/* Set, but do not enable the memory */
+	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+	asm volatile("sync;isync");
+	udelay(500);
+
+	/* Let the controller go */
+	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifndef CONFIG_QE
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+#ifndef CONFIG_QE
+	/* init DDR3 reset signal */
+	__raw_writel(0x02000000, &pgpio->gpdir);
+	__raw_writel(0x00200000, &pgpio->gpodr);
+	__raw_writel(0x00000000, &pgpio->gpdat);
+	udelay(1000);
+	__raw_writel(0x00200000, &pgpio->gpdat);
+	udelay(1000);
+	__raw_writel(0x00000000, &pgpio->gpdir);
+#endif
+
+	/* Initialize the DDR3 */
+	sdram_init();
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
@@ -53,7 +53,7 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
  
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -85,7 +85,7 @@
 	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
+#endif /* not SPL */
  
 #ifdef CONFIG_SYS_NAND_BASE
 	/* *I*G - NAND */
@@ -94,7 +94,7 @@
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
  
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -108,7 +108,6 @@
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif
-
 };
  
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
...	...	@@ -2653,6 +2653,10 @@
2653	2653	CONFIG_SPL_TEXT_BASE
2654	2654	TEXT_BASE for linking the SPL binary.
2655	2655
	2656	+ CONFIG_SPL_RELOC_TEXT_BASE
	2657	+ Address to relocate to. If unspecified, this is equal to
	2658	+ CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
	2659	+
2656	2660	CONFIG_SPL_BSS_START_ADDR
2657	2661	Link address for the BSS within the SPL binary.
2658	2662
...	...	@@ -2661,6 +2665,11 @@
2661	2665
2662	2666	CONFIG_SPL_STACK
2663	2667	Adress of the start of the stack SPL will use
	2668	+
	2669	+ CONFIG_SPL_RELOC_STACK
	2670	+ Adress of the start of the stack SPL will use after
	2671	+ relocation. If unspecified, this is equal to
	2672	+ CONFIG_SPL_STACK.
2664	2673
2665	2674	CONFIG_SYS_SPL_MALLOC_START
2666	2675	Starting address of the malloc pool used in SPL.
...	...	@@ -24,10 +24,26 @@
24	24
25	25	LIB = $(obj)lib$(BOARD).o
26	26
	27	+MINIMAL=
	28	+
	29	+ifdef CONFIG_SPL_BUILD
	30	+ifdef CONFIG_SPL_INIT_MINIMAL
	31	+MINIMAL=y
	32	+endif
	33	+endif
	34	+
	35	+ifdef MINIMAL
	36	+
	37	+COBJS-y += spl_minimal.o tlb.o law.o
	38	+
	39	+else
	40	+
27	41	COBJS-y += $(BOARD).o
28	42	COBJS-y += ddr.o
29	43	COBJS-y += law.o
30	44	COBJS-y += tlb.o
	45	+
	46	+endif
31	47
32	48	SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
33	49	OBJS := $(addprefix $(obj),$(COBJS-y))
...	...	@@ -177,7 +177,7 @@
177	177	*/
178	178
179	179	setbits_be32(&pgpio->gpdir, 0x02130000);
180		-#ifndef CONFIG_SYS_RAMBOOT
	180	+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
181	181	/* init DDR3 reset signal */
182	182	setbits_be32(&pgpio->gpdir, 0x00200000);
183	183	setbits_be32(&pgpio->gpodr, 0x00200000);
	1	+/*
	2	+ * Copyright 2011 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License as
	6	+ * published by the Free Software Foundation; either version 2 of
	7	+ * the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ *
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ *
	20	+ */
	21	+
	22	+#include <common.h>
	23	+#include <ns16550.h>
	24	+#include <asm/io.h>
	25	+#include <nand.h>
	26	+#include <asm/fsl_law.h>
	27	+#include <asm/fsl_ddr_sdram.h>
	28	+#include <asm/global_data.h>
	29	+
	30	+DECLARE_GLOBAL_DATA_PTR;
	31	+
	32	+/*
	33	+ * Fixed sdram init -- doesn't use serial presence detect.
	34	+ */
	35	+void sdram_init(void)
	36	+{
	37	+ ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC85xx_DDR_ADDR;
	38	+
	39	+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
	40	+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
	41	+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
	42	+ __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
	43	+ __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
	44	+#endif
	45	+ __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
	46	+ __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
	47	+ __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
	48	+ __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
	49	+
	50	+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
	51	+ __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
	52	+ __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
	53	+
	54	+ __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
	55	+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
	56	+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
	57	+
	58	+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
	59	+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
	60	+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
	61	+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
	62	+
	63	+ /* Set, but do not enable the memory */
	64	+ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
	65	+
	66	+ asm volatile("sync;isync");
	67	+ udelay(500);
	68	+
	69	+ /* Let the controller go */
	70	+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) \| SDRAM_CFG_MEM_EN);
	71	+
	72	+ set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
	73	+}
	74	+
	75	+void board_init_f(ulong bootflag)
	76	+{
	77	+ u32 plat_ratio;
	78	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	79	+#ifndef CONFIG_QE
	80	+ ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	81	+#endif
	82	+
	83	+ /* initialize selected port with appropriate baud rate */
	84	+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
	85	+ plat_ratio >>= 1;
	86	+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
	87	+
	88	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	89	+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
	90	+
	91	+ puts("\nNAND boot... ");
	92	+
	93	+#ifndef CONFIG_QE
	94	+ /* init DDR3 reset signal */
	95	+ __raw_writel(0x02000000, &pgpio->gpdir);
	96	+ __raw_writel(0x00200000, &pgpio->gpodr);
	97	+ __raw_writel(0x00000000, &pgpio->gpdat);
	98	+ udelay(1000);
	99	+ __raw_writel(0x00200000, &pgpio->gpdat);
	100	+ udelay(1000);
	101	+ __raw_writel(0x00000000, &pgpio->gpdir);
	102	+#endif
	103	+
	104	+ /* Initialize the DDR3 */
	105	+ sdram_init();
	106	+
	107	+ /* copy code to RAM and jump to it - this should not return */
	108	+ /* NOTE - code has to be copied out of NAND buffer before
	109	+ * other blocks can be read.
	110	+ */
	111	+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
	112	+}
	113	+
	114	+void board_init_r(gd_t *gd, ulong dest_addr)
	115	+{
	116	+ nand_boot();
	117	+}
	118	+
	119	+void putc(char c)
	120	+{
	121	+ if (c == '\n')
	122	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
	123	+
	124	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
	125	+}
	126	+
	127	+void puts(const char *str)
	128	+{
	129	+ while (*str)
	130	+ putc(*str++);
	131	+}
...	...	@@ -53,7 +53,7 @@
53	53	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
54	54	0, 1, BOOKE_PAGESZ_1M, 1),
55	55
56		-#ifndef CONFIG_NAND_SPL
	56	+#ifndef CONFIG_SPL_BUILD
57	57	/* W*G - Flash/promjet, localbus */
58	58	/* This will be changed to IG* after relocation to RAM. */
59	59	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
...	...	@@ -85,7 +85,7 @@
85	85	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
86	86	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
87	87	0, 10, BOOKE_PAGESZ_64K, 1),
88		-#endif
	88	+#endif /* not SPL */
89	89
90	90	#ifdef CONFIG_SYS_NAND_BASE
91	91	/* IG - NAND */
...	...	@@ -94,7 +94,7 @@
94	94	0, 7, BOOKE_PAGESZ_1M, 1),
95	95	#endif
96	96
97		-#ifdef CONFIG_SYS_RAMBOOT
	97	+#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
98	98	/* IG - eSDHC/eSPI/NAND boot */
99	99	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
100	100	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
...	...	@@ -108,7 +108,6 @@
108	108	0, 9, BOOKE_PAGESZ_1G, 1),
109	109	#endif
110	110	#endif
111		-
112	111	};
113	112
114	113	int num_tlb_entries = ARRAY_SIZE(tlb_table);