mx6: Distinguish mx6dual from mx6quad

Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>

mx6: Distinguish mx6dual from mx6quad
Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam · Stefano Babic
1 parent 6a99f03d69
Showing 3 changed files with 14 additions and 3 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-imx/cpu.h
@@ -41,14 +41,19 @@
  
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
 			if (!cfg)
 				type = MXC_CPU_MX6SOLO;
 		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
 	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + 0x10);
@@ -61,6 +66,9 @@
 	u32 type = ((cpurev >> 12) & 0xff);
 	if (type == MXC_CPU_MX6SOLO)
 		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  
 	return cpurev;
 }
@@ -106,6 +106,8 @@
 	switch (imxtype) {
 	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
 	case MXC_CPU_MX6DL:
 		return "6DL";	/* Dual Lite version of the mx6 */
 	case MXC_CPU_MX6SOLO:
@@ -10,4 +10,5 @@
 #define MXC_CPU_MX6DL		0x61
 #define MXC_CPU_MX6SOLO		0x62
 #define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
...	...	@@ -41,14 +41,19 @@
41	41
42	42	if (type != MXC_CPU_MX6SL) {
43	43	reg = readl(&anatop->digprog);
	44	+ struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	45	+ u32 cfg = readl(&scu->config) & 3;
44	46	type = ((reg >> 16) & 0xff);
45	47	if (type == MXC_CPU_MX6DL) {
46		- struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
47		- u32 cfg = readl(&scu->config) & 3;
48		-
49	48	if (!cfg)
50	49	type = MXC_CPU_MX6SOLO;
51	50	}
	51	+
	52	+ if (type == MXC_CPU_MX6Q) {
	53	+ if (cfg == 1)
	54	+ type = MXC_CPU_MX6D;
	55	+ }
	56	+
52	57	}
53	58	reg &= 0xff; /* mx6 silicon revision */
54	59	return (type << 12) \| (reg + 0x10);
...	...	@@ -61,6 +66,9 @@
61	66	u32 type = ((cpurev >> 12) & 0xff);
62	67	if (type == MXC_CPU_MX6SOLO)
63	68	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	69	+
	70	+ if (type == MXC_CPU_MX6D)
	71	+ cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
64	72
65	73	return cpurev;
66	74	}
...	...	@@ -106,6 +106,8 @@
106	106	switch (imxtype) {
107	107	case MXC_CPU_MX6Q:
108	108	return "6Q"; /* Quad-core version of the mx6 */
	109	+ case MXC_CPU_MX6D:
	110	+ return "6D"; /* Dual-core version of the mx6 */
109	111	case MXC_CPU_MX6DL:
110	112	return "6DL"; /* Dual Lite version of the mx6 */
111	113	case MXC_CPU_MX6SOLO:
...	...	@@ -10,4 +10,5 @@
10	10	#define MXC_CPU_MX6DL 0x61
11	11	#define MXC_CPU_MX6SOLO 0x62
12	12	#define MXC_CPU_MX6Q 0x63
	13	+#define MXC_CPU_MX6D 0x64