Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 950b322fb0cc2fab8fe7418b952bb4f7ab19554c

Authored by Ye Li
1 parent 25515dfb16
Exists in smarc-n7.1.2_2.0.0-ga and in 4 other branches smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m

MLK-14915 mx6ul_arm2/mx6ull_arm2: Fix ENET PHY reset issue 

There are two pins used for ENET PHY reset, need to assert them before init the PHY.
Current DM driver does not have such operation, need board level codes to handle.
This patch moves the PHY reset operation into setup_fec, which is common for DM driver
and non-DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 3 changed files with 59 additions and 27 deletions Side-by-side Diff

board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
Diff comments   View file @ 950b322
... ... @@ -352,6 +352,9 @@
352 352 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
353 353 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
354 354 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  355 +};
  356 +
  357 +static iomux_v3_cfg_t const fec1_phy_rst[] = {
355 358 /*
356 359 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
357 360 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
358 361  
... ... @@ -381,7 +384,9 @@
381 384 MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
382 385 MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
383 386 MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  387 +};
384 388  
  389 +static iomux_v3_cfg_t const fec2_phy_rst[] = {
385 390 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
386 391 };
387 392  
388 393  
... ... @@ -390,17 +395,9 @@
390 395 if (fec_id == 0) {
391 396 imx_iomux_v3_setup_multiple_pads(fec1_pads,
392 397 ARRAY_SIZE(fec1_pads));
393   - gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
394   - gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
395   - udelay(50);
396   - gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
397 398 } else {
398 399 imx_iomux_v3_setup_multiple_pads(fec2_pads,
399 400 ARRAY_SIZE(fec2_pads));
400   - gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
401   - gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
402   - udelay(50);
403   - gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
404 401 }
405 402 }
406 403 #endif
... ... @@ -679,6 +676,13 @@
679 676 if (ret)
680 677 return ret;
681 678  
  679 + imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
  680 + ARRAY_SIZE(fec1_phy_rst));
  681 + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
  682 + gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
  683 + udelay(50);
  684 + gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
  685 +
682 686 } else {
683 687 if (check_module_fused(MX6_MODULE_ENET2))
684 688 return -1;
... ... @@ -686,6 +690,13 @@
686 690 /* clk from phy, set gpr1[14], clear gpr1[18]*/
687 691 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
688 692 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
  693 +
  694 + imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
  695 + ARRAY_SIZE(fec2_phy_rst));
  696 + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
  697 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  698 + udelay(50);
  699 + gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
689 700 }
690 701  
691 702 enable_enet_clk(1);
board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c
Diff comments   View file @ 950b322
... ... @@ -316,13 +316,16 @@
316 316 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
317 317 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
318 318 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  319 +};
  320 +
  321 +static iomux_v3_cfg_t const fec1_phy_rst[] = {
319 322 /*
320 323 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
321 324 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
322 325 *
323   - * ENET2_RST
  326 + * ENET1_RST
324 327 */
325   - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  328 + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
326 329 };
327 330  
328 331 /* Conflict with UART1 */
329 332  
... ... @@ -346,8 +349,10 @@
346 349 MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
347 350 MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
348 351 MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  352 +};
349 353  
350   - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  354 +static iomux_v3_cfg_t const fec2_phy_rst[] = {
  355 + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
351 356 };
352 357  
353 358 static void setup_iomux_fec(int fec_id)
354 359  
... ... @@ -355,17 +360,9 @@
355 360 if (fec_id == 0) {
356 361 imx_iomux_v3_setup_multiple_pads(fec1_pads,
357 362 ARRAY_SIZE(fec1_pads));
358   - gpio_request(IMX_GPIO_NR(5, 4), "fec1 reset");
359   - gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
360   - udelay(50);
361   - gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
362 363 } else {
363 364 imx_iomux_v3_setup_multiple_pads(fec2_pads,
364 365 ARRAY_SIZE(fec2_pads));
365   - gpio_request(IMX_GPIO_NR(5, 2), "fec2 reset");
366   - gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
367   - udelay(50);
368   - gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
369 366 }
370 367 }
371 368 #endif
372 369  
... ... @@ -626,10 +623,23 @@
626 623 if (ret)
627 624 return ret;
628 625  
  626 + imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
  627 + ARRAY_SIZE(fec1_phy_rst));
  628 + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
  629 + gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
  630 + udelay(50);
  631 + gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
629 632 } else {
630 633 /* clk from phy, set gpr1[13], clear gpr1[17]*/
631 634 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
632 635 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
  636 +
  637 + imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
  638 + ARRAY_SIZE(fec2_phy_rst));
  639 + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
  640 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  641 + udelay(50);
  642 + gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
633 643 }
634 644  
635 645 enable_enet_clk(1);
board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
Diff comments   View file @ 950b322
... ... @@ -272,6 +272,9 @@
272 272 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
273 273 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
274 274 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  275 +};
  276 +
  277 +static iomux_v3_cfg_t const fec1_phy_rst[] = {
275 278 /*
276 279 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
277 280 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
278 281  
... ... @@ -302,7 +305,9 @@
302 305  
303 306 MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
304 307 MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  308 +};
305 309  
  310 +static iomux_v3_cfg_t const fec2_phy_rst[] = {
306 311 /*
307 312 * ENET2_RST
308 313 *
309 314  
... ... @@ -316,17 +321,9 @@
316 321 if (fec_id == 0) {
317 322 imx_iomux_v3_setup_multiple_pads(fec1_pads,
318 323 ARRAY_SIZE(fec1_pads));
319   - gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
320   - gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
321   - udelay(50);
322   - gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
323 324 } else {
324 325 imx_iomux_v3_setup_multiple_pads(fec2_pads,
325 326 ARRAY_SIZE(fec2_pads));
326   - gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
327   - gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
328   - udelay(50);
329   - gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
330 327 }
331 328 }
332 329 #endif
... ... @@ -817,6 +814,13 @@
817 814 if (ret)
818 815 return ret;
819 816  
  817 + imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
  818 + ARRAY_SIZE(fec1_phy_rst));
  819 + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
  820 + gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
  821 + udelay(50);
  822 + gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
  823 +
820 824 } else {
821 825 if (check_module_fused(MX6_MODULE_ENET2))
822 826 return -1;
... ... @@ -824,6 +828,13 @@
824 828 /* clk from phy, set gpr1[14], clear gpr1[18]*/
825 829 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
826 830 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
  831 +
  832 + imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
  833 + ARRAY_SIZE(fec2_phy_rst));
  834 + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
  835 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  836 + udelay(50);
  837 + gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
827 838 }
828 839  
829 840 enable_enet_clk(1);