Eric Lee / smarc-uboot

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Commit 9531a2388ccaeaabb33a359a0bbf2e1d792c7dde

Authored by Sergei Poselenov
Committed by Wolfgang Denk
1 parent 3831530dcb
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

A4M072: Added support for the board. 

This patch provides support for the A4M072 board with the following features:
 UART
 NOR flash
 FEC Ethernet
 External SRAM
 I2C EEPROM
 CompactFlash cards on IDE/ATA port
 USB Host
 PCI initialization

The 7-segment LED indicator is not yet supported.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>

Showing 8 changed files with 777 additions and 5 deletions Inline Diff

1 ######################################################################### 1 #########################################################################
2 # # 2 # #
3 # Regular Maintainers for U-Boot board support: # 3 # Regular Maintainers for U-Boot board support: #
4 # # 4 # #
5 # For any board without permanent maintainer, please contact # 5 # For any board without permanent maintainer, please contact #
6 # Wolfgang Denk <wd@denx.de> # 6 # Wolfgang Denk <wd@denx.de> #
7 # and Cc: the <u-boot@lists.denx.de> mailing list. # 7 # and Cc: the <u-boot@lists.denx.de> mailing list. #
8 # # 8 # #
9 # Note: lists sorted by Maintainer Name # 9 # Note: lists sorted by Maintainer Name #
10 ######################################################################### 10 #########################################################################
11 11
12 12
13 ######################################################################### 13 #########################################################################
14 # PowerPC Systems: # 14 # PowerPC Systems: #
15 # # 15 # #
16 # Maintainer Name, Email Address # 16 # Maintainer Name, Email Address #
17 # Board CPU # 17 # Board CPU #
18 ######################################################################### 18 #########################################################################
19 19
20 Poonam Aggrwal <poonam.aggrwal@freescale.com> 20 Poonam Aggrwal <poonam.aggrwal@freescale.com>
21 21
22 P2020RDB P2020 22 P2020RDB P2020
23 23
24 Greg Allen <gallen@arlut.utexas.edu> 24 Greg Allen <gallen@arlut.utexas.edu>
25 25
26 UTX8245 MPC8245 26 UTX8245 MPC8245
27 27
28 Pantelis Antoniou <panto@intracom.gr> 28 Pantelis Antoniou <panto@intracom.gr>
29 29
30 NETVIA MPC8xx 30 NETVIA MPC8xx
31 31
32 Reinhard Arlt <reinhard.arlt@esd-electronics.com> 32 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
33 33
34 cpci5200 MPC5200 34 cpci5200 MPC5200
35 mecp5123 MPC5121 35 mecp5123 MPC5121
36 mecp5200 MPC5200 36 mecp5200 MPC5200
37 pf5200 MPC5200 37 pf5200 MPC5200
38 38
39 caddy2 MPC8349 39 caddy2 MPC8349
40 vme8349 MPC8349 40 vme8349 MPC8349
41 41
42 CPCI750 PPC750FX/GX 42 CPCI750 PPC750FX/GX
43 43
44 Yuli Barcohen <yuli@arabellasw.com> 44 Yuli Barcohen <yuli@arabellasw.com>
45 45
46 Adder MPC87x/MPC852T 46 Adder MPC87x/MPC852T
47 ep8248 MPC8248 47 ep8248 MPC8248
48 ISPAN MPC8260 48 ISPAN MPC8260
49 MPC8260ADS MPC826x/MPC827x/MPC8280 49 MPC8260ADS MPC826x/MPC827x/MPC8280
50 Rattler MPC8248 50 Rattler MPC8248
51 ZPC1900 MPC8265 51 ZPC1900 MPC8265
52 52
53 Michael Barkowski <michael.barkowski@freescale.com> 53 Michael Barkowski <michael.barkowski@freescale.com>
54 54
55 MPC8323ERDB MPC8323 55 MPC8323ERDB MPC8323
56 56
57 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> 57 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
58 58
59 sacsng MPC8260 59 sacsng MPC8260
60 60
61 Oliver Brown <obrown@adventnetworks.com> 61 Oliver Brown <obrown@adventnetworks.com>
62 62
63 gw8260 MPC8260 63 gw8260 MPC8260
64 64
65 Cyril Chemparathy <cyril@ti.com> 65 Cyril Chemparathy <cyril@ti.com>
66 66
67 tnetv107x_evm tnetv107x 67 tnetv107x_evm tnetv107x
68 68
69 Conn Clark <clark@esteem.com> 69 Conn Clark <clark@esteem.com>
70 70
71 ESTEEM192E MPC8xx 71 ESTEEM192E MPC8xx
72 72
73 Joe D'Abbraccio <ljd015@freescale.com> 73 Joe D'Abbraccio <ljd015@freescale.com>
74 74
75 MPC837xERDB MPC837x 75 MPC837xERDB MPC837x
76 76
77 Kári Davíðsson <kd@flaga.is> 77 Kári Davíðsson <kd@flaga.is>
78 78
79 FLAGADM MPC823 79 FLAGADM MPC823
80 80
81 Torsten Demke <torsten.demke@fci.com> 81 Torsten Demke <torsten.demke@fci.com>
82 82
83 eXalion MPC824x 83 eXalion MPC824x
84 84
85 Wolfgang Denk <wd@denx.de> 85 Wolfgang Denk <wd@denx.de>
86 86
87 IceCube_5200 MPC5200 87 IceCube_5200 MPC5200
88 88
89 ARIA MPC5121e 89 ARIA MPC5121e
90 90
91 AMX860 MPC860 91 AMX860 MPC860
92 ETX094 MPC850 92 ETX094 MPC850
93 FPS850L MPC850 93 FPS850L MPC850
94 FPS860L MPC860 94 FPS860L MPC860
95 ICU862 MPC862 95 ICU862 MPC862
96 IP860 MPC860 96 IP860 MPC860
97 IVML24 MPC860 97 IVML24 MPC860
98 IVML24_128 MPC860 98 IVML24_128 MPC860
99 IVML24_256 MPC860 99 IVML24_256 MPC860
100 IVMS8 MPC860 100 IVMS8 MPC860
101 IVMS8_128 MPC860 101 IVMS8_128 MPC860
102 IVMS8_256 MPC860 102 IVMS8_256 MPC860
103 LANTEC MPC850 103 LANTEC MPC850
104 LWMON MPC823 104 LWMON MPC823
105 NC650 MPC852 105 NC650 MPC852
106 R360MPI MPC823 106 R360MPI MPC823
107 RMU MPC850 107 RMU MPC850
108 RRvision MPC823 108 RRvision MPC823
109 SM850 MPC850 109 SM850 MPC850
110 SPD823TS MPC823 110 SPD823TS MPC823
111 TQM823L MPC823 111 TQM823L MPC823
112 TQM823L_LCD MPC823 112 TQM823L_LCD MPC823
113 TQM850L MPC850 113 TQM850L MPC850
114 TQM855L MPC855 114 TQM855L MPC855
115 TQM860L MPC860 115 TQM860L MPC860
116 TQM860L_FEC MPC860 116 TQM860L_FEC MPC860
117 c2mon MPC855 117 c2mon MPC855
118 hermes MPC860 118 hermes MPC860
119 lwmon MPC823 119 lwmon MPC823
120 120
121 CU824 MPC8240 121 CU824 MPC8240
122 Sandpoint8240 MPC8240 122 Sandpoint8240 MPC8240
123 123
124 ATC MPC8250 124 ATC MPC8250
125 PM825 MPC8250 125 PM825 MPC8250
126 126
127 TQM8255 MPC8255 127 TQM8255 MPC8255
128 128
129 CPU86 MPC8260 129 CPU86 MPC8260
130 PM826 MPC8260 130 PM826 MPC8260
131 TQM8260 MPC8260 131 TQM8260 MPC8260
132 132
133 P3G4 MPC7410 133 P3G4 MPC7410
134 134
135 PCIPPC2 MPC750 135 PCIPPC2 MPC750
136 PCIPPC6 MPC750 136 PCIPPC6 MPC750
137 137
138 Jon Diekema <jon.diekema@smiths-aerospace.com> 138 Jon Diekema <jon.diekema@smiths-aerospace.com>
139 139
140 sbc8260 MPC8260 140 sbc8260 MPC8260
141 141
142 Dirk Eibach <eibach@gdsys.de> 142 Dirk Eibach <eibach@gdsys.de>
143 143
144 devconcenter PPC460EX 144 devconcenter PPC460EX
145 dlvision PPC405EP 145 dlvision PPC405EP
146 gdppc440etx PPC440EP/GR 146 gdppc440etx PPC440EP/GR
147 intip PPC460EX 147 intip PPC460EX
148 neo PPC405EP 148 neo PPC405EP
149 149
150 Dave Ellis <DGE@sixnetio.com> 150 Dave Ellis <DGE@sixnetio.com>
151 151
152 SXNI855T MPC8xx 152 SXNI855T MPC8xx
153 153
154 Thomas Frieden <ThomasF@hyperion-entertainment.com> 154 Thomas Frieden <ThomasF@hyperion-entertainment.com>
155 155
156 AmigaOneG3SE MPC7xx 156 AmigaOneG3SE MPC7xx
157 157
158 Matthias Fuchs <matthias.fuchs@esd-electronics.com> 158 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
159 159
160 ADCIOP IOP480 (PPC401) 160 ADCIOP IOP480 (PPC401)
161 APC405 PPC405GP 161 APC405 PPC405GP
162 AR405 PPC405GP 162 AR405 PPC405GP
163 ASH405 PPC405EP 163 ASH405 PPC405EP
164 CANBT PPC405CR 164 CANBT PPC405CR
165 CPCI2DP PPC405GP 165 CPCI2DP PPC405GP
166 CPCI405 PPC405GP 166 CPCI405 PPC405GP
167 CPCI4052 PPC405GP 167 CPCI4052 PPC405GP
168 CPCI405AB PPC405GP 168 CPCI405AB PPC405GP
169 CPCI405DT PPC405GP 169 CPCI405DT PPC405GP
170 CPCIISER4 PPC405GP 170 CPCIISER4 PPC405GP
171 DASA_SIM IOP480 (PPC401) 171 DASA_SIM IOP480 (PPC401)
172 DP405 PPC405EP 172 DP405 PPC405EP
173 DU405 PPC405GP 173 DU405 PPC405GP
174 DU440 PPC440EPx 174 DU440 PPC440EPx
175 G2000 PPC405EP 175 G2000 PPC405EP
176 HH405 PPC405EP 176 HH405 PPC405EP
177 HUB405 PPC405EP 177 HUB405 PPC405EP
178 OCRTC PPC405GP 178 OCRTC PPC405GP
179 ORSG PPC405GP 179 ORSG PPC405GP
180 PCI405 PPC405GP 180 PCI405 PPC405GP
181 PLU405 PPC405EP 181 PLU405 PPC405EP
182 PMC405 PPC405GP 182 PMC405 PPC405GP
183 PMC405DE PPC405EP 183 PMC405DE PPC405EP
184 PMC440 PPC440EPx 184 PMC440 PPC440EPx
185 VOH405 PPC405EP 185 VOH405 PPC405EP
186 VOM405 PPC405EP 186 VOM405 PPC405EP
187 WUH405 PPC405EP 187 WUH405 PPC405EP
188 CMS700 PPC405EP 188 CMS700 PPC405EP
189 189
190 Niklaus Giger <niklaus.giger@netstal.com> 190 Niklaus Giger <niklaus.giger@netstal.com>
191 191
192 HCU4 PPC405GPr 192 HCU4 PPC405GPr
193 MCU25 PPC405GPr 193 MCU25 PPC405GPr
194 HCU5 PPC440EPx 194 HCU5 PPC440EPx
195 195
196 Siddarth Gore <gores@marvell.com> 196 Siddarth Gore <gores@marvell.com>
197 197
198 guruplug ARM926EJS (Kirkwood SoC) 198 guruplug ARM926EJS (Kirkwood SoC)
199 199
200 Frank Gottschling <fgottschling@eltec.de> 200 Frank Gottschling <fgottschling@eltec.de>
201 201
202 MHPC MPC8xx 202 MHPC MPC8xx
203 203
204 BAB7xx MPC740/MPC750 204 BAB7xx MPC740/MPC750
205 205
206 Wolfgang Grandegger <wg@denx.de> 206 Wolfgang Grandegger <wg@denx.de>
207 207
208 ipek01 MPC5200 208 ipek01 MPC5200
209 209
210 PN62 MPC8240 210 PN62 MPC8240
211 IPHASE4539 MPC8260 211 IPHASE4539 MPC8260
212 SCM MPC8260 212 SCM MPC8260
213 213
214 Joe Hamman <joe.hamman@embeddedspecialties.com> 214 Joe Hamman <joe.hamman@embeddedspecialties.com>
215 215
216 sbc8548 MPC8548 216 sbc8548 MPC8548
217 sbc8641d MPC8641D 217 sbc8641d MPC8641D
218 218
219 Klaus Heydeck <heydeck@kieback-peter.de> 219 Klaus Heydeck <heydeck@kieback-peter.de>
220 220
221 KUP4K MPC855 221 KUP4K MPC855
222 KUP4X MPC859 222 KUP4X MPC859
223 223
224 Ilko Iliev <iliev@ronetix.at> 224 Ilko Iliev <iliev@ronetix.at>
225 225
226 PM9261 AT91SAM9261 226 PM9261 AT91SAM9261
227 PM9263 AT91SAM9263 227 PM9263 AT91SAM9263
228 PM9G45 ARM926EJS (AT91SAM9G45 SoC) 228 PM9G45 ARM926EJS (AT91SAM9G45 SoC)
229 229
230 Gary Jennejohn <garyj@denx.de> 230 Gary Jennejohn <garyj@denx.de>
231 231
232 quad100hd PPC405EP 232 quad100hd PPC405EP
233 233
234 Murray Jensen <Murray.Jensen@csiro.au> 234 Murray Jensen <Murray.Jensen@csiro.au>
235 235
236 cogent_mpc8xx MPC8xx 236 cogent_mpc8xx MPC8xx
237 237
238 cogent_mpc8260 MPC8260 238 cogent_mpc8260 MPC8260
239 hymod MPC8260 239 hymod MPC8260
240 240
241 Larry Johnson <lrj@acm.org> 241 Larry Johnson <lrj@acm.org>
242 242
243 korat PPC440EPx 243 korat PPC440EPx
244 244
245 Feng Kan <fkan@amcc.com> 245 Feng Kan <fkan@amcc.com>
246 246
247 redwood PPC4xx 247 redwood PPC4xx
248 248
249 Brad Kemp <Brad.Kemp@seranoa.com> 249 Brad Kemp <Brad.Kemp@seranoa.com>
250 250
251 ppmc8260 MPC8260 251 ppmc8260 MPC8260
252 252
253 Sangmoon Kim <dogoil@etinsys.com> 253 Sangmoon Kim <dogoil@etinsys.com>
254 254
255 debris MPC8245 255 debris MPC8245
256 KVME080 MPC8245 256 KVME080 MPC8245
257 257
258 Robert Lazarski <robertlazarski@gmail.com> 258 Robert Lazarski <robertlazarski@gmail.com>
259 259
260 ATUM8548 MPC8548 260 ATUM8548 MPC8548
261 261
262 The LEOX team <team@leox.org> 262 The LEOX team <team@leox.org>
263 263
264 ELPT860 MPC860T 264 ELPT860 MPC860T
265 265
266 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 266 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
267 267
268 linkstation MPC8241 268 linkstation MPC8241
269 269
270 Dave Liu <daveliu@freescale.com> 270 Dave Liu <daveliu@freescale.com>
271 271
272 MPC8315ERDB MPC8315 272 MPC8315ERDB MPC8315
273 MPC832XEMDS MPC832x 273 MPC832XEMDS MPC832x
274 MPC8360EMDS MPC8360 274 MPC8360EMDS MPC8360
275 MPC837XEMDS MPC837x 275 MPC837XEMDS MPC837x
276 276
277 Nye Liu <nyet@zumanetworks.com> 277 Nye Liu <nyet@zumanetworks.com>
278 278
279 ZUMA MPC7xx_74xx 279 ZUMA MPC7xx_74xx
280 280
281 Kumar Gala <kumar.gala@freescale.com> 281 Kumar Gala <kumar.gala@freescale.com>
282 282
283 MPC8540ADS MPC8540 283 MPC8540ADS MPC8540
284 MPC8560ADS MPC8560 284 MPC8560ADS MPC8560
285 MPC8541CDS MPC8541 285 MPC8541CDS MPC8541
286 MPC8555CDS MPC8555 286 MPC8555CDS MPC8555
287 287
288 MPC8641HPCN MPC8641D 288 MPC8641HPCN MPC8641D
289 289
290 Ron Madrid <info@sheldoninst.com> 290 Ron Madrid <info@sheldoninst.com>
291 291
292 SIMPC8313 MPC8313 292 SIMPC8313 MPC8313
293 293
294 Dan Malek <dan@embeddedalley.com> 294 Dan Malek <dan@embeddedalley.com>
295 295
296 stxgp3 MPC85xx 296 stxgp3 MPC85xx
297 stxssa MPC85xx 297 stxssa MPC85xx
298 stxxtc MPC8xx 298 stxxtc MPC8xx
299 299
300 Eran Man <eran@nbase.co.il> 300 Eran Man <eran@nbase.co.il>
301 301
302 EVB64260_750CX MPC750CX 302 EVB64260_750CX MPC750CX
303 303
304 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 304 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
305 305
306 PPChameleonEVB PPC405EP 306 PPChameleonEVB PPC405EP
307 307
308 Tirumala Marri <tmarri@apm.com>
309
310 bluestone APM821XX
311
308 Reinhard Meyer <r.meyer@emk-elektronik.de> 312 Reinhard Meyer <r.meyer@emk-elektronik.de>
309 313
310 TOP860 MPC860T 314 TOP860 MPC860T
311 TOP5200 MPC5200 315 TOP5200 MPC5200
312 316
313 Tolunay Orkun <torkun@nextio.com> 317 Tolunay Orkun <torkun@nextio.com>
314 318
315 csb272 PPC405GP 319 csb272 PPC405GP
316 csb472 PPC405GP 320 csb472 PPC405GP
317 321
318 John Otken <jotken@softadvances.com> 322 John Otken <jotken@softadvances.com>
319 323
320 luan PPC440SP 324 luan PPC440SP
321 taihu PPC405EP 325 taihu PPC405EP
322 326
323 Keith Outwater <Keith_Outwater@mvis.com> 327 Keith Outwater <Keith_Outwater@mvis.com>
324 328
325 GEN860T MPC860T 329 GEN860T MPC860T
326 GEN860T_SC MPC860T 330 GEN860T_SC MPC860T
327 331
328 Frank Panno <fpanno@delphintech.com> 332 Frank Panno <fpanno@delphintech.com>
329 333
330 ep8260 MPC8260 334 ep8260 MPC8260
331 335
332 Denis Peter <d.peter@mpl.ch> 336 Denis Peter <d.peter@mpl.ch>
333 337
334 MIP405 PPC4xx 338 MIP405 PPC4xx
335 PIP405 PPC4xx 339 PIP405 PPC4xx
336 340
337 Kim Phillips <kim.phillips@freescale.com> 341 Kim Phillips <kim.phillips@freescale.com>
338 342
339 MPC8349EMDS MPC8349 343 MPC8349EMDS MPC8349
340 344
341 Daniel Poirot <dan.poirot@windriver.com> 345 Daniel Poirot <dan.poirot@windriver.com>
342 346
343 sbc8240 MPC8240 347 sbc8240 MPC8240
344 sbc405 PPC405GP 348 sbc405 PPC405GP
345 349
350 Sergei Poselenov <sposelenov@emcraft.com>
351
352 a4m072 MPC5200
353
346 Sudhakar Rajashekhara <sudhakar.raj@ti.com> 354 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
347 355
348 da850evm ARM926EJS (DA850/OMAP-L138) 356 da850evm ARM926EJS (DA850/OMAP-L138)
349 357
350 Ricardo Ribalda <ricardo.ribalda@uam.es> 358 Ricardo Ribalda <ricardo.ribalda@uam.es>
351 359
352 ml507 PPC440x5 360 ml507 PPC440x5
353 v5fx30teval PPC440x5 361 v5fx30teval PPC440x5
354 xilinx-ppc405-generic PPC405 362 xilinx-ppc405-generic PPC405
355 xilinx-ppc440-generic PPC440x5 363 xilinx-ppc440-generic PPC440x5
356 364
357 Stefan Roese <sr@denx.de> 365 Stefan Roese <sr@denx.de>
358 366
359 P3M7448 MPC7448 367 P3M7448 MPC7448
360 368
361 uc100 MPC857 369 uc100 MPC857
362 370
363 TQM85xx MPC8540/8541/8555/8560 371 TQM85xx MPC8540/8541/8555/8560
364 372
365 acadia PPC405EZ 373 acadia PPC405EZ
366 alpr PPC440GX 374 alpr PPC440GX
367 bamboo PPC440EP 375 bamboo PPC440EP
368 bunbinga PPC405EP 376 bunbinga PPC405EP
369 canyonlands PPC460EX 377 canyonlands PPC460EX
370 ebony PPC440GP 378 ebony PPC440GP
371 glacier PPC460GT 379 glacier PPC460GT
372 haleakala PPC405EXr 380 haleakala PPC405EXr
373 icon PPC440SPe 381 icon PPC440SPe
374 katmai PPC440SPe 382 katmai PPC440SPe
375 kilauea PPC405EX 383 kilauea PPC405EX
376 lwmon5 PPC440EPx 384 lwmon5 PPC440EPx
377 makalu PPC405EX 385 makalu PPC405EX
378 ocotea PPC440GX 386 ocotea PPC440GX
379 p3p440 PPC440GP 387 p3p440 PPC440GP
380 pcs440ep PPC440EP 388 pcs440ep PPC440EP
381 rainier PPC440GRx 389 rainier PPC440GRx
382 sequoia PPC440EPx 390 sequoia PPC440EPx
383 sycamore PPC405GPr 391 sycamore PPC405GPr
384 t3corp PPC460GT 392 t3corp PPC460GT
385 taishan PPC440GX 393 taishan PPC440GX
386 walnut PPC405GP 394 walnut PPC405GP
387 yellowstone PPC440GR 395 yellowstone PPC440GR
388 yosemite PPC440EP 396 yosemite PPC440EP
389 zeus PPC405EP 397 zeus PPC405EP
390 398
391 P3M750 PPC750FX/GX/GL 399 P3M750 PPC750FX/GX/GL
392 400
393 Yusdi Santoso <yusdi_santoso@adaptec.com> 401 Yusdi Santoso <yusdi_santoso@adaptec.com>
394 402
395 HIDDEN_DRAGON MPC8241/MPC8245 403 HIDDEN_DRAGON MPC8241/MPC8245
396 404
397 Travis Sawyer (travis.sawyer@sandburst.com> 405 Travis Sawyer (travis.sawyer@sandburst.com>
398 406
399 KAREF PPC440GX 407 KAREF PPC440GX
400 METROBOX PPC440GX 408 METROBOX PPC440GX
401 409
402 Georg Schardt <schardt@team-ctech.de> 410 Georg Schardt <schardt@team-ctech.de>
403 411
404 fx12mm PPC405 412 fx12mm PPC405
405 413
406 Heiko Schocher <hs@denx.de> 414 Heiko Schocher <hs@denx.de>
407 415
408 ids8247 MPC8247 416 ids8247 MPC8247
409 jupiter MPC5200 417 jupiter MPC5200
410 kmeter1 MPC8360 418 kmeter1 MPC8360
411 kmsupx4 MPC852T 419 kmsupx4 MPC852T
412 mgcoge MPC8247 420 mgcoge MPC8247
413 mgsuvd MPC852 421 mgsuvd MPC852
414 mucmc52 MPC5200 422 mucmc52 MPC5200
415 muas3001 MPC8270 423 muas3001 MPC8270
416 municse MPC5200 424 municse MPC5200
417 sc3 PPC405GP 425 sc3 PPC405GP
418 suen3 ARM926EJS (Kirkwood SoC) 426 suen3 ARM926EJS (Kirkwood SoC)
419 uc101 MPC5200 427 uc101 MPC5200
420 ve8313 MPC8313 428 ve8313 MPC8313
421 429
422 Peter De Schrijver <p2@mind.be> 430 Peter De Schrijver <p2@mind.be>
423 431
424 ML2 PPC4xx 432 ML2 PPC4xx
425 433
426 Andre Schwarz <andre.schwarz@matrix-vision.de> 434 Andre Schwarz <andre.schwarz@matrix-vision.de>
427 435
428 mvbc_p MPC5200 436 mvbc_p MPC5200
429 mvblm7 MPC8343 437 mvblm7 MPC8343
430 mvsmr MPC5200 438 mvsmr MPC5200
431 439
432 Jon Smirl <jonsmirl@gmail.com> 440 Jon Smirl <jonsmirl@gmail.com>
433 441
434 pcm030 MPC5200 442 pcm030 MPC5200
435 443
436 Timur Tabi <timur@freescale.com> 444 Timur Tabi <timur@freescale.com>
437 445
438 MPC8349E-mITX MPC8349 446 MPC8349E-mITX MPC8349
439 MPC8349E-mITX-GP MPC8349 447 MPC8349E-mITX-GP MPC8349
440 P1022DS P1022 448 P1022DS P1022
441 449
442 Erik Theisen <etheisen@mindspring.com> 450 Erik Theisen <etheisen@mindspring.com>
443 451
444 W7OLMC PPC4xx 452 W7OLMC PPC4xx
445 W7OLMG PPC4xx 453 W7OLMG PPC4xx
446 454
447 Jim Thompson <jim@musenki.com> 455 Jim Thompson <jim@musenki.com>
448 456
449 MUSENKI MPC8245/8241 457 MUSENKI MPC8245/8241
450 Sandpoint8245 MPC8245 458 Sandpoint8245 MPC8245
451 459
452 Rune Torgersen <runet@innovsys.com> 460 Rune Torgersen <runet@innovsys.com>
453 461
454 MPC8266ADS MPC8266 462 MPC8266ADS MPC8266
455 463
456 Peter Tyser <ptyser@xes-inc.com> 464 Peter Tyser <ptyser@xes-inc.com>
457 465
458 XPEDITE1000 PPC440GX 466 XPEDITE1000 PPC440GX
459 XPEDITE5170 MPC8640 467 XPEDITE5170 MPC8640
460 XPEDITE5200 MPC8548 468 XPEDITE5200 MPC8548
461 XPEDITE5370 MPC8572 469 XPEDITE5370 MPC8572
462 470
463 David Updegraff <dave@cray.com> 471 David Updegraff <dave@cray.com>
464 472
465 CRAYL1 PPC4xx 473 CRAYL1 PPC4xx
466 474
467 Anton Vorontsov <avorontsov@ru.mvista.com> 475 Anton Vorontsov <avorontsov@ru.mvista.com>
468 476
469 MPC8360ERDK MPC8360 477 MPC8360ERDK MPC8360
470 478
471 Josef Wagner <Wagner@Microsys.de> 479 Josef Wagner <Wagner@Microsys.de>
472 480
473 CPC45 MPC8245 481 CPC45 MPC8245
474 PM520 MPC5200 482 PM520 MPC5200
475 483
476 Michael Weiss <michael.weiss@ifm.com> 484 Michael Weiss <michael.weiss@ifm.com>
477 485
478 PDM360NG MPC5121e 486 PDM360NG MPC5121e
479 487
480 Stephen Williams <steve@icarus.com> 488 Stephen Williams <steve@icarus.com>
481 489
482 JSE PPC405GPr 490 JSE PPC405GPr
483 491
484 Ilya Yanok <yanok@emcraft.com> 492 Ilya Yanok <yanok@emcraft.com>
485 493
486 mpc8308_p1m MPC8308 494 mpc8308_p1m MPC8308
487 MPC8308RDB MPC8308 495 MPC8308RDB MPC8308
488 496
489 Roy Zang <tie-fei.zang@freescale.com> 497 Roy Zang <tie-fei.zang@freescale.com>
490 498
491 mpc7448hpc2 MPC7448 499 mpc7448hpc2 MPC7448
492 500
493 John Zhan <zhanz@sinovee.com> 501 John Zhan <zhanz@sinovee.com>
494 502
495 svm_sc8xx MPC8xx 503 svm_sc8xx MPC8xx
496 504
497 Detlev Zundel <dzu@denx.de> 505 Detlev Zundel <dzu@denx.de>
498 506
499 inka4x0 MPC5200 507 inka4x0 MPC5200
500
501 Tirumala Marri <tmarri@apm.com>
502
503 bluestone APM821XX
504 508
505 ------------------------------------------------------------------------- 509 -------------------------------------------------------------------------
506 510
507 Unknown / orphaned boards: 511 Unknown / orphaned boards:
508 512
509 ADS860 MPC8xx 513 ADS860 MPC8xx
510 FADS823 MPC8xx 514 FADS823 MPC8xx
511 FADS850SAR MPC8xx 515 FADS850SAR MPC8xx
512 FADS860T MPC8xx 516 FADS860T MPC8xx
513 GENIETV MPC8xx 517 GENIETV MPC8xx
514 IAD210 MPC8xx 518 IAD210 MPC8xx
515 MBX MPC8xx 519 MBX MPC8xx
516 MBX860T MPC8xx 520 MBX860T MPC8xx
517 NX823 MPC8xx 521 NX823 MPC8xx
518 RPXClassic MPC8xx 522 RPXClassic MPC8xx
519 RPXlite MPC8xx 523 RPXlite MPC8xx
520 524
521 ERIC PPC4xx 525 ERIC PPC4xx
522 526
523 MOUSSE MPC824x 527 MOUSSE MPC824x
524 528
525 RPXsuper MPC8260 529 RPXsuper MPC8260
526 rsdproto MPC8260 530 rsdproto MPC8260
527 531
528 EVB64260 MPC7xx_74xx 532 EVB64260 MPC7xx_74xx
529 533
530 534
531 ######################################################################### 535 #########################################################################
532 # ARM Systems: # 536 # ARM Systems: #
533 # # 537 # #
534 # Maintainer Name, Email Address # 538 # Maintainer Name, Email Address #
535 # Board CPU # 539 # Board CPU #
536 ######################################################################### 540 #########################################################################
537 541
538 Albert ARIBAUD <albert.aribaud@free.fr> 542 Albert ARIBAUD <albert.aribaud@free.fr>
539 543
540 edminiv2 ARM926EJS (Orion5x SoC) 544 edminiv2 ARM926EJS (Orion5x SoC)
541 545
542 Rowel Atienza <rowel@diwalabs.com> 546 Rowel Atienza <rowel@diwalabs.com>
543 547
544 armadillo ARM720T 548 armadillo ARM720T
545 549
546 Stefano Babic <sbabic@denx.de> 550 Stefano Babic <sbabic@denx.de>
547 551
548 polaris xscale 552 polaris xscale
549 trizepsiv xscale 553 trizepsiv xscale
550 mx51evk i.MX51 554 mx51evk i.MX51
551 555
552 Dirk Behme <dirk.behme@gmail.com> 556 Dirk Behme <dirk.behme@gmail.com>
553 557
554 omap3_beagle ARM ARMV7 (OMAP3530 SoC) 558 omap3_beagle ARM ARMV7 (OMAP3530 SoC)
555 559
556 Eric Benard <eric@eukrea.com> 560 Eric Benard <eric@eukrea.com>
557 561
558 cpuat91 ARM920T 562 cpuat91 ARM920T
559 cpu9260 ARM926EJS (AT91SAM9260 SoC) 563 cpu9260 ARM926EJS (AT91SAM9260 SoC)
560 cpu9G20 ARM926EJS (AT91SAM9G20 SoC) 564 cpu9G20 ARM926EJS (AT91SAM9G20 SoC)
561 565
562 Rishi Bhattacharya <rishi@ti.com> 566 Rishi Bhattacharya <rishi@ti.com>
563 567
564 omap5912osk ARM926EJS 568 omap5912osk ARM926EJS
565 569
566 Cliff Brake <cliff.brake@gmail.com> 570 Cliff Brake <cliff.brake@gmail.com>
567 571
568 pxa255_idp xscale 572 pxa255_idp xscale
569 573
570 Rick Bronson <rick@efn.org> 574 Rick Bronson <rick@efn.org>
571 575
572 AT91RM9200DK at91rm9200 576 AT91RM9200DK at91rm9200
573 577
574 Po-Yu Chuang <ratbert@faraday-tech.com> 578 Po-Yu Chuang <ratbert@faraday-tech.com>
575 579
576 a320evb FA526 (ARM920T-like) (a320 SoC) 580 a320evb FA526 (ARM920T-like) (a320 SoC)
577 581
578 George G. Davis <gdavis@mvista.com> 582 George G. Davis <gdavis@mvista.com>
579 583
580 assabet SA1100 584 assabet SA1100
581 gcplus SA1100 585 gcplus SA1100
582 586
583 Wolfgang Denk <wd@denx.de> 587 Wolfgang Denk <wd@denx.de>
584 imx27lite i.MX27 588 imx27lite i.MX27
585 qong i.MX31 589 qong i.MX31
586 590
587 Thomas Elste <info@elste.org> 591 Thomas Elste <info@elste.org>
588 592
589 modnet50 ARM720T (NET+50) 593 modnet50 ARM720T (NET+50)
590 594
591 Fabio Estevam <Fabio.Estevam@freescale.com> 595 Fabio Estevam <Fabio.Estevam@freescale.com>
592 596
593 mx31pdk i.MX31 597 mx31pdk i.MX31
594 598
595 Peter Figuli <peposh@etc.sk> 599 Peter Figuli <peposh@etc.sk>
596 600
597 wepep250 xscale 601 wepep250 xscale
598 602
599 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 603 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
600 604
601 meesc ARM926EJS (AT91SAM9263 SoC) 605 meesc ARM926EJS (AT91SAM9263 SoC)
602 otc570 ARM926EJS (AT91SAM9263 SoC) 606 otc570 ARM926EJS (AT91SAM9263 SoC)
603 607
604 Sedji Gaouaou<sedji.gaouaou@atmel.com> 608 Sedji Gaouaou<sedji.gaouaou@atmel.com>
605 at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) 609 at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
606 at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) 610 at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)
607 611
608 Marius Gröger <mag@sysgo.de> 612 Marius Gröger <mag@sysgo.de>
609 613
610 impa7 ARM720T (EP7211) 614 impa7 ARM720T (EP7211)
611 ep7312 ARM720T (EP7312) 615 ep7312 ARM720T (EP7312)
612 616
613 Kshitij Gupta <kshitij@ti.com> 617 Kshitij Gupta <kshitij@ti.com>
614 618
615 omap1510inn ARM925T 619 omap1510inn ARM925T
616 omap1610inn ARM926EJS 620 omap1610inn ARM926EJS
617 621
618 Vaibhav Hiremath <hvaibhav@ti.com> 622 Vaibhav Hiremath <hvaibhav@ti.com>
619 623
620 am3517_evm ARM ARMV7 (AM35x SoC) 624 am3517_evm ARM ARMV7 (AM35x SoC)
621 625
622 Grazvydas Ignotas <notasas@gmail.com> 626 Grazvydas Ignotas <notasas@gmail.com>
623 627
624 omap3_pandora ARM ARMV7 (OMAP3xx SoC) 628 omap3_pandora ARM ARMV7 (OMAP3xx SoC)
625 629
626 Gary Jennejohn <garyj@denx.de> 630 Gary Jennejohn <garyj@denx.de>
627 631
628 smdk2400 ARM920T 632 smdk2400 ARM920T
629 trab ARM920T 633 trab ARM920T
630 634
631 Matthias Kaehlcke <matthias@kaehlcke.net> 635 Matthias Kaehlcke <matthias@kaehlcke.net>
632 edb9301 ARM920T (EP9301) 636 edb9301 ARM920T (EP9301)
633 edb9302 ARM920T (EP9302) 637 edb9302 ARM920T (EP9302)
634 edb9302a ARM920T (EP9302) 638 edb9302a ARM920T (EP9302)
635 edb9307 ARM920T (EP9307) 639 edb9307 ARM920T (EP9307)
636 edb9307a ARM920T (EP9307) 640 edb9307a ARM920T (EP9307)
637 edb9312 ARM920T (EP9312) 641 edb9312 ARM920T (EP9312)
638 edb9315 ARM920T (EP9315) 642 edb9315 ARM920T (EP9315)
639 edb9315a ARM920T (EP9315) 643 edb9315a ARM920T (EP9315)
640 644
641 Konstantin Kletschke <kletschke@synertronixx.de> 645 Konstantin Kletschke <kletschke@synertronixx.de>
642 scb9328 ARM920T 646 scb9328 ARM920T
643 647
644 Simon Kagstrom <simon.kagstrom@netinsight.net> 648 Simon Kagstrom <simon.kagstrom@netinsight.net>
645 649
646 openrd_base ARM926EJS (Kirkwood SoC) 650 openrd_base ARM926EJS (Kirkwood SoC)
647 651
648 Nishant Kamat <nskamat@ti.com> 652 Nishant Kamat <nskamat@ti.com>
649 653
650 omap1610h2 ARM926EJS 654 omap1610h2 ARM926EJS
651 655
652 Minkyu Kang <mk7.kang@samsung.com> 656 Minkyu Kang <mk7.kang@samsung.com>
653 657
654 s5p_goni ARM ARMV7 (S5PC110 SoC) 658 s5p_goni ARM ARMV7 (S5PC110 SoC)
655 SMDKC100 ARM ARMV7 (S5PC100 SoC) 659 SMDKC100 ARM ARMV7 (S5PC100 SoC)
656 660
657 Frederik Kriewitz <frederik@kriewitz.eu> 661 Frederik Kriewitz <frederik@kriewitz.eu>
658 662
659 devkit8000 ARM ARMV7 (OMAP3530 SoC) 663 devkit8000 ARM ARMV7 (OMAP3530 SoC)
660 664
661 Sergey Kubushyn <ksi@koi8.net> 665 Sergey Kubushyn <ksi@koi8.net>
662 666
663 DV-EVM ARM926EJS 667 DV-EVM ARM926EJS
664 SONATA ARM926EJS 668 SONATA ARM926EJS
665 SCHMOOGIE ARM926EJS 669 SCHMOOGIE ARM926EJS
666 670
667 Prakash Kumar <prakash@embedx.com> 671 Prakash Kumar <prakash@embedx.com>
668 672
669 cerf250 xscale 673 cerf250 xscale
670 674
671 Vipin Kumar <vipin.kumar@st.com> 675 Vipin Kumar <vipin.kumar@st.com>
672 676
673 spear300 ARM926EJS (spear300 Soc) 677 spear300 ARM926EJS (spear300 Soc)
674 spear310 ARM926EJS (spear310 Soc) 678 spear310 ARM926EJS (spear310 Soc)
675 spear320 ARM926EJS (spear320 Soc) 679 spear320 ARM926EJS (spear320 Soc)
676 spear600 ARM926EJS (spear600 Soc) 680 spear600 ARM926EJS (spear600 Soc)
677 681
678 Sergey Lapin <slapin@ossfans.org> 682 Sergey Lapin <slapin@ossfans.org>
679 683
680 afeb9260 ARM926EJS (AT91SAM9260 SoC) 684 afeb9260 ARM926EJS (AT91SAM9260 SoC)
681 685
682 Nishanth Menon <nm@ti.com> 686 Nishanth Menon <nm@ti.com>
683 687
684 omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC) 688 omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC)
685 omap3_zoom1 ARM ARMV7 (OMAP3xx SoC) 689 omap3_zoom1 ARM ARMV7 (OMAP3xx SoC)
686 690
687 David Müller <d.mueller@elsoft.ch> 691 David Müller <d.mueller@elsoft.ch>
688 692
689 smdk2410 ARM920T 693 smdk2410 ARM920T
690 VCMA9 ARM920T 694 VCMA9 ARM920T
691 695
692 Eric Millbrandt <emillbrandt@dekaresearch.com> 696 Eric Millbrandt <emillbrandt@dekaresearch.com>
693 697
694 galaxy5200 mpc5200 698 galaxy5200 mpc5200
695 699
696 Rolf Offermanns <rof@sysgo.de> 700 Rolf Offermanns <rof@sysgo.de>
697 701
698 shannon SA1100 702 shannon SA1100
699 703
700 Kyungmin Park <kyungmin.park@samsung.com> 704 Kyungmin Park <kyungmin.park@samsung.com>
701 705
702 apollon ARM1136EJS 706 apollon ARM1136EJS
703 707
704 Sandeep Paulraj <s-paulraj@ti.com> 708 Sandeep Paulraj <s-paulraj@ti.com>
705 709
706 davinci_dm355evm ARM926EJS 710 davinci_dm355evm ARM926EJS
707 davinci_dm355leopard ARM926EJS 711 davinci_dm355leopard ARM926EJS
708 davinci_dm365evm ARM926EJS 712 davinci_dm365evm ARM926EJS
709 davinci_dm6467evm ARM926EJS 713 davinci_dm6467evm ARM926EJS
710 714
711 Peter Pearse <peter.pearse@arm.com> 715 Peter Pearse <peter.pearse@arm.com>
712 integratorcp All current ARM supplied & supported core modules 716 integratorcp All current ARM supplied & supported core modules
713 -see http://www.arm.com/products/DevTools/Hardware_Platforms.html 717 -see http://www.arm.com/products/DevTools/Hardware_Platforms.html
714 versatile ARM926EJ-S 718 versatile ARM926EJ-S
715 versatile ARM926EJ-S 719 versatile ARM926EJ-S
716 720
717 Dave Peverley <dpeverley@mpc-data.co.uk> 721 Dave Peverley <dpeverley@mpc-data.co.uk>
718 722
719 omap730p2 ARM926EJS 723 omap730p2 ARM926EJS
720 724
721 Manikandan Pillai <mani.pillai@ti.com> 725 Manikandan Pillai <mani.pillai@ti.com>
722 726
723 omap3_evm ARM ARMV7 (OMAP3xx SoC) 727 omap3_evm ARM ARMV7 (OMAP3xx SoC)
724 728
725 Stelian Pop <stelian.pop@leadtechdesign.com> 729 Stelian Pop <stelian.pop@leadtechdesign.com>
726 730
727 at91cap9adk ARM926EJS (AT91CAP9 SoC) 731 at91cap9adk ARM926EJS (AT91CAP9 SoC)
728 at91sam9260ek ARM926EJS (AT91SAM9260 SoC) 732 at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
729 at91sam9261ek ARM926EJS (AT91SAM9261 SoC) 733 at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
730 at91sam9263ek ARM926EJS (AT91SAM9263 SoC) 734 at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
731 at91sam9rlek ARM926EJS (AT91SAM9RL SoC) 735 at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
732 736
733 Tom Rix <Tom.Rix@windriver.com> 737 Tom Rix <Tom.Rix@windriver.com>
734 738
735 omap3_zoom2 ARM ARMV7 (OMAP3xx SoC) 739 omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
736 740
737 John Rigby <jcrigby@gmail.com> 741 John Rigby <jcrigby@gmail.com>
738 742
739 tx25 i.MX25 743 tx25 i.MX25
740 744
741 Stefan Roese <sr@denx.de> 745 Stefan Roese <sr@denx.de>
742 746
743 ixdpg425 xscale 747 ixdpg425 xscale
744 pdnb3 xscale 748 pdnb3 xscale
745 scpu xscale 749 scpu xscale
746 750
747 Alessandro Rubini <rubini@unipv.it> 751 Alessandro Rubini <rubini@unipv.it>
748 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> 752 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
749 753
750 nhk8815 ARM926EJS (Nomadik 8815 Soc) 754 nhk8815 ARM926EJS (Nomadik 8815 Soc)
751 755
752 Steve Sakoman <sakoman@gmail.com> 756 Steve Sakoman <sakoman@gmail.com>
753 757
754 omap3_overo ARM ARMV7 (OMAP3xx SoC) 758 omap3_overo ARM ARMV7 (OMAP3xx SoC)
755 omap4_panda ARM ARMV7 (OMAP4xx SoC) 759 omap4_panda ARM ARMV7 (OMAP4xx SoC)
756 omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC) 760 omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
757 761
758 Jens Scharsig <esw@bus-elektronik.de> 762 Jens Scharsig <esw@bus-elektronik.de>
759 763
760 eb_cpux9k2 ARM920T (AT91RM9200 SoC) 764 eb_cpux9k2 ARM920T (AT91RM9200 SoC)
761 765
762 Heiko Schocher <hs@denx.de> 766 Heiko Schocher <hs@denx.de>
763 767
764 magnesium i.MX27 768 magnesium i.MX27
765 769
766 Robert Schwebel <r.schwebel@pengutronix.de> 770 Robert Schwebel <r.schwebel@pengutronix.de>
767 771
768 csb226 xscale 772 csb226 xscale
769 innokom xscale 773 innokom xscale
770 774
771 Michael Schwingen <michael@schwingen.org> 775 Michael Schwingen <michael@schwingen.org>
772 776
773 actux1 xscale 777 actux1 xscale
774 actux2 xscale 778 actux2 xscale
775 actux3 xscale 779 actux3 xscale
776 actux4 xscale 780 actux4 xscale
777 781
778 Andrea Scian <andrea.scian@dave-tech.it> 782 Andrea Scian <andrea.scian@dave-tech.it>
779 783
780 B2 ARM7TDMI (S3C44B0X) 784 B2 ARM7TDMI (S3C44B0X)
781 785
782 Nick Thompson <nick.thompson@gefanuc.com> 786 Nick Thompson <nick.thompson@gefanuc.com>
783 787
784 da830evm ARM926EJS (DA830/OMAP-L137) 788 da830evm ARM926EJS (DA830/OMAP-L137)
785 789
786 Albin Tonnerre <albin.tonnerre@free-electrons.com> 790 Albin Tonnerre <albin.tonnerre@free-electrons.com>
787 791
788 sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC) 792 sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
789 tny_a9260 ARM926EJS (AT91SAM9260 SoC) 793 tny_a9260 ARM926EJS (AT91SAM9260 SoC)
790 tny_a9g20 ARM926EJS (AT91SAM9G20 SoC) 794 tny_a9g20 ARM926EJS (AT91SAM9G20 SoC)
791 795
792 Greg Ungerer <greg.ungerer@opengear.com> 796 Greg Ungerer <greg.ungerer@opengear.com>
793 797
794 cm4008 ks8695p 798 cm4008 ks8695p
795 cm4116 ks8695p 799 cm4116 ks8695p
796 cm4148 ks8695p 800 cm4148 ks8695p
797 801
798 Hugo Villeneuve <hugo.villeneuve@lyrtech.com> 802 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
799 803
800 SFFSDR ARM926EJS 804 SFFSDR ARM926EJS
801 805
802 Prafulla Wadaskar <prafulla@marvell.com> 806 Prafulla Wadaskar <prafulla@marvell.com>
803 807
804 mv88f6281gtw_ge ARM926EJS (Kirkwood SoC) 808 mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
805 rd6281a ARM926EJS (Kirkwood SoC) 809 rd6281a ARM926EJS (Kirkwood SoC)
806 sheevaplug ARM926EJS (Kirkwood SoC) 810 sheevaplug ARM926EJS (Kirkwood SoC)
807 811
808 Matthias Weisser <weisserm@arcor.de> 812 Matthias Weisser <weisserm@arcor.de>
809 813
810 jadecpu ARM926EJS (MB86R01 SoC) 814 jadecpu ARM926EJS (MB86R01 SoC)
811 815
812 Richard Woodruff <r-woodruff2@ti.com> 816 Richard Woodruff <r-woodruff2@ti.com>
813 817
814 omap2420h4 ARM1136EJS 818 omap2420h4 ARM1136EJS
815 819
816 Alex Züpke <azu@sysgo.de> 820 Alex Züpke <azu@sysgo.de>
817 821
818 lart SA1100 822 lart SA1100
819 dnp1110 SA1110 823 dnp1110 SA1110
820 824
821 ------------------------------------------------------------------------- 825 -------------------------------------------------------------------------
822 826
823 Unknown / orphaned boards: 827 Unknown / orphaned boards:
824 Board CPU Last known maintainer / Comment 828 Board CPU Last known maintainer / Comment
825 ......................................................................... 829 .........................................................................
826 cradle xscale Kyle Harris <kharris@nexus-tech.net> / dead address 830 cradle xscale Kyle Harris <kharris@nexus-tech.net> / dead address
827 ixdp425 xscale Kyle Harris <kharris@nexus-tech.net> / dead address 831 ixdp425 xscale Kyle Harris <kharris@nexus-tech.net> / dead address
828 lubbock xscale Kyle Harris <kharris@nexus-tech.net> / dead address 832 lubbock xscale Kyle Harris <kharris@nexus-tech.net> / dead address
829 833
830 imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned 834 imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
831 mx31ads i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned 835 mx31ads i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
832 SMDK6400 S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned 836 SMDK6400 S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
833 837
834 ######################################################################### 838 #########################################################################
835 # x86 Systems: # 839 # x86 Systems: #
836 # # 840 # #
837 # Maintainer Name, Email Address # 841 # Maintainer Name, Email Address #
838 # Board CPU # 842 # Board CPU #
839 ######################################################################### 843 #########################################################################
840 844
841 Daniel Engström <daniel@omicron.se> 845 Daniel Engström <daniel@omicron.se>
842 846
843 sc520_cdp x86 847 sc520_cdp x86
844 848
845 ######################################################################### 849 #########################################################################
846 # MIPS Systems: # 850 # MIPS Systems: #
847 # # 851 # #
848 # Maintainer Name, Email Address # 852 # Maintainer Name, Email Address #
849 # Board CPU # 853 # Board CPU #
850 ######################################################################### 854 #########################################################################
851 855
852 Wolfgang Denk <wd@denx.de> 856 Wolfgang Denk <wd@denx.de>
853 857
854 incaip MIPS32 4Kc 858 incaip MIPS32 4Kc
855 purple MIPS64 5Kc 859 purple MIPS64 5Kc
856 860
857 Thomas Lange <thomas@corelatus.se> 861 Thomas Lange <thomas@corelatus.se>
858 dbau1x00 MIPS32 Au1000 862 dbau1x00 MIPS32 Au1000
859 gth2 MIPS32 Au1000 863 gth2 MIPS32 Au1000
860 864
861 Vlad Lungu <vlad.lungu@windriver.com> 865 Vlad Lungu <vlad.lungu@windriver.com>
862 qemu_mips MIPS32 866 qemu_mips MIPS32
863 867
864 Stefan Roese <sr@denx.de> 868 Stefan Roese <sr@denx.de>
865 869
866 vct_xxx MIPS32 4Kc 870 vct_xxx MIPS32 4Kc
867 871
868 ######################################################################### 872 #########################################################################
869 # Nios-II Systems: # 873 # Nios-II Systems: #
870 # # 874 # #
871 # Maintainer Name, Email Address # 875 # Maintainer Name, Email Address #
872 # Board CPU # 876 # Board CPU #
873 ######################################################################### 877 #########################################################################
874 878
875 Scott McNutt <smcnutt@psyent.com> 879 Scott McNutt <smcnutt@psyent.com>
876 880
877 PCI5441 Nios-II 881 PCI5441 Nios-II
878 PK1C20 Nios-II 882 PK1C20 Nios-II
879 nios2-generic Nios-II 883 nios2-generic Nios-II
880 884
881 ######################################################################### 885 #########################################################################
882 # MicroBlaze Systems: # 886 # MicroBlaze Systems: #
883 # # 887 # #
884 # Maintainer Name, Email Address # 888 # Maintainer Name, Email Address #
885 # Board CPU # 889 # Board CPU #
886 ######################################################################### 890 #########################################################################
887 891
888 Michal Simek <monstr@monstr.eu> 892 Michal Simek <monstr@monstr.eu>
889 893
890 microblaze-generic MicroBlaze 894 microblaze-generic MicroBlaze
891 895
892 ######################################################################### 896 #########################################################################
893 # Coldfire Systems: # 897 # Coldfire Systems: #
894 # # 898 # #
895 # Maintainer Name, Email Address # 899 # Maintainer Name, Email Address #
896 # Board CPU # 900 # Board CPU #
897 ######################################################################### 901 #########################################################################
898 902
899 Hayden Fraser <Hayden.Fraser@freescale.com> 903 Hayden Fraser <Hayden.Fraser@freescale.com>
900 904
901 M5253EVBE mcf52x2 905 M5253EVBE mcf52x2
902 906
903 Matthias Fuchs <matthias.fuchs@esd-electronics.com> 907 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
904 908
905 TASREG MCF5249 909 TASREG MCF5249
906 910
907 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 911 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
908 912
909 M52277EVB mcf5227x 913 M52277EVB mcf5227x
910 M5235EVB mcf52x2 914 M5235EVB mcf52x2
911 M5253DEMO mcf52x2 915 M5253DEMO mcf52x2
912 M53017EVB mcf532x 916 M53017EVB mcf532x
913 M5329EVB mcf532x 917 M5329EVB mcf532x
914 M5373EVB mcf532x 918 M5373EVB mcf532x
915 M54455EVB mcf5445x 919 M54455EVB mcf5445x
916 M5475EVB mcf547x_8x 920 M5475EVB mcf547x_8x
917 M5485EVB mcf547x_8x 921 M5485EVB mcf547x_8x
918 922
919 Wolfgang Wegner <w.wegner@astro-kom.de> 923 Wolfgang Wegner <w.wegner@astro-kom.de>
920 924
921 astro_mcf5373l MCF5373L 925 astro_mcf5373l MCF5373L
922 926
923 ######################################################################### 927 #########################################################################
924 # AVR32 Systems: # 928 # AVR32 Systems: #
925 # # 929 # #
926 # Maintainer Name, Email Address # 930 # Maintainer Name, Email Address #
927 # Board CPU # 931 # Board CPU #
928 ######################################################################### 932 #########################################################################
929 933
930 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> 934 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
931 935
932 FAVR-32-EZKIT AT32AP7000 936 FAVR-32-EZKIT AT32AP7000
933 937
934 Mark Jackson <mpfj@mimc.co.uk> 938 Mark Jackson <mpfj@mimc.co.uk>
935 939
936 MIMC200 AT32AP7000 940 MIMC200 AT32AP7000
937 941
938 Alex Raimondi <alex.raimondi@miromico.ch> 942 Alex Raimondi <alex.raimondi@miromico.ch>
939 Julien May <julien.may@miromico.ch> 943 Julien May <julien.may@miromico.ch>
940 944
941 HAMMERHEAD AT32AP7000 945 HAMMERHEAD AT32AP7000
942 946
943 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 947 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
944 948
945 ATSTK1000 AT32AP7xxx 949 ATSTK1000 AT32AP7xxx
946 ATSTK1002 AT32AP7000 950 ATSTK1002 AT32AP7000
947 ATSTK1003 AT32AP7001 951 ATSTK1003 AT32AP7001
948 ATSTK1004 AT32AP7002 952 ATSTK1004 AT32AP7002
949 ATSTK1006 AT32AP7000 953 ATSTK1006 AT32AP7000
950 ATNGW100 AT32AP7000 954 ATNGW100 AT32AP7000
951 955
952 ######################################################################### 956 #########################################################################
953 # SuperH Systems: # 957 # SuperH Systems: #
954 # # 958 # #
955 # Maintainer Name, Email Address # 959 # Maintainer Name, Email Address #
956 # Board CPU # 960 # Board CPU #
957 ######################################################################### 961 #########################################################################
958 962
959 Yusuke Goda <goda.yusuke@renesas.com> 963 Yusuke Goda <goda.yusuke@renesas.com>
960 964
961 MIGO-R SH7722 965 MIGO-R SH7722
962 966
963 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 967 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
964 <iwamatsu.nobuhiro@renesas.com> 968 <iwamatsu.nobuhiro@renesas.com>
965 969
966 MS7750SE SH7750 970 MS7750SE SH7750
967 MS7722SE SH7722 971 MS7722SE SH7722
968 R7780MP SH7780 972 R7780MP SH7780
969 R2DPlus SH7751R 973 R2DPlus SH7751R
970 SH7763RDP SH7763 974 SH7763RDP SH7763
971 RSK7203 SH7203 975 RSK7203 SH7203
972 AP325RXA SH7723 976 AP325RXA SH7723
973 977
974 Mark Jonas <mark.jonas@de.bosch.com> 978 Mark Jonas <mark.jonas@de.bosch.com>
975 979
976 mpr2 SH7720 980 mpr2 SH7720
977 981
978 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 982 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
979 983
980 MS7720SE SH7720 984 MS7720SE SH7720
981 R0P77850011RL SH7785 985 R0P77850011RL SH7785
982 986
983 ######################################################################### 987 #########################################################################
984 # Blackfin Systems: # 988 # Blackfin Systems: #
985 # # 989 # #
986 # Maintainer Name, Email Address # 990 # Maintainer Name, Email Address #
987 # Board CPU # 991 # Board CPU #
988 ######################################################################### 992 #########################################################################
989 993
990 Mike Frysinger <vapier@gentoo.org> 994 Mike Frysinger <vapier@gentoo.org>
991 Blackfin Team <u-boot-devel@blackfin.uclinux.org> 995 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
992 996
993 BF518F-EZBRD BF518 997 BF518F-EZBRD BF518
994 BF526-EZBRD BF526 998 BF526-EZBRD BF526
995 BF527-EZKIT BF527 999 BF527-EZKIT BF527
996 BF527-EZKIT-V2 BF527 1000 BF527-EZKIT-V2 BF527
997 BF527-SDP BF527 1001 BF527-SDP BF527
998 BF533-EZKIT BF533 1002 BF533-EZKIT BF533
999 BF533-STAMP BF533 1003 BF533-STAMP BF533
1000 BF537-PNAV BF537 1004 BF537-PNAV BF537
1001 BF537-STAMP BF537 1005 BF537-STAMP BF537
1002 BF538F-EZKIT BF538 1006 BF538F-EZKIT BF538
1003 BF548-EZKIT BF548 1007 BF548-EZKIT BF548
1004 BF561-EZKIT BF561 1008 BF561-EZKIT BF561
1005 1009
1006 BF527-AD7160-EVAL BF527 1010 BF527-AD7160-EVAL BF527
1007 1011
1008 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 1012 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
1009 Blackfin Team <u-boot-devel@blackfin.uclinux.org> 1013 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
1010 1014
1011 CM-BF527 BF527 1015 CM-BF527 BF527
1012 CM-BF533 BF533 1016 CM-BF533 BF533
1013 CM-BF537E BF537 1017 CM-BF537E BF537
1014 CM-BF537U BF537 1018 CM-BF537U BF537
1015 CM-BF548 BF548 1019 CM-BF548 BF548
1016 CM-BF561 BF561 1020 CM-BF561 BF561
1017 TCM-BF518 BF518 1021 TCM-BF518 BF518
1018 TCM-BF537 BF537 1022 TCM-BF537 BF537
1019 1023
1020 Martin Strubel <strubel@section5.ch> 1024 Martin Strubel <strubel@section5.ch>
1021 Blackfin Team <u-boot-devel@blackfin.uclinux.org> 1025 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
1022 1026
1023 BF537-minotaur BF537 1027 BF537-minotaur BF537
1024 BF537-srv1 BF537 1028 BF537-srv1 BF537
1025 1029
1026 Wojtek Skulski <skulski@pas.rochester.edu> 1030 Wojtek Skulski <skulski@pas.rochester.edu>
1027 Wojtek Skulski <info@skutek.com> 1031 Wojtek Skulski <info@skutek.com>
1028 Blackfin Team <u-boot-devel@blackfin.uclinux.org> 1032 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
1029 Benjamin Matthews <mben12@gmail.com> 1033 Benjamin Matthews <mben12@gmail.com>
1030 1034
1031 BlackStamp BF533 1035 BlackStamp BF533
1032 BlackVME BF561 1036 BlackVME BF561
1033 1037
1034 I-SYST Micromodule <support@i-syst.com> 1038 I-SYST Micromodule <support@i-syst.com>
1035 Blackfin Team <u-boot-devel@blackfin.uclinux.org> 1039 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
1036 1040
1037 IBF-DSP561 BF561 1041 IBF-DSP561 BF561
1038 1042
1039 Valentin Yakovenkov <yakovenkov@niistt.ru> 1043 Valentin Yakovenkov <yakovenkov@niistt.ru>
1040 Anton Shurpin <shurpin.aa@niistt.ru> 1044 Anton Shurpin <shurpin.aa@niistt.ru>
1041 1045
1042 BF561-ACVILON BF561 1046 BF561-ACVILON BF561
1043 1047
1044 Brent Kandetzki <brentk@teleco.com> 1048 Brent Kandetzki <brentk@teleco.com>
1045 1049
1046 IP04 BF532 1050 IP04 BF532
1047 1051
1048 Peter Meerwald <devel@bct-electronic.com> 1052 Peter Meerwald <devel@bct-electronic.com>
1049 1053
1050 bct-brettl2 BF536 1054 bct-brettl2 BF536
1051 1055
board/a4m072/Makefile
Diff comments   View file @ 9531a23
File was created 1 #
2 # (C) Copyright 2003-2006
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 #
5 # See file CREDITS for list of people who contributed to this
6 # project.
7 #
8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version.
12 #
13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details.
17 #
18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 # MA 02111-1307 USA
22 #
23
24 include $(TOPDIR)/config.mk
25
26 LIB = $(obj)lib$(BOARD).a
27
28 COBJS := $(BOARD).o
29
30 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31 OBJS := $(addprefix $(obj),$(COBJS))
32 SOBJS := $(addprefix $(obj),$(SOBJS))
33
34 $(LIB): $(obj).depend $(OBJS)
35 $(AR) $(ARFLAGS) $@ $(OBJS)
36
37 clean:
38 rm -f $(SOBJS) $(OBJS)
39
40 distclean: clean
41 rm -f $(LIB) core *.bak $(obj).depend
42
43 #########################################################################
44
45 # defines $(obj).depend target
46 include $(SRCTREE)/rules.mk
47
48 sinclude $(obj).depend
49
50 #########################################################################
51
board/a4m072/a4m072.c
Diff comments   View file @ 9531a23
File was created 1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2010
9 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30 #include <common.h>
31 #include <mpc5xxx.h>
32 #include <pci.h>
33 #include <asm/processor.h>
34 #include <asm/io.h>
35 #include <libfdt.h>
36 #include <netdev.h>
37
38 #include "mt46v32m16.h"
39
40 #ifndef CONFIG_SYS_RAMBOOT
41 static void sdram_start (int hi_addr)
42 {
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 long control = SDRAM_CONTROL | hi_addr_bit;
45
46 /* unlock mode register */
47 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
48 __asm__ volatile ("sync");
49
50 /* precharge all banks */
51 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
52 __asm__ volatile ("sync");
53
54 #if SDRAM_DDR
55 /* set mode register: extended mode */
56 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
57 __asm__ volatile ("sync");
58
59 /* set mode register: reset DLL */
60 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
61 __asm__ volatile ("sync");
62 #endif
63
64 /* precharge all banks */
65 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
66 __asm__ volatile ("sync");
67
68 /* auto refresh */
69 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
70 __asm__ volatile ("sync");
71
72 /* set mode register */
73 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
74 __asm__ volatile ("sync");
75
76 /* normal operation */
77 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
78 __asm__ volatile ("sync");
79 }
80 #endif
81
82 /*
83 * ATTENTION: Although partially referenced initdram does NOT make real use
84 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
85 * is something else than 0x00000000.
86 */
87
88 phys_size_t initdram (int board_type)
89 {
90 ulong dramsize = 0;
91 uint svr, pvr;
92
93 #ifndef CONFIG_SYS_RAMBOOT
94 ulong test1, test2;
95
96 /* setup SDRAM chip selects */
97 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
98 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
99 __asm__ volatile ("sync");
100
101 /* setup config registers */
102 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
103 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
104 __asm__ volatile ("sync");
105
106 #if SDRAM_DDR
107 /* set tap delay */
108 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
109 __asm__ volatile ("sync");
110 #endif
111
112 /* find RAM size using SDRAM CS0 only */
113 sdram_start(0);
114 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
115 sdram_start(1);
116 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
117 if (test1 > test2) {
118 sdram_start(0);
119 dramsize = test1;
120 } else {
121 dramsize = test2;
122 }
123
124 /* memory smaller than 1MB is impossible */
125 if (dramsize < (1 << 20)) {
126 dramsize = 0;
127 }
128
129 /* set SDRAM CS0 size according to the amount of RAM found */
130 if (dramsize > 0) {
131 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
132 0x13 + __builtin_ffs(dramsize >> 20) - 1);
133 } else {
134 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
135 }
136
137 #else /* CONFIG_SYS_RAMBOOT */
138
139 /* retrieve size of memory connected to SDRAM CS0 */
140 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
141 if (dramsize >= 0x13) {
142 dramsize = (1 << (dramsize - 0x13)) << 20;
143 } else {
144 dramsize = 0;
145 }
146
147 #endif /* CONFIG_SYS_RAMBOOT */
148
149 /*
150 * On MPC5200B we need to set the special configuration delay in the
151 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
152 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
153 *
154 * "The SDelay should be written to a value of 0x00000004. It is
155 * required to account for changes caused by normal wafer processing
156 * parameters."
157 */
158 svr = get_svr();
159 pvr = get_pvr();
160 if ((SVR_MJREV(svr) >= 2) &&
161 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
162
163 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
164 __asm__ volatile ("sync");
165 }
166
167 return dramsize;
168 }
169
170 int checkboard (void)
171 {
172 puts ("Board: A4M072\n");
173 return 0;
174 }
175
176 #ifdef CONFIG_PCI
177 static struct pci_controller hose;
178
179 extern void pci_mpc5xxx_init(struct pci_controller *);
180
181 void pci_init_board(void)
182 {
183 pci_mpc5xxx_init(&hose);
184 }
185 #endif
186
187 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
188 void
189 ft_board_setup(void *blob, bd_t *bd)
190 {
191 ft_cpu_setup(blob, bd);
192 }
193 #endif
194
195 int board_eth_init(bd_t *bis)
196 {
197 int rv, num_if = 0;
198
199 /* Initialize TSECs first */
200 if ((rv = cpu_eth_init(bis)) >= 0)
201 num_if += rv;
202 else
203 printf("ERROR: failed to initialize FEC.\n");
204
205 if ((rv = pci_eth_init(bis)) >= 0)
206 num_if += rv;
207 else
208 printf("ERROR: failed to initialize PCI Ethernet.\n");
209
210 return num_if;
211 }
212 /*
213 * Miscellaneous late-boot configurations
214 *
215 * Initialize EEPROM write-protect GPIO pin.
216 */
217 int misc_init_r(void)
218 {
219 #if defined(CONFIG_SYS_EEPROM_WREN)
220 /* Enable GPIO pin */
221 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
222 /* Set direction, output */
223 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
224 /* De-assert write enable */
225 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
226 #endif
227 return 0;
228 }
229 #if defined(CONFIG_SYS_EEPROM_WREN)
230 /* Input: <dev_addr> I2C address of EEPROM device to enable.
231 * <state> -1: deliver current state
232 * 0: disable write
233 * 1: enable write
234 * Returns: -1: wrong device address
235 * 0: dis-/en- able done
236 * 0/1: current state if <state> was -1.
237 */
238 int eeprom_write_enable (unsigned dev_addr, int state)
239 {
240 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
241 return -1;
242 } else {
243 switch (state) {
244 case 1:
245 /* Enable write access */
246 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
247 state = 0;
248 break;
249 case 0:
250 /* Disable write access */
251 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
252 state = 0;
253 break;
254 default:
255 /* Read current status back. */
256 state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
257 CONFIG_SYS_EEPROM_WP));
258 break;
259 }
260 }
261 return state;
262 }
263 #endif
264
board/a4m072/config.mk
Diff comments   View file @ 9531a23
File was created 1 #
2 # (C) Copyright 2003
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 #
5 # See file CREDITS for list of people who contributed to this
6 # project.
7 #
8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version.
12 #
13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details.
17 #
18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 # MA 02111-1307 USA
22 #
23
24 #
25 # a4m072 board:
26 #
27 # Valid values for TEXT_BASE is:
28 #
29 # 0xFE000000 boot low
30 #
31
32 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
33
34 ifndef TEXT_BASE
35 ## Standard: boot low
36 TEXT_BASE = 0xFE000000
37 endif
38
39 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
40
board/a4m072/mt46v32m16.h
Diff comments   View file @ 9531a23
File was created 1 /*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #define SDRAM_DDR 1 /* is DDR */
25
26 #if defined(CONFIG_MPC5200)
27 /* Settings for XLB = 132 MHz */
28 #define SDRAM_MODE 0x018D0000
29 #define SDRAM_EMODE 0x40010000
30 #define SDRAM_CONTROL 0x704f0f00
31 #define SDRAM_CONFIG1 0x73722930
32 #define SDRAM_CONFIG2 0x47770000
33 #define SDRAM_TAPDELAY 0x10000000
34
35 #else
36 #error CONFIG_MPC5200 not defined
37 #endif
38
1 # 1 #
2 # List of boards 2 # List of boards
3 # 3 #
4 # Syntax: 4 # Syntax:
5 # white-space separated list of entries; 5 # white-space separated list of entries;
6 # each entry has the following fields: 6 # each entry has the following fields:
7 # 7 #
8 # Targetname Architecture CPU Boardname Vendor SoC 8 # Targetname Architecture CPU Boardname Vendor SoC
9 # 9 #
10 # Unused fields can be specified as "-", or omitted if they 10 # Unused fields can be specified as "-", or omitted if they
11 # are the last field on the line. 11 # are the last field on the line.
12 # 12 #
13 # Lines starting with '#' are comments. 13 # Lines starting with '#' are comments.
14 # Blank lines are ignored. 14 # Blank lines are ignored.
15 # 15 #
16 # To keep the list sorted, use something like 16 # To keep the list sorted, use something like
17 # 17 #
18 # :.,$! sort -f -k2,2 -k3,3 -k6,6 -k5,5 -k1,1 18 # :.,$! sort -f -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
19 # 19 #
20 # Target ARCH CPU Board name Vendor SoC 20 # Target ARCH CPU Board name Vendor SoC
21 ########################################################################### 21 ###########################################################################
22 22
23 qong arm arm1136 - davedenx mx31 23 qong arm arm1136 - davedenx mx31
24 mx31ads arm arm1136 - freescale mx31 24 mx31ads arm arm1136 - freescale mx31
25 ep7312 arm arm720t 25 ep7312 arm arm720t
26 impa7 arm arm720t 26 impa7 arm arm720t
27 SMN42 arm arm720t - siemens lpc2292 27 SMN42 arm arm720t - siemens lpc2292
28 evb4510 arm arm720t - - s3c4510b 28 evb4510 arm arm720t - - s3c4510b
29 a320evb arm arm920t - faraday a320 29 a320evb arm arm920t - faraday a320
30 cmc_pu2 arm arm920t - - at91rm9200 30 cmc_pu2 arm arm920t - - at91rm9200
31 csb637 arm arm920t - - at91rm9200 31 csb637 arm arm920t - - at91rm9200
32 kb9202 arm arm920t - - at91rm9200 32 kb9202 arm arm920t - - at91rm9200
33 m501sk arm arm920t - - at91rm9200 33 m501sk arm arm920t - - at91rm9200
34 mp2usb arm arm920t - - at91rm9200 34 mp2usb arm arm920t - - at91rm9200
35 mx1ads arm arm920t - - imx 35 mx1ads arm arm920t - - imx
36 mx1fs2 arm arm920t - - imx 36 mx1fs2 arm arm920t - - imx
37 scb9328 arm arm920t - - imx 37 scb9328 arm arm920t - - imx
38 cm4008 arm arm920t - - ks8695 38 cm4008 arm arm920t - - ks8695
39 cm41xx arm arm920t - - ks8695 39 cm41xx arm arm920t - - ks8695
40 VCMA9 arm arm920t vcma9 mpl s3c24x0 40 VCMA9 arm arm920t vcma9 mpl s3c24x0
41 netstar arm arm925t 41 netstar arm arm925t
42 meesc arm arm926ejs - esd at91 42 meesc arm arm926ejs - esd at91
43 otc570 arm arm926ejs - esd at91 43 otc570 arm arm926ejs - esd at91
44 pm9261 arm arm926ejs - ronetix at91 44 pm9261 arm arm926ejs - ronetix at91
45 pm9263 arm arm926ejs - ronetix at91 45 pm9263 arm arm926ejs - ronetix at91
46 jadecpu arm arm926ejs jadecpu syteco mb86r0x 46 jadecpu arm arm926ejs jadecpu syteco mb86r0x
47 suen3 arm arm926ejs km_arm keymile kirkwood 47 suen3 arm arm926ejs km_arm keymile kirkwood
48 rd6281a arm arm926ejs - Marvell kirkwood 48 rd6281a arm arm926ejs - Marvell kirkwood
49 mx51evk arm armv7 mx51evk freescale mx51 49 mx51evk arm armv7 mx51evk freescale mx51
50 actux1 arm ixp 50 actux1 arm ixp
51 actux2 arm ixp 51 actux2 arm ixp
52 actux3 arm ixp 52 actux3 arm ixp
53 actux4 arm ixp 53 actux4 arm ixp
54 ixdp425 arm ixp 54 ixdp425 arm ixp
55 cerf250 arm pxa 55 cerf250 arm pxa
56 colibri_pxa270 arm pxa 56 colibri_pxa270 arm pxa
57 cradle arm pxa 57 cradle arm pxa
58 csb226 arm pxa 58 csb226 arm pxa
59 delta arm pxa 59 delta arm pxa
60 innokom arm pxa 60 innokom arm pxa
61 logodl arm pxa 61 logodl arm pxa
62 lubbock arm pxa 62 lubbock arm pxa
63 pleb2 arm pxa 63 pleb2 arm pxa
64 xaeniax arm pxa 64 xaeniax arm pxa
65 xm250 arm pxa 65 xm250 arm pxa
66 zipitz2 arm pxa 66 zipitz2 arm pxa
67 B2 arm s3c44b0 - dave 67 B2 arm s3c44b0 - dave
68 assabet arm sa1100 68 assabet arm sa1100
69 dnp1110 arm sa1100 69 dnp1110 arm sa1100
70 gcplus arm sa1100 70 gcplus arm sa1100
71 lart arm sa1100 71 lart arm sa1100
72 shannon arm sa1100 72 shannon arm sa1100
73 mimc200 avr32 at32ap - mimc at32ap700x 73 mimc200 avr32 at32ap - mimc at32ap700x
74 eNET i386 i386 - - sc520 74 eNET i386 i386 - - sc520
75 idmr m68k mcf52x2 75 idmr m68k mcf52x2
76 TASREG m68k mcf52x2 tasreg esd 76 TASREG m68k mcf52x2 tasreg esd
77 M5272C3 m68k mcf52x2 m5272c3 freescale 77 M5272C3 m68k mcf52x2 m5272c3 freescale
78 EP2500 m68k mcf52x2 ep2500 Mercury 78 EP2500 m68k mcf52x2 ep2500 Mercury
79 purple mips mips 79 purple mips mips
80 tb0229 mips mips 80 tb0229 mips mips
81 PCI5441 nios2 nios2 pci5441 psyent 81 PCI5441 nios2 nios2 pci5441 psyent
82 PK1C20 nios2 nios2 pk1c20 psyent 82 PK1C20 nios2 nios2 pk1c20 psyent
83 P3G4 powerpc 74xx_7xx evb64260 83 P3G4 powerpc 74xx_7xx evb64260
84 ppmc7xx powerpc 74xx_7xx 84 ppmc7xx powerpc 74xx_7xx
85 ZUMA powerpc 74xx_7xx evb64260 85 ZUMA powerpc 74xx_7xx evb64260
86 BAB7xx powerpc 74xx_7xx bab7xx eltec 86 BAB7xx powerpc 74xx_7xx bab7xx eltec
87 ELPPC powerpc 74xx_7xx elppc eltec 87 ELPPC powerpc 74xx_7xx elppc eltec
88 CPCI750 powerpc 74xx_7xx cpci750 esd 88 CPCI750 powerpc 74xx_7xx cpci750 esd
89 DB64360 powerpc 74xx_7xx db64360 Marvell 89 DB64360 powerpc 74xx_7xx db64360 Marvell
90 DB64460 powerpc 74xx_7xx db64460 Marvell 90 DB64460 powerpc 74xx_7xx db64460 Marvell
91 aria powerpc mpc512x - davedenx 91 aria powerpc mpc512x - davedenx
92 PATI powerpc mpc5xx pati mpl 92 PATI powerpc mpc5xx pati mpl
93 a4m072 powerpc mpc5xxx a4m072
93 BC3450 powerpc mpc5xxx bc3450 94 BC3450 powerpc mpc5xxx bc3450
94 canmb powerpc mpc5xxx 95 canmb powerpc mpc5xxx
95 cm5200 powerpc mpc5xxx 96 cm5200 powerpc mpc5xxx
96 hmi1001 powerpc mpc5xxx - manroland 97 hmi1001 powerpc mpc5xxx - manroland
97 inka4x0 powerpc mpc5xxx 98 inka4x0 powerpc mpc5xxx
98 ipek01 powerpc mpc5xxx 99 ipek01 powerpc mpc5xxx
99 jupiter powerpc mpc5xxx 100 jupiter powerpc mpc5xxx
100 mucmc52 powerpc mpc5xxx - manroland 101 mucmc52 powerpc mpc5xxx - manroland
101 munices powerpc mpc5xxx 102 munices powerpc mpc5xxx
102 o2dnt powerpc mpc5xxx 103 o2dnt powerpc mpc5xxx
103 uc101 powerpc mpc5xxx - manroland 104 uc101 powerpc mpc5xxx - manroland
104 v38b powerpc mpc5xxx 105 v38b powerpc mpc5xxx
105 pf5200 powerpc mpc5xxx - esd 106 pf5200 powerpc mpc5xxx - esd
106 aev powerpc mpc5xxx tqm5200 tqc 107 aev powerpc mpc5xxx tqm5200 tqc
107 sorcery powerpc mpc8220 108 sorcery powerpc mpc8220
108 A3000 powerpc mpc824x a3000 109 A3000 powerpc mpc824x a3000
109 barco powerpc mpc824x 110 barco powerpc mpc824x
110 BMW powerpc mpc824x bmw 111 BMW powerpc mpc824x bmw
111 CU824 powerpc mpc824x cu824 112 CU824 powerpc mpc824x cu824
112 MOUSSE powerpc mpc824x mousse 113 MOUSSE powerpc mpc824x mousse
113 MUSENKI powerpc mpc824x musenki 114 MUSENKI powerpc mpc824x musenki
114 MVBLUE powerpc mpc824x mvblue 115 MVBLUE powerpc mpc824x mvblue
115 OXC powerpc mpc824x oxc 116 OXC powerpc mpc824x oxc
116 PN62 powerpc mpc824x pn62 117 PN62 powerpc mpc824x pn62
117 sbc8240 powerpc mpc824x 118 sbc8240 powerpc mpc824x
118 utx8245 powerpc mpc824x 119 utx8245 powerpc mpc824x
119 debris powerpc mpc824x - etin 120 debris powerpc mpc824x - etin
120 kvme080 powerpc mpc824x - etin 121 kvme080 powerpc mpc824x - etin
121 atc powerpc mpc8260 122 atc powerpc mpc8260
122 ep8260 powerpc mpc8260 123 ep8260 powerpc mpc8260
123 ep82xxm powerpc mpc8260 124 ep82xxm powerpc mpc8260
124 gw8260 powerpc mpc8260 125 gw8260 powerpc mpc8260
125 hymod powerpc mpc8260 126 hymod powerpc mpc8260
126 IDS8247 powerpc mpc8260 ids8247 127 IDS8247 powerpc mpc8260 ids8247
127 sacsng powerpc mpc8260 128 sacsng powerpc mpc8260
128 sbc8260 powerpc mpc8260 129 sbc8260 powerpc mpc8260
129 ZPC1900 powerpc mpc8260 zpc1900 130 ZPC1900 powerpc mpc8260 zpc1900
130 mgcoge powerpc mpc8260 - keymile 131 mgcoge powerpc mpc8260 - keymile
131 SCM powerpc mpc8260 - siemens 132 SCM powerpc mpc8260 - siemens
132 TQM8272 powerpc mpc8260 tqm8272 tqc 133 TQM8272 powerpc mpc8260 tqm8272 tqc
133 ve8313 powerpc mpc83xx ve8313 134 ve8313 powerpc mpc83xx ve8313
134 kmeter1 powerpc mpc83xx kmeter1 keymile 135 kmeter1 powerpc mpc83xx kmeter1 keymile
135 MVBLM7 powerpc mpc83xx mvblm7 matrix_vision 136 MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
136 TQM834x powerpc mpc83xx tqm834x tqc 137 TQM834x powerpc mpc83xx tqm834x tqc
137 PM854 powerpc mpc85xx pm854 138 PM854 powerpc mpc85xx pm854
138 PM856 powerpc mpc85xx pm856 139 PM856 powerpc mpc85xx pm856
139 stxgp3 powerpc mpc85xx stxgp3 stx 140 stxgp3 powerpc mpc85xx stxgp3 stx
140 c2mon powerpc mpc8xx 141 c2mon powerpc mpc8xx
141 EP88x powerpc mpc8xx ep88x 142 EP88x powerpc mpc8xx ep88x
142 ETX094 powerpc mpc8xx etx094 143 ETX094 powerpc mpc8xx etx094
143 FLAGADM powerpc mpc8xx flagadm 144 FLAGADM powerpc mpc8xx flagadm
144 GENIETV powerpc mpc8xx genietv 145 GENIETV powerpc mpc8xx genietv
145 hermes powerpc mpc8xx 146 hermes powerpc mpc8xx
146 IP860 powerpc mpc8xx ip860 147 IP860 powerpc mpc8xx ip860
147 LANTEC powerpc mpc8xx lantec 148 LANTEC powerpc mpc8xx lantec
148 lwmon powerpc mpc8xx 149 lwmon powerpc mpc8xx
149 NX823 powerpc mpc8xx nx823 150 NX823 powerpc mpc8xx nx823
150 quantum powerpc mpc8xx 151 quantum powerpc mpc8xx
151 R360MPI powerpc mpc8xx r360mpi 152 R360MPI powerpc mpc8xx r360mpi
152 RBC823 powerpc mpc8xx rbc823 153 RBC823 powerpc mpc8xx rbc823
153 rmu powerpc mpc8xx 154 rmu powerpc mpc8xx
154 RPXlite powerpc mpc8xx 155 RPXlite powerpc mpc8xx
155 spc1920 powerpc mpc8xx 156 spc1920 powerpc mpc8xx
156 uc100 powerpc mpc8xx - manroland 157 uc100 powerpc mpc8xx - manroland
157 MHPC powerpc mpc8xx mhpc eltec 158 MHPC powerpc mpc8xx mhpc eltec
158 TOP860 powerpc mpc8xx top860 emk 159 TOP860 powerpc mpc8xx top860 emk
159 kmsupx4 powerpc mpc8xx km8xx keymile 160 kmsupx4 powerpc mpc8xx km8xx keymile
160 mgsuvd powerpc mpc8xx km8xx keymile 161 mgsuvd powerpc mpc8xx km8xx keymile
161 KUP4K powerpc mpc8xx kup4k kup 162 KUP4K powerpc mpc8xx kup4k kup
162 KUP4X powerpc mpc8xx kup4x kup 163 KUP4X powerpc mpc8xx kup4x kup
163 ELPT860 powerpc mpc8xx elpt860 LEOX 164 ELPT860 powerpc mpc8xx elpt860 LEOX
164 IAD210 powerpc mpc8xx - siemens 165 IAD210 powerpc mpc8xx - siemens
165 QS823 powerpc mpc8xx qs850 snmc 166 QS823 powerpc mpc8xx qs850 snmc
166 QS850 powerpc mpc8xx qs850 snmc 167 QS850 powerpc mpc8xx qs850 snmc
167 QS860T powerpc mpc8xx qs860t snmc 168 QS860T powerpc mpc8xx qs860t snmc
168 stxxtc powerpc mpc8xx stxxtc stx 169 stxxtc powerpc mpc8xx stxxtc stx
169 SM850 powerpc mpc8xx tqm8xx tqc 170 SM850 powerpc mpc8xx tqm8xx tqc
170 AMX860 powerpc mpc8xx amx860 westel 171 AMX860 powerpc mpc8xx amx860 westel
171 csb272 powerpc ppc4xx 172 csb272 powerpc ppc4xx
172 csb472 powerpc ppc4xx 173 csb472 powerpc ppc4xx
173 ERIC powerpc ppc4xx eric 174 ERIC powerpc ppc4xx eric
174 G2000 powerpc ppc4xx g2000 175 G2000 powerpc ppc4xx g2000
175 JSE powerpc ppc4xx jse 176 JSE powerpc ppc4xx jse
176 korat powerpc ppc4xx 177 korat powerpc ppc4xx
177 lwmon5 powerpc ppc4xx 178 lwmon5 powerpc ppc4xx
178 ML2 powerpc ppc4xx ml2 179 ML2 powerpc ppc4xx ml2
179 sbc405 powerpc ppc4xx 180 sbc405 powerpc ppc4xx
180 sc3 powerpc ppc4xx 181 sc3 powerpc ppc4xx
181 t3corp powerpc ppc4xx 182 t3corp powerpc ppc4xx
182 zeus powerpc ppc4xx 183 zeus powerpc ppc4xx
183 acadia powerpc ppc4xx - amcc 184 acadia powerpc ppc4xx - amcc
184 bamboo powerpc ppc4xx - amcc 185 bamboo powerpc ppc4xx - amcc
185 bluestone powerpc ppc4xx - amcc 186 bluestone powerpc ppc4xx - amcc
186 bubinga powerpc ppc4xx - amcc 187 bubinga powerpc ppc4xx - amcc
187 ebony powerpc ppc4xx - amcc 188 ebony powerpc ppc4xx - amcc
188 katmai powerpc ppc4xx - amcc 189 katmai powerpc ppc4xx - amcc
189 luan powerpc ppc4xx - amcc 190 luan powerpc ppc4xx - amcc
190 makalu powerpc ppc4xx - amcc 191 makalu powerpc ppc4xx - amcc
191 ocotea powerpc ppc4xx - amcc 192 ocotea powerpc ppc4xx - amcc
192 redwood powerpc ppc4xx - amcc 193 redwood powerpc ppc4xx - amcc
193 taihu powerpc ppc4xx - amcc 194 taihu powerpc ppc4xx - amcc
194 taishan powerpc ppc4xx - amcc 195 taishan powerpc ppc4xx - amcc
195 yucca powerpc ppc4xx - amcc 196 yucca powerpc ppc4xx - amcc
196 AP1000 powerpc ppc4xx ap1000 amirix 197 AP1000 powerpc ppc4xx ap1000 amirix
197 CRAYL1 powerpc ppc4xx L1 cray 198 CRAYL1 powerpc ppc4xx L1 cray
198 ADCIOP powerpc ppc4xx adciop esd 199 ADCIOP powerpc ppc4xx adciop esd
199 APC405 powerpc ppc4xx apc405 esd 200 APC405 powerpc ppc4xx apc405 esd
200 AR405 powerpc ppc4xx ar405 esd 201 AR405 powerpc ppc4xx ar405 esd
201 ASH405 powerpc ppc4xx ash405 esd 202 ASH405 powerpc ppc4xx ash405 esd
202 CANBT powerpc ppc4xx canbt esd 203 CANBT powerpc ppc4xx canbt esd
203 CMS700 powerpc ppc4xx cms700 esd 204 CMS700 powerpc ppc4xx cms700 esd
204 CPCI2DP powerpc ppc4xx cpci2dp esd 205 CPCI2DP powerpc ppc4xx cpci2dp esd
205 DP405 powerpc ppc4xx dp405 esd 206 DP405 powerpc ppc4xx dp405 esd
206 DU405 powerpc ppc4xx du405 esd 207 DU405 powerpc ppc4xx du405 esd
207 DU440 powerpc ppc4xx du440 esd 208 DU440 powerpc ppc4xx du440 esd
208 HH405 powerpc ppc4xx hh405 esd 209 HH405 powerpc ppc4xx hh405 esd
209 HUB405 powerpc ppc4xx hub405 esd 210 HUB405 powerpc ppc4xx hub405 esd
210 PCI405 powerpc ppc4xx pci405 esd 211 PCI405 powerpc ppc4xx pci405 esd
211 PLU405 powerpc ppc4xx plu405 esd 212 PLU405 powerpc ppc4xx plu405 esd
212 PMC405 powerpc ppc4xx pmc405 esd 213 PMC405 powerpc ppc4xx pmc405 esd
213 PMC440 powerpc ppc4xx pmc440 esd 214 PMC440 powerpc ppc4xx pmc440 esd
214 VOH405 powerpc ppc4xx voh405 esd 215 VOH405 powerpc ppc4xx voh405 esd
215 VOM405 powerpc ppc4xx vom405 esd 216 VOM405 powerpc ppc4xx vom405 esd
216 WUH405 powerpc ppc4xx wuh405 esd 217 WUH405 powerpc ppc4xx wuh405 esd
217 neo powerpc ppc4xx - gdsys 218 neo powerpc ppc4xx - gdsys
218 icon powerpc ppc4xx - mosaixtech 219 icon powerpc ppc4xx - mosaixtech
219 MIP405 powerpc ppc4xx mip405 mpl 220 MIP405 powerpc ppc4xx mip405 mpl
220 PIP405 powerpc ppc4xx pip405 mpl 221 PIP405 powerpc ppc4xx pip405 mpl
221 alpr powerpc ppc4xx - prodrive 222 alpr powerpc ppc4xx - prodrive
222 p3p440 powerpc ppc4xx - prodrive 223 p3p440 powerpc ppc4xx - prodrive
223 KAREF powerpc ppc4xx karef sandburst 224 KAREF powerpc ppc4xx karef sandburst
224 grsim sparc leon3 - gaisler 225 grsim sparc leon3 - gaisler
225 imx31_litekit arm arm1136 - logicpd mx31 226 imx31_litekit arm arm1136 - logicpd mx31
226 omap2420h4 arm arm1136 - ti omap24xx 227 omap2420h4 arm arm1136 - ti omap24xx
227 tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x 228 tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
228 armadillo arm arm720t 229 armadillo arm arm720t
229 modnet50 arm arm720t 230 modnet50 arm arm720t
230 lpc2292sodimm arm arm720t - - lpc2292 231 lpc2292sodimm arm arm720t - - lpc2292
231 eb_cpux9k2 arm arm920t - BuS at91 232 eb_cpux9k2 arm arm920t - BuS at91
232 at91rm9200dk arm arm920t - atmel at91rm9200 233 at91rm9200dk arm arm920t - atmel at91rm9200
233 at91rm9200ek arm arm920t - atmel at91rm9200 234 at91rm9200ek arm arm920t - atmel at91rm9200
234 sbc2410x arm arm920t - - s3c24x0 235 sbc2410x arm arm920t - - s3c24x0
235 smdk2400 arm arm920t - samsung s3c24x0 236 smdk2400 arm arm920t - samsung s3c24x0
236 smdk2410 arm arm920t - samsung s3c24x0 237 smdk2410 arm arm920t - samsung s3c24x0
237 voiceblue arm arm925t 238 voiceblue arm arm925t
238 omap1510inn arm arm925t - ti 239 omap1510inn arm arm925t - ti
239 afeb9260 arm arm926ejs - - at91 240 afeb9260 arm arm926ejs - - at91
240 at91cap9adk arm arm926ejs - atmel at91 241 at91cap9adk arm arm926ejs - atmel at91
241 davinci_dvevm arm arm926ejs dvevm davinci davinci 242 davinci_dvevm arm arm926ejs dvevm davinci davinci
242 davinci_sffsdr arm arm926ejs sffsdr davinci davinci 243 davinci_sffsdr arm arm926ejs sffsdr davinci davinci
243 davinci_sonata arm arm926ejs sonata davinci davinci 244 davinci_sonata arm arm926ejs sonata davinci davinci
244 da830evm arm arm926ejs da8xxevm davinci davinci 245 da830evm arm arm926ejs da8xxevm davinci davinci
245 da850evm arm arm926ejs da8xxevm davinci davinci 246 da850evm arm arm926ejs da8xxevm davinci davinci
246 guruplug arm arm926ejs - Marvell kirkwood 247 guruplug arm arm926ejs - Marvell kirkwood
247 mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood 248 mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
248 openrd_base arm arm926ejs - Marvell kirkwood 249 openrd_base arm arm926ejs - Marvell kirkwood
249 sheevaplug arm arm926ejs - Marvell kirkwood 250 sheevaplug arm arm926ejs - Marvell kirkwood
250 imx27lite arm arm926ejs imx27lite logicpd mx27 251 imx27lite arm arm926ejs imx27lite logicpd mx27
251 magnesium arm arm926ejs imx27lite logicpd mx27 252 magnesium arm arm926ejs imx27lite logicpd mx27
252 omap5912osk arm arm926ejs - ti omap 253 omap5912osk arm arm926ejs - ti omap
253 edminiv2 arm arm926ejs - LaCie orion5x 254 edminiv2 arm arm926ejs - LaCie orion5x
254 omap3_overo arm armv7 overo - omap3 255 omap3_overo arm armv7 overo - omap3
255 omap3_pandora arm armv7 pandora - omap3 256 omap3_pandora arm armv7 pandora - omap3
256 omap3_zoom1 arm armv7 zoom1 logicpd omap3 257 omap3_zoom1 arm armv7 zoom1 logicpd omap3
257 omap3_zoom2 arm armv7 zoom2 logicpd omap3 258 omap3_zoom2 arm armv7 zoom2 logicpd omap3
258 omap3_beagle arm armv7 beagle ti omap3 259 omap3_beagle arm armv7 beagle ti omap3
259 omap3_evm arm armv7 evm ti omap3 260 omap3_evm arm armv7 evm ti omap3
260 omap3_sdp3430 arm armv7 sdp3430 ti omap3 261 omap3_sdp3430 arm armv7 sdp3430 ti omap3
261 omap4_panda arm armv7 panda ti omap4 262 omap4_panda arm armv7 panda ti omap4
262 omap4_sdp4430 arm armv7 sdp4430 ti omap4 263 omap4_sdp4430 arm armv7 sdp4430 ti omap4
263 am3517_evm arm armv7 am3517evm logicpd omap3 264 am3517_evm arm armv7 am3517evm logicpd omap3
264 devkit8000 arm armv7 devkit8000 timll omap3 265 devkit8000 arm armv7 devkit8000 timll omap3
265 s5p_goni arm armv7 goni samsung s5pc1xx 266 s5p_goni arm armv7 goni samsung s5pc1xx
266 smdkc100 arm armv7 smdkc100 samsung s5pc1xx 267 smdkc100 arm armv7 smdkc100 samsung s5pc1xx
267 ixdpg425 arm ixp 268 ixdpg425 arm ixp
268 lpd7a400 arm lh7a40x lpd7a40x 269 lpd7a400 arm lh7a40x lpd7a40x
269 lpd7a404 arm lh7a40x lpd7a40x 270 lpd7a404 arm lh7a40x lpd7a40x
270 pxa255_idp arm pxa 271 pxa255_idp arm pxa
271 wepep250 arm pxa 272 wepep250 arm pxa
272 xsengine arm pxa 273 xsengine arm pxa
273 zylonite arm pxa 274 zylonite arm pxa
274 atngw100 avr32 at32ap - atmel at32ap700x 275 atngw100 avr32 at32ap - atmel at32ap700x
275 atstk1002 avr32 at32ap atstk1000 atmel at32ap700x 276 atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
276 atstk1003 avr32 at32ap atstk1000 atmel at32ap700x 277 atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
277 atstk1004 avr32 at32ap atstk1000 atmel at32ap700x 278 atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
278 atstk1006 avr32 at32ap atstk1000 atmel at32ap700x 279 atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
279 favr-32-ezkit avr32 at32ap - earthlcd at32ap700x 280 favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
280 hammerhead avr32 at32ap - miromico at32ap700x 281 hammerhead avr32 at32ap - miromico at32ap700x
281 bct-brettl2 blackfin blackfin 282 bct-brettl2 blackfin blackfin
282 bf518f-ezbrd blackfin blackfin 283 bf518f-ezbrd blackfin blackfin
283 bf526-ezbrd blackfin blackfin 284 bf526-ezbrd blackfin blackfin
284 bf527-ad7160-eval blackfin blackfin 285 bf527-ad7160-eval blackfin blackfin
285 bf527-ezkit blackfin blackfin 286 bf527-ezkit blackfin blackfin
286 bf527-sdp blackfin blackfin 287 bf527-sdp blackfin blackfin
287 bf533-ezkit blackfin blackfin 288 bf533-ezkit blackfin blackfin
288 bf533-stamp blackfin blackfin 289 bf533-stamp blackfin blackfin
289 bf537-minotaur blackfin blackfin 290 bf537-minotaur blackfin blackfin
290 bf537-pnav blackfin blackfin 291 bf537-pnav blackfin blackfin
291 bf537-srv1 blackfin blackfin 292 bf537-srv1 blackfin blackfin
292 bf537-stamp blackfin blackfin 293 bf537-stamp blackfin blackfin
293 bf538f-ezkit blackfin blackfin 294 bf538f-ezkit blackfin blackfin
294 bf548-ezkit blackfin blackfin 295 bf548-ezkit blackfin blackfin
295 bf561-acvilon blackfin blackfin 296 bf561-acvilon blackfin blackfin
296 bf561-ezkit blackfin blackfin 297 bf561-ezkit blackfin blackfin
297 blackstamp blackfin blackfin 298 blackstamp blackfin blackfin
298 blackvme blackfin blackfin 299 blackvme blackfin blackfin
299 cm-bf527 blackfin blackfin 300 cm-bf527 blackfin blackfin
300 cm-bf533 blackfin blackfin 301 cm-bf533 blackfin blackfin
301 cm-bf537e blackfin blackfin 302 cm-bf537e blackfin blackfin
302 cm-bf537u blackfin blackfin 303 cm-bf537u blackfin blackfin
303 cm-bf548 blackfin blackfin 304 cm-bf548 blackfin blackfin
304 cm-bf561 blackfin blackfin 305 cm-bf561 blackfin blackfin
305 ibf-dsp561 blackfin blackfin 306 ibf-dsp561 blackfin blackfin
306 ip04 blackfin blackfin 307 ip04 blackfin blackfin
307 tcm-bf518 blackfin blackfin 308 tcm-bf518 blackfin blackfin
308 tcm-bf537 blackfin blackfin 309 tcm-bf537 blackfin blackfin
309 M5208EVBE m68k mcf52x2 m5208evbe freescale 310 M5208EVBE m68k mcf52x2 m5208evbe freescale
310 M5249EVB m68k mcf52x2 m5249evb freescale 311 M5249EVB m68k mcf52x2 m5249evb freescale
311 M5253DEMO m68k mcf52x2 m5253demo freescale 312 M5253DEMO m68k mcf52x2 m5253demo freescale
312 M5253EVBE m68k mcf52x2 m5253evbe freescale 313 M5253EVBE m68k mcf52x2 m5253evbe freescale
313 M5271EVB m68k mcf52x2 m5271evb freescale 314 M5271EVB m68k mcf52x2 m5271evb freescale
314 M5275EVB m68k mcf52x2 m5275evb freescale 315 M5275EVB m68k mcf52x2 m5275evb freescale
315 M5282EVB m68k mcf52x2 m5282evb freescale 316 M5282EVB m68k mcf52x2 m5282evb freescale
316 M53017EVB m68k mcf52x2 m53017evb freescale 317 M53017EVB m68k mcf52x2 m53017evb freescale
317 microblaze-generic microblaze microblaze microblaze-generic xilinx 318 microblaze-generic microblaze microblaze microblaze-generic xilinx
318 mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale 319 mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale
319 pdm360ng powerpc mpc512x 320 pdm360ng powerpc mpc512x
320 mecp5123 powerpc mpc512x - esd 321 mecp5123 powerpc mpc512x - esd
321 cmi_mpc5xx powerpc mpc5xx cmi 322 cmi_mpc5xx powerpc mpc5xx cmi
322 motionpro powerpc mpc5xxx 323 motionpro powerpc mpc5xxx
323 cpci5200 powerpc mpc5xxx - esd 324 cpci5200 powerpc mpc5xxx - esd
324 mecp5200 powerpc mpc5xxx - esd 325 mecp5200 powerpc mpc5xxx - esd
325 Alaska8220 powerpc mpc8220 alaska 326 Alaska8220 powerpc mpc8220 alaska
326 Yukon8220 powerpc mpc8220 alaska 327 Yukon8220 powerpc mpc8220 alaska
327 HIDDEN_DRAGON powerpc mpc824x hidden_dragon 328 HIDDEN_DRAGON powerpc mpc824x hidden_dragon
328 IPHASE4539 powerpc mpc8260 iphase4539 329 IPHASE4539 powerpc mpc8260 iphase4539
329 ppmc8260 powerpc mpc8260 330 ppmc8260 powerpc mpc8260
330 RPXsuper powerpc mpc8260 rpxsuper 331 RPXsuper powerpc mpc8260 rpxsuper
331 rsdproto powerpc mpc8260 332 rsdproto powerpc mpc8260
332 MPC8266ADS powerpc mpc8260 mpc8266ads freescale 333 MPC8266ADS powerpc mpc8260 mpc8266ads freescale
333 mpc8308_p1m powerpc mpc83xx 334 mpc8308_p1m powerpc mpc83xx
334 MPC8308RDB powerpc mpc83xx mpc8308rdb freescale 335 MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
335 MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale 336 MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
336 MPC8349EMDS powerpc mpc83xx mpc8349emds freescale 337 MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
337 MPC837XERDB powerpc mpc83xx mpc837xerdb freescale 338 MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
338 ATUM8548 powerpc mpc85xx atum8548 339 ATUM8548 powerpc mpc85xx atum8548
339 socrates powerpc mpc85xx socrates 340 socrates powerpc mpc85xx socrates
340 MPC8540ADS powerpc mpc85xx mpc8540ads freescale 341 MPC8540ADS powerpc mpc85xx mpc8540ads freescale
341 MPC8544DS powerpc mpc85xx mpc8544ds freescale 342 MPC8544DS powerpc mpc85xx mpc8544ds freescale
342 MPC8560ADS powerpc mpc85xx mpc8560ads freescale 343 MPC8560ADS powerpc mpc85xx mpc8560ads freescale
343 MPC8568MDS powerpc mpc85xx mpc8568mds freescale 344 MPC8568MDS powerpc mpc85xx mpc8568mds freescale
344 P4080DS powerpc mpc85xx corenet_ds freescale 345 P4080DS powerpc mpc85xx corenet_ds freescale
345 XPEDITE5200 powerpc mpc85xx xpedite5200 xes 346 XPEDITE5200 powerpc mpc85xx xpedite5200 xes
346 XPEDITE5370 powerpc mpc85xx xpedite5370 xes 347 XPEDITE5370 powerpc mpc85xx xpedite5370 xes
347 P1022DS powerpc mpc85xx p1022ds freescale 348 P1022DS powerpc mpc85xx p1022ds freescale
348 sbc8641d powerpc mpc86xx 349 sbc8641d powerpc mpc86xx
349 MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale 350 MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
350 XPEDITE5170 powerpc mpc86xx xpedite5170 xes 351 XPEDITE5170 powerpc mpc86xx xpedite5170 xes
351 cogent_mpc8xx powerpc mpc8xx cogent 352 cogent_mpc8xx powerpc mpc8xx cogent
352 ESTEEM192E powerpc mpc8xx esteem192e 353 ESTEEM192E powerpc mpc8xx esteem192e
353 RPXClassic powerpc mpc8xx 354 RPXClassic powerpc mpc8xx
354 RRvision powerpc mpc8xx 355 RRvision powerpc mpc8xx
355 svm_sc8xx powerpc mpc8xx 356 svm_sc8xx powerpc mpc8xx
356 pcs440ep powerpc ppc4xx 357 pcs440ep powerpc ppc4xx
357 quad100hd powerpc ppc4xx 358 quad100hd powerpc ppc4xx
358 dlvision powerpc ppc4xx - gdsys 359 dlvision powerpc ppc4xx - gdsys
359 gdppc440etx powerpc ppc4xx - gdsys 360 gdppc440etx powerpc ppc4xx - gdsys
360 CPCIISER4 powerpc ppc4xx cpciiser4 esd 361 CPCIISER4 powerpc ppc4xx cpciiser4 esd
361 DASA_SIM powerpc ppc4xx dasa_sim esd 362 DASA_SIM powerpc ppc4xx dasa_sim esd
362 PMC405DE powerpc ppc4xx pmc405de esd 363 PMC405DE powerpc ppc4xx pmc405de esd
363 METROBOX powerpc ppc4xx metrobox sandburst 364 METROBOX powerpc ppc4xx metrobox sandburst
364 XPEDITE1000 powerpc ppc4xx xpedite1000 xes 365 XPEDITE1000 powerpc ppc4xx xpedite1000 xes
365 grsim_leon2 sparc leon2 - gaisler 366 grsim_leon2 sparc leon2 - gaisler
366 gr_cpci_ax2000 sparc leon3 - gaisler 367 gr_cpci_ax2000 sparc leon3 - gaisler
367 gr_ep2s60 sparc leon3 - gaisler 368 gr_ep2s60 sparc leon3 - gaisler
368 gr_xc3s_1500 sparc leon3 - gaisler 369 gr_xc3s_1500 sparc leon3 - gaisler
369 davinci_dm355evm arm arm926ejs dm355evm davinci davinci 370 davinci_dm355evm arm arm926ejs dm355evm davinci davinci
370 davinci_dm365evm arm arm926ejs dm365evm davinci davinci 371 davinci_dm365evm arm arm926ejs dm365evm davinci davinci
371 davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci 372 davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci
372 davinci_schmoogie arm arm926ejs schmoogie davinci davinci 373 davinci_schmoogie arm arm926ejs schmoogie davinci davinci
373 davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci 374 davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
374 375
include/configs/a4m072.h
Diff comments   View file @ 9531a23
File was created 1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2010
6 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 /*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
37 #define CONFIG_A4M072 1 /* ... on A4M072 board */
38 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
39
40 #define CONFIG_MISC_INIT_R
41
42 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
43
44 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45 #define BOOTFLAG_WARM 0x02 /* Software reboot */
46
47 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
48
49 /*
50 * Serial console configuration
51 */
52 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
54 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55 /* define to enable silent console */
56 #define CONFIG_SILENT_CONSOLE
57 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
58
59 /*
60 * PCI Mapping:
61 * 0x40000000 - 0x4fffffff - PCI Memory
62 * 0x50000000 - 0x50ffffff - PCI IO Space
63 */
64 #define CONFIG_PCI
65
66 #if defined(CONFIG_PCI)
67 #define CONFIG_PCI_PNP 1
68 #define CONFIG_PCI_SCAN_SHOW 1
69 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
70
71 #define CONFIG_PCI_MEM_BUS 0x40000000
72 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73 #define CONFIG_PCI_MEM_SIZE 0x10000000
74
75 #define CONFIG_PCI_IO_BUS 0x50000000
76 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77 #define CONFIG_PCI_IO_SIZE 0x01000000
78 #endif
79
80 #define CONFIG_SYS_XLB_PIPELINING 1
81
82 #undef CONFIG_NET_MULTI
83 #undef CONFIG_EEPRO100
84
85 /* Partitions */
86 #define CONFIG_MAC_PARTITION
87 #define CONFIG_DOS_PARTITION
88
89 /* USB */
90 #define CONFIG_USB_OHCI_NEW
91 #define CONFIG_USB_STORAGE
92 #define CONFIG_SYS_OHCI_BE_CONTROLLER
93 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
94 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
95 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
96 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
97 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
98
99 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
100
101 /*
102 * BOOTP options
103 */
104 #define CONFIG_BOOTP_BOOTFILESIZE
105 #define CONFIG_BOOTP_BOOTPATH
106 #define CONFIG_BOOTP_GATEWAY
107 #define CONFIG_BOOTP_HOSTNAME
108
109
110 /*
111 * Command line configuration.
112 */
113 #include <config_cmd_default.h>
114
115 #define CONFIG_CMD_EEPROM
116 #define CONFIG_CMD_FAT
117 #define CONFIG_CMD_I2C
118 #define CONFIG_CMD_IDE
119 #define CONFIG_CMD_NFS
120 #define CONFIG_CMD_SNTP
121 #define CONFIG_CMD_USB
122 #define CONFIG_CMD_MII
123 #define CONFIG_CMD_DHCP
124 #define CONFIG_CMD_PING
125
126 #if defined(CONFIG_PCI)
127 #define CONFIG_CMD_PCI
128 #endif
129
130 #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
131 #define CONFIG_SYS_LOWBOOT 1
132 #define CONFIG_SYS_LOWBOOT32 1
133 #endif
134
135 /*
136 * Autobooting
137 */
138 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
139
140 #define CONFIG_SYS_AUTOLOAD "n"
141
142 #define CONFIG_AUTOBOOT_KEYED
143 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
144 #define CONFIG_AUTOBOOT_DELAY_STR "asdfg"
145
146 #undef CONFIG_BOOTARGS
147 #define CONFIG_PREBOOT "run try_update"
148
149 #define CONFIG_EXTRA_ENV_SETTINGS \
150 "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
151 "cf1=diskboot 200000 0:1\0" \
152 "bootcmd_cf1=run bcf1\0" \
153 "bcf=setenv bootargs root=/dev/hda3\0" \
154 "bootcmd_nfs=run bnfs\0" \
155 "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
156 "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
157 "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
158 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
159 "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
160 "env_addr=FE060000\0" \
161 "kernel_addr=FE100000\0" \
162 "rootfs_addr=FE200000\0" \
163 "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
164 "bcf1=run cf1; run bcf; run addip; run bk\0" \
165 "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
166 "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
167 "hostname=CPUP0\0" \
168 "ethaddr=00:00:00:00:00:00\0" \
169 "netdev=eth0\0" \
170 "bootcmd=run bootcmd_nor\0" \
171 ""
172 /*
173 * IPB Bus clocking configuration.
174 */
175 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
176
177 /*
178 * I2C configuration
179 */
180 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
181 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
182
183 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
184 #define CONFIG_SYS_I2C_SLAVE 0x7F
185
186 /*
187 * EEPROM configuration
188 */
189 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
193 #define CONFIG_SYS_EEPROM_WREN 1
194 #define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
195
196 /*
197 * Flash configuration
198 */
199 #define CONFIG_SYS_FLASH_BASE 0xFE000000
200 #define CONFIG_SYS_FLASH_SIZE 0x02000000
201 #if !defined(CONFIG_SYS_LOWBOOT)
202 #error "CONFIG_SYS_LOWBOOT not defined?"
203 #else /* CONFIG_SYS_LOWBOOT */
204 #if defined(CONFIG_SYS_LOWBOOT32)
205 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
206 #endif
207 #endif /* CONFIG_SYS_LOWBOOT */
208
209 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
210 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
211 #define CONFIG_FLASH_CFI_DRIVER
212 #define CONFIG_SYS_FLASH_CFI
213 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
215
216 /*
217 * Environment settings
218 */
219 #define CONFIG_ENV_IS_IN_FLASH 1
220 #define CONFIG_ENV_SIZE 0x10000
221 #define CONFIG_ENV_SECT_SIZE 0x20000
222 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
223 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
224
225 #define CONFIG_ENV_OVERWRITE 1
226
227 /*
228 * Memory map
229 */
230 #define CONFIG_SYS_MBAR 0xF0000000
231 #define CONFIG_SYS_SDRAM_BASE 0x00000000
232 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
233
234 /* Use SRAM until RAM will be available */
235 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
236 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
237
238
239 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
240 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
241 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242
243 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
244 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
245 # define CONFIG_SYS_RAMBOOT 1
246 #endif
247
248 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
249 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
250 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
251
252 /*
253 * Ethernet configuration
254 */
255 #define CONFIG_MPC5xxx_FEC 1
256 #define CONFIG_MPC5xxx_FEC_MII100
257 /*
258 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
259 */
260 /* #define CONFIG_MPC5xxx_FEC_MII10 */
261 #define CONFIG_PHY_ADDR 0x1f
262 #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
263
264 /*
265 * GPIO configuration
266 */
267 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
268
269 /*
270 * Miscellaneous configurable options
271 */
272 #define CONFIG_SYS_HUSH_PARSER
273 #define CONFIG_CMDLINE_EDITING 1
274 #ifdef CONFIG_SYS_HUSH_PARSER
275 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
276 #endif
277 #define CONFIG_SYS_LONGHELP /* undef to save memory */
278 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
279 #if defined(CONFIG_CMD_KGDB)
280 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
281 #else
282 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
283 #endif
284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
285 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
286 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
287
288 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
289 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
290
291 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
292
293 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
294
295 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
296 #if defined(CONFIG_CMD_KGDB)
297 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
298 #endif
299
300
301 /*
302 * Various low-level settings
303 */
304 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
305 #define CONFIG_SYS_HID0_FINAL HID0_ICE
306 /* Flash at CSBoot, CS0 */
307 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
308 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
309 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
310 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
311 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
312 /* External SRAM at CS1 */
313 #define CONFIG_SYS_CS1_START 0x62000000
314 #define CONFIG_SYS_CS1_SIZE 0x00400000
315 #define CONFIG_SYS_CS1_CFG 0x00009930
316 #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
317 #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
318
319
320 #define CONFIG_SYS_CS_BURST 0x00000000
321 #define CONFIG_SYS_CS_DEADCYCLE 0x33333003
322
323 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
324
325 /*-----------------------------------------------------------------------
326 * USB stuff
327 *-----------------------------------------------------------------------
328 */
329 #define CONFIG_USB_CLOCK 0x0001BBBB
330 #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
331
332 /*-----------------------------------------------------------------------
333 * IDE/ATA stuff Supports IDE harddisk
334 *-----------------------------------------------------------------------
335 */
336
337 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
338
339 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
340 #undef CONFIG_IDE_LED /* LED for ide not supported */
341
342 #define CONFIG_IDE_PREINIT
343
344 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
345 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
346
347 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
348
349 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
350
351 /* Offset for data I/O */
352 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
353
354 /* Offset for normal register accesses */
355 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
356
357 /* Offset for alternate registers */
358 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
359
360 /* Interval between registers */
361 #define CONFIG_SYS_ATA_STRIDE 4
362
363 #define CONFIG_ATAPI 1
364
365 /*-----------------------------------------------------------------------
366 * Open firmware flat tree support
367 *-----------------------------------------------------------------------
368 */
369 #define CONFIG_OF_LIBFDT 1
370 #define CONFIG_OF_BOARD_SETUP 1
371
372 #define OF_CPU "PowerPC,5200@0"
373 #define OF_SOC "soc5200@f0000000"
374 #define OF_TBCLK (bd->bi_busfreq / 4)
375 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
376
377 #endif /* __CONFIG_H */
378
1 /* 1 /*
2 * include/asm-ppc/mpc5xxx.h 2 * include/asm-ppc/mpc5xxx.h
3 * 3 *
4 * Prototypes, etc. for the Motorola MPC5xxx 4 * Prototypes, etc. for the Motorola MPC5xxx
5 * embedded cpu chips 5 * embedded cpu chips
6 * 6 *
7 * 2003 (c) MontaVista, Software, Inc. 7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com> 8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 * 9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * 11 *
12 * See file CREDITS for list of people who contributed to this 12 * See file CREDITS for list of people who contributed to this
13 * project. 13 * project.
14 * 14 *
15 * This program is free software; you can redistribute it and/or 15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as 16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of 17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version. 18 * the License, or (at your option) any later version.
19 * 19 *
20 * This program is distributed in the hope that it will be useful, 20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details. 23 * GNU General Public License for more details.
24 * 24 *
25 * You should have received a copy of the GNU General Public License 25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software 26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA 28 * MA 02111-1307 USA
29 */ 29 */
30 #ifndef __ASMPPC_MPC5XXX_H 30 #ifndef __ASMPPC_MPC5XXX_H
31 #define __ASMPPC_MPC5XXX_H 31 #define __ASMPPC_MPC5XXX_H
32 32
33 #include <asm/types.h> 33 #include <asm/types.h>
34 34
35 /* Processor name */ 35 /* Processor name */
36 #define CPU_ID_STR "MPC5200" 36 #define CPU_ID_STR "MPC5200"
37 37
38 /* Exception offsets (PowerPC standard) */ 38 /* Exception offsets (PowerPC standard) */
39 #define EXC_OFF_SYS_RESET 0x0100 39 #define EXC_OFF_SYS_RESET 0x0100
40 #define _START_OFFSET EXC_OFF_SYS_RESET 40 #define _START_OFFSET EXC_OFF_SYS_RESET
41 41
42 /* useful macros for manipulating CSx_START/STOP */ 42 /* useful macros for manipulating CSx_START/STOP */
43 #define START_REG(start) ((start) >> 16) 43 #define START_REG(start) ((start) >> 16)
44 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) 44 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
45 45
46 /* Internal memory map */ 46 /* Internal memory map */
47 47
48 #define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004) 48 #define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004)
49 #define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008) 49 #define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008)
50 #define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c) 50 #define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c)
51 #define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010) 51 #define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010)
52 #define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014) 52 #define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014)
53 #define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018) 53 #define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018)
54 #define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c) 54 #define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c)
55 #define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020) 55 #define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020)
56 #define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024) 56 #define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024)
57 #define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028) 57 #define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028)
58 #define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c) 58 #define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c)
59 #define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030) 59 #define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030)
60 #define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c) 60 #define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c)
61 #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) 61 #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
62 #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) 62 #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
63 63
64 #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) 64 #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
65 #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) 65 #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
66 #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) 66 #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
67 #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) 67 #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
68 #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) 68 #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
69 #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) 69 #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
70 70
71 #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) 71 #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
72 #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) 72 #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
73 #define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300) 73 #define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300)
74 #define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500) 74 #define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500)
75 #define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600) 75 #define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600)
76 #define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00) 76 #define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00)
77 #define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00) 77 #define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00)
78 #define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00) 78 #define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00)
79 #define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00) 79 #define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00)
80 #define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000) 80 #define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000)
81 #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) 81 #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
82 #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) 82 #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
83 83
84 #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) 84 #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
85 #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) 85 #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
86 #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) 86 #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
87 #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) 87 #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
88 #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) 88 #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
89 #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) 89 #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
90 90
91 #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) 91 #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
92 #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) 92 #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
93 93
94 #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) 94 #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
95 #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) 95 #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
96 96
97 #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) 97 #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
98 #define MPC5XXX_SRAM_SIZE (16*1024) 98 #define MPC5XXX_SRAM_SIZE (16*1024)
99 99
100 /* SDRAM Controller */ 100 /* SDRAM Controller */
101 #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) 101 #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
102 #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) 102 #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
103 #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) 103 #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
104 #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) 104 #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
105 #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) 105 #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
106 106
107 /* Clock Distribution Module */ 107 /* Clock Distribution Module */
108 #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) 108 #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
109 #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) 109 #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
110 #define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) 110 #define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008)
111 #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) 111 #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
112 #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) 112 #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
113 #define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014) 113 #define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014)
114 #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) 114 #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
115 115
116 /* Local Plus Bus interface */ 116 /* Local Plus Bus interface */
117 #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) 117 #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
118 #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) 118 #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
119 #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) 119 #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
120 #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) 120 #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
121 #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) 121 #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
122 #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) 122 #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
123 #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG 123 #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
124 #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) 124 #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
125 #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) 125 #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
126 #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) 126 #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
127 #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) 127 #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
128 #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) 128 #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
129 #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) 129 #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
130 130
131 /* XLB Arbiter registers */ 131 /* XLB Arbiter registers */
132 #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) 132 #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
133 #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) 133 #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
134 #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) 134 #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
135 135
136 /* GPIO registers */ 136 /* GPIO registers */
137 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) 137 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
138 138
139 /* Standard GPIO registers (simple, output only and simple interrupt */ 139 /* Standard GPIO registers (simple, output only and simple interrupt */
140 #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) 140 #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
141 #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) 141 #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
142 #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) 142 #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
143 #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) 143 #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
144 #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) 144 #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
145 #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) 145 #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
146 #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) 146 #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
147 #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) 147 #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
148 #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) 148 #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
149 #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) 149 #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
150 #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) 150 #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
151 #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) 151 #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
152 #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) 152 #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
153 #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) 153 #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
154 #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) 154 #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
155 155
156 /* WakeUp GPIO registers */ 156 /* WakeUp GPIO registers */
157 #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) 157 #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
158 #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) 158 #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
159 #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) 159 #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
160 #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) 160 #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
161 #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) 161 #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
162 162
163 /* GPIO pins */ 163 /* GPIO pins, for Rev.B chip */
164 #define GPIO_WKUP_7 0x80000000UL 164 #define GPIO_WKUP_7 0x80000000UL
165 #define GPIO_PSC6_0 0x10000000UL 165 #define GPIO_PSC6_0 0x10000000UL
166 #define GPIO_PSC3_9 0x04000000UL 166 #define GPIO_PSC3_9 0x04000000UL
167 #define GPIO_PSC1_4 0x01000000UL 167 #define GPIO_PSC1_4 0x01000000UL
168 #define GPIO_PSC2_4 0x02000000UL
168 169
169 #define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL 170 #define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
170 #define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL 171 #define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
171 #define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL 172 #define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
172 #define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL 173 #define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
173 #define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL 174 #define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
174 #define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL 175 #define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
175 #define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL 176 #define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
176 #define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL 177 #define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
177 #define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL 178 #define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
178 #define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL 179 #define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
179 #define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL 180 #define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
180 #define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL 181 #define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
181 #define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL 182 #define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
182 #define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL 183 #define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
183 #define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL 184 #define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
184 #define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL 185 #define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
185 186
186 #define MPC5XXX_GPIO_SINT_ETH_16 0x80 187 #define MPC5XXX_GPIO_SINT_ETH_16 0x80
187 #define MPC5XXX_GPIO_SINT_ETH_15 0x40 188 #define MPC5XXX_GPIO_SINT_ETH_15 0x40
188 #define MPC5XXX_GPIO_SINT_ETH_14 0x20 189 #define MPC5XXX_GPIO_SINT_ETH_14 0x20
189 #define MPC5XXX_GPIO_SINT_ETH_13 0x10 190 #define MPC5XXX_GPIO_SINT_ETH_13 0x10
190 #define MPC5XXX_GPIO_SINT_USB1_9 0x08 191 #define MPC5XXX_GPIO_SINT_USB1_9 0x08
191 #define MPC5XXX_GPIO_SINT_PSC3_8 0x04 192 #define MPC5XXX_GPIO_SINT_PSC3_8 0x04
192 #define MPC5XXX_GPIO_SINT_PSC3_5 0x02 193 #define MPC5XXX_GPIO_SINT_PSC3_5 0x02
193 #define MPC5XXX_GPIO_SINT_PSC3_4 0x01 194 #define MPC5XXX_GPIO_SINT_PSC3_4 0x01
194 195
195 #define MPC5XXX_GPIO_WKUP_7 0x80 196 #define MPC5XXX_GPIO_WKUP_7 0x80
196 #define MPC5XXX_GPIO_WKUP_6 0x40 197 #define MPC5XXX_GPIO_WKUP_6 0x40
197 #define MPC5XXX_GPIO_WKUP_PSC6_1 0x20 198 #define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
198 #define MPC5XXX_GPIO_WKUP_PSC6_0 0x10 199 #define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
199 #define MPC5XXX_GPIO_WKUP_ETH17 0x08 200 #define MPC5XXX_GPIO_WKUP_ETH17 0x08
200 #define MPC5XXX_GPIO_WKUP_PSC3_9 0x04 201 #define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
201 #define MPC5XXX_GPIO_WKUP_PSC2_4 0x02 202 #define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
202 #define MPC5XXX_GPIO_WKUP_PSC1_4 0x01 203 #define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
203 204
204 /* PCI registers */ 205 /* PCI registers */
205 #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) 206 #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
206 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) 207 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
207 #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) 208 #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
208 #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) 209 #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
209 #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) 210 #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
210 #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) 211 #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
211 #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) 212 #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
212 #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) 213 #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
213 #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) 214 #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
214 #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) 215 #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
215 #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) 216 #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
216 #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) 217 #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
217 #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) 218 #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
218 #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) 219 #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
219 #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) 220 #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
220 #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) 221 #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
221 222
222 /* Interrupt Controller registers */ 223 /* Interrupt Controller registers */
223 #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) 224 #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
224 #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) 225 #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
225 #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) 226 #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
226 #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) 227 #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
227 #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) 228 #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
228 #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) 229 #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
229 #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) 230 #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
230 #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) 231 #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
231 #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) 232 #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
232 #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) 233 #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
233 #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) 234 #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
234 #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) 235 #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
235 #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) 236 #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
236 237
237 #define NR_IRQS 64 238 #define NR_IRQS 64
238 239
239 /* IRQ mapping - these are our logical IRQ numbers */ 240 /* IRQ mapping - these are our logical IRQ numbers */
240 #define MPC5XXX_CRIT_IRQ_NUM 4 241 #define MPC5XXX_CRIT_IRQ_NUM 4
241 #define MPC5XXX_MAIN_IRQ_NUM 17 242 #define MPC5XXX_MAIN_IRQ_NUM 17
242 #define MPC5XXX_SDMA_IRQ_NUM 17 243 #define MPC5XXX_SDMA_IRQ_NUM 17
243 #define MPC5XXX_PERP_IRQ_NUM 23 244 #define MPC5XXX_PERP_IRQ_NUM 23
244 245
245 #define MPC5XXX_CRIT_IRQ_BASE 1 246 #define MPC5XXX_CRIT_IRQ_BASE 1
246 #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) 247 #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
247 #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) 248 #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
248 #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) 249 #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
249 250
250 #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) 251 #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
251 #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) 252 #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
252 #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) 253 #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
253 #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) 254 #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
254 255
255 #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) 256 #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
256 #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) 257 #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
257 #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) 258 #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
258 #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) 259 #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
259 #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) 260 #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
260 #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) 261 #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
261 #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) 262 #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
262 #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) 263 #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
263 #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) 264 #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
264 #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) 265 #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
265 #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) 266 #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
266 #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) 267 #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
267 #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) 268 #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
268 #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) 269 #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
269 #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) 270 #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
270 271
271 #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) 272 #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
272 #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) 273 #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
273 #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) 274 #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
274 #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) 275 #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
275 #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) 276 #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
276 #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) 277 #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
277 #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) 278 #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
278 #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) 279 #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
279 #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) 280 #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
280 #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) 281 #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
281 #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) 282 #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
282 #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) 283 #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
283 #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) 284 #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
284 #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) 285 #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
285 #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) 286 #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
286 #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) 287 #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
287 #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) 288 #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
288 #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) 289 #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
289 #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) 290 #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
290 #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) 291 #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
291 #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) 292 #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
292 #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) 293 #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
293 #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) 294 #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
294 #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) 295 #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
295 296
296 /* General Purpose Timers registers */ 297 /* General Purpose Timers registers */
297 #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) 298 #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
298 #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) 299 #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
299 #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) 300 #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
300 #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) 301 #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
301 #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) 302 #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
302 #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) 303 #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
303 #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) 304 #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
304 #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) 305 #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
305 #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) 306 #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
306 #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) 307 #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
307 #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) 308 #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
308 #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) 309 #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
309 #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) 310 #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
310 #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) 311 #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
311 #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) 312 #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
312 #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) 313 #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
313 #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) 314 #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
314 #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) 315 #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
315 #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) 316 #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
316 #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) 317 #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
317 #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) 318 #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
318 #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) 319 #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
319 #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) 320 #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
320 #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) 321 #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
321 322
322 #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) 323 #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
323 324
324 #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) 325 #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
325 326
326 /* ATA registers */ 327 /* ATA registers */
327 #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) 328 #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
328 #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) 329 #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
329 #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) 330 #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
330 #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) 331 #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
331 332
332 /* I2Cn control register bits */ 333 /* I2Cn control register bits */
333 #define I2C_EN 0x80 334 #define I2C_EN 0x80
334 #define I2C_IEN 0x40 335 #define I2C_IEN 0x40
335 #define I2C_STA 0x20 336 #define I2C_STA 0x20
336 #define I2C_TX 0x10 337 #define I2C_TX 0x10
337 #define I2C_TXAK 0x08 338 #define I2C_TXAK 0x08
338 #define I2C_RSTA 0x04 339 #define I2C_RSTA 0x04
339 #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) 340 #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
340 341
341 /* I2Cn status register bits */ 342 /* I2Cn status register bits */
342 #define I2C_CF 0x80 343 #define I2C_CF 0x80
343 #define I2C_AAS 0x40 344 #define I2C_AAS 0x40
344 #define I2C_BB 0x20 345 #define I2C_BB 0x20
345 #define I2C_AL 0x10 346 #define I2C_AL 0x10
346 #define I2C_SRW 0x04 347 #define I2C_SRW 0x04
347 #define I2C_IF 0x02 348 #define I2C_IF 0x02
348 #define I2C_RXAK 0x01 349 #define I2C_RXAK 0x01
349 350
350 /* SPI control register 1 bits */ 351 /* SPI control register 1 bits */
351 #define SPI_CR_LSBFE 0x01 352 #define SPI_CR_LSBFE 0x01
352 #define SPI_CR_SSOE 0x02 353 #define SPI_CR_SSOE 0x02
353 #define SPI_CR_CPHA 0x04 354 #define SPI_CR_CPHA 0x04
354 #define SPI_CR_CPOL 0x08 355 #define SPI_CR_CPOL 0x08
355 #define SPI_CR_MSTR 0x10 356 #define SPI_CR_MSTR 0x10
356 #define SPI_CR_SWOM 0x20 357 #define SPI_CR_SWOM 0x20
357 #define SPI_CR_SPE 0x40 358 #define SPI_CR_SPE 0x40
358 #define SPI_CR_SPIE 0x80 359 #define SPI_CR_SPIE 0x80
359 360
360 /* SPI status register bits */ 361 /* SPI status register bits */
361 #define SPI_SR_MODF 0x10 362 #define SPI_SR_MODF 0x10
362 #define SPI_SR_WCOL 0x40 363 #define SPI_SR_WCOL 0x40
363 #define SPI_SR_SPIF 0x80 364 #define SPI_SR_SPIF 0x80
364 365
365 /* SPI port data register bits */ 366 /* SPI port data register bits */
366 #define SPI_PDR_SS 0x08 367 #define SPI_PDR_SS 0x08
367 368
368 /* Programmable Serial Controller (PSC) status register bits */ 369 /* Programmable Serial Controller (PSC) status register bits */
369 #define PSC_SR_CDE 0x0080 370 #define PSC_SR_CDE 0x0080
370 #define PSC_SR_RXRDY 0x0100 371 #define PSC_SR_RXRDY 0x0100
371 #define PSC_SR_RXFULL 0x0200 372 #define PSC_SR_RXFULL 0x0200
372 #define PSC_SR_TXRDY 0x0400 373 #define PSC_SR_TXRDY 0x0400
373 #define PSC_SR_TXEMP 0x0800 374 #define PSC_SR_TXEMP 0x0800
374 #define PSC_SR_OE 0x1000 375 #define PSC_SR_OE 0x1000
375 #define PSC_SR_PE 0x2000 376 #define PSC_SR_PE 0x2000
376 #define PSC_SR_FE 0x4000 377 #define PSC_SR_FE 0x4000
377 #define PSC_SR_RB 0x8000 378 #define PSC_SR_RB 0x8000
378 379
379 /* PSC Command values */ 380 /* PSC Command values */
380 #define PSC_RX_ENABLE 0x0001 381 #define PSC_RX_ENABLE 0x0001
381 #define PSC_RX_DISABLE 0x0002 382 #define PSC_RX_DISABLE 0x0002
382 #define PSC_TX_ENABLE 0x0004 383 #define PSC_TX_ENABLE 0x0004
383 #define PSC_TX_DISABLE 0x0008 384 #define PSC_TX_DISABLE 0x0008
384 #define PSC_SEL_MODE_REG_1 0x0010 385 #define PSC_SEL_MODE_REG_1 0x0010
385 #define PSC_RST_RX 0x0020 386 #define PSC_RST_RX 0x0020
386 #define PSC_RST_TX 0x0030 387 #define PSC_RST_TX 0x0030
387 #define PSC_RST_ERR_STAT 0x0040 388 #define PSC_RST_ERR_STAT 0x0040
388 #define PSC_RST_BRK_CHG_INT 0x0050 389 #define PSC_RST_BRK_CHG_INT 0x0050
389 #define PSC_START_BRK 0x0060 390 #define PSC_START_BRK 0x0060
390 #define PSC_STOP_BRK 0x0070 391 #define PSC_STOP_BRK 0x0070
391 392
392 /* PSC Rx FIFO status bits */ 393 /* PSC Rx FIFO status bits */
393 #define PSC_RX_FIFO_ERR 0x0040 394 #define PSC_RX_FIFO_ERR 0x0040
394 #define PSC_RX_FIFO_UF 0x0020 395 #define PSC_RX_FIFO_UF 0x0020
395 #define PSC_RX_FIFO_OF 0x0010 396 #define PSC_RX_FIFO_OF 0x0010
396 #define PSC_RX_FIFO_FR 0x0008 397 #define PSC_RX_FIFO_FR 0x0008
397 #define PSC_RX_FIFO_FULL 0x0004 398 #define PSC_RX_FIFO_FULL 0x0004
398 #define PSC_RX_FIFO_ALARM 0x0002 399 #define PSC_RX_FIFO_ALARM 0x0002
399 #define PSC_RX_FIFO_EMPTY 0x0001 400 #define PSC_RX_FIFO_EMPTY 0x0001
400 401
401 /* PSC interrupt mask bits */ 402 /* PSC interrupt mask bits */
402 #define PSC_IMR_TXRDY 0x0100 403 #define PSC_IMR_TXRDY 0x0100
403 #define PSC_IMR_RXRDY 0x0200 404 #define PSC_IMR_RXRDY 0x0200
404 #define PSC_IMR_DB 0x0400 405 #define PSC_IMR_DB 0x0400
405 #define PSC_IMR_IPC 0x8000 406 #define PSC_IMR_IPC 0x8000
406 407
407 /* PSC input port change bits */ 408 /* PSC input port change bits */
408 #define PSC_IPCR_CTS 0x01 409 #define PSC_IPCR_CTS 0x01
409 #define PSC_IPCR_DCD 0x02 410 #define PSC_IPCR_DCD 0x02
410 411
411 /* PSC mode fields */ 412 /* PSC mode fields */
412 #define PSC_MODE_5_BITS 0x00 413 #define PSC_MODE_5_BITS 0x00
413 #define PSC_MODE_6_BITS 0x01 414 #define PSC_MODE_6_BITS 0x01
414 #define PSC_MODE_7_BITS 0x02 415 #define PSC_MODE_7_BITS 0x02
415 #define PSC_MODE_8_BITS 0x03 416 #define PSC_MODE_8_BITS 0x03
416 #define PSC_MODE_PAREVEN 0x00 417 #define PSC_MODE_PAREVEN 0x00
417 #define PSC_MODE_PARODD 0x04 418 #define PSC_MODE_PARODD 0x04
418 #define PSC_MODE_PARFORCE 0x08 419 #define PSC_MODE_PARFORCE 0x08
419 #define PSC_MODE_PARNONE 0x10 420 #define PSC_MODE_PARNONE 0x10
420 #define PSC_MODE_ERR 0x20 421 #define PSC_MODE_ERR 0x20
421 #define PSC_MODE_FFULL 0x40 422 #define PSC_MODE_FFULL 0x40
422 #define PSC_MODE_RXRTS 0x80 423 #define PSC_MODE_RXRTS 0x80
423 424
424 #define PSC_MODE_ONE_STOP_5_BITS 0x00 425 #define PSC_MODE_ONE_STOP_5_BITS 0x00
425 #define PSC_MODE_ONE_STOP 0x07 426 #define PSC_MODE_ONE_STOP 0x07
426 #define PSC_MODE_TWO_STOP 0x0f 427 #define PSC_MODE_TWO_STOP 0x0f
427 428
428 /* ATA config fields */ 429 /* ATA config fields */
429 #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine 430 #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
430 reset */ 431 reset */
431 #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ 432 #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
432 #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt 433 #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
433 in PIO */ 434 in PIO */
434 #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports 435 #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
435 IORDY protocol */ 436 IORDY protocol */
436 437
437 #ifndef __ASSEMBLY__ 438 #ifndef __ASSEMBLY__
438 /* Memory map registers */ 439 /* Memory map registers */
439 struct mpc5xxx_mmap_ctl { 440 struct mpc5xxx_mmap_ctl {
440 volatile u32 mbar; 441 volatile u32 mbar;
441 volatile u32 cs0_start; /* 0x0004 */ 442 volatile u32 cs0_start; /* 0x0004 */
442 volatile u32 cs0_stop; 443 volatile u32 cs0_stop;
443 volatile u32 cs1_start; /* 0x000c */ 444 volatile u32 cs1_start; /* 0x000c */
444 volatile u32 cs1_stop; 445 volatile u32 cs1_stop;
445 volatile u32 cs2_start; /* 0x0014 */ 446 volatile u32 cs2_start; /* 0x0014 */
446 volatile u32 cs2_stop; 447 volatile u32 cs2_stop;
447 volatile u32 cs3_start; /* 0x001c */ 448 volatile u32 cs3_start; /* 0x001c */
448 volatile u32 cs3_stop; 449 volatile u32 cs3_stop;
449 volatile u32 cs4_start; /* 0x0024 */ 450 volatile u32 cs4_start; /* 0x0024 */
450 volatile u32 cs4_stop; 451 volatile u32 cs4_stop;
451 volatile u32 cs5_start; /* 0x002c */ 452 volatile u32 cs5_start; /* 0x002c */
452 volatile u32 cs5_stop; 453 volatile u32 cs5_stop;
453 volatile u32 sdram0; /* 0x0034 */ 454 volatile u32 sdram0; /* 0x0034 */
454 volatile u32 sdram1; /* 0x0038 */ 455 volatile u32 sdram1; /* 0x0038 */
455 volatile u32 dummy1[4]; /* 0x003c */ 456 volatile u32 dummy1[4]; /* 0x003c */
456 volatile u32 boot_start; /* 0x004c */ 457 volatile u32 boot_start; /* 0x004c */
457 volatile u32 boot_stop; 458 volatile u32 boot_stop;
458 volatile u32 ipbi_ws_ctrl; /* 0x0054 */ 459 volatile u32 ipbi_ws_ctrl; /* 0x0054 */
459 volatile u32 cs6_start; /* 0x0058 */ 460 volatile u32 cs6_start; /* 0x0058 */
460 volatile u32 cs6_stop; 461 volatile u32 cs6_stop;
461 volatile u32 cs7_start; /* 0x0060 */ 462 volatile u32 cs7_start; /* 0x0060 */
462 volatile u32 cs7_stop; 463 volatile u32 cs7_stop;
463 }; 464 };
464 465
465 /* Clock distribution module */ 466 /* Clock distribution module */
466 struct mpc5xxx_cdm { 467 struct mpc5xxx_cdm {
467 volatile u32 jtagid; /* 0x0000 */ 468 volatile u32 jtagid; /* 0x0000 */
468 volatile u32 porcfg; 469 volatile u32 porcfg;
469 volatile u32 brdcrmb; /* 0x0008 */ 470 volatile u32 brdcrmb; /* 0x0008 */
470 volatile u32 cfg; 471 volatile u32 cfg;
471 volatile u32 fourtyeight_fdc;/* 0x0010 */ 472 volatile u32 fourtyeight_fdc;/* 0x0010 */
472 volatile u32 clock_enable; 473 volatile u32 clock_enable;
473 volatile u32 system_osc; /* 0x0018 */ 474 volatile u32 system_osc; /* 0x0018 */
474 volatile u32 ccscr; 475 volatile u32 ccscr;
475 volatile u32 sreset; /* 0x0020 */ 476 volatile u32 sreset; /* 0x0020 */
476 volatile u32 pll_status; 477 volatile u32 pll_status;
477 volatile u32 psc1_mccr; /* 0x0028 */ 478 volatile u32 psc1_mccr; /* 0x0028 */
478 volatile u32 psc2_mccr; 479 volatile u32 psc2_mccr;
479 volatile u32 psc3_mccr; /* 0x0030 */ 480 volatile u32 psc3_mccr; /* 0x0030 */
480 volatile u32 psc6_mccr; 481 volatile u32 psc6_mccr;
481 }; 482 };
482 483
483 /* SDRAM controller */ 484 /* SDRAM controller */
484 struct mpc5xxx_sdram { 485 struct mpc5xxx_sdram {
485 volatile u32 mode; 486 volatile u32 mode;
486 volatile u32 ctrl; 487 volatile u32 ctrl;
487 volatile u32 config1; 488 volatile u32 config1;
488 volatile u32 config2; 489 volatile u32 config2;
489 volatile u32 dummy[32]; 490 volatile u32 dummy[32];
490 volatile u32 sdelay; 491 volatile u32 sdelay;
491 }; 492 };
492 493
493 struct mpc5xxx_lpb { 494 struct mpc5xxx_lpb {
494 volatile u32 cs0_cfg; 495 volatile u32 cs0_cfg;
495 volatile u32 cs1_cfg; 496 volatile u32 cs1_cfg;
496 volatile u32 cs2_cfg; 497 volatile u32 cs2_cfg;
497 volatile u32 cs3_cfg; 498 volatile u32 cs3_cfg;
498 volatile u32 cs4_cfg; 499 volatile u32 cs4_cfg;
499 volatile u32 cs5_cfg; 500 volatile u32 cs5_cfg;
500 volatile u32 cs_ctrl; 501 volatile u32 cs_ctrl;
501 volatile u32 cs_status; 502 volatile u32 cs_status;
502 volatile u32 cs6_cfg; 503 volatile u32 cs6_cfg;
503 volatile u32 cs7_cfg; 504 volatile u32 cs7_cfg;
504 volatile u32 cs_burst; 505 volatile u32 cs_burst;
505 volatile u32 cs_deadcycle; 506 volatile u32 cs_deadcycle;
506 }; 507 };
507 508
508 509
509 struct mpc5xxx_psc { 510 struct mpc5xxx_psc {
510 volatile u8 mode; /* PSC + 0x00 */ 511 volatile u8 mode; /* PSC + 0x00 */
511 volatile u8 reserved0[3]; 512 volatile u8 reserved0[3];
512 union { /* PSC + 0x04 */ 513 union { /* PSC + 0x04 */
513 volatile u16 status; 514 volatile u16 status;
514 volatile u16 clock_select; 515 volatile u16 clock_select;
515 } sr_csr; 516 } sr_csr;
516 #define psc_status sr_csr.status 517 #define psc_status sr_csr.status
517 #define psc_clock_select sr_csr.clock_select 518 #define psc_clock_select sr_csr.clock_select
518 volatile u16 reserved1; 519 volatile u16 reserved1;
519 volatile u8 command; /* PSC + 0x08 */ 520 volatile u8 command; /* PSC + 0x08 */
520 volatile u8 reserved2[3]; 521 volatile u8 reserved2[3];
521 union { /* PSC + 0x0c */ 522 union { /* PSC + 0x0c */
522 volatile u8 buffer_8; 523 volatile u8 buffer_8;
523 volatile u16 buffer_16; 524 volatile u16 buffer_16;
524 volatile u32 buffer_32; 525 volatile u32 buffer_32;
525 } buffer; 526 } buffer;
526 #define psc_buffer_8 buffer.buffer_8 527 #define psc_buffer_8 buffer.buffer_8
527 #define psc_buffer_16 buffer.buffer_16 528 #define psc_buffer_16 buffer.buffer_16
528 #define psc_buffer_32 buffer.buffer_32 529 #define psc_buffer_32 buffer.buffer_32
529 union { /* PSC + 0x10 */ 530 union { /* PSC + 0x10 */
530 volatile u8 ipcr; 531 volatile u8 ipcr;
531 volatile u8 acr; 532 volatile u8 acr;
532 } ipcr_acr; 533 } ipcr_acr;
533 #define psc_ipcr ipcr_acr.ipcr 534 #define psc_ipcr ipcr_acr.ipcr
534 #define psc_acr ipcr_acr.acr 535 #define psc_acr ipcr_acr.acr
535 volatile u8 reserved3[3]; 536 volatile u8 reserved3[3];
536 union { /* PSC + 0x14 */ 537 union { /* PSC + 0x14 */
537 volatile u16 isr; 538 volatile u16 isr;
538 volatile u16 imr; 539 volatile u16 imr;
539 } isr_imr; 540 } isr_imr;
540 #define psc_isr isr_imr.isr 541 #define psc_isr isr_imr.isr
541 #define psc_imr isr_imr.imr 542 #define psc_imr isr_imr.imr
542 volatile u16 reserved4; 543 volatile u16 reserved4;
543 volatile u8 ctur; /* PSC + 0x18 */ 544 volatile u8 ctur; /* PSC + 0x18 */
544 volatile u8 reserved5[3]; 545 volatile u8 reserved5[3];
545 volatile u8 ctlr; /* PSC + 0x1c */ 546 volatile u8 ctlr; /* PSC + 0x1c */
546 volatile u8 reserved6[3]; 547 volatile u8 reserved6[3];
547 volatile u16 ccr; /* PSC + 0x20 */ 548 volatile u16 ccr; /* PSC + 0x20 */
548 volatile u8 reserved7[14]; 549 volatile u8 reserved7[14];
549 volatile u8 ivr; /* PSC + 0x30 */ 550 volatile u8 ivr; /* PSC + 0x30 */
550 volatile u8 reserved8[3]; 551 volatile u8 reserved8[3];
551 volatile u8 ip; /* PSC + 0x34 */ 552 volatile u8 ip; /* PSC + 0x34 */
552 volatile u8 reserved9[3]; 553 volatile u8 reserved9[3];
553 volatile u8 op1; /* PSC + 0x38 */ 554 volatile u8 op1; /* PSC + 0x38 */
554 volatile u8 reserved10[3]; 555 volatile u8 reserved10[3];
555 volatile u8 op0; /* PSC + 0x3c */ 556 volatile u8 op0; /* PSC + 0x3c */
556 volatile u8 reserved11[3]; 557 volatile u8 reserved11[3];
557 volatile u32 sicr; /* PSC + 0x40 */ 558 volatile u32 sicr; /* PSC + 0x40 */
558 volatile u8 ircr1; /* PSC + 0x44 */ 559 volatile u8 ircr1; /* PSC + 0x44 */
559 volatile u8 reserved12[3]; 560 volatile u8 reserved12[3];
560 volatile u8 ircr2; /* PSC + 0x44 */ 561 volatile u8 ircr2; /* PSC + 0x44 */
561 volatile u8 reserved13[3]; 562 volatile u8 reserved13[3];
562 volatile u8 irsdr; /* PSC + 0x4c */ 563 volatile u8 irsdr; /* PSC + 0x4c */
563 volatile u8 reserved14[3]; 564 volatile u8 reserved14[3];
564 volatile u8 irmdr; /* PSC + 0x50 */ 565 volatile u8 irmdr; /* PSC + 0x50 */
565 volatile u8 reserved15[3]; 566 volatile u8 reserved15[3];
566 volatile u8 irfdr; /* PSC + 0x54 */ 567 volatile u8 irfdr; /* PSC + 0x54 */
567 volatile u8 reserved16[3]; 568 volatile u8 reserved16[3];
568 volatile u16 rfnum; /* PSC + 0x58 */ 569 volatile u16 rfnum; /* PSC + 0x58 */
569 volatile u16 reserved17; 570 volatile u16 reserved17;
570 volatile u16 tfnum; /* PSC + 0x5c */ 571 volatile u16 tfnum; /* PSC + 0x5c */
571 volatile u16 reserved18; 572 volatile u16 reserved18;
572 volatile u32 rfdata; /* PSC + 0x60 */ 573 volatile u32 rfdata; /* PSC + 0x60 */
573 volatile u16 rfstat; /* PSC + 0x64 */ 574 volatile u16 rfstat; /* PSC + 0x64 */
574 volatile u16 reserved20; 575 volatile u16 reserved20;
575 volatile u8 rfcntl; /* PSC + 0x68 */ 576 volatile u8 rfcntl; /* PSC + 0x68 */
576 volatile u8 reserved21[5]; 577 volatile u8 reserved21[5];
577 volatile u16 rfalarm; /* PSC + 0x6e */ 578 volatile u16 rfalarm; /* PSC + 0x6e */
578 volatile u16 reserved22; 579 volatile u16 reserved22;
579 volatile u16 rfrptr; /* PSC + 0x72 */ 580 volatile u16 rfrptr; /* PSC + 0x72 */
580 volatile u16 reserved23; 581 volatile u16 reserved23;
581 volatile u16 rfwptr; /* PSC + 0x76 */ 582 volatile u16 rfwptr; /* PSC + 0x76 */
582 volatile u16 reserved24; 583 volatile u16 reserved24;
583 volatile u16 rflrfptr; /* PSC + 0x7a */ 584 volatile u16 rflrfptr; /* PSC + 0x7a */
584 volatile u16 reserved25; 585 volatile u16 reserved25;
585 volatile u16 rflwfptr; /* PSC + 0x7e */ 586 volatile u16 rflwfptr; /* PSC + 0x7e */
586 volatile u32 tfdata; /* PSC + 0x80 */ 587 volatile u32 tfdata; /* PSC + 0x80 */
587 volatile u16 tfstat; /* PSC + 0x84 */ 588 volatile u16 tfstat; /* PSC + 0x84 */
588 volatile u16 reserved26; 589 volatile u16 reserved26;
589 volatile u8 tfcntl; /* PSC + 0x88 */ 590 volatile u8 tfcntl; /* PSC + 0x88 */
590 volatile u8 reserved27[5]; 591 volatile u8 reserved27[5];
591 volatile u16 tfalarm; /* PSC + 0x8e */ 592 volatile u16 tfalarm; /* PSC + 0x8e */
592 volatile u16 reserved28; 593 volatile u16 reserved28;
593 volatile u16 tfrptr; /* PSC + 0x92 */ 594 volatile u16 tfrptr; /* PSC + 0x92 */
594 volatile u16 reserved29; 595 volatile u16 reserved29;
595 volatile u16 tfwptr; /* PSC + 0x96 */ 596 volatile u16 tfwptr; /* PSC + 0x96 */
596 volatile u16 reserved30; 597 volatile u16 reserved30;
597 volatile u16 tflrfptr; /* PSC + 0x9a */ 598 volatile u16 tflrfptr; /* PSC + 0x9a */
598 volatile u16 reserved31; 599 volatile u16 reserved31;
599 volatile u16 tflwfptr; /* PSC + 0x9e */ 600 volatile u16 tflwfptr; /* PSC + 0x9e */
600 }; 601 };
601 602
602 struct mpc5xxx_intr { 603 struct mpc5xxx_intr {
603 volatile u32 per_mask; /* INTR + 0x00 */ 604 volatile u32 per_mask; /* INTR + 0x00 */
604 volatile u32 per_pri1; /* INTR + 0x04 */ 605 volatile u32 per_pri1; /* INTR + 0x04 */
605 volatile u32 per_pri2; /* INTR + 0x08 */ 606 volatile u32 per_pri2; /* INTR + 0x08 */
606 volatile u32 per_pri3; /* INTR + 0x0c */ 607 volatile u32 per_pri3; /* INTR + 0x0c */
607 volatile u32 ctrl; /* INTR + 0x10 */ 608 volatile u32 ctrl; /* INTR + 0x10 */
608 volatile u32 main_mask; /* INTR + 0x14 */ 609 volatile u32 main_mask; /* INTR + 0x14 */
609 volatile u32 main_pri1; /* INTR + 0x18 */ 610 volatile u32 main_pri1; /* INTR + 0x18 */
610 volatile u32 main_pri2; /* INTR + 0x1c */ 611 volatile u32 main_pri2; /* INTR + 0x1c */
611 volatile u32 reserved1; /* INTR + 0x20 */ 612 volatile u32 reserved1; /* INTR + 0x20 */
612 volatile u32 enc_status; /* INTR + 0x24 */ 613 volatile u32 enc_status; /* INTR + 0x24 */
613 volatile u32 crit_status; /* INTR + 0x28 */ 614 volatile u32 crit_status; /* INTR + 0x28 */
614 volatile u32 main_status; /* INTR + 0x2c */ 615 volatile u32 main_status; /* INTR + 0x2c */
615 volatile u32 per_status; /* INTR + 0x30 */ 616 volatile u32 per_status; /* INTR + 0x30 */
616 volatile u32 reserved2; /* INTR + 0x34 */ 617 volatile u32 reserved2; /* INTR + 0x34 */
617 volatile u32 per_error; /* INTR + 0x38 */ 618 volatile u32 per_error; /* INTR + 0x38 */
618 }; 619 };
619 620
620 struct mpc5xxx_gpio { 621 struct mpc5xxx_gpio {
621 volatile u32 port_config; /* GPIO + 0x00 */ 622 volatile u32 port_config; /* GPIO + 0x00 */
622 volatile u32 simple_gpioe; /* GPIO + 0x04 */ 623 volatile u32 simple_gpioe; /* GPIO + 0x04 */
623 volatile u32 simple_ode; /* GPIO + 0x08 */ 624 volatile u32 simple_ode; /* GPIO + 0x08 */
624 volatile u32 simple_ddr; /* GPIO + 0x0c */ 625 volatile u32 simple_ddr; /* GPIO + 0x0c */
625 volatile u32 simple_dvo; /* GPIO + 0x10 */ 626 volatile u32 simple_dvo; /* GPIO + 0x10 */
626 volatile u32 simple_ival; /* GPIO + 0x14 */ 627 volatile u32 simple_ival; /* GPIO + 0x14 */
627 volatile u8 outo_gpioe; /* GPIO + 0x18 */ 628 volatile u8 outo_gpioe; /* GPIO + 0x18 */
628 volatile u8 reserved1[3]; /* GPIO + 0x19 */ 629 volatile u8 reserved1[3]; /* GPIO + 0x19 */
629 volatile u8 outo_dvo; /* GPIO + 0x1c */ 630 volatile u8 outo_dvo; /* GPIO + 0x1c */
630 volatile u8 reserved2[3]; /* GPIO + 0x1d */ 631 volatile u8 reserved2[3]; /* GPIO + 0x1d */
631 volatile u8 sint_gpioe; /* GPIO + 0x20 */ 632 volatile u8 sint_gpioe; /* GPIO + 0x20 */
632 volatile u8 reserved3[3]; /* GPIO + 0x21 */ 633 volatile u8 reserved3[3]; /* GPIO + 0x21 */
633 volatile u8 sint_ode; /* GPIO + 0x24 */ 634 volatile u8 sint_ode; /* GPIO + 0x24 */
634 volatile u8 reserved4[3]; /* GPIO + 0x25 */ 635 volatile u8 reserved4[3]; /* GPIO + 0x25 */
635 volatile u8 sint_ddr; /* GPIO + 0x28 */ 636 volatile u8 sint_ddr; /* GPIO + 0x28 */
636 volatile u8 reserved5[3]; /* GPIO + 0x29 */ 637 volatile u8 reserved5[3]; /* GPIO + 0x29 */
637 volatile u8 sint_dvo; /* GPIO + 0x2c */ 638 volatile u8 sint_dvo; /* GPIO + 0x2c */
638 volatile u8 reserved6[3]; /* GPIO + 0x2d */ 639 volatile u8 reserved6[3]; /* GPIO + 0x2d */
639 volatile u8 sint_inten; /* GPIO + 0x30 */ 640 volatile u8 sint_inten; /* GPIO + 0x30 */
640 volatile u8 reserved7[3]; /* GPIO + 0x31 */ 641 volatile u8 reserved7[3]; /* GPIO + 0x31 */
641 volatile u16 sint_itype; /* GPIO + 0x34 */ 642 volatile u16 sint_itype; /* GPIO + 0x34 */
642 volatile u16 reserved8; /* GPIO + 0x36 */ 643 volatile u16 reserved8; /* GPIO + 0x36 */
643 volatile u8 gpio_control; /* GPIO + 0x38 */ 644 volatile u8 gpio_control; /* GPIO + 0x38 */
644 volatile u8 reserved9[3]; /* GPIO + 0x39 */ 645 volatile u8 reserved9[3]; /* GPIO + 0x39 */
645 volatile u8 sint_istat; /* GPIO + 0x3c */ 646 volatile u8 sint_istat; /* GPIO + 0x3c */
646 volatile u8 sint_ival; /* GPIO + 0x3d */ 647 volatile u8 sint_ival; /* GPIO + 0x3d */
647 volatile u8 bus_errs; /* GPIO + 0x3e */ 648 volatile u8 bus_errs; /* GPIO + 0x3e */
648 volatile u8 reserved10; /* GPIO + 0x3f */ 649 volatile u8 reserved10; /* GPIO + 0x3f */
649 }; 650 };
650 651
651 struct mpc5xxx_wu_gpio { 652 struct mpc5xxx_wu_gpio {
652 volatile u8 enable; /* WU_GPIO + 0x00 */ 653 volatile u8 enable; /* WU_GPIO + 0x00 */
653 volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */ 654 volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */
654 volatile u8 ode; /* WU_GPIO + 0x04 */ 655 volatile u8 ode; /* WU_GPIO + 0x04 */
655 volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */ 656 volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */
656 volatile u8 ddr; /* WU_GPIO + 0x08 */ 657 volatile u8 ddr; /* WU_GPIO + 0x08 */
657 volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */ 658 volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */
658 volatile u8 dvo; /* WU_GPIO + 0x0c */ 659 volatile u8 dvo; /* WU_GPIO + 0x0c */
659 volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */ 660 volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */
660 volatile u8 inten; /* WU_GPIO + 0x10 */ 661 volatile u8 inten; /* WU_GPIO + 0x10 */
661 volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */ 662 volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */
662 volatile u8 iinten; /* WU_GPIO + 0x14 */ 663 volatile u8 iinten; /* WU_GPIO + 0x14 */
663 volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */ 664 volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */
664 volatile u16 itype; /* WU_GPIO + 0x18 */ 665 volatile u16 itype; /* WU_GPIO + 0x18 */
665 volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */ 666 volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */
666 volatile u8 master_enable; /* WU_GPIO + 0x1c */ 667 volatile u8 master_enable; /* WU_GPIO + 0x1c */
667 volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */ 668 volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */
668 volatile u8 ival; /* WU_GPIO + 0x20 */ 669 volatile u8 ival; /* WU_GPIO + 0x20 */
669 volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */ 670 volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */
670 volatile u8 status; /* WU_GPIO + 0x24 */ 671 volatile u8 status; /* WU_GPIO + 0x24 */
671 volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */ 672 volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */
672 }; 673 };
673 674
674 struct mpc5xxx_sdma { 675 struct mpc5xxx_sdma {
675 volatile u32 taskBar; /* SDMA + 0x00 */ 676 volatile u32 taskBar; /* SDMA + 0x00 */
676 volatile u32 currentPointer; /* SDMA + 0x04 */ 677 volatile u32 currentPointer; /* SDMA + 0x04 */
677 volatile u32 endPointer; /* SDMA + 0x08 */ 678 volatile u32 endPointer; /* SDMA + 0x08 */
678 volatile u32 variablePointer; /* SDMA + 0x0c */ 679 volatile u32 variablePointer; /* SDMA + 0x0c */
679 680
680 volatile u8 IntVect1; /* SDMA + 0x10 */ 681 volatile u8 IntVect1; /* SDMA + 0x10 */
681 volatile u8 IntVect2; /* SDMA + 0x11 */ 682 volatile u8 IntVect2; /* SDMA + 0x11 */
682 volatile u16 PtdCntrl; /* SDMA + 0x12 */ 683 volatile u16 PtdCntrl; /* SDMA + 0x12 */
683 684
684 volatile u32 IntPend; /* SDMA + 0x14 */ 685 volatile u32 IntPend; /* SDMA + 0x14 */
685 volatile u32 IntMask; /* SDMA + 0x18 */ 686 volatile u32 IntMask; /* SDMA + 0x18 */
686 687
687 volatile u16 tcr_0; /* SDMA + 0x1c */ 688 volatile u16 tcr_0; /* SDMA + 0x1c */
688 volatile u16 tcr_1; /* SDMA + 0x1e */ 689 volatile u16 tcr_1; /* SDMA + 0x1e */
689 volatile u16 tcr_2; /* SDMA + 0x20 */ 690 volatile u16 tcr_2; /* SDMA + 0x20 */
690 volatile u16 tcr_3; /* SDMA + 0x22 */ 691 volatile u16 tcr_3; /* SDMA + 0x22 */
691 volatile u16 tcr_4; /* SDMA + 0x24 */ 692 volatile u16 tcr_4; /* SDMA + 0x24 */
692 volatile u16 tcr_5; /* SDMA + 0x26 */ 693 volatile u16 tcr_5; /* SDMA + 0x26 */
693 volatile u16 tcr_6; /* SDMA + 0x28 */ 694 volatile u16 tcr_6; /* SDMA + 0x28 */
694 volatile u16 tcr_7; /* SDMA + 0x2a */ 695 volatile u16 tcr_7; /* SDMA + 0x2a */
695 volatile u16 tcr_8; /* SDMA + 0x2c */ 696 volatile u16 tcr_8; /* SDMA + 0x2c */
696 volatile u16 tcr_9; /* SDMA + 0x2e */ 697 volatile u16 tcr_9; /* SDMA + 0x2e */
697 volatile u16 tcr_a; /* SDMA + 0x30 */ 698 volatile u16 tcr_a; /* SDMA + 0x30 */
698 volatile u16 tcr_b; /* SDMA + 0x32 */ 699 volatile u16 tcr_b; /* SDMA + 0x32 */
699 volatile u16 tcr_c; /* SDMA + 0x34 */ 700 volatile u16 tcr_c; /* SDMA + 0x34 */
700 volatile u16 tcr_d; /* SDMA + 0x36 */ 701 volatile u16 tcr_d; /* SDMA + 0x36 */
701 volatile u16 tcr_e; /* SDMA + 0x38 */ 702 volatile u16 tcr_e; /* SDMA + 0x38 */
702 volatile u16 tcr_f; /* SDMA + 0x3a */ 703 volatile u16 tcr_f; /* SDMA + 0x3a */
703 704
704 volatile u8 IPR0; /* SDMA + 0x3c */ 705 volatile u8 IPR0; /* SDMA + 0x3c */
705 volatile u8 IPR1; /* SDMA + 0x3d */ 706 volatile u8 IPR1; /* SDMA + 0x3d */
706 volatile u8 IPR2; /* SDMA + 0x3e */ 707 volatile u8 IPR2; /* SDMA + 0x3e */
707 volatile u8 IPR3; /* SDMA + 0x3f */ 708 volatile u8 IPR3; /* SDMA + 0x3f */
708 volatile u8 IPR4; /* SDMA + 0x40 */ 709 volatile u8 IPR4; /* SDMA + 0x40 */
709 volatile u8 IPR5; /* SDMA + 0x41 */ 710 volatile u8 IPR5; /* SDMA + 0x41 */
710 volatile u8 IPR6; /* SDMA + 0x42 */ 711 volatile u8 IPR6; /* SDMA + 0x42 */
711 volatile u8 IPR7; /* SDMA + 0x43 */ 712 volatile u8 IPR7; /* SDMA + 0x43 */
712 volatile u8 IPR8; /* SDMA + 0x44 */ 713 volatile u8 IPR8; /* SDMA + 0x44 */
713 volatile u8 IPR9; /* SDMA + 0x45 */ 714 volatile u8 IPR9; /* SDMA + 0x45 */
714 volatile u8 IPR10; /* SDMA + 0x46 */ 715 volatile u8 IPR10; /* SDMA + 0x46 */
715 volatile u8 IPR11; /* SDMA + 0x47 */ 716 volatile u8 IPR11; /* SDMA + 0x47 */
716 volatile u8 IPR12; /* SDMA + 0x48 */ 717 volatile u8 IPR12; /* SDMA + 0x48 */
717 volatile u8 IPR13; /* SDMA + 0x49 */ 718 volatile u8 IPR13; /* SDMA + 0x49 */
718 volatile u8 IPR14; /* SDMA + 0x4a */ 719 volatile u8 IPR14; /* SDMA + 0x4a */
719 volatile u8 IPR15; /* SDMA + 0x4b */ 720 volatile u8 IPR15; /* SDMA + 0x4b */
720 volatile u8 IPR16; /* SDMA + 0x4c */ 721 volatile u8 IPR16; /* SDMA + 0x4c */
721 volatile u8 IPR17; /* SDMA + 0x4d */ 722 volatile u8 IPR17; /* SDMA + 0x4d */
722 volatile u8 IPR18; /* SDMA + 0x4e */ 723 volatile u8 IPR18; /* SDMA + 0x4e */
723 volatile u8 IPR19; /* SDMA + 0x4f */ 724 volatile u8 IPR19; /* SDMA + 0x4f */
724 volatile u8 IPR20; /* SDMA + 0x50 */ 725 volatile u8 IPR20; /* SDMA + 0x50 */
725 volatile u8 IPR21; /* SDMA + 0x51 */ 726 volatile u8 IPR21; /* SDMA + 0x51 */
726 volatile u8 IPR22; /* SDMA + 0x52 */ 727 volatile u8 IPR22; /* SDMA + 0x52 */
727 volatile u8 IPR23; /* SDMA + 0x53 */ 728 volatile u8 IPR23; /* SDMA + 0x53 */
728 volatile u8 IPR24; /* SDMA + 0x54 */ 729 volatile u8 IPR24; /* SDMA + 0x54 */
729 volatile u8 IPR25; /* SDMA + 0x55 */ 730 volatile u8 IPR25; /* SDMA + 0x55 */
730 volatile u8 IPR26; /* SDMA + 0x56 */ 731 volatile u8 IPR26; /* SDMA + 0x56 */
731 volatile u8 IPR27; /* SDMA + 0x57 */ 732 volatile u8 IPR27; /* SDMA + 0x57 */
732 volatile u8 IPR28; /* SDMA + 0x58 */ 733 volatile u8 IPR28; /* SDMA + 0x58 */
733 volatile u8 IPR29; /* SDMA + 0x59 */ 734 volatile u8 IPR29; /* SDMA + 0x59 */
734 volatile u8 IPR30; /* SDMA + 0x5a */ 735 volatile u8 IPR30; /* SDMA + 0x5a */
735 volatile u8 IPR31; /* SDMA + 0x5b */ 736 volatile u8 IPR31; /* SDMA + 0x5b */
736 737
737 volatile u32 res1; /* SDMA + 0x5c */ 738 volatile u32 res1; /* SDMA + 0x5c */
738 volatile u32 res2; /* SDMA + 0x60 */ 739 volatile u32 res2; /* SDMA + 0x60 */
739 volatile u32 res3; /* SDMA + 0x64 */ 740 volatile u32 res3; /* SDMA + 0x64 */
740 volatile u32 MDEDebug; /* SDMA + 0x68 */ 741 volatile u32 MDEDebug; /* SDMA + 0x68 */
741 volatile u32 ADSDebug; /* SDMA + 0x6c */ 742 volatile u32 ADSDebug; /* SDMA + 0x6c */
742 volatile u32 Value1; /* SDMA + 0x70 */ 743 volatile u32 Value1; /* SDMA + 0x70 */
743 volatile u32 Value2; /* SDMA + 0x74 */ 744 volatile u32 Value2; /* SDMA + 0x74 */
744 volatile u32 Control; /* SDMA + 0x78 */ 745 volatile u32 Control; /* SDMA + 0x78 */
745 volatile u32 Status; /* SDMA + 0x7c */ 746 volatile u32 Status; /* SDMA + 0x7c */
746 volatile u32 EU00; /* SDMA + 0x80 */ 747 volatile u32 EU00; /* SDMA + 0x80 */
747 volatile u32 EU01; /* SDMA + 0x84 */ 748 volatile u32 EU01; /* SDMA + 0x84 */
748 volatile u32 EU02; /* SDMA + 0x88 */ 749 volatile u32 EU02; /* SDMA + 0x88 */
749 volatile u32 EU03; /* SDMA + 0x8c */ 750 volatile u32 EU03; /* SDMA + 0x8c */
750 volatile u32 EU04; /* SDMA + 0x90 */ 751 volatile u32 EU04; /* SDMA + 0x90 */
751 volatile u32 EU05; /* SDMA + 0x94 */ 752 volatile u32 EU05; /* SDMA + 0x94 */
752 volatile u32 EU06; /* SDMA + 0x98 */ 753 volatile u32 EU06; /* SDMA + 0x98 */
753 volatile u32 EU07; /* SDMA + 0x9c */ 754 volatile u32 EU07; /* SDMA + 0x9c */
754 volatile u32 EU10; /* SDMA + 0xa0 */ 755 volatile u32 EU10; /* SDMA + 0xa0 */
755 volatile u32 EU11; /* SDMA + 0xa4 */ 756 volatile u32 EU11; /* SDMA + 0xa4 */
756 volatile u32 EU12; /* SDMA + 0xa8 */ 757 volatile u32 EU12; /* SDMA + 0xa8 */
757 volatile u32 EU13; /* SDMA + 0xac */ 758 volatile u32 EU13; /* SDMA + 0xac */
758 volatile u32 EU14; /* SDMA + 0xb0 */ 759 volatile u32 EU14; /* SDMA + 0xb0 */
759 volatile u32 EU15; /* SDMA + 0xb4 */ 760 volatile u32 EU15; /* SDMA + 0xb4 */
760 volatile u32 EU16; /* SDMA + 0xb8 */ 761 volatile u32 EU16; /* SDMA + 0xb8 */
761 volatile u32 EU17; /* SDMA + 0xbc */ 762 volatile u32 EU17; /* SDMA + 0xbc */
762 volatile u32 EU20; /* SDMA + 0xc0 */ 763 volatile u32 EU20; /* SDMA + 0xc0 */
763 volatile u32 EU21; /* SDMA + 0xc4 */ 764 volatile u32 EU21; /* SDMA + 0xc4 */
764 volatile u32 EU22; /* SDMA + 0xc8 */ 765 volatile u32 EU22; /* SDMA + 0xc8 */
765 volatile u32 EU23; /* SDMA + 0xcc */ 766 volatile u32 EU23; /* SDMA + 0xcc */
766 volatile u32 EU24; /* SDMA + 0xd0 */ 767 volatile u32 EU24; /* SDMA + 0xd0 */
767 volatile u32 EU25; /* SDMA + 0xd4 */ 768 volatile u32 EU25; /* SDMA + 0xd4 */
768 volatile u32 EU26; /* SDMA + 0xd8 */ 769 volatile u32 EU26; /* SDMA + 0xd8 */
769 volatile u32 EU27; /* SDMA + 0xdc */ 770 volatile u32 EU27; /* SDMA + 0xdc */
770 volatile u32 EU30; /* SDMA + 0xe0 */ 771 volatile u32 EU30; /* SDMA + 0xe0 */
771 volatile u32 EU31; /* SDMA + 0xe4 */ 772 volatile u32 EU31; /* SDMA + 0xe4 */
772 volatile u32 EU32; /* SDMA + 0xe8 */ 773 volatile u32 EU32; /* SDMA + 0xe8 */
773 volatile u32 EU33; /* SDMA + 0xec */ 774 volatile u32 EU33; /* SDMA + 0xec */
774 volatile u32 EU34; /* SDMA + 0xf0 */ 775 volatile u32 EU34; /* SDMA + 0xf0 */
775 volatile u32 EU35; /* SDMA + 0xf4 */ 776 volatile u32 EU35; /* SDMA + 0xf4 */
776 volatile u32 EU36; /* SDMA + 0xf8 */ 777 volatile u32 EU36; /* SDMA + 0xf8 */
777 volatile u32 EU37; /* SDMA + 0xfc */ 778 volatile u32 EU37; /* SDMA + 0xfc */
778 }; 779 };
779 780
780 struct mpc5xxx_i2c { 781 struct mpc5xxx_i2c {
781 volatile u32 madr; /* I2Cn + 0x00 */ 782 volatile u32 madr; /* I2Cn + 0x00 */
782 volatile u32 mfdr; /* I2Cn + 0x04 */ 783 volatile u32 mfdr; /* I2Cn + 0x04 */
783 volatile u32 mcr; /* I2Cn + 0x08 */ 784 volatile u32 mcr; /* I2Cn + 0x08 */
784 volatile u32 msr; /* I2Cn + 0x0C */ 785 volatile u32 msr; /* I2Cn + 0x0C */
785 volatile u32 mdr; /* I2Cn + 0x10 */ 786 volatile u32 mdr; /* I2Cn + 0x10 */
786 }; 787 };
787 788
788 struct mpc5xxx_spi { 789 struct mpc5xxx_spi {
789 volatile u8 cr1; /* SPI + 0x0F00 */ 790 volatile u8 cr1; /* SPI + 0x0F00 */
790 volatile u8 cr2; /* SPI + 0x0F01 */ 791 volatile u8 cr2; /* SPI + 0x0F01 */
791 volatile u8 reserved1[2]; 792 volatile u8 reserved1[2];
792 volatile u8 brr; /* SPI + 0x0F04 */ 793 volatile u8 brr; /* SPI + 0x0F04 */
793 volatile u8 sr; /* SPI + 0x0F05 */ 794 volatile u8 sr; /* SPI + 0x0F05 */
794 volatile u8 reserved2[3]; 795 volatile u8 reserved2[3];
795 volatile u8 dr; /* SPI + 0x0F09 */ 796 volatile u8 dr; /* SPI + 0x0F09 */
796 volatile u8 reserved3[3]; 797 volatile u8 reserved3[3];
797 volatile u8 pdr; /* SPI + 0x0F0D */ 798 volatile u8 pdr; /* SPI + 0x0F0D */
798 volatile u8 reserved4[2]; 799 volatile u8 reserved4[2];
799 volatile u8 ddr; /* SPI + 0x0F10 */ 800 volatile u8 ddr; /* SPI + 0x0F10 */
800 }; 801 };
801 802
802 803
803 struct mpc5xxx_gpt { 804 struct mpc5xxx_gpt {
804 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ 805 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
805 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ 806 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
806 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ 807 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
807 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ 808 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
808 }; 809 };
809 810
810 struct mpc5xxx_gpt_0_7 { 811 struct mpc5xxx_gpt_0_7 {
811 struct mpc5xxx_gpt gpt0; 812 struct mpc5xxx_gpt gpt0;
812 struct mpc5xxx_gpt gpt1; 813 struct mpc5xxx_gpt gpt1;
813 struct mpc5xxx_gpt gpt2; 814 struct mpc5xxx_gpt gpt2;
814 struct mpc5xxx_gpt gpt3; 815 struct mpc5xxx_gpt gpt3;
815 struct mpc5xxx_gpt gpt4; 816 struct mpc5xxx_gpt gpt4;
816 struct mpc5xxx_gpt gpt5; 817 struct mpc5xxx_gpt gpt5;
817 struct mpc5xxx_gpt gpt6; 818 struct mpc5xxx_gpt gpt6;
818 struct mpc5xxx_gpt gpt7; 819 struct mpc5xxx_gpt gpt7;
819 }; 820 };
820 821
821 struct mscan_buffer { 822 struct mscan_buffer {
822 volatile u8 idr[0x8]; /* 0x00 */ 823 volatile u8 idr[0x8]; /* 0x00 */
823 volatile u8 dsr[0x10]; /* 0x08 */ 824 volatile u8 dsr[0x10]; /* 0x08 */
824 volatile u8 dlr; /* 0x18 */ 825 volatile u8 dlr; /* 0x18 */
825 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ 826 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
826 volatile u16 rsrv1; /* 0x1A */ 827 volatile u16 rsrv1; /* 0x1A */
827 volatile u8 tsrh; /* 0x1C */ 828 volatile u8 tsrh; /* 0x1C */
828 volatile u8 tsrl; /* 0x1D */ 829 volatile u8 tsrl; /* 0x1D */
829 volatile u16 rsrv2; /* 0x1E */ 830 volatile u16 rsrv2; /* 0x1E */
830 }; 831 };
831 832
832 struct mpc5xxx_mscan { 833 struct mpc5xxx_mscan {
833 volatile u8 canctl0; /* MSCAN + 0x00 */ 834 volatile u8 canctl0; /* MSCAN + 0x00 */
834 volatile u8 canctl1; /* MSCAN + 0x01 */ 835 volatile u8 canctl1; /* MSCAN + 0x01 */
835 volatile u16 rsrv1; /* MSCAN + 0x02 */ 836 volatile u16 rsrv1; /* MSCAN + 0x02 */
836 volatile u8 canbtr0; /* MSCAN + 0x04 */ 837 volatile u8 canbtr0; /* MSCAN + 0x04 */
837 volatile u8 canbtr1; /* MSCAN + 0x05 */ 838 volatile u8 canbtr1; /* MSCAN + 0x05 */
838 volatile u16 rsrv2; /* MSCAN + 0x06 */ 839 volatile u16 rsrv2; /* MSCAN + 0x06 */
839 volatile u8 canrflg; /* MSCAN + 0x08 */ 840 volatile u8 canrflg; /* MSCAN + 0x08 */
840 volatile u8 canrier; /* MSCAN + 0x09 */ 841 volatile u8 canrier; /* MSCAN + 0x09 */
841 volatile u16 rsrv3; /* MSCAN + 0x0A */ 842 volatile u16 rsrv3; /* MSCAN + 0x0A */
842 volatile u8 cantflg; /* MSCAN + 0x0C */ 843 volatile u8 cantflg; /* MSCAN + 0x0C */
843 volatile u8 cantier; /* MSCAN + 0x0D */ 844 volatile u8 cantier; /* MSCAN + 0x0D */
844 volatile u16 rsrv4; /* MSCAN + 0x0E */ 845 volatile u16 rsrv4; /* MSCAN + 0x0E */
845 volatile u8 cantarq; /* MSCAN + 0x10 */ 846 volatile u8 cantarq; /* MSCAN + 0x10 */
846 volatile u8 cantaak; /* MSCAN + 0x11 */ 847 volatile u8 cantaak; /* MSCAN + 0x11 */
847 volatile u16 rsrv5; /* MSCAN + 0x12 */ 848 volatile u16 rsrv5; /* MSCAN + 0x12 */
848 volatile u8 cantbsel; /* MSCAN + 0x14 */ 849 volatile u8 cantbsel; /* MSCAN + 0x14 */
849 volatile u8 canidac; /* MSCAN + 0x15 */ 850 volatile u8 canidac; /* MSCAN + 0x15 */
850 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ 851 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
851 volatile u8 canrxerr; /* MSCAN + 0x1C */ 852 volatile u8 canrxerr; /* MSCAN + 0x1C */
852 volatile u8 cantxerr; /* MSCAN + 0x1D */ 853 volatile u8 cantxerr; /* MSCAN + 0x1D */
853 volatile u16 rsrv7; /* MSCAN + 0x1E */ 854 volatile u16 rsrv7; /* MSCAN + 0x1E */
854 volatile u8 canidar0; /* MSCAN + 0x20 */ 855 volatile u8 canidar0; /* MSCAN + 0x20 */
855 volatile u8 canidar1; /* MSCAN + 0x21 */ 856 volatile u8 canidar1; /* MSCAN + 0x21 */
856 volatile u16 rsrv8; /* MSCAN + 0x22 */ 857 volatile u16 rsrv8; /* MSCAN + 0x22 */
857 volatile u8 canidar2; /* MSCAN + 0x24 */ 858 volatile u8 canidar2; /* MSCAN + 0x24 */
858 volatile u8 canidar3; /* MSCAN + 0x25 */ 859 volatile u8 canidar3; /* MSCAN + 0x25 */
859 volatile u16 rsrv9; /* MSCAN + 0x26 */ 860 volatile u16 rsrv9; /* MSCAN + 0x26 */
860 volatile u8 canidmr0; /* MSCAN + 0x28 */ 861 volatile u8 canidmr0; /* MSCAN + 0x28 */
861 volatile u8 canidmr1; /* MSCAN + 0x29 */ 862 volatile u8 canidmr1; /* MSCAN + 0x29 */
862 volatile u16 rsrv10; /* MSCAN + 0x2A */ 863 volatile u16 rsrv10; /* MSCAN + 0x2A */
863 volatile u8 canidmr2; /* MSCAN + 0x2C */ 864 volatile u8 canidmr2; /* MSCAN + 0x2C */
864 volatile u8 canidmr3; /* MSCAN + 0x2D */ 865 volatile u8 canidmr3; /* MSCAN + 0x2D */
865 volatile u16 rsrv11; /* MSCAN + 0x2E */ 866 volatile u16 rsrv11; /* MSCAN + 0x2E */
866 volatile u8 canidar4; /* MSCAN + 0x30 */ 867 volatile u8 canidar4; /* MSCAN + 0x30 */
867 volatile u8 canidar5; /* MSCAN + 0x31 */ 868 volatile u8 canidar5; /* MSCAN + 0x31 */
868 volatile u16 rsrv12; /* MSCAN + 0x32 */ 869 volatile u16 rsrv12; /* MSCAN + 0x32 */
869 volatile u8 canidar6; /* MSCAN + 0x34 */ 870 volatile u8 canidar6; /* MSCAN + 0x34 */
870 volatile u8 canidar7; /* MSCAN + 0x35 */ 871 volatile u8 canidar7; /* MSCAN + 0x35 */
871 volatile u16 rsrv13; /* MSCAN + 0x36 */ 872 volatile u16 rsrv13; /* MSCAN + 0x36 */
872 volatile u8 canidmr4; /* MSCAN + 0x38 */ 873 volatile u8 canidmr4; /* MSCAN + 0x38 */
873 volatile u8 canidmr5; /* MSCAN + 0x39 */ 874 volatile u8 canidmr5; /* MSCAN + 0x39 */
874 volatile u16 rsrv14; /* MSCAN + 0x3A */ 875 volatile u16 rsrv14; /* MSCAN + 0x3A */
875 volatile u8 canidmr6; /* MSCAN + 0x3C */ 876 volatile u8 canidmr6; /* MSCAN + 0x3C */
876 volatile u8 canidmr7; /* MSCAN + 0x3D */ 877 volatile u8 canidmr7; /* MSCAN + 0x3D */
877 volatile u16 rsrv15; /* MSCAN + 0x3E */ 878 volatile u16 rsrv15; /* MSCAN + 0x3E */
878 879
879 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ 880 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
880 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ 881 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
881 }; 882 };
882 883
883 struct mpc5xxx_xlb { 884 struct mpc5xxx_xlb {
884 volatile u8 reserved[0x40]; /* XLB + 0x00 */ 885 volatile u8 reserved[0x40]; /* XLB + 0x00 */
885 volatile u32 config; /* XLB + 0x40 */ 886 volatile u32 config; /* XLB + 0x40 */
886 volatile u32 version; /* XLB + 0x44 */ 887 volatile u32 version; /* XLB + 0x44 */
887 volatile u32 status; /* XLB + 0x48 */ 888 volatile u32 status; /* XLB + 0x48 */
888 volatile u32 int_enable; /* XLB + 0x4c */ 889 volatile u32 int_enable; /* XLB + 0x4c */
889 volatile u32 addr_capture; /* XLB + 0x50 */ 890 volatile u32 addr_capture; /* XLB + 0x50 */
890 volatile u32 bus_sig_capture; /* XLB + 0x54 */ 891 volatile u32 bus_sig_capture; /* XLB + 0x54 */
891 volatile u32 addr_timeout; /* XLB + 0x58 */ 892 volatile u32 addr_timeout; /* XLB + 0x58 */
892 volatile u32 data_timeout; /* XLB + 0x5c */ 893 volatile u32 data_timeout; /* XLB + 0x5c */
893 volatile u32 bus_act_timeout; /* XLB + 0x60 */ 894 volatile u32 bus_act_timeout; /* XLB + 0x60 */
894 volatile u32 master_pri_enable; /* XLB + 0x64 */ 895 volatile u32 master_pri_enable; /* XLB + 0x64 */
895 volatile u32 master_priority; /* XLB + 0x68 */ 896 volatile u32 master_priority; /* XLB + 0x68 */
896 volatile u32 base_address; /* XLB + 0x6c */ 897 volatile u32 base_address; /* XLB + 0x6c */
897 volatile u32 snoop_window; /* XLB + 0x70 */ 898 volatile u32 snoop_window; /* XLB + 0x70 */
898 }; 899 };
899 900
900 /* function prototypes */ 901 /* function prototypes */
901 void loadtask(int basetask, int tasks); 902 void loadtask(int basetask, int tasks);
902 903
903 #endif /* __ASSEMBLY__ */ 904 #endif /* __ASSEMBLY__ */
904 905
905 #endif /* __ASMPPC_MPC5XXX_H */ 906 #endif /* __ASMPPC_MPC5XXX_H */
906 907