A4M072: Added support for the board.

This patch provides support for the A4M072 board with the following features: UART NOR flash FEC Ethernet External SRAM I2C EEPROM CompactFlash cards on IDE/ATA port USB Host PCI initialization The 7-segment LED indicator is not yet supported. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>

A4M072: Added support for the board.
This patch provides support for the A4M072 board with the following features: UART NOR flash FEC Ethernet External SRAM I2C EEPROM CompactFlash cards on IDE/ATA port USB Host PCI initialization The 7-segment LED indicator is not yet supported. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Sergei Poselenov · Wolfgang Denk
1 parent 3831530dcb
Showing 8 changed files with 777 additions and 5 deletions Side-by-side Diff
MAINTAINERS
board/a4m072/Makefile
board/a4m072/a4m072.c
board/a4m072/config.mk
board/a4m072/mt46v32m16.h
boards.cfg
include/configs/a4m072.h
include/mpc5xxx.h
@@ -305,6 +305,10 @@
  
 	PPChameleonEVB	PPC405EP
  
+Tirumala Marri <tmarri@apm.com>
+
+	bluestone       APM821XX
+
 Reinhard Meyer <r.meyer@emk-elektronik.de>
  
 	TOP860		MPC860T
@@ -343,6 +347,10 @@
 	sbc8240		MPC8240
 	sbc405		PPC405GP
  
+Sergei Poselenov <sposelenov@emcraft.com>
+
+	a4m072		MPC5200
+
 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
  
 	da850evm	ARM926EJS (DA850/OMAP-L138)
@@ -497,10 +505,6 @@
 Detlev Zundel <dzu@denx.de>
  
 	inka4x0		MPC5200
-
-Tirumala Marri <tmarri@apm.com>
-
-	bluestone       APM821XX
  
 -------------------------------------------------------------------------
  
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <netdev.h>
+
+#include "mt46v32m16.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	ulong dramsize = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: A4M072\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize FEC.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Initialize EEPROM write-protect GPIO pin.
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	/* Enable GPIO pin */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
+	/* Set direction, output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
+	/* De-assert write enable */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+#endif
+	return 0;
+}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access */
+			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access */
+			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+						   CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# a4m072 board:
+#
+#	Valid values for TEXT_BASE is:
+#
+#	0xFE000000   boot low
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot low
+TEXT_BASE = 0xFE000000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40010000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
@@ -90,6 +90,7 @@
 DB64460		powerpc	74xx_7xx 	db64460		Marvell
 aria		powerpc	mpc512x		-		davedenx
 PATI		powerpc	mpc5xx		pati		mpl
+a4m072		powerpc	mpc5xxx		a4m072
 BC3450		powerpc	mpc5xxx		bc3450
 canmb		powerpc	mpc5xxx
 cm5200		powerpc	mpc5xxx
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
+#define CONFIG_A4M072		1	/* ... on A4M072 board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+/* define to enable silent console */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+#undef CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100 
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if (TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
+#define CONFIG_SYS_LOWBOOT		1
+#define CONFIG_SYS_LOWBOOT32		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
+
+#define CONFIG_SYS_AUTOLOAD	"n"
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"asdfg"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_PREBOOT				"run try_update"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"	\
+	"cf1=diskboot 200000 0:1\0"	\
+	"bootcmd_cf1=run bcf1\0"	\
+	"bcf=setenv bootargs root=/dev/hda3\0"	\
+	"bootcmd_nfs=run bnfs\0"	\
+	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0"	\
+	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0"	\
+	"bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0"	\
+	"env_addr=FE060000\0"	\
+	"kernel_addr=FE100000\0"	\
+	"rootfs_addr=FE200000\0"	\
+	"add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
+	"bcf1=run cf1; run bcf; run addip; run bk\0"	\
+	"add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0"	\
+	"addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0"	\
+	"hostname=CPUP0\0"	\
+	"ethaddr=00:00:00:00:00:00\0"	\
+	"netdev=eth0\0"	\
+	"bootcmd=run bootcmd_nor\0" \
+	""
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1010010x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_WREN			1
+#define CONFIG_SYS_EEPROM_WP			GPIO_PSC2_4
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#error "CONFIG_SYS_LOWBOOT not defined?"
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT32)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif
+#endif	/* CONFIG_SYS_LOWBOOT */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x1f
+#define CONFIG_PHY_TYPE		0x79c874		/* AMD Phy Controller */
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING	1
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#endif
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+/* Flash at CSBoot, CS0 */
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+/* External SRAM at CS1 */
+#define CONFIG_SYS_CS1_START		0x62000000
+#define CONFIG_SYS_CS1_SIZE		0x00400000
+#define CONFIG_SYS_CS1_CFG		0x00009930
+#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_CS1_START
+#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
+
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333003
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000 /* 0x4000 for SE mode */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#define CONFIG_ATAPI                   1
+
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
@@ -160,11 +160,12 @@
 #define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
 #define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
  
-/* GPIO pins */
+/* GPIO pins, for Rev.B chip */
 #define GPIO_WKUP_7		0x80000000UL
 #define GPIO_PSC6_0		0x10000000UL
 #define GPIO_PSC3_9		0x04000000UL
 #define GPIO_PSC1_4		0x01000000UL
+#define GPIO_PSC2_4		0x02000000UL
  
 #define MPC5XXX_GPIO_SIMPLE_PSC6_3   0x20000000UL
 #define MPC5XXX_GPIO_SIMPLE_PSC6_2   0x10000000UL
...	...	@@ -305,6 +305,10 @@
305	305
306	306	PPChameleonEVB PPC405EP
307	307
	308	+Tirumala Marri <tmarri@apm.com>
	309	+
	310	+ bluestone APM821XX
	311	+
308	312	Reinhard Meyer <r.meyer@emk-elektronik.de>
309	313
310	314	TOP860 MPC860T
...	...	@@ -343,6 +347,10 @@
343	347	sbc8240 MPC8240
344	348	sbc405 PPC405GP
345	349
	350	+Sergei Poselenov <sposelenov@emcraft.com>
	351	+
	352	+ a4m072 MPC5200
	353	+
346	354	Sudhakar Rajashekhara <sudhakar.raj@ti.com>
347	355
348	356	da850evm ARM926EJS (DA850/OMAP-L138)
...	...	@@ -497,10 +505,6 @@
497	505	Detlev Zundel <dzu@denx.de>
498	506
499	507	inka4x0 MPC5200
500		-
501		-Tirumala Marri <tmarri@apm.com>
502		-
503		- bluestone APM821XX
504	508
505	509	-------------------------------------------------------------------------
506	510
	1	+#
	2	+# (C) Copyright 2003-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = $(obj)lib$(BOARD).a
	27	+
	28	+COBJS := $(BOARD).o
	29	+
	30	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	31	+OBJS := $(addprefix $(obj),$(COBJS))
	32	+SOBJS := $(addprefix $(obj),$(SOBJS))
	33	+
	34	+$(LIB): $(obj).depend $(OBJS)
	35	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	36	+
	37	+clean:
	38	+ rm -f $(SOBJS) $(OBJS)
	39	+
	40	+distclean: clean
	41	+ rm -f $(LIB) core *.bak $(obj).depend
	42	+
	43	+#########################################################################
	44	+
	45	+# defines $(obj).depend target
	46	+include $(SRCTREE)/rules.mk
	47	+
	48	+sinclude $(obj).depend
	49	+
	50	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2003
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * (C) Copyright 2004
	6	+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	+ *
	8	+ * (C) Copyright 2010
	9	+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	10	+ *
	11	+ * See file CREDITS for list of people who contributed to this
	12	+ * project.
	13	+ *
	14	+ * This program is free software; you can redistribute it and/or
	15	+ * modify it under the terms of the GNU General Public License as
	16	+ * published by the Free Software Foundation; either version 2 of
	17	+ * the License, or (at your option) any later version.
	18	+ *
	19	+ * This program is distributed in the hope that it will be useful,
	20	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	+ * GNU General Public License for more details.
	23	+ *
	24	+ * You should have received a copy of the GNU General Public License
	25	+ * along with this program; if not, write to the Free Software
	26	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	+ * MA 02111-1307 USA
	28	+ */
	29	+
	30	+#include <common.h>
	31	+#include <mpc5xxx.h>
	32	+#include <pci.h>
	33	+#include <asm/processor.h>
	34	+#include <asm/io.h>
	35	+#include <libfdt.h>
	36	+#include <netdev.h>
	37	+
	38	+#include "mt46v32m16.h"
	39	+
	40	+#ifndef CONFIG_SYS_RAMBOOT
	41	+static void sdram_start (int hi_addr)
	42	+{
	43	+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	44	+ long control = SDRAM_CONTROL \| hi_addr_bit;
	45	+
	46	+ /* unlock mode register */
	47	+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000000);
	48	+ __asm__ volatile ("sync");
	49	+
	50	+ /* precharge all banks */
	51	+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);
	52	+ __asm__ volatile ("sync");
	53	+
	54	+#if SDRAM_DDR
	55	+ /* set mode register: extended mode */
	56	+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
	57	+ __asm__ volatile ("sync");
	58	+
	59	+ /* set mode register: reset DLL */
	60	+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE \| 0x04000000);
	61	+ __asm__ volatile ("sync");
	62	+#endif
	63	+
	64	+ /* precharge all banks */
	65	+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);
	66	+ __asm__ volatile ("sync");
	67	+
	68	+ /* auto refresh */
	69	+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000004);
	70	+ __asm__ volatile ("sync");
	71	+
	72	+ /* set mode register */
	73	+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
	74	+ __asm__ volatile ("sync");
	75	+
	76	+ /* normal operation */
	77	+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
	78	+ __asm__ volatile ("sync");
	79	+}
	80	+#endif
	81	+
	82	+/*
	83	+ * ATTENTION: Although partially referenced initdram does NOT make real use
	84	+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
	85	+ * is something else than 0x00000000.
	86	+ */
	87	+
	88	+phys_size_t initdram (int board_type)
	89	+{
	90	+ ulong dramsize = 0;
	91	+ uint svr, pvr;
	92	+
	93	+#ifndef CONFIG_SYS_RAMBOOT
	94	+ ulong test1, test2;
	95	+
	96	+ /* setup SDRAM chip selects */
	97	+ out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0x0000001e); / 2GB at 0x0 */
	98	+ out_be32((void )MPC5XXX_SDRAM_CS1CFG, 0x80000000); / disabled */
	99	+ __asm__ volatile ("sync");
	100	+
	101	+ /* setup config registers */
	102	+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	103	+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
	104	+ __asm__ volatile ("sync");
	105	+
	106	+#if SDRAM_DDR
	107	+ /* set tap delay */
	108	+ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
	109	+ __asm__ volatile ("sync");
	110	+#endif
	111	+
	112	+ /* find RAM size using SDRAM CS0 only */
	113	+ sdram_start(0);
	114	+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	115	+ sdram_start(1);
	116	+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	117	+ if (test1 > test2) {
	118	+ sdram_start(0);
	119	+ dramsize = test1;
	120	+ } else {
	121	+ dramsize = test2;
	122	+ }
	123	+
	124	+ /* memory smaller than 1MB is impossible */
	125	+ if (dramsize < (1 << 20)) {
	126	+ dramsize = 0;
	127	+ }
	128	+
	129	+ /* set SDRAM CS0 size according to the amount of RAM found */
	130	+ if (dramsize > 0) {
	131	+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
	132	+ 0x13 + __builtin_ffs(dramsize >> 20) - 1);
	133	+ } else {
	134	+ out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0); / disabled */
	135	+ }
	136	+
	137	+#else /* CONFIG_SYS_RAMBOOT */
	138	+
	139	+ /* retrieve size of memory connected to SDRAM CS0 */
	140	+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
	141	+ if (dramsize >= 0x13) {
	142	+ dramsize = (1 << (dramsize - 0x13)) << 20;
	143	+ } else {
	144	+ dramsize = 0;
	145	+ }
	146	+
	147	+#endif /* CONFIG_SYS_RAMBOOT */
	148	+
	149	+ /*
	150	+ * On MPC5200B we need to set the special configuration delay in the
	151	+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	152	+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	153	+ *
	154	+ * "The SDelay should be written to a value of 0x00000004. It is
	155	+ * required to account for changes caused by normal wafer processing
	156	+ * parameters."
	157	+ */
	158	+ svr = get_svr();
	159	+ pvr = get_pvr();
	160	+ if ((SVR_MJREV(svr) >= 2) &&
	161	+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	162	+
	163	+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
	164	+ __asm__ volatile ("sync");
	165	+ }
	166	+
	167	+ return dramsize;
	168	+}
	169	+
	170	+int checkboard (void)
	171	+{
	172	+ puts ("Board: A4M072\n");
	173	+ return 0;
	174	+}
	175	+
	176	+#ifdef CONFIG_PCI
	177	+static struct pci_controller hose;
	178	+
	179	+extern void pci_mpc5xxx_init(struct pci_controller *);
	180	+
	181	+void pci_init_board(void)
	182	+{
	183	+ pci_mpc5xxx_init(&hose);
	184	+}
	185	+#endif
	186	+
	187	+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	188	+void
	189	+ft_board_setup(void blob, bd_t bd)
	190	+{
	191	+ ft_cpu_setup(blob, bd);
	192	+}
	193	+#endif
	194	+
	195	+int board_eth_init(bd_t *bis)
	196	+{
	197	+ int rv, num_if = 0;
	198	+
	199	+ /* Initialize TSECs first */
	200	+ if ((rv = cpu_eth_init(bis)) >= 0)
	201	+ num_if += rv;
	202	+ else
	203	+ printf("ERROR: failed to initialize FEC.\n");
	204	+
	205	+ if ((rv = pci_eth_init(bis)) >= 0)
	206	+ num_if += rv;
	207	+ else
	208	+ printf("ERROR: failed to initialize PCI Ethernet.\n");
	209	+
	210	+ return num_if;
	211	+}
	212	+/*
	213	+ * Miscellaneous late-boot configurations
	214	+ *
	215	+ * Initialize EEPROM write-protect GPIO pin.
	216	+ */
	217	+int misc_init_r(void)
	218	+{
	219	+#if defined(CONFIG_SYS_EEPROM_WREN)
	220	+ /* Enable GPIO pin */
	221	+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
	222	+ /* Set direction, output */
	223	+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
	224	+ /* De-assert write enable */
	225	+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
	226	+#endif
	227	+ return 0;
	228	+}
	229	+#if defined(CONFIG_SYS_EEPROM_WREN)
	230	+/* Input: <dev_addr> I2C address of EEPROM device to enable.
	231	+ * <state> -1: deliver current state
	232	+ * 0: disable write
	233	+ * 1: enable write
	234	+ * Returns: -1: wrong device address
	235	+ * 0: dis-/en- able done
	236	+ * 0/1: current state if <state> was -1.
	237	+ */
	238	+int eeprom_write_enable (unsigned dev_addr, int state)
	239	+{
	240	+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
	241	+ return -1;
	242	+ } else {
	243	+ switch (state) {
	244	+ case 1:
	245	+ /* Enable write access */
	246	+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
	247	+ state = 0;
	248	+ break;
	249	+ case 0:
	250	+ /* Disable write access */
	251	+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
	252	+ state = 0;
	253	+ break;
	254	+ default:
	255	+ /* Read current status back. */
	256	+ state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
	257	+ CONFIG_SYS_EEPROM_WP));
	258	+ break;
	259	+ }
	260	+ }
	261	+ return state;
	262	+}
	263	+#endif
	1	+#
	2	+# (C) Copyright 2003
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+#
	25	+# a4m072 board:
	26	+#
	27	+# Valid values for TEXT_BASE is:
	28	+#
	29	+# 0xFE000000 boot low
	30	+#
	31	+
	32	+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
	33	+
	34	+ifndef TEXT_BASE
	35	+## Standard: boot low
	36	+TEXT_BASE = 0xFE000000
	37	+endif
	38	+
	39	+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
...	...	@@ -90,6 +90,7 @@
90	90	DB64460 powerpc 74xx_7xx db64460 Marvell
91	91	aria powerpc mpc512x - davedenx
92	92	PATI powerpc mpc5xx pati mpl
	93	+a4m072 powerpc mpc5xxx a4m072
93	94	BC3450 powerpc mpc5xxx bc3450
94	95	canmb powerpc mpc5xxx
95	96	cm5200 powerpc mpc5xxx
	1	+/*
	2	+ * (C) Copyright 2003-2005
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * (C) Copyright 2010
	6	+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#ifndef __CONFIG_H
	28	+#define __CONFIG_H
	29	+
	30	+/*
	31	+ * High Level Configuration Options
	32	+ * (easy to change)
	33	+ */
	34	+
	35	+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	+#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
	37	+#define CONFIG_A4M072 1 /* ... on A4M072 board */
	38	+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	39	+
	40	+#define CONFIG_MISC_INIT_R
	41	+
	42	+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	43	+
	44	+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	45	+#define BOOTFLAG_WARM 0x02 /* Software reboot */
	46	+
	47	+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	48	+
	49	+/*
	50	+ * Serial console configuration
	51	+ */
	52	+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	53	+#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
	54	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	55	+/* define to enable silent console */
	56	+#define CONFIG_SILENT_CONSOLE
	57	+#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
	58	+
	59	+/*
	60	+ * PCI Mapping:
	61	+ * 0x40000000 - 0x4fffffff - PCI Memory
	62	+ * 0x50000000 - 0x50ffffff - PCI IO Space
	63	+ */
	64	+#define CONFIG_PCI
	65	+
	66	+#if defined(CONFIG_PCI)
	67	+#define CONFIG_PCI_PNP 1
	68	+#define CONFIG_PCI_SCAN_SHOW 1
	69	+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	70	+
	71	+#define CONFIG_PCI_MEM_BUS 0x40000000
	72	+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	73	+#define CONFIG_PCI_MEM_SIZE 0x10000000
	74	+
	75	+#define CONFIG_PCI_IO_BUS 0x50000000
	76	+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	77	+#define CONFIG_PCI_IO_SIZE 0x01000000
	78	+#endif
	79	+
	80	+#define CONFIG_SYS_XLB_PIPELINING 1
	81	+
	82	+#undef CONFIG_NET_MULTI
	83	+#undef CONFIG_EEPRO100
	84	+
	85	+/* Partitions */
	86	+#define CONFIG_MAC_PARTITION
	87	+#define CONFIG_DOS_PARTITION
	88	+
	89	+/* USB */
	90	+#define CONFIG_USB_OHCI_NEW
	91	+#define CONFIG_USB_STORAGE
	92	+#define CONFIG_SYS_OHCI_BE_CONTROLLER
	93	+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	94	+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	95	+#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	96	+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	97	+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	98	+
	99	+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	100	+
	101	+/*
	102	+ * BOOTP options
	103	+ */
	104	+#define CONFIG_BOOTP_BOOTFILESIZE
	105	+#define CONFIG_BOOTP_BOOTPATH
	106	+#define CONFIG_BOOTP_GATEWAY
	107	+#define CONFIG_BOOTP_HOSTNAME
	108	+
	109	+
	110	+/*
	111	+ * Command line configuration.
	112	+ */
	113	+#include <config_cmd_default.h>
	114	+
	115	+#define CONFIG_CMD_EEPROM
	116	+#define CONFIG_CMD_FAT
	117	+#define CONFIG_CMD_I2C
	118	+#define CONFIG_CMD_IDE
	119	+#define CONFIG_CMD_NFS
	120	+#define CONFIG_CMD_SNTP
	121	+#define CONFIG_CMD_USB
	122	+#define CONFIG_CMD_MII
	123	+#define CONFIG_CMD_DHCP
	124	+#define CONFIG_CMD_PING
	125	+
	126	+#if defined(CONFIG_PCI)
	127	+#define CONFIG_CMD_PCI
	128	+#endif
	129	+
	130	+#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
	131	+#define CONFIG_SYS_LOWBOOT 1
	132	+#define CONFIG_SYS_LOWBOOT32 1
	133	+#endif
	134	+
	135	+/*
	136	+ * Autobooting
	137	+ */
	138	+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
	139	+
	140	+#define CONFIG_SYS_AUTOLOAD "n"
	141	+
	142	+#define CONFIG_AUTOBOOT_KEYED
	143	+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
	144	+#define CONFIG_AUTOBOOT_DELAY_STR "asdfg"
	145	+
	146	+#undef CONFIG_BOOTARGS
	147	+#define CONFIG_PREBOOT "run try_update"
	148	+
	149	+#define CONFIG_EXTRA_ENV_SETTINGS \
	150	+ "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
	151	+ "cf1=diskboot 200000 0:1\0" \
	152	+ "bootcmd_cf1=run bcf1\0" \
	153	+ "bcf=setenv bootargs root=/dev/hda3\0" \
	154	+ "bootcmd_nfs=run bnfs\0" \
	155	+ "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
	156	+ "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
	157	+ "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
	158	+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
	159	+ "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
	160	+ "env_addr=FE060000\0" \
	161	+ "kernel_addr=FE100000\0" \
	162	+ "rootfs_addr=FE200000\0" \
	163	+ "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
	164	+ "bcf1=run cf1; run bcf; run addip; run bk\0" \
	165	+ "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
	166	+ "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
	167	+ "hostname=CPUP0\0" \
	168	+ "ethaddr=00:00:00:00:00:00\0" \
	169	+ "netdev=eth0\0" \
	170	+ "bootcmd=run bootcmd_nor\0" \
	171	+ ""
	172	+/*
	173	+ * IPB Bus clocking configuration.
	174	+ */
	175	+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	176	+
	177	+/*
	178	+ * I2C configuration
	179	+ */
	180	+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	181	+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	182	+
	183	+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	184	+#define CONFIG_SYS_I2C_SLAVE 0x7F
	185	+
	186	+/*
	187	+ * EEPROM configuration
	188	+ */
	189	+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
	190	+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	191	+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	192	+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	193	+#define CONFIG_SYS_EEPROM_WREN 1
	194	+#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
	195	+
	196	+/*
	197	+ * Flash configuration
	198	+ */
	199	+#define CONFIG_SYS_FLASH_BASE 0xFE000000
	200	+#define CONFIG_SYS_FLASH_SIZE 0x02000000
	201	+#if !defined(CONFIG_SYS_LOWBOOT)
	202	+#error "CONFIG_SYS_LOWBOOT not defined?"
	203	+#else /* CONFIG_SYS_LOWBOOT */
	204	+#if defined(CONFIG_SYS_LOWBOOT32)
	205	+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
	206	+#endif
	207	+#endif /* CONFIG_SYS_LOWBOOT */
	208	+
	209	+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	210	+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	211	+#define CONFIG_FLASH_CFI_DRIVER
	212	+#define CONFIG_SYS_FLASH_CFI
	213	+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	214	+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
	215	+
	216	+/*
	217	+ * Environment settings
	218	+ */
	219	+#define CONFIG_ENV_IS_IN_FLASH 1
	220	+#define CONFIG_ENV_SIZE 0x10000
	221	+#define CONFIG_ENV_SECT_SIZE 0x20000
	222	+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	223	+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	224	+
	225	+#define CONFIG_ENV_OVERWRITE 1
	226	+
	227	+/*
	228	+ * Memory map
	229	+ */
	230	+#define CONFIG_SYS_MBAR 0xF0000000
	231	+#define CONFIG_SYS_SDRAM_BASE 0x00000000
	232	+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	233	+
	234	+/* Use SRAM until RAM will be available */
	235	+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
	236	+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	237	+
	238	+
	239	+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	240	+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	241	+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	242	+
	243	+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	244	+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	245	+# define CONFIG_SYS_RAMBOOT 1
	246	+#endif
	247	+
	248	+#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	249	+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	250	+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	251	+
	252	+/*
	253	+ * Ethernet configuration
	254	+ */
	255	+#define CONFIG_MPC5xxx_FEC 1
	256	+#define CONFIG_MPC5xxx_FEC_MII100
	257	+/*
	258	+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
	259	+ */
	260	+/* #define CONFIG_MPC5xxx_FEC_MII10 */
	261	+#define CONFIG_PHY_ADDR 0x1f
	262	+#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
	263	+
	264	+/*
	265	+ * GPIO configuration
	266	+ */
	267	+#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
	268	+
	269	+/*
	270	+ * Miscellaneous configurable options
	271	+ */
	272	+#define CONFIG_SYS_HUSH_PARSER
	273	+#define CONFIG_CMDLINE_EDITING 1
	274	+#ifdef CONFIG_SYS_HUSH_PARSER
	275	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	276	+#endif
	277	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	278	+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	279	+#if defined(CONFIG_CMD_KGDB)
	280	+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	281	+#else
	282	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	283	+#endif
	284	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	285	+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	286	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	287	+
	288	+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	289	+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	290	+
	291	+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	292	+
	293	+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
	294	+
	295	+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	296	+#if defined(CONFIG_CMD_KGDB)
	297	+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	298	+#endif
	299	+
	300	+
	301	+/*
	302	+ * Various low-level settings
	303	+ */
	304	+#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	305	+#define CONFIG_SYS_HID0_FINAL HID0_ICE
	306	+/* Flash at CSBoot, CS0 */
	307	+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	308	+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	309	+#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
	310	+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	311	+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	312	+/* External SRAM at CS1 */
	313	+#define CONFIG_SYS_CS1_START 0x62000000
	314	+#define CONFIG_SYS_CS1_SIZE 0x00400000
	315	+#define CONFIG_SYS_CS1_CFG 0x00009930
	316	+#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
	317	+#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
	318	+
	319	+
	320	+#define CONFIG_SYS_CS_BURST 0x00000000
	321	+#define CONFIG_SYS_CS_DEADCYCLE 0x33333003
	322	+
	323	+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
	324	+
	325	+/*-----------------------------------------------------------------------
	326	+ * USB stuff
	327	+ *-----------------------------------------------------------------------
	328	+ */
	329	+#define CONFIG_USB_CLOCK 0x0001BBBB
	330	+#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
	331	+
	332	+/*-----------------------------------------------------------------------
	333	+ * IDE/ATA stuff Supports IDE harddisk
	334	+ *-----------------------------------------------------------------------
	335	+ */
	336	+
	337	+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	338	+
	339	+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	340	+#undef CONFIG_IDE_LED /* LED for ide not supported */
	341	+
	342	+#define CONFIG_IDE_PREINIT
	343	+
	344	+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	345	+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
	346	+
	347	+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	348	+
	349	+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	350	+
	351	+/* Offset for data I/O */
	352	+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	353	+
	354	+/* Offset for normal register accesses */
	355	+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
	356	+
	357	+/* Offset for alternate registers */
	358	+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
	359	+
	360	+/* Interval between registers */
	361	+#define CONFIG_SYS_ATA_STRIDE 4
	362	+
	363	+#define CONFIG_ATAPI 1
	364	+
	365	+/*-----------------------------------------------------------------------
	366	+ * Open firmware flat tree support
	367	+ *-----------------------------------------------------------------------
	368	+ */
	369	+#define CONFIG_OF_LIBFDT 1
	370	+#define CONFIG_OF_BOARD_SETUP 1
	371	+
	372	+#define OF_CPU "PowerPC,5200@0"
	373	+#define OF_SOC "soc5200@f0000000"
	374	+#define OF_TBCLK (bd->bi_busfreq / 4)
	375	+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	376	+
	377	+#endif /* __CONFIG_H */
...	...	@@ -160,11 +160,12 @@
160	160	#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
161	161	#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
162	162
163		-/* GPIO pins */
	163	+/* GPIO pins, for Rev.B chip */
164	164	#define GPIO_WKUP_7 0x80000000UL
165	165	#define GPIO_PSC6_0 0x10000000UL
166	166	#define GPIO_PSC3_9 0x04000000UL
167	167	#define GPIO_PSC1_4 0x01000000UL
	168	+#define GPIO_PSC2_4 0x02000000UL
168	169
169	170	#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
170	171	#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL