Eric Lee / smarc-uboot

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Commit 95688de311e238ccfba21c50b1b67ceffbdc7fc5

Authored by Tuomas Tynkkynen
Committed by Tom Rini
1 parent 7b7341d7f3
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

spi: Drop CONFIG_ATMEL_DATAFLASH_SPI 

Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>

Showing 2 changed files with 0 additions and 185 deletions Side-by-side Diff

drivers/spi/Makefile
Diff comments   View file @ 95688de
... ... @@ -17,7 +17,6 @@
17 17  
18 18 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
19 19 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
20   -obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
21 20 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
22 21 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
23 22 obj-$(CONFIG_CF_SPI) += cf_spi.o
drivers/spi/atmel_dataflash_spi.c
View file @ 95688de
1   -/*
2   - * Driver for ATMEL DataFlash support
3   - * Author : Hamid Ikdoumi (Atmel)
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * This driver desperately needs rework:
10   - *
11   - * - use structure SoC access
12   - * - get rid of including asm/arch/at91_spi.h
13   - * - remove asm/arch/at91_spi.h
14   - * - get rid of all CONFIG_ATMEL_LEGACY defines and uses
15   - *
16   - * 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de>
17   - */
18   -
19   -#include <common.h>
20   -#ifndef CONFIG_ATMEL_LEGACY
21   -# define CONFIG_ATMEL_LEGACY
22   -#endif
23   -#include <spi.h>
24   -#include <malloc.h>
25   -
26   -#include <asm/io.h>
27   -
28   -#include <asm/arch/clk.h>
29   -#include <asm/arch/hardware.h>
30   -
31   -#include "atmel_spi.h"
32   -
33   -#include <asm/arch/gpio.h>
34   -#include <asm/arch/at91_pio.h>
35   -#include <asm/arch/at91_spi.h>
36   -
37   -#include <dataflash.h>
38   -
39   -#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
40   -#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
41   -#define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
42   -#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
43   -
44   -void AT91F_SpiInit(void)
45   -{
46   - /* Reset the SPI */
47   - writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
48   -
49   - /* Configure SPI in Master Mode with No CS selected !!! */
50   - writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
51   - ATMEL_BASE_SPI0 + AT91_SPI_MR);
52   -
53   - /* Configure CS0 */
54   - writel(AT91_SPI_NCPHA |
55   - (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
56   - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
57   - ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
58   - ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
59   -
60   -#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
61   - /* Configure CS1 */
62   - writel(AT91_SPI_NCPHA |
63   - (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
64   - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
65   - ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
66   - ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
67   -#endif
68   -#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
69   - /* Configure CS2 */
70   - writel(AT91_SPI_NCPHA |
71   - (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
72   - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
73   - ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
74   - ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
75   -#endif
76   -#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
77   - /* Configure CS3 */
78   - writel(AT91_SPI_NCPHA |
79   - (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
80   - (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
81   - ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
82   - ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
83   -#endif
84   -
85   - /* SPI_Enable */
86   - writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
87   -
88   - while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
89   - ;
90   -
91   - /*
92   - * Add tempo to get SPI in a safe state.
93   - * Should not be needed for new silicon (Rev B)
94   - */
95   - udelay(500000);
96   - readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
97   - readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
98   -
99   -}
100   -
101   -void AT91F_SpiEnable(int cs)
102   -{
103   - unsigned long mode;
104   -
105   - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
106   - mode &= ~AT91_SPI_PCS;
107   -
108   - switch (cs) {
109   - case 0:
110   - mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16;
111   - break;
112   - case 1:
113   - mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16;
114   - break;
115   - case 2:
116   - mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16;
117   - break;
118   - case 3:
119   - mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16;
120   - break;
121   - }
122   -
123   - writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR);
124   -
125   - /* SPI_Enable */
126   - writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
127   -}
128   -
129   -unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
130   -
131   -unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
132   -{
133   - unsigned int timeout;
134   - unsigned int timebase;
135   -
136   - pDesc->state = BUSY;
137   -
138   - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
139   - ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
140   -
141   - /* Initialize the Transmit and Receive Pointer */
142   - writel((unsigned int)pDesc->rx_cmd_pt,
143   - ATMEL_BASE_SPI0 + AT91_SPI_RPR);
144   - writel((unsigned int)pDesc->tx_cmd_pt,
145   - ATMEL_BASE_SPI0 + AT91_SPI_TPR);
146   -
147   - /* Intialize the Transmit and Receive Counters */
148   - writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
149   - writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
150   -
151   - if (pDesc->tx_data_size != 0) {
152   - /* Initialize the Next Transmit and Next Receive Pointer */
153   - writel((unsigned int)pDesc->rx_data_pt,
154   - ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
155   - writel((unsigned int)pDesc->tx_data_pt,
156   - ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
157   -
158   - /* Intialize the Next Transmit and Next Receive Counters */
159   - writel(pDesc->rx_data_size,
160   - ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
161   - writel(pDesc->tx_data_size,
162   - ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
163   - }
164   -
165   - /* arm simple, non interrupt dependent timer */
166   - timebase = get_timer(0);
167   - timeout = 0;
168   -
169   - writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
170   - ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
171   - while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
172   - ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
173   - ;
174   - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
175   - ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
176   - pDesc->state = IDLE;
177   -
178   - if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
179   - printf("Error Timeout\n\r");
180   - return DATAFLASH_ERROR;
181   - }
182   -
183   - return DATAFLASH_OK;
184   -}