edminiv2: switch to SPL

ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

edminiv2: switch to SPL
ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert ARIBAUD
1 parent c1b0fad9b6
Showing 8 changed files with 132 additions and 6 deletions Side-by-side Diff
arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
arch/arm/include/asm/arch-orion5x/spl.h
arch/arm/mach-orion5x/Kconfig
arch/arm/mach-orion5x/cpu.c
arch/arm/mach-orion5x/lowlevel_init.S
board/LaCie/edminiv2/edminiv2.c
configs/edminiv2_defconfig
include/configs/edminiv2.h
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on:
+ *
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		CPUDIR/start.o	(.text)
+		*(.text*)
+	} > .nor
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .nor
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss
+}
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NOR		1
@@ -5,6 +5,7 @@
  
 config TARGET_EDMINIV2
 	bool "LaCie Ethernet Disk mini V2"
+	select SUPPORT_SPL
  
 endchoice
  
@@ -234,7 +234,9 @@
 	/* Enable and invalidate L2 cache in write through mode */
 	invalidate_l2_cache();
  
+#ifdef CONFIG_SPL_BUILD
 	orion5x_config_adr_windows();
+#endif
  
 	return 0;
 }
@@ -62,14 +62,16 @@
 /*
  * Low-level init happens right after start.S has switched to SVC32,
  * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
+ * from the boot chip select, so the first thing SPL should do is to
+ * set up the RAM to copy U-Boot into.
  */
  
 .globl lowlevel_init
  
 lowlevel_init:
  
+#ifdef CONFIG_SPL_BUILD
+
 	/* Use 'r4 as the base for internal register accesses */
 	ldr	r4, =ORION5X_REGS_PHY_BASE
  
@@ -272,6 +274,14 @@
 	ldr	r2, [r3, #0x484]
 	orr	r2, r2, r6
 	str	r2, [r3, #0x484]
+
+	/* enable for 2 GB DDR; detection should find out real amount */
+	sub	r6, r6, r6
+	str	r6, [r3, #0x500]
+	ldr	r6, =0x7fff0001
+	str	r6, [r3, #0x504]
+
+#endif /* CONFIG_SPL_BUILD */
  
 	/* Return to U-boot via saved link register */
 	mov	pc, lr
@@ -12,6 +12,8 @@
 #include <miiphy.h>
 #include <asm/arch/orion5x.h>
 #include "../common/common.h"
+#include <spl.h>
+#include <ns16550.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -83,4 +85,22 @@
 	mv_phy_88e1116_init("egiga0", 8);
 }
 #endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * SPL serial setup and NOR boot device selection
+ */
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+#endif /* CONFIG_SPL_BUILD */
-CONFIG_ARM=y
-CONFIG_ORION5X=y
-CONFIG_TARGET_EDMINIV2=y
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ORION5X=y
++S:CONFIG_TARGET_EDMINIV2=y
@@ -13,8 +13,29 @@
 #define _CONFIG_EDMINIV2_H
  
 /* general settings */
-#define CONFIG_SYS_TEXT_BASE 0xfff90000
 #define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE		0xffff0000
+#define CONFIG_SPL_MAX_SIZE		0x0000fff0
+#define CONFIG_SPL_STACK		0x00020000
+#define CONFIG_SPL_BSS_START_ADDR	0x00020000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
+#define CONFIG_SYS_SPL_MALLOC_START	0x00040000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/orion5x/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_UBOOT_BASE		0xfff90000
+#define CONFIG_SYS_UBOOT_START		0x00800000
+#define CONFIG_SYS_TEXT_BASE 		0x00800000
  
 /*
  * Version number information
	1	+/*
	2	+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
	3	+ *
	4	+ * Based on:
	5	+ *
	6	+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	7	+ * Tom Cubie <tangliang@allwinnertech.com>
	8	+ *
	9	+ * Based on omap-common/u-boot-spl.lds:
	10	+ *
	11	+ * (C) Copyright 2002
	12	+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
	13	+ *
	14	+ * (C) Copyright 2010
	15	+ * Texas Instruments, <www.ti.com>
	16	+ * Aneesh V <aneesh@ti.com>
	17	+ *
	18	+ * SPDX-License-Identifier: GPL-2.0+
	19	+ */
	20	+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
	21	+ LENGTH = CONFIG_SPL_MAX_SIZE }
	22	+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
	23	+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
	24	+
	25	+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
	26	+OUTPUT_ARCH(arm)
	27	+ENTRY(_start)
	28	+SECTIONS
	29	+{
	30	+ .text :
	31	+ {
	32	+ __start = .;
	33	+ *(.vectors)
	34	+ CPUDIR/start.o (.text)
	35	+ (.text)
	36	+ } > .nor
	37	+
	38	+ . = ALIGN(4);
	39	+ .rodata : { (SORT_BY_ALIGNMENT(.rodata)) } >.nor
	40	+
	41	+ . = ALIGN(4);
	42	+ .data : { (SORT_BY_ALIGNMENT(.data)) } >.nor
	43	+
	44	+ . = ALIGN(4);
	45	+ .u_boot_list : {
	46	+ KEEP((SORT(.u_boot_list)));
	47	+ } > .nor
	48	+
	49	+ . = ALIGN(4);
	50	+ __image_copy_end = .;
	51	+ _end = .;
	52	+
	53	+ .bss :
	54	+ {
	55	+ . = ALIGN(4);
	56	+ __bss_start = .;
	57	+ (.bss)
	58	+ . = ALIGN(4);
	59	+ __bss_end = .;
	60	+ } > .bss
	61	+}
...	...	@@ -5,6 +5,7 @@
5	5
6	6	config TARGET_EDMINIV2
7	7	bool "LaCie Ethernet Disk mini V2"
	8	+ select SUPPORT_SPL
8	9
9	10	endchoice
10	11
...	...	@@ -234,7 +234,9 @@
234	234	/* Enable and invalidate L2 cache in write through mode */
235	235	invalidate_l2_cache();
236	236
	237	+#ifdef CONFIG_SPL_BUILD
237	238	orion5x_config_adr_windows();
	239	+#endif
238	240
239	241	return 0;
240	242	}
...	...	@@ -62,14 +62,16 @@
62	62	/*
63	63	* Low-level init happens right after start.S has switched to SVC32,
64	64	* flushed and disabled caches and disabled MMU. We're still running
65		- * from the boot chip select, so the first thing we should do is set
66		- * up RAM for us to relocate into.
	65	+ * from the boot chip select, so the first thing SPL should do is to
	66	+ * set up the RAM to copy U-Boot into.
67	67	*/
68	68
69	69	.globl lowlevel_init
70	70
71	71	lowlevel_init:
72	72
	73	+#ifdef CONFIG_SPL_BUILD
	74	+
73	75	/* Use 'r4 as the base for internal register accesses */
74	76	ldr r4, =ORION5X_REGS_PHY_BASE
75	77
...	...	@@ -272,6 +274,14 @@
272	274	ldr r2, [r3, #0x484]
273	275	orr r2, r2, r6
274	276	str r2, [r3, #0x484]
	277	+
	278	+ /* enable for 2 GB DDR; detection should find out real amount */
	279	+ sub r6, r6, r6
	280	+ str r6, [r3, #0x500]
	281	+ ldr r6, =0x7fff0001
	282	+ str r6, [r3, #0x504]
	283	+
	284	+#endif /* CONFIG_SPL_BUILD */
275	285
276	286	/* Return to U-boot via saved link register */
277	287	mov pc, lr
...	...	@@ -12,6 +12,8 @@
12	12	#include <miiphy.h>
13	13	#include <asm/arch/orion5x.h>
14	14	#include "../common/common.h"
	15	+#include <spl.h>
	16	+#include <ns16550.h>
15	17
16	18	DECLARE_GLOBAL_DATA_PTR;
17	19
...	...	@@ -83,4 +85,22 @@
83	85	mv_phy_88e1116_init("egiga0", 8);
84	86	}
85	87	#endif /* CONFIG_RESET_PHY_R */
	88	+
	89	+/*
	90	+ * SPL serial setup and NOR boot device selection
	91	+ */
	92	+
	93	+#ifdef CONFIG_SPL_BUILD
	94	+
	95	+void spl_board_init(void)
	96	+{
	97	+ preloader_console_init();
	98	+}
	99	+
	100	+u32 spl_boot_device(void)
	101	+{
	102	+ return BOOT_DEVICE_NOR;
	103	+}
	104	+
	105	+#endif /* CONFIG_SPL_BUILD */
1		-CONFIG_ARM=y
2		-CONFIG_ORION5X=y
3		-CONFIG_TARGET_EDMINIV2=y
	1	+CONFIG_SPL=y
	2	++S:CONFIG_ARM=y
	3	++S:CONFIG_ORION5X=y
	4	++S:CONFIG_TARGET_EDMINIV2=y
...	...	@@ -13,8 +13,29 @@
13	13	#define _CONFIG_EDMINIV2_H
14	14
15	15	/* general settings */
16		-#define CONFIG_SYS_TEXT_BASE 0xfff90000
17	16	#define CONFIG_SYS_GENERIC_BOARD
	17	+
	18	+/*
	19	+ * SPL
	20	+ */
	21	+
	22	+#define CONFIG_SPL_FRAMEWORK
	23	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	24	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	25	+#define CONFIG_SPL_SERIAL_SUPPORT
	26	+#define CONFIG_SPL_NOR_SUPPORT
	27	+#define CONFIG_SPL_TEXT_BASE 0xffff0000
	28	+#define CONFIG_SPL_MAX_SIZE 0x0000fff0
	29	+#define CONFIG_SPL_STACK 0x00020000
	30	+#define CONFIG_SPL_BSS_START_ADDR 0x00020000
	31	+#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
	32	+#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
	33	+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
	34	+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
	35	+#define CONFIG_SPL_BOARD_INIT
	36	+#define CONFIG_SYS_UBOOT_BASE 0xfff90000
	37	+#define CONFIG_SYS_UBOOT_START 0x00800000
	38	+#define CONFIG_SYS_TEXT_BASE 0x00800000
18	39
19	40	/*
20	41	* Version number information