FSL DDR: Convert MPC8540ADS to new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

FSL DDR: Convert MPC8540ADS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala
1 parent 2a6c2d7ab2
Showing 4 changed files with 110 additions and 40 deletions Side-by-side Diff
board/freescale/mpc8540ads/Makefile
board/freescale/mpc8540ads/ddr.c
board/freescale/mpc8540ads/mpc8540ads.c
include/configs/MPC8540ADS.h
@@ -25,11 +25,14 @@
  
 LIB	= $(obj)lib$(BOARD).a
  
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
  
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
  
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
- /*
+/*
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2002,2003, Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
  
@@ -28,8 +28,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <spd_sdram.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
  
  
@@ -82,10 +83,13 @@
 	}
 #endif
  
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+	dram_size *= 0x100000;
 #else
-	dram_size = fixed_sdram ();
+	dram_size = fixed_sdram();
 #endif
  
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -48,13 +48,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
  
 /*
  
  
  
  
@@ -100,33 +93,33 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
  
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
  
-/*
- * DDR Setup
- */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
  
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000002
-    #define CFG_DDR_TIMING_1	0x37344321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
-#endif
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
  
+/* These are used when DDR doesn't use SPD. */
+#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
  
 /*
  * SDRAM on the Local Bus
...	...	@@ -25,11 +25,14 @@
25	25
26	26	LIB = $(obj)lib$(BOARD).a
27	27
28		-COBJS := $(BOARD).o law.o tlb.o
	28	+COBJS-y += $(BOARD).o
	29	+COBJS-y += ddr.o
	30	+COBJS-y += law.o
	31	+COBJS-y += tlb.o
29	32
30		-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31		-OBJS := $(addprefix $(obj),$(COBJS))
32		-SOBJS := $(addprefix $(obj),$(SOBJS))
	33	+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
	34	+OBJS := $(addprefix $(obj),$(COBJS-y))
	35	+SOBJS := $(addprefix $(obj),$(SOBJS-y))
33	36
34	37	$(LIB): $(obj).depend $(OBJS) $(SOBJS)
35	38	$(AR) $(ARFLAGS) $@ $(OBJS)
	1	+/*
	2	+ * Copyright 2008 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * Version 2 as published by the Free Software Foundation.
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <i2c.h>
	11	+
	12	+#include <asm/fsl_ddr_sdram.h>
	13	+
	14	+static void
	15	+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
	16	+{
	17	+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
	18	+}
	19	+
	20	+
	21	+unsigned int
	22	+fsl_ddr_get_mem_data_rate(void)
	23	+{
	24	+ return get_ddr_freq(0);
	25	+}
	26	+
	27	+
	28	+void
	29	+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
	30	+ unsigned int ctrl_num)
	31	+{
	32	+ unsigned int i;
	33	+ unsigned int i2c_address = 0;
	34	+
	35	+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
	36	+ if (ctrl_num == 0 && i == 0) {
	37	+ i2c_address = SPD_EEPROM_ADDRESS;
	38	+ }
	39	+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
	40	+ }
	41	+}
	42	+
	43	+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
	44	+{
	45	+ /*
	46	+ * Factors to consider for CPO:
	47	+ * - frequency
	48	+ * - ddr1 vs. ddr2
	49	+ */
	50	+ popts->cpo_override = 0;
	51	+
	52	+ /*
	53	+ * Factors to consider for write data delay:
	54	+ * - number of DIMMs
	55	+ *
	56	+ * 1 = 1/4 clock delay
	57	+ * 2 = 1/2 clock delay
	58	+ * 3 = 3/4 clock delay
	59	+ * 4 = 1 clock delay
	60	+ * 5 = 5/4 clock delay
	61	+ * 6 = 3/2 clock delay
	62	+ */
	63	+ popts->write_data_delay = 3;
	64	+
	65	+ /*
	66	+ * Factors to consider for half-strength driver enable:
	67	+ * - number of DIMMs installed
	68	+ */
	69	+ popts->half_strength_driver_enable = 0;
	70	+}
1		- /*
	1	+/*
2	2	* Copyright 2004 Freescale Semiconductor.
3	3	* (C) Copyright 2002,2003, Motorola Inc.
4	4	* Xianghua Xiao, (X.Xiao@motorola.com)
5	5
...	...	@@ -28,8 +28,9 @@
28	28	#include <common.h>
29	29	#include <pci.h>
30	30	#include <asm/processor.h>
	31	+#include <asm/mmu.h>
31	32	#include <asm/immap_85xx.h>
32		-#include <spd_sdram.h>
	33	+#include <asm/fsl_ddr_sdram.h>
33	34	#include <libfdt.h>
34	35	#include <fdt_support.h>
35	36
36	37
...	...	@@ -82,10 +83,13 @@
82	83	}
83	84	#endif
84	85
85		-#if defined(CONFIG_SPD_EEPROM)
86		- dram_size = spd_sdram ();
	86	+#ifdef CONFIG_SPD_EEPROM
	87	+ dram_size = fsl_ddr_sdram();
	88	+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	89	+
	90	+ dram_size *= 0x100000;
87	91	#else
88		- dram_size = fixed_sdram ();
	92	+ dram_size = fixed_sdram();
89	93	#endif
90	94
91	95	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
...	...	@@ -48,13 +48,6 @@
48	48	#define CONFIG_PCI
49	49	#define CONFIG_TSEC_ENET /* tsec ethernet support */
50	50	#define CONFIG_ENV_OVERWRITE
51		-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
52		-#define CONFIG_DDR_DLL /* possible DLL fix needed */
53		-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
54		-
55		-#define CONFIG_DDR_ECC /* only for ECC DDR module */
56		-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57		-
58	51	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
59	52
60	53	/*
61	54
62	55
63	56
64	57
...	...	@@ -100,33 +93,33 @@
100	93	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
101	94	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
102	95
	96	+/* DDR Setup */
	97	+#define CONFIG_FSL_DDR1
	98	+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	99	+#define CONFIG_DDR_SPD
	100	+#undef CONFIG_FSL_DDR_INTERACTIVE
103	101
104		-/*
105		- * DDR Setup
106		- */
	102	+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	103	+
107	104	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108	105	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
109	106
110		-#if defined(CONFIG_SPD_EEPROM)
111		- /*
112		- * Determine DDR configuration from I2C interface.
113		- */
114		- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	107	+#define CONFIG_NUM_DDR_CONTROLLERS 1
	108	+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	109	+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
115	110
116		-#else
117		- /*
118		- * Manually set up DDR parameters
119		- */
120		- #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
121		- #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
122		- #define CFG_DDR_CS0_CONFIG 0x80000002
123		- #define CFG_DDR_TIMING_1 0x37344321
124		- #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
125		- #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
126		- #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
127		- #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
128		-#endif
	111	+/* I2C addresses of SPD EEPROMs */
	112	+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
129	113
	114	+/* These are used when DDR doesn't use SPD. */
	115	+#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
	116	+#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	117	+#define CFG_DDR_CS0_CONFIG 0x80000002
	118	+#define CFG_DDR_TIMING_1 0x37344321
	119	+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	120	+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	121	+#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	122	+#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
130	123
131	124	/*
132	125	* SDRAM on the Local Bus