ARM: AM33xx+: Update ioregs to pass different values

Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>

ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
Lokesh Vutla · Tom Rini
1 parent cf04d0326b
Showing 11 changed files with 134 additions and 26 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/emif4.c
board/compulab/cm_t335/spl.c
board/isee/igep0033/board.c
board/phytec/pcm051/board.c
board/siemens/dxr2/board.c
board/siemens/pxm2/board.c
board/siemens/rut/board.c
board/ti/am335x/board.c
board/ti/ti814x/evm.c
board/ti/ti816x/evm.c
@@ -88,6 +88,9 @@
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
+	if (!cmd)
+		return;
+
 	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
  
@@ -105,6 +108,9 @@
 {
 	int i;
  
+	if (!data)
+		return;
+
 	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 		writel(data->datardsratio0,
 			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
  
@@ -121,12 +127,21 @@
 	}
 }
  
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 {
-	writel(val, &ioctrl_reg->cm0ioctl);
-	writel(val, &ioctrl_reg->cm1ioctl);
-	writel(val, &ioctrl_reg->cm2ioctl);
-	writel(val, &ioctrl_reg->dt0ioctl);
-	writel(val, &ioctrl_reg->dt1ioctl);
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
 }
@@ -87,7 +87,7 @@
 {
 }
  
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
 {
  
@@ -99,12 +99,11 @@
  
 	config_ddr_data(data, nr);
 #ifdef CONFIG_AM33XX
-	config_io_ctrl(ioctrl);
+	config_io_ctrl(ioregs);
  
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 #endif
-
 	/* Program EMIF instance */
 	config_ddr_phy(regs, nr);
 	set_sdram_timings(regs, nr);
@@ -20,6 +20,14 @@
 #include <asm/arch/hardware_am33xx.h>
 #include <asm/sizes.h>
  
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0		= MT41J128MJT125_RD_DQS,
 	.datawdsratio0		= MT41J128MJT125_WR_DQS,
@@ -89,7 +97,7 @@
 		reset_cpu(0);
 	}
 	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
-	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(303, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
  
@@ -77,9 +77,17 @@
 	enable_board_pin_mux();
 }
  
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
-	config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(400, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif
@@ -50,6 +50,14 @@
 }
  
 #ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
 	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  
@@ -81,10 +89,18 @@
  
 void sdram_init(void)
 {
-	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #else
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
@@ -116,7 +132,7 @@
  
 void sdram_init(void)
 {
-	config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif
@@ -144,6 +144,10 @@
  
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 };
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
 	/* pass values from eeprom */
 	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 	dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -165,7 +169,13 @@
 	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
  
-	config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
+	dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+	config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
 		   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
  
@@ -69,7 +69,15 @@
 	.cmd2iclkout = 0,
 };
  
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= DXR2_IOCTRL_VAL,
+	.cm1ioctl		= DXR2_IOCTRL_VAL,
+	.cm2ioctl		= DXR2_IOCTRL_VAL,
+	.dt0ioctl		= DXR2_IOCTRL_VAL,
+	.dt1ioctl		= DXR2_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
 		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
 }
  
@@ -74,7 +74,15 @@
 	.cmd2iclkout = 1,
 };
  
-	config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= RUT_IOCTRL_VAL,
+	.cm1ioctl		= RUT_IOCTRL_VAL,
+	.cm2ioctl		= RUT_IOCTRL_VAL,
+	.dt0ioctl		= RUT_IOCTRL_VAL,
+	.dt1ioctl		= RUT_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
 		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
 }
  
@@ -426,6 +426,38 @@
 	enable_board_pin_mux(&header);
 }
  
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
  
  
  
@@ -443,18 +475,18 @@
 	}
  
 	if (board_is_evm_sk(&header))
-		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_bone_lt(&header))
-		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
 	else if (board_is_evm_15_or_later(&header))
-		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
-		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
@@ -95,9 +95,9 @@
 {
 	config_dmm(&evm_lisa_map_regs);
  
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif0_regs, 0);
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif1_regs, 1);
 }
 #endif
@@ -191,22 +191,26 @@
 	if (CONFIG_TI816X_USE_EMIF0) {
 		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+			   0);
 	}
  
 	if (CONFIG_TI816X_USE_EMIF1) {
 		ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+			   1);
 	}
 #endif
  
 #ifdef CONFIG_TI816X_EVM_DDR3
 	if (CONFIG_TI816X_USE_EMIF0)
-		config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+			   0);
  
 	if (CONFIG_TI816X_USE_EMIF1)
-		config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+			   1);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
...	...	@@ -88,6 +88,9 @@
88	88	*/
89	89	void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
90	90	{
	91	+ if (!cmd)
	92	+ return;
	93	+
91	94	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
92	95	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
93	96
...	...	@@ -105,6 +108,9 @@
105	108	{
106	109	int i;
107	110
	111	+ if (!data)
	112	+ return;
	113	+
108	114	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
109	115	writel(data->datardsratio0,
110	116	&(ddr_data_reg[nr]+i)->dt0rdsratio0);
111	117
...	...	@@ -121,12 +127,21 @@
121	127	}
122	128	}
123	129
124		-void config_io_ctrl(unsigned long val)
	130	+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
125	131	{
126		- writel(val, &ioctrl_reg->cm0ioctl);
127		- writel(val, &ioctrl_reg->cm1ioctl);
128		- writel(val, &ioctrl_reg->cm2ioctl);
129		- writel(val, &ioctrl_reg->dt0ioctl);
130		- writel(val, &ioctrl_reg->dt1ioctl);
	132	+ if (!ioregs)
	133	+ return;
	134	+
	135	+ writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	136	+ writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	137	+ writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	138	+ writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	139	+ writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
	140	+#ifdef CONFIG_AM43XX
	141	+ writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	142	+ writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	143	+ writel(ioregs->emif_sdram_config_ext,
	144	+ &ioctrl_reg->emif_sdram_config_ext);
	145	+#endif
131	146	}
...	...	@@ -87,7 +87,7 @@
87	87	{
88	88	}
89	89
90		-void config_ddr(unsigned int pll, unsigned int ioctrl,
	90	+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
91	91	const struct ddr_data data, const struct cmd_control ctrl,
92	92	const struct emif_regs *regs, int nr)
93	93	{
94	94
...	...	@@ -99,12 +99,11 @@
99	99
100	100	config_ddr_data(data, nr);
101	101	#ifdef CONFIG_AM33XX
102		- config_io_ctrl(ioctrl);
	102	+ config_io_ctrl(ioregs);
103	103
104	104	/* Set CKE to be controlled by EMIF/DDR PHY */
105	105	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
106	106	#endif
107		-
108	107	/* Program EMIF instance */
109	108	config_ddr_phy(regs, nr);
110	109	set_sdram_timings(regs, nr);
...	...	@@ -20,6 +20,14 @@
20	20	#include <asm/arch/hardware_am33xx.h>
21	21	#include <asm/sizes.h>
22	22
	23	+const struct ctrl_ioregs ioregs = {
	24	+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	25	+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	26	+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
	27	+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	28	+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	29	+};
	30	+
23	31	static const struct ddr_data ddr3_data = {
24	32	.datardsratio0 = MT41J128MJT125_RD_DQS,
25	33	.datawdsratio0 = MT41J128MJT125_WR_DQS,
...	...	@@ -89,7 +97,7 @@
89	97	reset_cpu(0);
90	98	}
91	99	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
92		- config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
	100	+ config_ddr(303, &ioregs, &ddr3_data,
93	101	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
94	102	}
95	103
...	...	@@ -77,9 +77,17 @@
77	77	enable_board_pin_mux();
78	78	}
79	79
	80	+const struct ctrl_ioregs ioregs = {
	81	+ .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	82	+ .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	83	+ .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	84	+ .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	85	+ .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	86	+};
	87	+
80	88	void sdram_init(void)
81	89	{
82		- config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
	90	+ config_ddr(400, &ioregs, &ddr3_data,
83	91	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
84	92	}
85	93	#endif
...	...	@@ -50,6 +50,14 @@
50	50	}
51	51
52	52	#ifdef CONFIG_REV1
	53	+const struct ctrl_ioregs ioregs = {
	54	+ .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
	55	+ .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
	56	+ .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
	57	+ .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
	58	+ .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
	59	+};
	60	+
53	61	static const struct ddr_data ddr3_data = {
54	62	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
55	63	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
56	64
...	...	@@ -81,10 +89,18 @@
81	89
82	90	void sdram_init(void)
83	91	{
84		- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
	92	+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
85	93	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
86	94	}
87	95	#else
	96	+const struct ctrl_ioregs ioregs = {
	97	+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	98	+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	99	+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	100	+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	101	+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	102	+};
	103	+
88	104	static const struct ddr_data ddr3_data = {
89	105	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
90	106	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
...	...	@@ -116,7 +132,7 @@
116	132
117	133	void sdram_init(void)
118	134	{
119		- config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
	135	+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
120	136	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
121	137	}
122	138	#endif
...	...	@@ -144,6 +144,10 @@
144	144
145	145	struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
146	146	};
	147	+
	148	+struct ctrl_ioregs dxr2_ddr3_ioregs = {
	149	+};
	150	+
147	151	/* pass values from eeprom */
148	152	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
149	153	dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
...	...	@@ -165,7 +169,13 @@
165	169	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
166	170	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
167	171
168		- config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
	172	+ dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
	173	+ dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
	174	+ dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
	175	+ dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
	176	+ dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
	177	+
	178	+ config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
169	179	&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
170	180	}
171	181
...	...	@@ -69,7 +69,15 @@
69	69	.cmd2iclkout = 0,
70	70	};
71	71
72		- config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
	72	+const struct ctrl_ioregs ioregs = {
	73	+ .cm0ioctl = DXR2_IOCTRL_VAL,
	74	+ .cm1ioctl = DXR2_IOCTRL_VAL,
	75	+ .cm2ioctl = DXR2_IOCTRL_VAL,
	76	+ .dt0ioctl = DXR2_IOCTRL_VAL,
	77	+ .dt1ioctl = DXR2_IOCTRL_VAL,
	78	+};
	79	+
	80	+ config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
73	81	&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
74	82	}
75	83
...	...	@@ -74,7 +74,15 @@
74	74	.cmd2iclkout = 1,
75	75	};
76	76
77		- config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
	77	+const struct ctrl_ioregs ioregs = {
	78	+ .cm0ioctl = RUT_IOCTRL_VAL,
	79	+ .cm1ioctl = RUT_IOCTRL_VAL,
	80	+ .cm2ioctl = RUT_IOCTRL_VAL,
	81	+ .dt0ioctl = RUT_IOCTRL_VAL,
	82	+ .dt1ioctl = RUT_IOCTRL_VAL,
	83	+};
	84	+
	85	+ config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
78	86	&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
79	87	}
80	88
...	...	@@ -426,6 +426,38 @@
426	426	enable_board_pin_mux(&header);
427	427	}
428	428
	429	+const struct ctrl_ioregs ioregs_evmsk = {
	430	+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	431	+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	432	+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
	433	+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	434	+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	435	+};
	436	+
	437	+const struct ctrl_ioregs ioregs_bonelt = {
	438	+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	439	+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	440	+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	441	+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	442	+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	443	+};
	444	+
	445	+const struct ctrl_ioregs ioregs_evm15 = {
	446	+ .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	447	+ .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	448	+ .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	449	+ .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	450	+ .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	451	+};
	452	+
	453	+const struct ctrl_ioregs ioregs = {
	454	+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	455	+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	456	+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	457	+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	458	+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	459	+};
	460	+
429	461	void sdram_init(void)
430	462	{
431	463	__maybe_unused struct am335x_baseboard_id header;
432	464
433	465
434	466
...	...	@@ -443,18 +475,18 @@
443	475	}
444	476
445	477	if (board_is_evm_sk(&header))
446		- config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
	478	+ config_ddr(303, &ioregs_evmsk, &ddr3_data,
447	479	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
448	480	else if (board_is_bone_lt(&header))
449		- config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
	481	+ config_ddr(400, &ioregs_bonelt,
450	482	&ddr3_beagleblack_data,
451	483	&ddr3_beagleblack_cmd_ctrl_data,
452	484	&ddr3_beagleblack_emif_reg_data, 0);
453	485	else if (board_is_evm_15_or_later(&header))
454		- config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
	486	+ config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
455	487	&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
456	488	else
457		- config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
	489	+ config_ddr(266, &ioregs, &ddr2_data,
458	490	&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
459	491	}
460	492	#endif
...	...	@@ -95,9 +95,9 @@
95	95	{
96	96	config_dmm(&evm_lisa_map_regs);
97	97
98		- config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
	98	+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
99	99	&evm_ddr2_emif0_regs, 0);
100		- config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
	100	+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
101	101	&evm_ddr2_emif1_regs, 1);
102	102	}
103	103	#endif