Eric Lee / smarc-uboot | Embedian Git Server

Commit 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd

Authored by Priyanka Jain 2014-02-26 12:08:37 +0800

Committed by York Sun 2014-03-08 06:53:48 +0800

Exists in v2017.01-smarct4x and in 48 other branches

powerpc/t104xrdb: Update DDR initialization related settings

Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 25 additions and 30 deletions Inline Diff

board/freescale/t104xrdb/ddr.c
board/freescale/t104xrdb/ddr.h
include/configs/T1040RDB.h
include/configs/T1042RDB_PI.h

board/freescale/t104xrdb/ddr.c

Diff comments View file @ 96ac18c

 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 #include "ddr.h"
 DECLARE_GLOBAL_DATA_PTR;
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 		unsigned int controller_number,
 		unsigned int dimm_number)
 {
 	const char dimm_model[] = "RAW timing DDR";
 	if ((controller_number == 0) && (dimm_number == 0)) {
 		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 	}
 	return 0;
 }
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	if (ctrl_num > 1) {
 		printf("Not supported controller number %d\n", ctrl_num);
 		return;
 	}
 	if (!pdimm->n_ranks)
 		return;
 	pbsp = udimms[0];
-	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+	/* Get clk_adjust according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
 	while (pbsp->datarate_mhz_high) {
 		if (pbsp->n_ranks == pdimm->n_ranks &&
 		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
 			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
 		}
 		pbsp++;
 	}
 	if (pbsp_highest) {
 		printf("Error: board specific timing not found\n");
 		printf("for data rate %lu MT/s\n", ddr_freq);
 		printf("Trying to use the highest speed (%u) parameters\n",
 		       pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
 found:
 	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
 		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
 		"wrlvl_ctrl_3 0x%x\n",
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
 	/*
 	 * Write leveling override
 	 */
 	popts->wrlvl_override = 1;
 	popts->wrlvl_sample = 0xf;
 	/*
 	 * rtt and rtt_wr override
 	 */
 	popts->rtt_override = 0;
 	/* Enable ZQ calibration */
 	popts->zq_en = 1;
 	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
 }
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/t104xrdb/ddr.h

Diff comments View file @ 96ac18c

 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __DDR_H__
 #define __DDR_H__
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 2,
 	.rank_density = 2147483648u,
 	.capacity = 4294967296u,
 	.primary_sdram_width = 64,
 	.ec_sdram_width = 8,
 	.registered_dimm = 0,
-	.mirrored_dimm = 1,
+	.mirrored_dimm = 0,
 	.n_row_addr = 15,
 	.n_col_addr = 10,
 	.n_banks_per_sdram_device = 8,
 	.edc_config = 2,	/* ECC */
 	.burst_lengths_bitmask = 0x0c,
 	.tckmin_x_ps = 1071,
-	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
+	.caslat_x = 0xfe << 4,	/* 5,6,7,8,9,10,11 */
-	.taa_ps = 13910,
+	.taa_ps = 13125,
 	.twr_ps = 15000,
-	.trcd_ps = 13910,
+	.trcd_ps = 13125,
 	.trrd_ps = 6000,
-	.trp_ps = 13910,
+	.trp_ps = 13125,
 	.tras_ps = 34000,
-	.trc_ps = 48910,
+	.trc_ps = 48125,
 	.trfc_ps = 260000,
 	.twtr_ps = 7500,
 	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 35000,
 };
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
 	u32 rank_gb;
 	u32 clk_adjust;
 	u32 wrlvl_start;
 	u32 wrlvl_ctl_2;
 	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
 };
 /*
  * These tables contain all valid speeds we want to override with board
  * specific parameters. datarate_mhz_high values need to be in ascending order
  * for each n_ranks group.
  */
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
-	{2,  1066, 4, 8,     4, 0x05070609, 0x08090a08,   0xff,    2,  0},
+	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
 	{}
 };

include/configs/T1040RDB.h

Diff comments View file @ 96ac18c

include/configs/T1042RDB_PI.h

Diff comments View file @ 96ac18c

1	/*	1	/*
2	* Copyright 2013 Freescale Semiconductor, Inc.	2	* Copyright 2013 Freescale Semiconductor, Inc.
3	*	3	*
4	* See file CREDITS for list of people who contributed to this	4	* See file CREDITS for list of people who contributed to this
5	* project.	5	* project.
6	*	6	*
7	* This program is free software; you can redistribute it and/or	7	* This program is free software; you can redistribute it and/or
8	* modify it under the terms of the GNU General Public License as	8	* modify it under the terms of the GNU General Public License as
9	* published by the Free Software Foundation; either version 2 of	9	* published by the Free Software Foundation; either version 2 of
10	* the License, or (at your option) any later version.	10	* the License, or (at your option) any later version.
11	*	11	*
12	* This program is distributed in the hope that it will be useful,	12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.	15	* GNU General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the Free Software	18	* along with this program; if not, write to the Free Software
19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20	* MA 02111-1307 USA	20	* MA 02111-1307 USA
21	*/	21	*/
22		22
23	#ifndef __CONFIG_H	23	#ifndef __CONFIG_H
24	#define __CONFIG_H	24	#define __CONFIG_H
25		25
26	/*	26	/*
27	* T1040 RDB board configuration file	27	* T1040 RDB board configuration file
28	*/	28	*/
29	#define CONFIG_T104xRDB	29	#define CONFIG_T104xRDB
30	#define CONFIG_T1040RDB	30	#define CONFIG_T1040RDB
31	#define CONFIG_PHYS_64BIT	31	#define CONFIG_PHYS_64BIT
32		32
33	#ifdef CONFIG_RAMBOOT_PBL	33	#ifdef CONFIG_RAMBOOT_PBL
34	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE	34	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc	35	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36	#endif	36	#endif
37		37
38	/* High Level Configuration Options */	38	/* High Level Configuration Options */
39	#define CONFIG_BOOKE	39	#define CONFIG_BOOKE
40	#define CONFIG_E500 /* BOOKE e500 family */	40	#define CONFIG_E500 /* BOOKE e500 family */

1	/*	1	/*
2	* Copyright 2013 Freescale Semiconductor, Inc.	2	* Copyright 2013 Freescale Semiconductor, Inc.
3	*	3	*
4	* See file CREDITS for list of people who contributed to this	4	* See file CREDITS for list of people who contributed to this
5	* project.	5	* project.
6	*	6	*
7	* This program is free software; you can redistribute it and/or	7	* This program is free software; you can redistribute it and/or
8	* modify it under the terms of the GNU General Public License as	8	* modify it under the terms of the GNU General Public License as
9	* published by the Free Software Foundation; either version 2 of	9	* published by the Free Software Foundation; either version 2 of
10	* the License, or (at your option) any later version.	10	* the License, or (at your option) any later version.
11	*	11	*
12	* This program is distributed in the hope that it will be useful,	12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.	15	* GNU General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the Free Software	18	* along with this program; if not, write to the Free Software
19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20	* MA 02111-1307 USA	20	* MA 02111-1307 USA
21	*/	21	*/
22		22
23	#ifndef __CONFIG_H	23	#ifndef __CONFIG_H
24	#define __CONFIG_H	24	#define __CONFIG_H
25		25
26	/*	26	/*
27	* T1042RDB_PI board configuration file	27	* T1042RDB_PI board configuration file
28	*/	28	*/
29	#define CONFIG_T104xRDB	29	#define CONFIG_T104xRDB
30	#define CONFIG_T1042RDB_PI	30	#define CONFIG_T1042RDB_PI
31	#define CONFIG_PHYS_64BIT	31	#define CONFIG_PHYS_64BIT
32		32
33	#ifdef CONFIG_RAMBOOT_PBL	33	#ifdef CONFIG_RAMBOOT_PBL
34	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE	34	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc	35	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36	#endif	36	#endif
37		37
38	/* High Level Configuration Options */	38	/* High Level Configuration Options */
39	#define CONFIG_BOOKE	39	#define CONFIG_BOOKE
40	#define CONFIG_E500 /* BOOKE e500 family */	40	#define CONFIG_E500 /* BOOKE e500 family */