Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd

Authored by Priyanka Jain
Committed by York Sun
1 parent 337b0c52b3
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/t104xrdb: Update DDR initialization related settings 

Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 25 additions and 30 deletions Side-by-side Diff

board/freescale/t104xrdb/ddr.c
Diff comments   View file @ 96ac18c
... ... @@ -46,7 +46,7 @@
46 46  
47 47 pbsp = udimms[0];
48 48  
49   - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  49 + /* Get clk_adjust according to the board ddr
50 50 * freqency and n_banks specified in board_specific_parameters table.
51 51 */
52 52 ddr_freq = get_ddr_freq(0) / 1000000;
53 53  
... ... @@ -54,14 +54,10 @@
54 54 if (pbsp->n_ranks == pdimm->n_ranks &&
55 55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
56 56 if (ddr_freq <= pbsp->datarate_mhz_high) {
57   - popts->cpo_override = pbsp->cpo;
58   - popts->write_data_delay =
59   - pbsp->write_data_delay;
60 57 popts->clk_adjust = pbsp->clk_adjust;
61 58 popts->wrlvl_start = pbsp->wrlvl_start;
62 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64   - popts->twot_en = pbsp->force_2t;
65 61 goto found;
66 62 }
67 63 pbsp_highest = pbsp;
68 64  
... ... @@ -74,13 +70,10 @@
74 70 printf("for data rate %lu MT/s\n", ddr_freq);
75 71 printf("Trying to use the highest speed (%u) parameters\n",
76 72 pbsp_highest->datarate_mhz_high);
77   - popts->cpo_override = pbsp_highest->cpo;
78   - popts->write_data_delay = pbsp_highest->write_data_delay;
79 73 popts->clk_adjust = pbsp_highest->clk_adjust;
80 74 popts->wrlvl_start = pbsp_highest->wrlvl_start;
81 75 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
82 76 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
83   - popts->twot_en = pbsp_highest->force_2t;
84 77 } else {
85 78 panic("DIMM is not supported by this board");
86 79 }
... ... @@ -112,8 +105,8 @@
112 105 popts->zq_en = 1;
113 106  
114 107 /* DHC_EN =1, ODT = 75 Ohm */
115   - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
116   - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  108 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
  109 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
117 110 }
118 111  
119 112 phys_size_t initdram(int board_type)
board/freescale/t104xrdb/ddr.h
Diff comments   View file @ 96ac18c
... ... @@ -6,7 +6,6 @@
6 6  
7 7 #ifndef __DDR_H__
8 8 #define __DDR_H__
9   -
10 9 dimm_params_t ddr_raw_timing = {
11 10 .n_ranks = 2,
12 11 .rank_density = 2147483648u,
13 12  
14 13  
15 14  
16 15  
17 16  
... ... @@ -14,22 +13,21 @@
14 13 .primary_sdram_width = 64,
15 14 .ec_sdram_width = 8,
16 15 .registered_dimm = 0,
17   - .mirrored_dimm = 1,
  16 + .mirrored_dimm = 0,
18 17 .n_row_addr = 15,
19 18 .n_col_addr = 10,
20 19 .n_banks_per_sdram_device = 8,
21 20 .edc_config = 2, /* ECC */
22 21 .burst_lengths_bitmask = 0x0c,
23   -
24 22 .tckmin_x_ps = 1071,
25   - .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
26   - .taa_ps = 13910,
  23 + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
  24 + .taa_ps = 13125,
27 25 .twr_ps = 15000,
28   - .trcd_ps = 13910,
  26 + .trcd_ps = 13125,
29 27 .trrd_ps = 6000,
30   - .trp_ps = 13910,
  28 + .trp_ps = 13125,
31 29 .tras_ps = 34000,
32   - .trc_ps = 48910,
  30 + .trc_ps = 48125,
33 31 .trfc_ps = 260000,
34 32 .twtr_ps = 7500,
35 33 .trtp_ps = 7500,
... ... @@ -45,9 +43,6 @@
45 43 u32 wrlvl_start;
46 44 u32 wrlvl_ctl_2;
47 45 u32 wrlvl_ctl_3;
48   - u32 cpo;
49   - u32 write_data_delay;
50   - u32 force_2t;
51 46 };
52 47  
53 48 /*
54 49  
... ... @@ -59,14 +54,21 @@
59 54 static const struct board_specific_parameters udimm0[] = {
60 55 /*
61 56 * memory controller 0
62   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
63   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  57 + * num| hi| rank| clk| wrlvl | wrlvl
  58 + * ranks| mhz| GB |adjst| start | ctl2
64 59 */
65   - {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
66   - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
67   - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
68   - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
69   - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
  60 + {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
  61 + {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
  62 + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  63 + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  64 + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  65 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
  66 + {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
  67 + {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
  68 + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  69 + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  70 + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  71 + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
70 72 {}
71 73 };
72 74  
include/configs/T1040RDB.h
Diff comments   View file @ 96ac18c
... ... @@ -147,7 +147,7 @@
147 147  
148 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150   -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  150 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151  
152 152 #define CONFIG_DDR_SPD
153 153 #define CONFIG_SYS_DDR_RAW_TIMING
include/configs/T1042RDB_PI.h
Diff comments   View file @ 96ac18c
... ... @@ -147,7 +147,7 @@
147 147  
148 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150   -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  150 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151  
152 152 #define CONFIG_DDR_SPD
153 153 #define CONFIG_SYS_DDR_RAW_TIMING