phylib: add natsemi dp83630 phy

add natsemi dp83630 phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>

phylib: add natsemi dp83630 phy
add natsemi dp83630 phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
Heiko Schocher · Joe Hershberger
1 parent a8f9cd1893
Showing 1 changed file with 37 additions and 0 deletions Side-by-side Diff
drivers/net/phy/natsemi.c
@@ -22,6 +22,42 @@
  */
 #include <phy.h>
  
+/* NatSemi DP83630 */
+
+#define DP83630_PHY_PAGESEL_REG		0x13
+#define DP83630_PHY_PTP_COC_REG		0x14
+#define DP83630_PHY_PTP_CLKOUT_EN	(1<<15)
+#define DP83630_PHY_RBR_REG		0x17
+
+static int dp83630_config(struct phy_device *phydev)
+{
+	int ptp_coc_reg;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
+	ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+			       DP83630_PHY_PTP_COC_REG);
+	ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
+	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
+		  ptp_coc_reg);
+	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
+static struct phy_driver DP83630_driver = {
+	.name = "NatSemi DP83630",
+	.uid = 0x20005ce1,
+	.mask = 0xfffffff0,
+	.features = PHY_BASIC_FEATURES,
+	.config = &dp83630_config,
+	.startup = &genphy_startup,
+	.shutdown = &genphy_shutdown,
+};
+
+
 /* DP83865 Link and Auto-Neg Status Register */
 #define MIIM_DP83865_LANR      0x11
 #define MIIM_DP83865_SPD_MASK  0x0018
@@ -90,6 +126,7 @@
  
 int phy_natsemi_init(void)
 {
+	phy_register(&DP83630_driver);
 	phy_register(&DP83865_driver);
  
 	return 0;
...	...	@@ -22,6 +22,42 @@
22	22	*/
23	23	#include <phy.h>
24	24
	25	+/* NatSemi DP83630 */
	26	+
	27	+#define DP83630_PHY_PAGESEL_REG 0x13
	28	+#define DP83630_PHY_PTP_COC_REG 0x14
	29	+#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
	30	+#define DP83630_PHY_RBR_REG 0x17
	31	+
	32	+static int dp83630_config(struct phy_device *phydev)
	33	+{
	34	+ int ptp_coc_reg;
	35	+
	36	+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	37	+ phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
	38	+ ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
	39	+ DP83630_PHY_PTP_COC_REG);
	40	+ ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
	41	+ phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
	42	+ ptp_coc_reg);
	43	+ phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
	44	+
	45	+ genphy_config_aneg(phydev);
	46	+
	47	+ return 0;
	48	+}
	49	+
	50	+static struct phy_driver DP83630_driver = {
	51	+ .name = "NatSemi DP83630",
	52	+ .uid = 0x20005ce1,
	53	+ .mask = 0xfffffff0,
	54	+ .features = PHY_BASIC_FEATURES,
	55	+ .config = &dp83630_config,
	56	+ .startup = &genphy_startup,
	57	+ .shutdown = &genphy_shutdown,
	58	+};
	59	+
	60	+
25	61	/* DP83865 Link and Auto-Neg Status Register */
26	62	#define MIIM_DP83865_LANR 0x11
27	63	#define MIIM_DP83865_SPD_MASK 0x0018
...	...	@@ -90,6 +126,7 @@
90	126
91	127	int phy_natsemi_init(void)
92	128	{
	129	+ phy_register(&DP83630_driver);
93	130	phy_register(&DP83865_driver);
94	131
95	132	return 0;