* Fix PCI support for MPC5200 / IceCube Board

wdenk
1 parent bdccc4fedc
Showing 6 changed files with 261 additions and 9 deletions Side-by-side Diff
CHANGELOG
board/icecube/icecube.c
cpu/mpc5xxx/Makefile
cpu/mpc5xxx/pci_mpc5200.c
include/configs/IceCube.h
include/mpc5xxx.h
@@ -2,6 +2,8 @@
 Changes for U-Boot 0.4.5:
 ======================================================================
  
+* Fix PCI support for MPC5200 / IceCube Board
+
 * Map ISP1362 USB OTG controller for NSCU board
  
 * Patch by Brad Parker, 02 Aug 2003:
@@ -23,6 +23,7 @@
  
 #include <common.h>
 #include <mpc5xxx.h>
+#include <pci.h>
  
 long int initdram (int board_type)
 {
@@ -114,4 +115,15 @@
 #endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
@@ -28,7 +28,7 @@
 START	= start.o
 ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
 OBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
-	  loadtask.o fec.o
+	  loadtask.o fec.o pci_mpc5200.o
  
 all:	.depend $(START) $(ASOBJS) $(LIB)
  
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <mpc5xxx.h>
+
+/* System RAM mapped over PCI */
+#define CONFIG_PCI_MEMORY_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)
+
+/* PCIIWCR bit fields */
+#define IWCR_MEM	(0 << 3)
+#define IWCR_IO		(1 << 3)
+#define IWCR_READ	(0 << 1)
+#define IWCR_READLINE	(1 << 1)
+#define IWCR_READMULT	(2 << 1)
+#define IWCR_EN		(1 << 0)
+
+static int mpc5200_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
+	eieio();
+	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+	eieio();
+	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	/* skip MPC5200 */
+	if (offset == 0 && *value == 0x58031057)
+		*value = 0xffffffff;
+	return 0;
+}
+
+static int mpc5200_write_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32 value)
+{
+	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
+	eieio();
+	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
+	eieio();
+	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	return 0;
+}
+
+void pci_mpc5xxx_init (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEMORY_BUS,
+		       CONFIG_PCI_MEMORY_PHYS,
+		       CONFIG_PCI_MEMORY_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose->region_count = 3;
+
+	pci_register_hose(hose);
+
+	/* GPIO Multiplexing - enable PCI */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
+	
+	/* Set host bridge as pci master and enable memory decoding */
+	*(vu_long *)MPC5XXX_PCI_CMD |=
+		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	
+	/* Set maximum latency timer */
+	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
+
+	/* Set cache line size */
+	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
+		(CFG_CACHELINE_SIZE / 4);
+	
+	/* Map MBAR to PCI space */
+	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
+	*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
+	
+	/* Map RAM to PCI space */
+	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
+	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
+
+	/* Enable snooping for RAM */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
+
+	/* Park XLB on PCI */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
+
+	/* Enable piplining */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
+	
+	/* Disable interrupts from PCI controller */
+	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
+	*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
+	
+	/* Disable initiator windows */
+	*(vu_long *)MPC5XXX_PCI_IWCR = 0;
+	
+	/* Map PCI memory to physical space */
+	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
+		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
+		(CONFIG_PCI_MEM_BUS >> 16);
+	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
+
+	/* Map PCI I/O to physical space */
+	*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
+		(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
+		(CONFIG_PCI_IO_BUS >> 16);
+	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
+
+	/* Reset the PCI bus */
+	*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
+	udelay(1000);
+	*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
+	udelay(1000);
+
+	pci_set_ops(hose,
+		pci_hose_read_config_byte_via_dword,
+		pci_hose_read_config_word_via_dword,
+		mpc5200_read_config_dword,
+		pci_hose_write_config_byte_via_dword,
+		pci_hose_write_config_word_via_dword,
+		mpc5200_write_config_dword);
+	
+	udelay(1000);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCI && CONFIG_MPC5200 */
@@ -37,7 +37,7 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
  
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
  
  
@@ -49,10 +49,41 @@
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
  
+
+#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
 /*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* MPC5100 */
+
+#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/*
  * Supported commands
  */
-#define CONFIG_COMMANDS		CONFIG_CMD_DFL
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD)
  
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
  
  
  
@@ -83,18 +114,18 @@
 #define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
  
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
+#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
  
  
 /*
  * Environment settings
  */
-#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_SIZE		0x10000
-#define CFG_ENV_ADDR        (CFG_FLASH_BASE + 0x740000)
-#define CFG_ENV_SECT_SIZE   0x10000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x740000)
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
  
-
 /*
  * Memory map
  */
@@ -112,7 +143,7 @@
  
 #define CFG_MONITOR_BASE    TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT 1
+#   define CFG_RAMBOOT		1
 #endif
  
 #define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
@@ -61,6 +61,10 @@
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SDRAM_START	(CFG_MBAR + 0x0034)
 #define MPC5XXX_SDRAM_STOP	(CFG_MBAR + 0x0038)
+#define MPC5XXX_PCI1_START	(CFG_MBAR + 0x003c)
+#define MPC5XXX_PCI1_STOP	(CFG_MBAR + 0x0040)
+#define MPC5XXX_PCI2_START	(CFG_MBAR + 0x0044)
+#define MPC5XXX_PCI2_STOP	(CFG_MBAR + 0x0048)
 #elif defined(CONFIG_MPC5200)
 #define MPC5XXX_CS6_START	(CFG_MBAR + 0x0058)
 #define MPC5XXX_CS6_STOP	(CFG_MBAR + 0x005c)
@@ -75,6 +79,7 @@
 #define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
 #define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
 #define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
+#define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
 #define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
 #define MPC5XXX_XLBARB		(CFG_MBAR + 0x1f00)
  
@@ -135,6 +140,33 @@
  
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
+
+/* PCI registers */
+#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
+#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
+#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
+#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_PCI_CTRL	(MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_VALMSKR	(MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_VALMSKW	(MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_SUBW1	(MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_SUBW2	(MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_WINCOMMAND	(MPC5XXX_PCI + 0x7c)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
+#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
+#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)
+#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)
+#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
+#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
+#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
+#endif
  
 /* Interrupt Controller registers */
 #define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
...	...	@@ -2,6 +2,8 @@
2	2	Changes for U-Boot 0.4.5:
3	3	======================================================================
4	4
	5	+* Fix PCI support for MPC5200 / IceCube Board
	6	+
5	7	* Map ISP1362 USB OTG controller for NSCU board
6	8
7	9	* Patch by Brad Parker, 02 Aug 2003:
...	...	@@ -23,6 +23,7 @@
23	23
24	24	#include <common.h>
25	25	#include <mpc5xxx.h>
	26	+#include <pci.h>
26	27
27	28	long int initdram (int board_type)
28	29	{
...	...	@@ -114,4 +115,15 @@
114	115	#endif
115	116	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
116	117	}
	118	+
	119	+#ifdef CONFIG_PCI
	120	+static struct pci_controller hose;
	121	+
	122	+extern void pci_mpc5xxx_init(struct pci_controller *);
	123	+
	124	+void pci_init_board(void)
	125	+{
	126	+ pci_mpc5xxx_init(&hose);
	127	+}
	128	+#endif
...	...	@@ -28,7 +28,7 @@
28	28	START = start.o
29	29	ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
30	30	OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
31		- loadtask.o fec.o
	31	+ loadtask.o fec.o pci_mpc5200.o
32	32
33	33	all: .depend $(START) $(ASOBJS) $(LIB)
34	34
	1	+/*
	2	+ * (C) Copyright 2000-2003
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
	27	+
	28	+#include <asm/processor.h>
	29	+#include <asm/io.h>
	30	+#include <pci.h>
	31	+#include <mpc5xxx.h>
	32	+
	33	+/* System RAM mapped over PCI */
	34	+#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
	35	+#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
	36	+#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
	37	+
	38	+/* PCIIWCR bit fields */
	39	+#define IWCR_MEM (0 << 3)
	40	+#define IWCR_IO (1 << 3)
	41	+#define IWCR_READ (0 << 1)
	42	+#define IWCR_READLINE (1 << 1)
	43	+#define IWCR_READMULT (2 << 1)
	44	+#define IWCR_EN (1 << 0)
	45	+
	46	+static int mpc5200_read_config_dword(struct pci_controller *hose,
	47	+ pci_dev_t dev, int offset, u32* value)
	48	+{
	49	+ (volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	50	+ eieio();
	51	+ value = in_le32((volatile u32 )CONFIG_PCI_IO_PHYS);
	52	+ eieio();
	53	+ (volatile u32 )MPC5XXX_PCI_CAR = 0;
	54	+ /* skip MPC5200 */
	55	+ if (offset == 0 && *value == 0x58031057)
	56	+ *value = 0xffffffff;
	57	+ return 0;
	58	+}
	59	+
	60	+static int mpc5200_write_config_dword(struct pci_controller *hose,
	61	+ pci_dev_t dev, int offset, u32 value)
	62	+{
	63	+ (volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	64	+ eieio();
	65	+ out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
	66	+ eieio();
	67	+ (volatile u32 )MPC5XXX_PCI_CAR = 0;
	68	+ return 0;
	69	+}
	70	+
	71	+void pci_mpc5xxx_init (struct pci_controller *hose)
	72	+{
	73	+ hose->first_busno = 0;
	74	+ hose->last_busno = 0xff;
	75	+
	76	+ /* System space */
	77	+ pci_set_region(hose->regions + 0,
	78	+ CONFIG_PCI_MEMORY_BUS,
	79	+ CONFIG_PCI_MEMORY_PHYS,
	80	+ CONFIG_PCI_MEMORY_SIZE,
	81	+ PCI_REGION_MEM \| PCI_REGION_MEMORY);
	82	+
	83	+ /* PCI memory space */
	84	+ pci_set_region(hose->regions + 1,
	85	+ CONFIG_PCI_MEM_BUS,
	86	+ CONFIG_PCI_MEM_PHYS,
	87	+ CONFIG_PCI_MEM_SIZE,
	88	+ PCI_REGION_MEM);
	89	+
	90	+ /* PCI IO space */
	91	+ pci_set_region(hose->regions + 2,
	92	+ CONFIG_PCI_IO_BUS,
	93	+ CONFIG_PCI_IO_PHYS,
	94	+ CONFIG_PCI_IO_SIZE,
	95	+ PCI_REGION_IO);
	96	+
	97	+ hose->region_count = 3;
	98	+
	99	+ pci_register_hose(hose);
	100	+
	101	+ /* GPIO Multiplexing - enable PCI */
	102	+ (vu_long )MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
	103	+
	104	+ /* Set host bridge as pci master and enable memory decoding */
	105	+ (vu_long )MPC5XXX_PCI_CMD \|=
	106	+ PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	107	+
	108	+ /* Set maximum latency timer */
	109	+ (vu_long )MPC5XXX_PCI_CFG \|= (0xf800);
	110	+
	111	+ /* Set cache line size */
	112	+ (vu_long )MPC5XXX_PCI_CFG = ((vu_long )MPC5XXX_PCI_CFG & ~0xff) \|
	113	+ (CFG_CACHELINE_SIZE / 4);
	114	+
	115	+ /* Map MBAR to PCI space */
	116	+ (vu_long )MPC5XXX_PCI_BAR0 = CFG_MBAR;
	117	+ (vu_long )MPC5XXX_PCI_TBATR1 = CFG_MBAR \| 1;
	118	+
	119	+ /* Map RAM to PCI space */
	120	+ (vu_long )MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS \| (1 << 3);
	121	+ (vu_long )MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS \| 1;
	122	+
	123	+ /* Enable snooping for RAM */
	124	+ (vu_long )(MPC5XXX_XLBARB + 0x40) \|= (1 << 15);
	125	+ (vu_long )(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS \| 0x1d;
	126	+
	127	+ /* Park XLB on PCI */
	128	+ (vu_long )(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) \| (3 << 5));
	129	+ (vu_long )(MPC5XXX_XLBARB + 0x40) \|= (3 << 8) \| (3 << 5);
	130	+
	131	+ /* Enable piplining */
	132	+ (vu_long )(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
	133	+
	134	+ /* Disable interrupts from PCI controller */
	135	+ (vu_long )MPC5XXX_PCI_GSCR &= ~(7 << 12);
	136	+ (vu_long )MPC5XXX_PCI_ICR &= ~(7 << 24);
	137	+
	138	+ /* Disable initiator windows */
	139	+ (vu_long )MPC5XXX_PCI_IWCR = 0;
	140	+
	141	+ /* Map PCI memory to physical space */
	142	+ (vu_long )MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS \|
	143	+ (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) \|
	144	+ (CONFIG_PCI_MEM_BUS >> 16);
	145	+ (vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_MEM \| IWCR_READ \| IWCR_EN) << 24;
	146	+
	147	+ /* Map PCI I/O to physical space */
	148	+ (vu_long )MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS \|
	149	+ (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) \|
	150	+ (CONFIG_PCI_IO_BUS >> 16);
	151	+ (vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_IO \| IWCR_READ \| IWCR_EN) << 16;
	152	+
	153	+ /* Reset the PCI bus */
	154	+ (vu_long )MPC5XXX_PCI_GSCR \|= 1;
	155	+ udelay(1000);
	156	+ (vu_long )MPC5XXX_PCI_GSCR &= ~1;
	157	+ udelay(1000);
	158	+
	159	+ pci_set_ops(hose,
	160	+ pci_hose_read_config_byte_via_dword,
	161	+ pci_hose_read_config_word_via_dword,
	162	+ mpc5200_read_config_dword,
	163	+ pci_hose_write_config_byte_via_dword,
	164	+ pci_hose_write_config_word_via_dword,
	165	+ mpc5200_write_config_dword);
	166	+
	167	+ udelay(1000);
	168	+
	169	+#ifdef CONFIG_PCI_SCAN_SHOW
	170	+ printf("PCI: Bus Dev VenId DevId Class Int\n");
	171	+#endif
	172	+
	173	+ hose->last_busno = pci_hose_scan(hose);
	174	+}
	175	+#endif /* CONFIG_PCI && CONFIG_MPC5200 */
...	...	@@ -37,7 +37,7 @@
37	37	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38	38	#define BOOTFLAG_WARM 0x02 /* Software reboot */
39	39
40		-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
	40	+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41	41	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42	42	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43	43	#endif
44	44
45	45
...	...	@@ -49,10 +49,41 @@
49	49	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50	50	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51	51
	52	+
	53	+#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
52	54	/*
	55	+ * PCI Mapping:
	56	+ * 0x40000000 - 0x4fffffff - PCI Memory
	57	+ * 0x50000000 - 0x50ffffff - PCI IO Space
	58	+ */
	59	+#define CONFIG_PCI 1
	60	+#define CONFIG_PCI_PNP 1
	61	+#define CONFIG_PCI_SCAN_SHOW 1
	62	+
	63	+#define CONFIG_PCI_MEM_BUS 0x40000000
	64	+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	65	+#define CONFIG_PCI_MEM_SIZE 0x10000000
	66	+
	67	+#define CONFIG_PCI_IO_BUS 0x50000000
	68	+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	69	+#define CONFIG_PCI_IO_SIZE 0x01000000
	70	+
	71	+#define CONFIG_NET_MULTI 1
	72	+#define CONFIG_EEPRO100 1
	73	+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	74	+
	75	+#define ADD_PCI_CMD CFG_CMD_PCI
	76	+
	77	+#else /* MPC5100 */
	78	+
	79	+#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	80	+
	81	+#endif
	82	+
	83	+/*
53	84	* Supported commands
54	85	*/
55		-#define CONFIG_COMMANDS CONFIG_CMD_DFL
	86	+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| ADD_PCI_CMD)
56	87
57	88	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
58	89	#include <cmd_confdefs.h>
59	90
60	91
61	92
...	...	@@ -83,18 +114,18 @@
83	114	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
84	115	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
85	116
86		-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
	117	+#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
87	118
88	119
89	120	/*
90	121	* Environment settings
91	122	*/
92		-#define CFG_ENV_IS_IN_FLASH 1
	123	+#define CFG_ENV_IS_IN_FLASH 1
93	124	#define CFG_ENV_SIZE 0x10000
94		-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
95		-#define CFG_ENV_SECT_SIZE 0x10000
	125	+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
	126	+#define CFG_ENV_SECT_SIZE 0x10000
	127	+#define CONFIG_ENV_OVERWRITE 1
96	128
97		-
98	129	/*
99	130	* Memory map
100	131	*/
...	...	@@ -112,7 +143,7 @@
112	143
113	144	#define CFG_MONITOR_BASE TEXT_BASE
114	145	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
115		-# define CFG_RAMBOOT 1
	146	+# define CFG_RAMBOOT 1
116	147	#endif
117	148
118	149	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
...	...	@@ -61,6 +61,10 @@
61	61	#if defined(CONFIG_MGT5100)
62	62	#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
63	63	#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
	64	+#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
	65	+#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
	66	+#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
	67	+#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
64	68	#elif defined(CONFIG_MPC5200)
65	69	#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
66	70	#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
...	...	@@ -75,6 +79,7 @@
75	79	#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
76	80	#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
77	81	#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
	82	+#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
78	83	#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
79	84	#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
80	85
...	...	@@ -135,6 +140,33 @@
135	140
136	141	/* GPIO registers */
137	142	#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
	143	+
	144	+/* PCI registers */
	145	+#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
	146	+#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
	147	+#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
	148	+#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
	149	+#if defined(CONFIG_MGT5100)
	150	+#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
	151	+#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
	152	+#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
	153	+#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
	154	+#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
	155	+#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
	156	+#elif defined(CONFIG_MPC5200)
	157	+#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
	158	+#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
	159	+#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
	160	+#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
	161	+#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
	162	+#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
	163	+#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
	164	+#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
	165	+#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
	166	+#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
	167	+#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
	168	+#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
	169	+#endif
138	170
139	171	/* Interrupt Controller registers */
140	172	#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)