arm: dts: zynq: Add digilent ZYBO board dts

It's a Zynq board similar in design to the currently supported ones. 512MB of RAM and UART1 is used. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm: dts: zynq: Add digilent ZYBO board dts
It's a Zynq board similar in design to the currently supported ones. 512MB of RAM and UART1 is used. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Peter Crosthwaite · Michal Simek
1 parent 290f1f999a
Showing 2 changed files with 24 additions and 0 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/zynq-zybo.dts
@@ -34,6 +34,7 @@
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb \
+	zynq-zybo.dtb \
 	zynq-microzed.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm012.dtb \
+/*
+ * Digilent ZYBO board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZYBO Board";
+	compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x20000000>;
+	};
+};
...	...	@@ -34,6 +34,7 @@
34	34	dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
35	35	zynq-zc706.dtb \
36	36	zynq-zed.dtb \
	37	+ zynq-zybo.dtb \
37	38	zynq-microzed.dtb \
38	39	zynq-zc770-xm010.dtb \
39	40	zynq-zc770-xm012.dtb \
	1	+/*
	2	+ * Digilent ZYBO board DTS
	3	+ *
	4	+ * Copyright (C) 2013 Xilinx, Inc.
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+/dts-v1/;
	9	+#include "zynq-7000.dtsi"
	10	+
	11	+/ {
	12	+ model = "Zynq ZYBO Board";
	13	+ compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
	14	+
	15	+ aliases {
	16	+ serial0 = &uart1;
	17	+ };
	18	+
	19	+ memory {
	20	+ device_type = "memory";
	21	+ reg = <0 0x20000000>;
	22	+ };
	23	+};