Commit 97ce274d97e9c1796d58ae34aadcbc10293cccd7
Committed by
Marek Vasut
1 parent
ddcbed04a2
Exists in
v2017.01-smarct4x
and in
37 other branches
arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage. Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 18 additions and 4 deletions Inline Diff
include/configs/socfpga_cyclone5.h
1 | /* | 1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
3 | * | 3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | */ | 5 | */ |
6 | #ifndef __CONFIG_H | 6 | #ifndef __CONFIG_H |
7 | #define __CONFIG_H | 7 | #define __CONFIG_H |
8 | 8 | ||
9 | #include <asm/arch/socfpga_base_addrs.h> | 9 | #include <asm/arch/socfpga_base_addrs.h> |
10 | #include "../../board/altera/socfpga/pinmux_config.h" | 10 | #include "../../board/altera/socfpga/pinmux_config.h" |
11 | #include "../../board/altera/socfpga/iocsr_config.h" | 11 | #include "../../board/altera/socfpga/iocsr_config.h" |
12 | #include "../../board/altera/socfpga/pll_config.h" | 12 | #include "../../board/altera/socfpga/pll_config.h" |
13 | 13 | ||
14 | /* | 14 | /* |
15 | * High level configuration | 15 | * High level configuration |
16 | */ | 16 | */ |
17 | /* Virtual target or real hardware */ | 17 | /* Virtual target or real hardware */ |
18 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET | 18 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET |
19 | 19 | ||
20 | #define CONFIG_ARMV7 | 20 | #define CONFIG_ARMV7 |
21 | #undef CONFIG_USE_IRQ | 21 | #undef CONFIG_USE_IRQ |
22 | 22 | ||
23 | #define CONFIG_MISC_INIT_R | 23 | #define CONFIG_MISC_INIT_R |
24 | #define CONFIG_SINGLE_BOOTLOADER | 24 | #define CONFIG_SINGLE_BOOTLOADER |
25 | #define CONFIG_SOCFPGA | 25 | #define CONFIG_SOCFPGA |
26 | #define CONFIG_CLOCKS | 26 | #define CONFIG_CLOCKS |
27 | 27 | ||
28 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC | 28 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC |
29 | #define CONFIG_SYS_CACHELINE_SIZE 32 | 29 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
30 | #define CONFIG_SYS_L2_PL310 | 30 | #define CONFIG_SYS_L2_PL310 |
31 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | 31 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS |
32 | 32 | ||
33 | /* base address for .text section */ | 33 | /* base address for .text section */ |
34 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 34 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
35 | #define CONFIG_SYS_TEXT_BASE 0x08000040 | 35 | #define CONFIG_SYS_TEXT_BASE 0x08000040 |
36 | #else | 36 | #else |
37 | #define CONFIG_SYS_TEXT_BASE 0x01000040 | 37 | #define CONFIG_SYS_TEXT_BASE 0x01000040 |
38 | #endif | 38 | #endif |
39 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 | 39 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 |
40 | 40 | ||
41 | /* Console I/O Buffer Size */ | 41 | /* Console I/O Buffer Size */ |
42 | #define CONFIG_SYS_CBSIZE 256 | 42 | #define CONFIG_SYS_CBSIZE 256 |
43 | /* Monitor Command Prompt */ | 43 | /* Monitor Command Prompt */ |
44 | #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " | 44 | #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " |
45 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | 45 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
46 | sizeof(CONFIG_SYS_PROMPT) + 16) | 46 | sizeof(CONFIG_SYS_PROMPT) + 16) |
47 | 47 | ||
48 | /* | 48 | /* |
49 | * Display CPU and Board Info | 49 | * Display CPU and Board Info |
50 | */ | 50 | */ |
51 | #define CONFIG_DISPLAY_CPUINFO | 51 | #define CONFIG_DISPLAY_CPUINFO |
52 | #define CONFIG_DISPLAY_BOARDINFO | 52 | #define CONFIG_DISPLAY_BOARDINFO |
53 | 53 | ||
54 | /* | 54 | /* |
55 | * Enable early stage initialization at C environment | 55 | * Enable early stage initialization at C environment |
56 | */ | 56 | */ |
57 | #define CONFIG_BOARD_EARLY_INIT_F | 57 | #define CONFIG_BOARD_EARLY_INIT_F |
58 | 58 | ||
59 | /* flat device tree */ | 59 | /* flat device tree */ |
60 | #define CONFIG_OF_LIBFDT | 60 | #define CONFIG_OF_LIBFDT |
61 | /* skip updating the FDT blob */ | 61 | /* skip updating the FDT blob */ |
62 | #define CONFIG_FDT_BLOB_SKIP_UPDATE | 62 | #define CONFIG_FDT_BLOB_SKIP_UPDATE |
63 | /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ | 63 | /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ |
64 | #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) | 64 | #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) |
65 | 65 | ||
66 | #define CONFIG_SPL_RAM_DEVICE | 66 | #define CONFIG_SPL_RAM_DEVICE |
67 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | 67 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
68 | #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) | 68 | #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) |
69 | #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) | 69 | #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) |
70 | 70 | ||
71 | /* | 71 | /* |
72 | * Memory allocation (MALLOC) | 72 | * Memory allocation (MALLOC) |
73 | */ | 73 | */ |
74 | /* Room required on the stack for the environment data */ | 74 | /* Room required on the stack for the environment data */ |
75 | #define CONFIG_ENV_SIZE 1024 | 75 | #define CONFIG_ENV_SIZE 1024 |
76 | /* Size of DRAM reserved for malloc() use */ | 76 | /* Size of DRAM reserved for malloc() use */ |
77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | 77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
78 | 78 | ||
79 | /* SP location before relocation, must use scratch RAM */ | 79 | /* SP location before relocation, must use scratch RAM */ |
80 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 | 80 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
81 | /* Reserving 0x100 space at back of scratch RAM for debug info */ | 81 | /* Reserving 0x100 space at back of scratch RAM for debug info */ |
82 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) | 82 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) |
83 | /* Stack pointer prior relocation, must situated at on-chip RAM */ | 83 | /* Stack pointer prior relocation, must situated at on-chip RAM */ |
84 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | 84 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
85 | CONFIG_SYS_INIT_RAM_SIZE - \ | 85 | CONFIG_SYS_INIT_RAM_SIZE - \ |
86 | GENERATED_GBL_DATA_SIZE) | 86 | GENERATED_GBL_DATA_SIZE) |
87 | 87 | ||
88 | 88 | ||
89 | /* | 89 | /* |
90 | * Command line configuration. | 90 | * Command line configuration. |
91 | */ | 91 | */ |
92 | #define CONFIG_SYS_NO_FLASH | 92 | #define CONFIG_SYS_NO_FLASH |
93 | #include <config_cmd_default.h> | 93 | #include <config_cmd_default.h> |
94 | /* FAT file system support */ | 94 | /* FAT file system support */ |
95 | #define CONFIG_CMD_FAT | 95 | #define CONFIG_CMD_FAT |
96 | /* bootz command support */ | ||
97 | #define CONFIG_CMD_BOOTZ | ||
96 | 98 | ||
97 | 99 | ||
98 | /* | 100 | /* |
99 | * Misc | 101 | * Misc |
100 | */ | 102 | */ |
101 | #define CONFIG_DOS_PARTITION 1 | 103 | #define CONFIG_DOS_PARTITION 1 |
102 | 104 | ||
103 | #ifdef CONFIG_SPL_BUILD | 105 | #ifdef CONFIG_SPL_BUILD |
104 | #undef CONFIG_PARTITIONS | 106 | #undef CONFIG_PARTITIONS |
105 | #endif | 107 | #endif |
106 | 108 | ||
107 | /* | 109 | /* |
108 | * Environment setup | 110 | * Environment setup |
109 | */ | 111 | */ |
110 | 112 | ||
111 | /* Delay before automatically booting the default image */ | 113 | /* Delay before automatically booting the default image */ |
112 | #define CONFIG_BOOTDELAY 3 | 114 | #define CONFIG_BOOTDELAY 3 |
113 | /* Enable auto completion of commands using TAB */ | 115 | /* Enable auto completion of commands using TAB */ |
114 | #define CONFIG_AUTO_COMPLETE | 116 | #define CONFIG_AUTO_COMPLETE |
115 | /* use "hush" command parser */ | 117 | /* use "hush" command parser */ |
116 | #define CONFIG_SYS_HUSH_PARSER | 118 | #define CONFIG_SYS_HUSH_PARSER |
117 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | 119 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
118 | #define CONFIG_CMD_RUN | 120 | #define CONFIG_CMD_RUN |
119 | 121 | ||
122 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | ||
120 | #define CONFIG_BOOTCOMMAND "run ramboot" | 123 | #define CONFIG_BOOTCOMMAND "run ramboot" |
124 | #else | ||
125 | #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" | ||
126 | #endif | ||
121 | 127 | ||
122 | /* | 128 | /* |
123 | * arguments passed to the bootm command. The value of | 129 | * arguments passed to the bootm command. The value of |
124 | * CONFIG_BOOTARGS goes into the environment value "bootargs". | 130 | * CONFIG_BOOTARGS goes into the environment value "bootargs". |
125 | * Do note the value will overide also the chosen node in FDT blob. | 131 | * Do note the value will overide also the chosen node in FDT blob. |
126 | */ | 132 | */ |
127 | #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" | 133 | #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) |
128 | 134 | ||
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 135 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
130 | "verify=n\0" \ | 136 | "verify=n\0" \ |
131 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | 137 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
132 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ | 138 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ |
133 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 139 | "bootm ${loadaddr} - ${fdt_addr}\0" \ |
134 | "bootimage=uImage\0" \ | 140 | "bootimage=zImage\0" \ |
135 | "fdt_addr=100\0" \ | 141 | "fdt_addr=100\0" \ |
136 | "fsloadcmd=ext2load\0" \ | 142 | "fdtimage=socfpga.dtb\0" \ |
137 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 143 | "fsloadcmd=ext2load\0" \ |
144 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | ||
145 | "mmcroot=/dev/mmcblk0p2\0" \ | ||
146 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ | ||
147 | " root=${mmcroot} rw rootwait;" \ | ||
148 | "bootz ${loadaddr} - ${fdt_addr}\0" \ | ||
149 | "mmcload=mmc rescan;" \ | ||
150 | "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ | ||
151 | "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ | ||
138 | "qspiroot=/dev/mtdblock0\0" \ | 152 | "qspiroot=/dev/mtdblock0\0" \ |
139 | "qspirootfstype=jffs2\0" \ | 153 | "qspirootfstype=jffs2\0" \ |
140 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ | 154 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ |
141 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ | 155 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ |
142 | "bootm ${loadaddr} - ${fdt_addr}\0" | 156 | "bootm ${loadaddr} - ${fdt_addr}\0" |
143 | 157 | ||
144 | /* using environment setting for stdin, stdout, stderr */ | 158 | /* using environment setting for stdin, stdout, stderr */ |
145 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | 159 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
146 | /* Enable the call to overwrite_console() */ | 160 | /* Enable the call to overwrite_console() */ |
147 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | 161 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
148 | /* Enable overwrite of previous console environment settings */ | 162 | /* Enable overwrite of previous console environment settings */ |
149 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | 163 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
150 | 164 | ||
151 | /* max number of command args */ | 165 | /* max number of command args */ |
152 | #define CONFIG_SYS_MAXARGS 16 | 166 | #define CONFIG_SYS_MAXARGS 16 |
153 | 167 | ||
154 | 168 | ||
155 | /* | 169 | /* |
156 | * Hardware drivers | 170 | * Hardware drivers |
157 | */ | 171 | */ |
158 | 172 | ||
159 | /* | 173 | /* |
160 | * SDRAM Memory Map | 174 | * SDRAM Memory Map |
161 | */ | 175 | */ |
162 | /* We have 1 bank of DRAM */ | 176 | /* We have 1 bank of DRAM */ |
163 | #define CONFIG_NR_DRAM_BANKS 1 | 177 | #define CONFIG_NR_DRAM_BANKS 1 |
164 | /* SDRAM Bank #1 */ | 178 | /* SDRAM Bank #1 */ |
165 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | 179 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
166 | /* SDRAM memory size */ | 180 | /* SDRAM memory size */ |
167 | #define PHYS_SDRAM_1_SIZE 0x40000000 | 181 | #define PHYS_SDRAM_1_SIZE 0x40000000 |
168 | 182 | ||
169 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | 183 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
170 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | 184 | #define CONFIG_SYS_MEMTEST_START 0x00000000 |
171 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE | 185 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE |
172 | 186 | ||
173 | /* | 187 | /* |
174 | * NS16550 Configuration | 188 | * NS16550 Configuration |
175 | */ | 189 | */ |
176 | #define UART0_BASE SOCFPGA_UART0_ADDRESS | 190 | #define UART0_BASE SOCFPGA_UART0_ADDRESS |
177 | #define CONFIG_SYS_NS16550 | 191 | #define CONFIG_SYS_NS16550 |
178 | #define CONFIG_SYS_NS16550_SERIAL | 192 | #define CONFIG_SYS_NS16550_SERIAL |
179 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | 193 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
180 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | 194 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
181 | #define CONFIG_CONS_INDEX 1 | 195 | #define CONFIG_CONS_INDEX 1 |
182 | #define CONFIG_SYS_NS16550_COM1 UART0_BASE | 196 | #define CONFIG_SYS_NS16550_COM1 UART0_BASE |
183 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} | 197 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
184 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 198 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
185 | #define V_NS16550_CLK 1000000 | 199 | #define V_NS16550_CLK 1000000 |
186 | #else | 200 | #else |
187 | #define V_NS16550_CLK 100000000 | 201 | #define V_NS16550_CLK 100000000 |
188 | #endif | 202 | #endif |
189 | #define CONFIG_BAUDRATE 115200 | 203 | #define CONFIG_BAUDRATE 115200 |
190 | 204 | ||
191 | /* | 205 | /* |
192 | * FLASH | 206 | * FLASH |
193 | */ | 207 | */ |
194 | #define CONFIG_SYS_NO_FLASH | 208 | #define CONFIG_SYS_NO_FLASH |
195 | 209 | ||
196 | /* | 210 | /* |
197 | * L4 OSC1 Timer 0 | 211 | * L4 OSC1 Timer 0 |
198 | */ | 212 | */ |
199 | /* This timer use eosc1 where the clock frequency is fixed | 213 | /* This timer use eosc1 where the clock frequency is fixed |
200 | * throughout any condition */ | 214 | * throughout any condition */ |
201 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS | 215 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
202 | /* Timer info */ | 216 | /* Timer info */ |
203 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 217 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
204 | #define CONFIG_SYS_TIMER_RATE 2400000 | 218 | #define CONFIG_SYS_TIMER_RATE 2400000 |
205 | #else | 219 | #else |
206 | #define CONFIG_SYS_TIMER_RATE 25000000 | 220 | #define CONFIG_SYS_TIMER_RATE 25000000 |
207 | #endif | 221 | #endif |
208 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | 222 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
209 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | 223 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
210 | 224 | ||
211 | #define CONFIG_ENV_IS_NOWHERE | 225 | #define CONFIG_ENV_IS_NOWHERE |
212 | 226 | ||
213 | /* | 227 | /* |
214 | * network support | 228 | * network support |
215 | */ | 229 | */ |
216 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET | 230 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
217 | #define CONFIG_DESIGNWARE_ETH 1 | 231 | #define CONFIG_DESIGNWARE_ETH 1 |
218 | #endif | 232 | #endif |
219 | 233 | ||
220 | #ifdef CONFIG_DESIGNWARE_ETH | 234 | #ifdef CONFIG_DESIGNWARE_ETH |
221 | #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS | 235 | #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS |
222 | #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS | 236 | #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS |
223 | /* console support for network */ | 237 | /* console support for network */ |
224 | #define CONFIG_CMD_DHCP | 238 | #define CONFIG_CMD_DHCP |
225 | #define CONFIG_CMD_MII | 239 | #define CONFIG_CMD_MII |
226 | #define CONFIG_CMD_NET | 240 | #define CONFIG_CMD_NET |
227 | #define CONFIG_CMD_PING | 241 | #define CONFIG_CMD_PING |
228 | /* designware */ | 242 | /* designware */ |
229 | #define CONFIG_NET_MULTI | 243 | #define CONFIG_NET_MULTI |
230 | #define CONFIG_DW_ALTDESCRIPTOR | 244 | #define CONFIG_DW_ALTDESCRIPTOR |
231 | #define CONFIG_MII | 245 | #define CONFIG_MII |
232 | #define CONFIG_PHY_GIGE | 246 | #define CONFIG_PHY_GIGE |
233 | #define CONFIG_DW_AUTONEG | 247 | #define CONFIG_DW_AUTONEG |
234 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) | 248 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) |
235 | #define CONFIG_PHYLIB | 249 | #define CONFIG_PHYLIB |
236 | #define CONFIG_PHY_MICREL | 250 | #define CONFIG_PHY_MICREL |
237 | #define CONFIG_PHY_MICREL_KSZ9021 | 251 | #define CONFIG_PHY_MICREL_KSZ9021 |
238 | /* EMAC controller and PHY used */ | 252 | /* EMAC controller and PHY used */ |
239 | #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE | 253 | #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE |
240 | #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR | 254 | #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR |
241 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | 255 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
242 | #endif /* CONFIG_DESIGNWARE_ETH */ | 256 | #endif /* CONFIG_DESIGNWARE_ETH */ |
243 | 257 | ||
244 | /* | 258 | /* |
245 | * L4 Watchdog | 259 | * L4 Watchdog |
246 | */ | 260 | */ |
247 | #define CONFIG_HW_WATCHDOG | 261 | #define CONFIG_HW_WATCHDOG |
248 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 | 262 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 |
249 | #define CONFIG_DESIGNWARE_WATCHDOG | 263 | #define CONFIG_DESIGNWARE_WATCHDOG |
250 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS | 264 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
251 | /* Clocks source frequency to watchdog timer */ | 265 | /* Clocks source frequency to watchdog timer */ |
252 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 | 266 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
253 | 267 | ||
254 | /* | 268 | /* |
255 | * MMC support | 269 | * MMC support |
256 | */ | 270 | */ |
257 | #define CONFIG_MMC | 271 | #define CONFIG_MMC |
258 | #ifdef CONFIG_MMC | 272 | #ifdef CONFIG_MMC |
259 | #define CONFIG_BOUNCE_BUFFER | 273 | #define CONFIG_BOUNCE_BUFFER |
260 | #define CONFIG_CMD_MMC | 274 | #define CONFIG_CMD_MMC |
261 | #define CONFIG_GENERIC_MMC | 275 | #define CONFIG_GENERIC_MMC |
262 | #define CONFIG_DWMMC | 276 | #define CONFIG_DWMMC |
263 | #define CONFIG_SOCFPGA_DWMMC | 277 | #define CONFIG_SOCFPGA_DWMMC |
264 | #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 | 278 | #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 |
265 | #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 | 279 | #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 |
266 | #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 | 280 | #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 |
267 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ | 281 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ |
268 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 | 282 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
269 | #endif /* CONFIG_MMC */ | 283 | #endif /* CONFIG_MMC */ |
270 | 284 | ||
271 | /* | 285 | /* |
272 | * SPL "Second Program Loader" aka Initial Software | 286 | * SPL "Second Program Loader" aka Initial Software |
273 | */ | 287 | */ |
274 | 288 | ||
275 | /* Enable building of SPL globally */ | 289 | /* Enable building of SPL globally */ |
276 | #define CONFIG_SPL_FRAMEWORK | 290 | #define CONFIG_SPL_FRAMEWORK |
277 | 291 | ||
278 | /* TEXT_BASE for linking the SPL binary */ | 292 | /* TEXT_BASE for linking the SPL binary */ |
279 | #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 | 293 | #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 |
280 | 294 | ||
281 | /* Stack size for SPL */ | 295 | /* Stack size for SPL */ |
282 | #define CONFIG_SPL_STACK_SIZE (4 * 1024) | 296 | #define CONFIG_SPL_STACK_SIZE (4 * 1024) |
283 | 297 | ||
284 | /* MALLOC size for SPL */ | 298 | /* MALLOC size for SPL */ |
285 | #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) | 299 | #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) |
286 | 300 | ||
287 | #define CONFIG_SPL_SERIAL_SUPPORT | 301 | #define CONFIG_SPL_SERIAL_SUPPORT |
288 | #define CONFIG_SPL_BOARD_INIT | 302 | #define CONFIG_SPL_BOARD_INIT |
289 | 303 | ||
290 | #define CHUNKSZ_CRC32 (1 * 1024) | 304 | #define CHUNKSZ_CRC32 (1 * 1024) |
291 | 305 | ||
292 | #define CONFIG_CRC32_VERIFY | 306 | #define CONFIG_CRC32_VERIFY |
293 | 307 | ||
294 | /* Linker script for SPL */ | 308 | /* Linker script for SPL */ |
295 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" | 309 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" |
296 | 310 | ||
297 | /* Support for common/libcommon.o in SPL binary */ | 311 | /* Support for common/libcommon.o in SPL binary */ |
298 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | 312 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
299 | /* Support for lib/libgeneric.o in SPL binary */ | 313 | /* Support for lib/libgeneric.o in SPL binary */ |
300 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | 314 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
301 | 315 | ||
302 | /* Support for watchdog */ | 316 | /* Support for watchdog */ |
303 | #define CONFIG_SPL_WATCHDOG_SUPPORT | 317 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
304 | 318 | ||
305 | #endif /* __CONFIG_H */ | 319 | #endif /* __CONFIG_H */ |
306 | 320 |