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Commit ddcbed04a21857cb0a457b0ff3de26c750815632

Authored by Chin Liang See
Committed by Marek Vasut
1 parent 13e81d45f8
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: Enable DWMMC for SOCFPGA 

Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 16 additions and 0 deletions Side-by-side Diff

include/configs/socfpga_cyclone5.h
Diff comments   View file @ ddcbed0
... ... @@ -251,6 +251,22 @@
251 251 /* Clocks source frequency to watchdog timer */
252 252 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
253 253  
  254 +/*
  255 + * MMC support
  256 + */
  257 +#define CONFIG_MMC
  258 +#ifdef CONFIG_MMC
  259 +#define CONFIG_BOUNCE_BUFFER
  260 +#define CONFIG_CMD_MMC
  261 +#define CONFIG_GENERIC_MMC
  262 +#define CONFIG_DWMMC
  263 +#define CONFIG_SOCFPGA_DWMMC
  264 +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
  265 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
  266 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
  267 +/* using smaller max blk cnt to avoid flooding the limited stack we have */
  268 +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  269 +#endif /* CONFIG_MMC */
254 270  
255 271 /*
256 272 * SPL "Second Program Loader" aka Initial Software