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Commit 98250e8e17fc76b3981708c6e63d41f875bf0359

Authored by Jens Scharsig
Committed by Tom Rix
1 parent 1b34f00c28
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

prepare joining at91rm9200 into at91 

* prepare joining at91 and at91rm9200
 * add modified copy of soc files to cpu/arm920t/at91 to make
   possible to compile at91rm9200 boards in at91 tree instead
   of at91rm9200
 * add header files with c structure defs for AT91 MC, ST and TC
 * the new cpu files are using at91 c structure soc access
 * please read README.soc-at91 for details

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>

Showing 12 changed files with 825 additions and 6 deletions Side-by-side Diff

cpu/arm920t/at91/Makefile
Diff comments   View file @ 98250e8
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(SOC).a
  27 +
  28 +SOBJS += lowlevel_init.o
  29 +COBJS += reset.o
  30 +COBJS += timer.o
  31 +
  32 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  33 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  34 +
  35 +all: $(obj).depend $(LIB)
  36 +
  37 +$(LIB): $(OBJS)
  38 + $(AR) $(ARFLAGS) $@ $(OBJS)
  39 +
  40 +#########################################################################
  41 +
  42 +# defines $(obj).depend target
  43 +include $(SRCTREE)/rules.mk
  44 +
  45 +sinclude $(obj).depend
  46 +
  47 +#########################################################################
cpu/arm920t/at91/lowlevel_init.S
Diff comments   View file @ 98250e8
  1 +/*
  2 + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  3 + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  4 + *
  5 + * Modified for the at91rm9200dk board by
  6 + * (C) Copyright 2004
  7 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + */
  27 +
  28 +#include <config.h>
  29 +
  30 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  31 +
  32 +#include <asm/arch/hardware.h>
  33 +#include <asm/arch/at91_mc.h>
  34 +#include <asm/arch/at91_pmc.h>
  35 +#include <asm/arch/at91_pio.h>
  36 +
  37 +#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
  38 +
  39 +_MTEXT_BASE:
  40 +#undef START_FROM_MEM
  41 +#ifdef START_FROM_MEM
  42 + .word TEXT_BASE-PHYS_FLASH_1
  43 +#else
  44 + .word TEXT_BASE
  45 +#endif
  46 +
  47 +.globl lowlevel_init
  48 +lowlevel_init:
  49 + ldr r1, =AT91_ASM_PMC_MOR
  50 + /* Main oscillator Enable register */
  51 +#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
  52 + ldr r0, =0x0000FF01 /* Enable main oscillator */
  53 +#else
  54 + ldr r0, =0x0000FF00 /* Disable main oscillator */
  55 +#endif
  56 + str r0, [r1] /*AT91C_CKGR_MOR] */
  57 + /* Add loop to compensate Main Oscillator startup time */
  58 + ldr r0, =0x00000010
  59 +LoopOsc:
  60 + subs r0, r0, #1
  61 + bhi LoopOsc
  62 +
  63 + /* memory control configuration */
  64 + /* this isn't very elegant, but what the heck */
  65 + ldr r0, =SMRDATA
  66 + ldr r1, _MTEXT_BASE
  67 + sub r0, r0, r1
  68 + add r2, r0, #80
  69 +pllloop:
  70 + /* the address */
  71 + ldr r1, [r0], #4
  72 + /* the value */
  73 + ldr r3, [r0], #4
  74 + str r3, [r1]
  75 + cmp r2, r0
  76 + bne pllloop
  77 + /* delay - this is all done by guess */
  78 + ldr r0, =0x00010000
  79 + /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
  80 +lock:
  81 + subs r0, r0, #1
  82 + bhi lock
  83 + ldr r0, =SMRDATA1
  84 + ldr r1, _MTEXT_BASE
  85 + sub r0, r0, r1
  86 + add r2, r0, #176
  87 +sdinit:
  88 + /* the address */
  89 + ldr r1, [r0], #4
  90 + /* the value */
  91 + ldr r3, [r0], #4
  92 + str r3, [r1]
  93 + cmp r2, r0
  94 + bne sdinit
  95 +
  96 + /* switch from FastBus to Asynchronous clock mode */
  97 + mrc p15, 0, r0, c1, c0, 0
  98 + orr r0, r0, #ARM920T_CONTROL
  99 + mcr p15, 0, r0, c1, c0, 0
  100 +
  101 + /* everything is fine now */
  102 + mov pc, lr
  103 +
  104 + .ltorg
  105 +
  106 +SMRDATA:
  107 + .word AT91_ASM_MC_EBI_CFG
  108 + .word CONFIG_SYS_EBI_CFGR_VAL
  109 + .word AT91_ASM_MC_SMC_CSR0
  110 + .word CONFIG_SYS_SMC_CSR0_VAL
  111 + .word AT91_ASM_PMC_PLLAR
  112 + .word CONFIG_SYS_PLLAR_VAL
  113 + .word AT91_ASM_PMC_PLLBR
  114 + .word CONFIG_SYS_PLLBR_VAL
  115 + .word AT91_ASM_PMC_MCKR
  116 + .word CONFIG_SYS_MCKR_VAL
  117 + /* here there's a delay */
  118 +SMRDATA1:
  119 + .word AT91_ASM_PIOC_ASR
  120 + .word CONFIG_SYS_PIOC_ASR_VAL
  121 + .word AT91_ASM_PIOC_BSR
  122 + .word CONFIG_SYS_PIOC_BSR_VAL
  123 + .word AT91_ASM_PIOC_PDR
  124 + .word CONFIG_SYS_PIOC_PDR_VAL
  125 + .word AT91_ASM_MC_EBI_CSA
  126 + .word CONFIG_SYS_EBI_CSA_VAL
  127 + .word AT91_ASM_MC_SDRAMC_CR
  128 + .word CONFIG_SYS_SDRC_CR_VAL
  129 + .word AT91_ASM_MC_SDRAMC_MR
  130 + .word CONFIG_SYS_SDRC_MR_VAL
  131 + .word CONFIG_SYS_SDRAM
  132 + .word CONFIG_SYS_SDRAM_VAL
  133 + .word AT91_ASM_MC_SDRAMC_MR
  134 + .word CONFIG_SYS_SDRC_MR_VAL1
  135 + .word CONFIG_SYS_SDRAM
  136 + .word CONFIG_SYS_SDRAM_VAL
  137 + .word CONFIG_SYS_SDRAM
  138 + .word CONFIG_SYS_SDRAM_VAL
  139 + .word CONFIG_SYS_SDRAM
  140 + .word CONFIG_SYS_SDRAM_VAL
  141 + .word CONFIG_SYS_SDRAM
  142 + .word CONFIG_SYS_SDRAM_VAL
  143 + .word CONFIG_SYS_SDRAM
  144 + .word CONFIG_SYS_SDRAM_VAL
  145 + .word CONFIG_SYS_SDRAM
  146 + .word CONFIG_SYS_SDRAM_VAL
  147 + .word CONFIG_SYS_SDRAM
  148 + .word CONFIG_SYS_SDRAM_VAL
  149 + .word CONFIG_SYS_SDRAM
  150 + .word CONFIG_SYS_SDRAM_VAL
  151 + .word AT91_ASM_MC_SDRAMC_MR
  152 + .word CONFIG_SYS_SDRC_MR_VAL2
  153 + .word CONFIG_SYS_SDRAM1
  154 + .word CONFIG_SYS_SDRAM_VAL
  155 + .word AT91_ASM_MC_SDRAMC_TR
  156 + .word CONFIG_SYS_SDRC_TR_VAL
  157 + .word CONFIG_SYS_SDRAM
  158 + .word CONFIG_SYS_SDRAM_VAL
  159 + .word AT91_ASM_MC_SDRAMC_MR
  160 + .word CONFIG_SYS_SDRC_MR_VAL3
  161 + .word CONFIG_SYS_SDRAM
  162 + .word CONFIG_SYS_SDRAM_VAL
  163 + /* SMRDATA1 is 176 bytes long */
  164 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
cpu/arm920t/at91/reset.c
Diff comments   View file @ 98250e8
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Lineo, Inc. <www.lineo.com>
  4 + * Bernhard Kuhn <bkuhn@lineo.com>
  5 + *
  6 + * (C) Copyright 2002
  7 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8 + * Marius Groeger <mgroeger@sysgo.de>
  9 + *
  10 + * (C) Copyright 2002
  11 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12 + * Alex Zuepke <azu@sysgo.de>
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + *
  27 + * You should have received a copy of the GNU General Public License
  28 + * along with this program; if not, write to the Free Software
  29 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 + * MA 02111-1307 USA
  31 + */
  32 +
  33 +#include <common.h>
  34 +#include <asm/io.h>
  35 +#include <asm/arch/hardware.h>
  36 +#include <asm/arch/at91_st.h>
  37 +
  38 +void board_reset(void) __attribute__((__weak__));
  39 +
  40 +void reset_cpu(ulong ignored)
  41 +{
  42 + at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
  43 +#if defined(CONFIG_AT91RM9200_USART)
  44 + /*shutdown the console to avoid strange chars during reset */
  45 + serial_exit();
  46 +#endif
  47 +
  48 + if (board_reset)
  49 + board_reset();
  50 +
  51 + /* Reset the cpu by setting up the watchdog timer */
  52 + writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
  53 + &st->wdmr);
  54 + writel(AT91_ST_CR_WDRST, &st->cr);
  55 + /* and let it timeout */
  56 + while (1)
  57 + ;
  58 + /* Never reached */
  59 +}
cpu/arm920t/at91/timer.c
Diff comments   View file @ 98250e8
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Lineo, Inc. <www.lineo.com>
  4 + * Bernhard Kuhn <bkuhn@lineo.com>
  5 + *
  6 + * (C) Copyright 2002
  7 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8 + * Marius Groeger <mgroeger@sysgo.de>
  9 + *
  10 + * (C) Copyright 2002
  11 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12 + * Alex Zuepke <azu@sysgo.de>
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + *
  27 + * You should have received a copy of the GNU General Public License
  28 + * along with this program; if not, write to the Free Software
  29 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 + * MA 02111-1307 USA
  31 + */
  32 +
  33 +#include <common.h>
  34 +
  35 +#include <asm/io.h>
  36 +#include <asm/hardware.h>
  37 +#include <asm/arch/at91_tc.h>
  38 +#include <asm/arch/at91_pmc.h>
  39 +
  40 +/* the number of clocks per CONFIG_SYS_HZ */
  41 +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
  42 +
  43 +static u32 timestamp;
  44 +static u32 lastinc;
  45 +
  46 +int timer_init(void)
  47 +{
  48 + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
  49 + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
  50 +
  51 + /* enables TC1.0 clock */
  52 + writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */
  53 +
  54 + writel(0, &tc->bcr);
  55 + writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
  56 + AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
  57 +
  58 + writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
  59 + /* set to MCLK/2 and restart the timer
  60 + when the value in TC_RC is reached */
  61 + writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
  62 +
  63 + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
  64 + writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
  65 +
  66 + writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
  67 + lastinc = 0;
  68 + timestamp = 0;
  69 +
  70 + return 0;
  71 +}
  72 +
  73 +/*
  74 + * timer without interrupts
  75 + */
  76 +
  77 +void reset_timer(void)
  78 +{
  79 + reset_timer_masked();
  80 +}
  81 +
  82 +ulong get_timer(ulong base)
  83 +{
  84 + return get_timer_masked() - base;
  85 +}
  86 +
  87 +void set_timer(ulong t)
  88 +{
  89 + timestamp = t;
  90 +}
  91 +
  92 +void __udelay(unsigned long usec)
  93 +{
  94 + udelay_masked(usec);
  95 +}
  96 +
  97 +void reset_timer_masked(void)
  98 +{
  99 + /* reset time */
  100 + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
  101 + lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
  102 + timestamp = 0;
  103 +}
  104 +
  105 +ulong get_timer_raw(void)
  106 +{
  107 + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
  108 + u32 now;
  109 +
  110 + now = readl(&tc->tc[0].cv) & 0x0000ffff;
  111 +
  112 + if (now >= lastinc) {
  113 + /* normal mode */
  114 + timestamp += now - lastinc;
  115 + } else {
  116 + /* we have an overflow ... */
  117 + timestamp += now + TIMER_LOAD_VAL - lastinc;
  118 + }
  119 + lastinc = now;
  120 +
  121 + return timestamp;
  122 +}
  123 +
  124 +ulong get_timer_masked(void)
  125 +{
  126 + return get_timer_raw()/TIMER_LOAD_VAL;
  127 +}
  128 +
  129 +void udelay_masked(unsigned long usec)
  130 +{
  131 + u32 tmo;
  132 + u32 endtime;
  133 + signed long diff;
  134 +
  135 + tmo = CONFIG_SYS_HZ_CLOCK / 1000;
  136 + tmo *= usec;
  137 + tmo /= 1000;
  138 +
  139 + endtime = get_timer_raw() + tmo;
  140 +
  141 + do {
  142 + u32 now = get_timer_raw();
  143 + diff = endtime - now;
  144 + } while (diff >= 0);
  145 +}
  146 +
  147 +/*
  148 + * This function is derived from PowerPC code (read timebase as long long).
  149 + * On ARM it just returns the timer value.
  150 + */
  151 +unsigned long long get_ticks(void)
  152 +{
  153 + return get_timer(0);
  154 +}
  155 +
  156 +/*
  157 + * This function is derived from PowerPC code (timebase clock frequency).
  158 + * On ARM it returns the number of timer ticks per second.
  159 + */
  160 +ulong get_tbclk(void)
  161 +{
  162 + return CONFIG_SYS_HZ;
  163 +}
... ... @@ -33,6 +33,10 @@
33 33 #include <command.h>
34 34 #include <asm/system.h>
35 35  
  36 +#ifdef CONFIG_AT91_LEGACY
  37 +#warning Your board is using legacy AT91RM9200 SoC access. Please update!
  38 +#endif
  39 +
36 40 static void cache_flush(void);
37 41  
38 42 int cleanup_before_linux (void)
... ... @@ -39,4 +39,27 @@
39 39 3. add new structures for SoC access
40 40 4. Convert arch, driver and boards file to new SoC
41 41 5. remove legacy code, if all boards and drives are ready
  42 +
  43 + Join AT91 and AT91RM9200 SoC
  44 +==============================
  45 +
  46 +Approximately 95 percent of AT91 and AT91RM9200 SoC parts are the same.
  47 +So, we should use the chance, to join both archs togetter.
  48 +
  49 +To do this follow step needed:
  50 +
  51 +1. change Makefile
  52 + @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91rm9200
  53 + to
  54 + @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91
  55 +2. remove CONFIG_AT91_LEGACY in board config
  56 +3. convert boards file to new SoC access
  57 +4. convert or change drivers
  58 +
  59 +To support the joining process, a new SoC dir (at91) has been adding to
  60 +arm920t arch directory. This directory contains files like at91rm9200 dir, but
  61 +uses the new c structure Soc access. The advantage of this is, we don't merge
  62 +old Soc access code and new code while the board are not converted.
  63 +Finally we can delete the whole at91rm9200 dir, if all board support the
  64 +new AT91-SoC access.
include/asm-arm/arch-at91/at91_mc.h
Diff comments   View file @ 98250e8
  1 +/*
  2 + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef AT91_MC_H
  24 +#define AT91_MC_H
  25 +
  26 +#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60)
  27 +#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64)
  28 +#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70)
  29 +#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90)
  30 +#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94)
  31 +#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98)
  32 +
  33 +#ifndef __ASSEMBLY__
  34 +
  35 +typedef struct at91_ebi {
  36 + u32 csa; /* 0x00 Chip Select Assignment Register */
  37 + u32 cfgr; /* 0x04 Configuration Register */
  38 + u32 reserved[2];
  39 +} __attribute__ ((packed)) at91_ebi_t;
  40 +
  41 +#define AT91_EBI_CSA_CS0A 0x0001
  42 +#define AT91_EBI_CSA_CS1A 0x0002
  43 +
  44 +#define AT91_EBI_CSA_CS3A 0x0008
  45 +#define AT91_EBI_CSA_CS4A 0x0010
  46 +
  47 +typedef struct at91_sdramc {
  48 + u32 mr; /* 0x00 SDRAMC Mode Register */
  49 + u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
  50 + u32 cr; /* 0x08 SDRAMC Configuration Register */
  51 + u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
  52 + u32 lpr; /* 0x10 SDRAMC Low Power Register */
  53 + u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
  54 + u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
  55 + u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
  56 + u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
  57 + u32 reserved[3];
  58 +} __attribute__ ((packed)) at91_sdramc_t;
  59 +
  60 +typedef struct at91_smc {
  61 + u32 csr[8]; /* 0x00 SDRAMC Mode Register */
  62 +} __attribute__ ((packed)) at91_smc_t;
  63 +
  64 +#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
  65 +#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
  66 +#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
  67 +#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
  68 +#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
  69 +#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
  70 +#define AT91_SMC_CSR_DRP 0x00008000
  71 +#define AT91_SMC_CSR_DBW_8 0x00004000
  72 +#define AT91_SMC_CSR_DBW_16 0x00002000
  73 +#define AT91_SMC_CSR_BAT_8 0x00000000
  74 +#define AT91_SMC_CSR_BAT_16 0x00001000
  75 +#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
  76 +#define AT91_SMC_CSR_WSEN 0x00000080
  77 +#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
  78 +
  79 +typedef struct at91_bfc {
  80 + u32 mr; /* 0x00 SDRAMC Mode Register */
  81 +} __attribute__ ((packed)) at91_bfc_t;
  82 +
  83 +typedef struct at91_mc {
  84 + u32 rcr; /* 0x00 MC Remap Control Register */
  85 + u32 asr; /* 0x04 MC Abort Status Register */
  86 + u32 aasr; /* 0x08 MC Abort Address Status Reg */
  87 + u32 mpr; /* 0x0C MC Master Priority Register */
  88 + u32 reserved1[20]; /* 0x10-0x5C */
  89 + at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
  90 + at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
  91 + at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
  92 + at91_bfc_t bfc; /* 0xC0 BFC User Interface */
  93 + u32 reserved2[15];
  94 +} __attribute__ ((packed)) at91_mc_t;
  95 +
  96 +#endif
  97 +#endif
include/asm-arm/arch-at91/at91_pio.h
Diff comments   View file @ 98250e8
... ... @@ -19,17 +19,21 @@
19 19  
20 20  
21 21 #define AT91_ASM_PIO_RANGE 0x200
  22 +#define AT91_ASM_PIOC_ASR \
  23 + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
  24 +#define AT91_ASM_PIOC_BSR \
  25 + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
22 26 #define AT91_ASM_PIOC_PDR \
23   - (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04)
  27 + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
24 28 #define AT91_ASM_PIOC_PUDR \
25   - (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60)
  29 + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
26 30  
27 31 #define AT91_ASM_PIOD_PDR \
28   - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04)
  32 + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
29 33 #define AT91_ASM_PIOD_PUDR \
30   - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60)
  34 + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
31 35 #define AT91_ASM_PIOD_ASR \
32   - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70)
  36 + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
33 37  
34 38 #ifndef __ASSEMBLY__
35 39  
include/asm-arm/arch-at91/at91_st.h
Diff comments   View file @ 98250e8
  1 +/*
  2 + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef AT91_ST_H
  24 +#define AT91_ST_H
  25 +
  26 +typedef struct at91_st {
  27 +
  28 + u32 cr;
  29 + u32 pimr;
  30 + u32 wdmr;
  31 + u32 rtmr;
  32 + u32 sr;
  33 + u32 ier;
  34 + u32 idr;
  35 + u32 imr;
  36 + u32 rtar;
  37 + u32 crtr;
  38 +} __attribute__ ((packed)) at91_st_t ;
  39 +
  40 +#define AT91_ST_CR_WDRST 1
  41 +
  42 +#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
  43 +#define AT91_ST_WDMR_RSTEN 0x00010000
  44 +#define AT91_ST_WDMR_EXTEN 0x00020000
  45 +
  46 +#endif
include/asm-arm/arch-at91/at91_tc.h
Diff comments   View file @ 98250e8
  1 +/*
  2 + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef AT91_TC_H
  24 +#define AT91_TC_H
  25 +
  26 +typedef struct at91_tcc {
  27 + u32 ccr; /* 0x00 Channel Control Register */
  28 + u32 cmr; /* 0x04 Channel Mode Register */
  29 + u32 reserved1[2];
  30 + u32 cv; /* 0x10 Counter Value */
  31 + u32 ra; /* 0x14 Register A */
  32 + u32 rb; /* 0x18 Register B */
  33 + u32 rc; /* 0x1C Register C */
  34 + u32 sr; /* 0x20 Status Register */
  35 + u32 ier; /* 0x24 Interrupt Enable Register */
  36 + u32 idr; /* 0x28 Interrupt Disable Register */
  37 + u32 imr; /* 0x2C Interrupt Mask Register */
  38 + u32 reserved3[4];
  39 +} __attribute__ ((packed)) at91_tcc_t;
  40 +
  41 +#define AT91_TC_CCR_CLKEN 0x00000001
  42 +#define AT91_TC_CCR_CLKDIS 0x00000002
  43 +#define AT91_TC_CCR_SWTRG 0x00000004
  44 +
  45 +#define AT91_TC_CMR_CPCTRG 0x00004000
  46 +
  47 +#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
  48 +#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
  49 +#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
  50 +#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
  51 +#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
  52 +#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
  53 +#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
  54 +#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
  55 +
  56 +typedef struct at91_tc {
  57 + at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
  58 + u32 bcr; /* 0xC0 TC Block Control Register */
  59 + u32 bmr; /* 0xC4 TC Block Mode Register */
  60 +} __attribute__ ((packed)) at91_tc_t;
  61 +
  62 +#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
  63 +#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
  64 +#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
  65 +#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
  66 +
  67 +#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
  68 +#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
  69 +#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
  70 +#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
  71 +
  72 +#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
  73 +#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
  74 +#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
  75 +#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
  76 +
  77 +#endif
include/asm-arm/arch-at91/at91rm9200.h
Diff comments   View file @ 98250e8
  1 +/*
  2 + * See file CREDITS for list of people who contributed to this
  3 + * project.
  4 + *
  5 + * This program is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 + * MA 02111-1307 USA
  19 + */
  20 +
  21 +#ifndef __AT91RM9200_H__
  22 +#define __AT91RM9200_H__
  23 +
  24 +/* Periperial Identifiers */
  25 +
  26 +#define AT91_ID_SYS 1 /* System Peripheral */
  27 +#define AT91_ID_PIOA 2 /* PIO port A */
  28 +#define AT91_ID_PIOB 3 /* PIO port B */
  29 +#define AT91_ID_PIOC 4 /* PIO port C */
  30 +#define AT91_ID_PIOD 5 /* PIO port D BGA only */
  31 +#define AT91_ID_USART0 6 /* USART 0 */
  32 +#define AT91_ID_USART1 7 /* USART 1 */
  33 +#define AT91_ID_USART2 8 /* USART 2 */
  34 +#define AT91_ID_USART3 9 /* USART 3 */
  35 +#define AT91_ID_MCI 10 /* Multimedia Card Interface */
  36 +#define AT91_ID_UDP 11 /* USB Device Port */
  37 +#define AT91_ID_TWI 12 /* Two Wire Interface */
  38 +#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
  39 +#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */
  40 +#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */
  41 +#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */
  42 +#define AT91_ID_TC0 17 /* Timer Counter 0 */
  43 +#define AT91_ID_TC1 18 /* Timer Counter 1 */
  44 +#define AT91_ID_TC2 19 /* Timer Counter 2 */
  45 +#define AT91_ID_TC3 20 /* Timer Counter 3 */
  46 +#define AT91_ID_TC4 21 /* Timer Counter 4 */
  47 +#define AT91_ID_TC5 22 /* Timer Counter 5 */
  48 +#define AT91_ID_UHP 23 /* OHCI USB Host Port */
  49 +#define AT91_ID_EMAC 24 /* Ethernet MAC */
  50 +#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */
  51 +#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */
  52 +#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */
  53 +#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */
  54 +#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */
  55 +#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */
  56 +#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */
  57 +
  58 +#define AT91_USB_HOST_BASE 0x00300000
  59 +
  60 +#define AT91_TC_BASE 0xFFFA0000
  61 +#define AT91_UDP_BASE 0xFFFB0000
  62 +#define AT91_MCI_BASE 0xFFFB4000
  63 +#define AT91_TWI_BASE 0xFFFB8000
  64 +#define AT91_EMAC_BASE 0xFFFBC000
  65 +#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */
  66 +#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */
  67 +#define AT91_SPI_BASE 0xFFFE0000
  68 +
  69 +#define AT91_AIC_BASE 0xFFFFF000
  70 +#define AT91_DBGU_BASE 0xFFFFF200
  71 +#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */
  72 +#define AT91_PMC_BASE 0xFFFFFC00
  73 +#define AT91_ST_BASE 0xFFFFFD00
  74 +#define AT91_ST_BASE 0xFFFFFD00
  75 +#define AT91_RTC_BASE 0xFFFFFE00
  76 +#define AT91_MC_BASE 0xFFFFFF00
  77 +
  78 +
  79 +/* AT91RM9200 Periperial Multiplexing A */
  80 +/* Port A */
  81 +#define AT91_PMX_AA_EREFCK 0x00000080
  82 +#define AT91_PMX_AA_ETXCK 0x00000080
  83 +#define AT91_PMX_AA_ETXEN 0x00000100
  84 +#define AT91_PMX_AA_ETX0 0x00000200
  85 +#define AT91_PMX_AA_ETX1 0x00000400
  86 +#define AT91_PMX_AA_ECRS 0x00000800
  87 +#define AT91_PMX_AA_ECRSDV 0x00000800
  88 +#define AT91_PMX_AA_ERX0 0x00001000
  89 +#define AT91_PMX_AA_ERX1 0x00002000
  90 +#define AT91_PMX_AA_ERXER 0x00004000
  91 +#define AT91_PMX_AA_EMDC 0x00008000
  92 +#define AT91_PMX_AA_EMDIO 0x00010000
  93 +
  94 +#define AT91_PMX_AA_TXD2 0x00810000
  95 +
  96 +#define AT91_PMX_AA_TWD 0x02000000
  97 +#define AT91_PMX_AA_TWCK 0x04000000
  98 +
  99 +/* Port B */
  100 +#define AT91_PMX_BA_ERXCK 0x00080000
  101 +#define AT91_PMX_BA_ECOL 0x00040000
  102 +#define AT91_PMX_BA_ERXDV 0x00020000
  103 +#define AT91_PMX_BA_ERX3 0x00010000
  104 +#define AT91_PMX_BA_ERX2 0x00008000
  105 +#define AT91_PMX_BA_ETXER 0x00004000
  106 +#define AT91_PMX_BA_ETX3 0x00002000
  107 +#define AT91_PMX_BA_ETX2 0x00001000
  108 +
  109 +/* Port B */
  110 +
  111 +#define AT91_PMX_CA_BFCK 0x00000001
  112 +#define AT91_PMX_CA_BFRDY 0x00000002
  113 +#define AT91_PMX_CA_SMOE 0x00000002
  114 +#define AT91_PMX_CA_BFAVD 0x00000004
  115 +#define AT91_PMX_CA_BFBAA 0x00000008
  116 +#define AT91_PMX_CA_SMWE 0x00000008
  117 +#define AT91_PMX_CA_BFOE 0x00000010
  118 +#define AT91_PMX_CA_BFWE 0x00000020
  119 +#define AT91_PMX_CA_NWAIT 0x00000040
  120 +#define AT91_PMX_CA_A23 0x00000080
  121 +#define AT91_PMX_CA_A24 0x00000100
  122 +#define AT91_PMX_CA_A25 0x00000200
  123 +#define AT91_PMX_CA_CFRNW 0x00000200
  124 +#define AT91_PMX_CA_NCS4 0x00000400
  125 +#define AT91_PMX_CA_CFCS 0x00000400
  126 +#define AT91_PMX_CA_NCS5 0x00000800
  127 +#define AT91_PMX_CA_CFCE1 0x00001000
  128 +#define AT91_PMX_CA_NCS6 0x00001000
  129 +#define AT91_PMX_CA_CFCE2 0x00002000
  130 +#define AT91_PMX_CA_NCS7 0x00002000
  131 +#define AT91_PMX_CA_D16_31 0xFFFF0000
  132 +
  133 +#define AT91_CPU_NAME "AT91RM9200"
  134 +
  135 +#endif
include/asm-arm/arch-at91/hardware.h
Diff comments   View file @ 98250e8
... ... @@ -17,7 +17,7 @@
17 17 #include <asm/sizes.h>
18 18  
19 19 #if defined(CONFIG_AT91RM9200)
20   -#include <asm/arch/at91rm9200.h>
  20 +#include <asm/arch-at91/at91rm9200.h>
21 21 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
22 22 #include <asm/arch/at91sam9260.h>
23 23 #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0