Commit 9886c3d7a803f639b975f63397cc24a3307fa7b6
Committed by
Tom Rini
1 parent
f4a40f05f5
Exists in
v2017.01-smarct4x
and in
37 other branches
omap3: cm-t35: move the SMC911x code
Extract the SMC911x initialization code to a common location where it can be reused by other compulab omap3 based boards. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
Showing 4 changed files with 112 additions and 43 deletions Side-by-side Diff
board/compulab/cm_t35/cm_t35.c
... | ... | @@ -23,6 +23,7 @@ |
23 | 23 | #include <linux/compiler.h> |
24 | 24 | |
25 | 25 | #include <asm/io.h> |
26 | +#include <asm/errno.h> | |
26 | 27 | #include <asm/arch/mem.h> |
27 | 28 | #include <asm/arch/mux.h> |
28 | 29 | #include <asm/arch/mmc_host_def.h> |
... | ... | @@ -42,16 +43,6 @@ |
42 | 43 | "NAND", |
43 | 44 | }; |
44 | 45 | |
45 | -static u32 gpmc_net_config[GPMC_MAX_REG] = { | |
46 | - NET_GPMC_CONFIG1, | |
47 | - NET_GPMC_CONFIG2, | |
48 | - NET_GPMC_CONFIG3, | |
49 | - NET_GPMC_CONFIG4, | |
50 | - NET_GPMC_CONFIG5, | |
51 | - NET_GPMC_CONFIG6, | |
52 | - 0 | |
53 | -}; | |
54 | - | |
55 | 46 | #ifdef CONFIG_SPL_BUILD |
56 | 47 | /* |
57 | 48 | * Routine: get_board_mem_timings |
58 | 49 | |
... | ... | @@ -391,37 +382,12 @@ |
391 | 382 | } |
392 | 383 | #endif |
393 | 384 | |
394 | -/* | |
395 | - * Routine: setup_net_chip_gmpc | |
396 | - * Description: Setting up the configuration GPMC registers specific to the | |
397 | - * Ethernet hardware. | |
398 | - */ | |
399 | -static void setup_net_chip_gmpc(void) | |
400 | -{ | |
401 | - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; | |
402 | - | |
403 | - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], | |
404 | - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); | |
405 | - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], | |
406 | - SB_T35_SMC911X_BASE, GPMC_SIZE_16M); | |
407 | - | |
408 | - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ | |
409 | - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); | |
410 | - | |
411 | - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ | |
412 | - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); | |
413 | - | |
414 | - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ | |
415 | - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, | |
416 | - &ctrl_base->gpmc_nadv_ale); | |
417 | -} | |
418 | - | |
419 | 385 | #ifdef CONFIG_SYS_I2C_OMAP34XX |
420 | 386 | /* |
421 | 387 | * Routine: reset_net_chip |
422 | 388 | * Description: reset the Ethernet controller via TPS65930 GPIO |
423 | 389 | */ |
424 | -static void reset_net_chip(void) | |
390 | +static int cm_t3x_reset_net_chip(int gpio) | |
425 | 391 | { |
426 | 392 | /* Set GPIO1 of TPS65930 as output */ |
427 | 393 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, |
428 | 394 | |
... | ... | @@ -436,9 +402,10 @@ |
436 | 402 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, |
437 | 403 | 0x02); |
438 | 404 | mdelay(1); |
405 | + return 0; | |
439 | 406 | } |
440 | 407 | #else |
441 | -static inline void reset_net_chip(void) {} | |
408 | +static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } | |
442 | 409 | #endif |
443 | 410 | |
444 | 411 | #ifdef CONFIG_SMC911X |
... | ... | @@ -465,7 +432,6 @@ |
465 | 432 | return eth_setenv_enetaddr("ethaddr", enetaddr); |
466 | 433 | } |
467 | 434 | |
468 | - | |
469 | 435 | /* |
470 | 436 | * Routine: board_eth_init |
471 | 437 | * Description: initialize module and base-board Ethernet chips |
472 | 438 | |
473 | 439 | |
... | ... | @@ -474,18 +440,16 @@ |
474 | 440 | { |
475 | 441 | int rc = 0, rc1 = 0; |
476 | 442 | |
477 | - setup_net_chip_gmpc(); | |
478 | - reset_net_chip(); | |
479 | - | |
480 | 443 | rc1 = handle_mac_address(); |
481 | 444 | if (rc1) |
482 | 445 | printf("No MAC address found! "); |
483 | 446 | |
484 | - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); | |
447 | + rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, | |
448 | + cm_t3x_reset_net_chip, -EINVAL); | |
485 | 449 | if (rc1 > 0) |
486 | 450 | rc++; |
487 | 451 | |
488 | - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); | |
452 | + rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); | |
489 | 453 | if (rc1 > 0) |
490 | 454 | rc++; |
491 | 455 |
board/compulab/common/Makefile
board/compulab/common/common.h
... | ... | @@ -33,5 +33,16 @@ |
33 | 33 | } |
34 | 34 | #endif /* CONFIG_SPLASH_SCREEN */ |
35 | 35 | |
36 | +#ifdef CONFIG_SMC911X | |
37 | +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, | |
38 | + int (*reset)(int), int rst_gpio); | |
39 | +#else /* !CONFIG_SMC911X */ | |
40 | +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, | |
41 | + int (*reset)(int), int rst_gpio) | |
42 | +{ | |
43 | + return -ENOSYS; | |
44 | +} | |
45 | +#endif /* CONFIG_SMC911X */ | |
46 | + | |
36 | 47 | #endif /* _CL_COMMON_ */ |
board/compulab/common/omap3_smc911x.c
1 | +/* | |
2 | + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> | |
3 | + * | |
4 | + * Authors: Igor Grinberg <grinberg@compulab.co.il> | |
5 | + * | |
6 | + * SPDX-License-Identifier: GPL-2.0+ | |
7 | + */ | |
8 | + | |
9 | +#include <common.h> | |
10 | +#include <netdev.h> | |
11 | + | |
12 | +#include <asm/io.h> | |
13 | +#include <asm/errno.h> | |
14 | +#include <asm/arch/cpu.h> | |
15 | +#include <asm/arch/mem.h> | |
16 | +#include <asm/arch/sys_proto.h> | |
17 | +#include <asm/gpio.h> | |
18 | + | |
19 | +#include "common.h" | |
20 | + | |
21 | +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { | |
22 | + NET_GPMC_CONFIG1, | |
23 | + NET_GPMC_CONFIG2, | |
24 | + NET_GPMC_CONFIG3, | |
25 | + NET_GPMC_CONFIG4, | |
26 | + NET_GPMC_CONFIG5, | |
27 | + NET_GPMC_CONFIG6, | |
28 | + 0 | |
29 | +}; | |
30 | + | |
31 | +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) | |
32 | +{ | |
33 | + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; | |
34 | + | |
35 | + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, | |
36 | + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); | |
37 | + | |
38 | + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ | |
39 | + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); | |
40 | + | |
41 | + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ | |
42 | + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); | |
43 | + | |
44 | + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ | |
45 | + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, | |
46 | + &ctrl_base->gpmc_nadv_ale); | |
47 | +} | |
48 | + | |
49 | +#ifdef CONFIG_OMAP_GPIO | |
50 | +static int cl_omap3_smc911x_reset_net_chip(int gpio) | |
51 | +{ | |
52 | + int err; | |
53 | + | |
54 | + if (!gpio_is_valid(gpio)) | |
55 | + return -EINVAL; | |
56 | + | |
57 | + err = gpio_request(gpio, "eth rst"); | |
58 | + if (err) | |
59 | + return err; | |
60 | + | |
61 | + /* Set gpio as output and send a pulse */ | |
62 | + gpio_direction_output(gpio, 1); | |
63 | + udelay(1); | |
64 | + gpio_set_value(gpio, 0); | |
65 | + mdelay(40); | |
66 | + gpio_set_value(gpio, 1); | |
67 | + mdelay(1); | |
68 | + | |
69 | + return 0; | |
70 | +} | |
71 | +#else /* !CONFIG_OMAP_GPIO */ | |
72 | +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } | |
73 | +#endif /* CONFIG_OMAP_GPIO */ | |
74 | + | |
75 | +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, | |
76 | + int (*reset)(int), int rst_gpio) | |
77 | +{ | |
78 | + int ret; | |
79 | + | |
80 | + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); | |
81 | + | |
82 | + if (reset) | |
83 | + reset(rst_gpio); | |
84 | + else | |
85 | + cl_omap3_smc911x_reset_net_chip(rst_gpio); | |
86 | + | |
87 | + ret = smc911x_initialize(id, base_addr); | |
88 | + if (ret > 0) | |
89 | + return ret; | |
90 | + | |
91 | + printf("Failed initializing SMC911x! "); | |
92 | + return 0; | |
93 | +} |