Eric Lee / smarc-uboot

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Commit 98addfd48773c1f1170c40f9067c2fc91efd3509

Authored by Roger Quadros
Committed by Lokesh Vutla
1 parent d7c2ab1ca8
Exists in v2016.05-smarct4x and in 3 other branches v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc

dra7xx: Enable USB_PHY3 32KHz clock 

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>

Showing 3 changed files with 14 additions and 2 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/hw_data.c
Diff comments   View file @ 98addfd
... ... @@ -626,9 +626,14 @@
626 626 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
627 627 OPTFCLKEN_REFCLK960M);
628 628  
629   - /* Enable 32 KHz clock for dwc3 */
  629 + /* Enable 32 KHz clock for USB_PHY1 */
630 630 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
631 631 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  632 +
  633 + /* Enable 32 KHz clock for USB_PHY3 */
  634 + if (is_dra7xx())
  635 + setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
  636 + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
632 637 } else if (index == 1) {
633 638 cm_l3init_usb_otg_ss_clkctrl =
634 639 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
635 640  
... ... @@ -676,9 +681,14 @@
676 681 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
677 682 OPTFCLKEN_REFCLK960M);
678 683  
679   - /* Disable 32 KHz clock for dwc3 */
  684 + /* Disable 32 KHz clock for USB_PHY1 */
680 685 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
681 686 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  687 +
  688 + /* Disable 32 KHz clock for USB_PHY3 */
  689 + if (is_dra7xx())
  690 + clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
  691 + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
682 692 } else if (index == 1) {
683 693 cm_l3init_usb_otg_ss_clkctrl =
684 694 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
arch/arm/cpu/armv7/omap5/prcm-regs.c
Diff comments   View file @ 98addfd
... ... @@ -820,6 +820,7 @@
820 820 .cm_clkmode_dpll_gmac = 0x4a0052a8,
821 821 .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
822 822 .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
  823 + .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
823 824 .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
824 825  
825 826 /* cm1.mpu */
arch/arm/include/asm/omap_common.h
Diff comments   View file @ 98addfd
... ... @@ -145,6 +145,7 @@
145 145 u32 cm_ssc_modfreqdiv_dpll_unipro;
146 146 u32 cm_coreaon_usb_phy1_core_clkctrl;
147 147 u32 cm_coreaon_usb_phy2_core_clkctrl;
  148 + u32 cm_coreaon_usb_phy3_core_clkctrl;
148 149 u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
149 150  
150 151 /* cm2.core */