Eric Lee / smarc-uboot

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Commit 98cecb610f3fa53aa7d825a634d35ef9cf6c5487

Authored by Wolfgang Denk
2 parents a747a7f310 3fca803759
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 27 changed files Side-by-side Diff

board/freescale/mpc8569mds/bcsr.h
Diff comments   View file @ 98cecb6
... ... @@ -33,7 +33,8 @@
33 33 #define BCSR6_UPC1_POS_EN 0x40
34 34 #define BCSR6_UPC1_ADDR_EN 0x20
35 35 #define BCSR6_UPC1_DEV2 0x10
36   -#define BCSR6_SD_ENABLE 0x04
  36 +#define BCSR6_SD_CARD_1BIT 0x08
  37 +#define BCSR6_SD_CARD_4BITS 0x04
37 38 #define BCSR6_TDM2G_EN 0x02
38 39 #define BCSR6_UCC7_RMII_EN 0x01
39 40  
40 41  
... ... @@ -67,9 +68,14 @@
67 68  
68 69 #define BCSR15_SMII6_DIS 0x08
69 70 #define BCSR15_SMII8_DIS 0x04
  71 +#define BCSR15_QEUART_EN 0x01
70 72  
71 73 #define BCSR16_UPC1_DEV2 0x02
72 74  
  75 +#define BCSR17_nUSBEN 0x80
  76 +#define BCSR17_nUSBLOWSPD 0x40
  77 +#define BCSR17_USBVCC 0x20
  78 +#define BCSR17_USBMODE 0x10
73 79 #define BCSR17_FLASH_nWP 0x01
74 80  
75 81 /*BCSR Utils functions*/
board/freescale/mpc8569mds/law.c
Diff comments   View file @ 98cecb6
... ... @@ -54,6 +54,7 @@
54 54 SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
55 55 SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
56 56 SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
  57 + SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
57 58 };
58 59  
59 60 int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/mpc8569mds/mpc8569mds.c
Diff comments   View file @ 98cecb6
... ... @@ -23,6 +23,7 @@
23 23 */
24 24  
25 25 #include <common.h>
  26 +#include <hwconfig.h>
26 27 #include <pci.h>
27 28 #include <asm/processor.h>
28 29 #include <asm/mmu.h>
... ... @@ -35,6 +36,7 @@
35 36 #include <ioports.h>
36 37 #include <libfdt.h>
37 38 #include <fdt_support.h>
  39 +#include <fsl_esdhc.h>
38 40  
39 41 #include "bcsr.h"
40 42  
... ... @@ -152,6 +154,27 @@
152 154 {5, 10, 2, 0, 3}, /* UART1_CTS_B */
153 155 {5, 11, 1, 0, 2}, /* UART1_RTS_B */
154 156  
  157 + /* QE UART */
  158 + {0, 19, 1, 0, 2}, /* QEUART_TX */
  159 + {1, 17, 2, 0, 3}, /* QEUART_RX */
  160 + {0, 25, 1, 0, 1}, /* QEUART_RTS */
  161 + {1, 23, 2, 0, 1}, /* QEUART_CTS */
  162 +
  163 + /* QE USB */
  164 + {5, 3, 1, 0, 1}, /* USB_OE */
  165 + {5, 4, 1, 0, 2}, /* USB_TP */
  166 + {5, 5, 1, 0, 2}, /* USB_TN */
  167 + {5, 6, 2, 0, 2}, /* USB_RP */
  168 + {5, 7, 2, 0, 1}, /* USB_RX */
  169 + {5, 8, 2, 0, 1}, /* USB_RN */
  170 + {2, 4, 2, 0, 2}, /* CLK5 */
  171 +
  172 + /* SPI Flash, M25P40 */
  173 + {4, 27, 3, 0, 1}, /* SPI_MOSI */
  174 + {4, 28, 3, 0, 1}, /* SPI_MISO */
  175 + {4, 29, 3, 0, 1}, /* SPI_CLK */
  176 + {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
  177 +
155 178 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
156 179 };
157 180  
... ... @@ -303,6 +326,190 @@
303 326 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
304 327 }
305 328  
  329 +static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
  330 +{
  331 + const char *status = "disabled";
  332 + int off;
  333 + int err;
  334 +
  335 + off = fdt_path_offset(blob, alias);
  336 + if (off < 0) {
  337 + printf("WARNING: could not find %s alias: %s.\n", alias,
  338 + fdt_strerror(off));
  339 + return;
  340 + }
  341 +
  342 + err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
  343 + if (err) {
  344 + printf("WARNING: could not set status for serial0: %s.\n",
  345 + fdt_strerror(err));
  346 + return;
  347 + }
  348 +}
  349 +
  350 +/*
  351 + * Because of an erratum in prototype boards it is impossible to use eSDHC
  352 + * without disabling UART0 (which makes it quite easy to 'brick' the board
  353 + * by simply issung 'setenv hwconfig esdhc', and not able to interact with
  354 + * U-Boot anylonger).
  355 + *
  356 + * So, but default we assume that the board is a prototype, which is a most
  357 + * safe assumption. There is no way to determine board revision from a
  358 + * register, so we use hwconfig.
  359 + */
  360 +
  361 +static int prototype_board(void)
  362 +{
  363 + if (hwconfig_subarg("board", "rev", NULL))
  364 + return hwconfig_subarg_cmp("board", "rev", "prototype");
  365 + return 1;
  366 +}
  367 +
  368 +static int esdhc_disables_uart0(void)
  369 +{
  370 + return prototype_board() ||
  371 + hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
  372 +}
  373 +
  374 +static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
  375 +{
  376 + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  377 + const char *devtype = "serial";
  378 + const char *compat = "ucc_uart";
  379 + const char *clk = "brg9";
  380 + u32 portnum = 0;
  381 + int off = -1;
  382 +
  383 + if (!hwconfig("qe_uart"))
  384 + return;
  385 +
  386 + if (hwconfig("esdhc") && esdhc_disables_uart0()) {
  387 + printf("QE UART: won't enable with esdhc.\n");
  388 + return;
  389 + }
  390 +
  391 + fdt_board_disable_serial(blob, bd, "serial1");
  392 +
  393 + while (1) {
  394 + const u32 *idx;
  395 + int len;
  396 +
  397 + off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
  398 + if (off < 0) {
  399 + printf("WARNING: unable to fixup device tree for "
  400 + "QE UART\n");
  401 + return;
  402 + }
  403 +
  404 + idx = fdt_getprop(blob, off, "cell-index", &len);
  405 + if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
  406 + continue;
  407 + break;
  408 + }
  409 +
  410 + fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
  411 + fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
  412 + fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
  413 + fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
  414 + fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
  415 +
  416 + setbits_8(&bcsr[15], BCSR15_QEUART_EN);
  417 +}
  418 +
  419 +#ifdef CONFIG_FSL_ESDHC
  420 +
  421 +int board_mmc_init(bd_t *bd)
  422 +{
  423 + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  424 + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  425 + u8 bcsr6 = BCSR6_SD_CARD_1BIT;
  426 +
  427 + if (!hwconfig("esdhc"))
  428 + return 0;
  429 +
  430 + printf("Enabling eSDHC...\n"
  431 + " For eSDHC to function, I2C2 ");
  432 + if (esdhc_disables_uart0()) {
  433 + printf("and UART0 should be disabled.\n");
  434 + printf(" Redirecting stderr, stdout and stdin to UART1...\n");
  435 + console_assign(stderr, "eserial1");
  436 + console_assign(stdout, "eserial1");
  437 + console_assign(stdin, "eserial1");
  438 + printf("Switched to UART1 (initial log has been printed to "
  439 + "UART0).\n");
  440 + bcsr6 |= BCSR6_SD_CARD_4BITS;
  441 + } else {
  442 + printf("should be disabled.\n");
  443 + }
  444 +
  445 + /* Assign I2C2 signals to eSDHC. */
  446 + clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
  447 + PLPPAR1_ESDHC_VAL);
  448 + clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
  449 + PLPDIR1_ESDHC_VAL);
  450 +
  451 + /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
  452 + setbits_8(&bcsr[6], bcsr6);
  453 +
  454 + return fsl_esdhc_mmc_init(bd);
  455 +}
  456 +
  457 +static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
  458 +{
  459 + const char *status = "disabled";
  460 + int off = -1;
  461 +
  462 + if (!hwconfig("esdhc"))
  463 + return;
  464 +
  465 + if (esdhc_disables_uart0())
  466 + fdt_board_disable_serial(blob, bd, "serial0");
  467 +
  468 + while (1) {
  469 + const u32 *idx;
  470 + int len;
  471 +
  472 + off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
  473 + if (off < 0)
  474 + break;
  475 +
  476 + idx = fdt_getprop(blob, off, "cell-index", &len);
  477 + if (!idx || len != sizeof(*idx))
  478 + continue;
  479 +
  480 + if (*idx == 1) {
  481 + fdt_setprop(blob, off, "status", status,
  482 + strlen(status) + 1);
  483 + break;
  484 + }
  485 + }
  486 +}
  487 +#else
  488 +static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
  489 +#endif
  490 +
  491 +static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
  492 +{
  493 + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  494 +
  495 + if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
  496 + clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  497 + else
  498 + setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  499 +
  500 + if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
  501 + clrbits_8(&bcsr[17], BCSR17_USBVCC);
  502 + clrbits_8(&bcsr[17], BCSR17_USBMODE);
  503 + do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
  504 + "peripheral", sizeof("peripheral"), 1);
  505 + } else {
  506 + setbits_8(&bcsr[17], BCSR17_USBVCC);
  507 + setbits_8(&bcsr[17], BCSR17_USBMODE);
  508 + }
  509 +
  510 + clrbits_8(&bcsr[17], BCSR17_nUSBEN);
  511 +}
  512 +
306 513 #ifdef CONFIG_PCIE1
307 514 static struct pci_controller pcie1_hose;
308 515 #endif /* CONFIG_PCIE1 */
... ... @@ -444,6 +651,9 @@
444 651 #ifdef CONFIG_PCIE1
445 652 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
446 653 #endif
  654 + fdt_board_fixup_esdhc(blob, bd);
  655 + fdt_board_fixup_qe_uart(blob, bd);
  656 + fdt_board_fixup_qe_usb(blob, bd);
447 657 }
448 658 #endif
board/freescale/mpc8569mds/tlb.c
Diff comments   View file @ 98cecb6
... ... @@ -46,22 +46,24 @@
46 46  
47 47 /* TLB 1 Initializations */
48 48 /*
49   - * TLBe 0: 16M Non-cacheable, guarded
50   - * 0xff000000 16M FLASH (upper half)
  49 + * TLBe 0: 64M Non-cacheable, guarded
51 50 * Out of reset this entry is only 4K.
  51 + * 0xfc000000 256K NAND FLASH (CS3)
  52 + * 0xfe000000 32M NOR FLASH (CS0)
52 53 */
53   - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
54   - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
  54 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
55 55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56   - 0, 0, BOOKE_PAGESZ_16M, 1),
  56 + 0, 0, BOOKE_PAGESZ_64M, 1),
57 57  
58 58 /*
59   - * TLBe 1: 16M Non-cacheable, guarded
60   - * 0xfe000000 16M FLASH (lower half)
  59 + * TLBe 1: 256KB Non-cacheable, guarded
  60 + * 0xf8000000 32K BCSR
  61 + * 0xf8008000 32K PIB (CS4)
  62 + * 0xf8010000 32K PIB (CS5)
61 63 */
62   - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  64 + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
63 65 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64   - 0, 1, BOOKE_PAGESZ_16M, 1),
  66 + 0, 1, BOOKE_PAGESZ_256K, 1),
65 67  
66 68 /*
67 69 * TLBe 2: 256M Non-cacheable, guarded
... ... @@ -88,16 +90,6 @@
88 90 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
89 91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 92 0, 4, BOOKE_PAGESZ_64M, 1),
91   -
92   - /*
93   - * TLBe 5: 256K Non-cacheable, guarded
94   - * 0xf8000000 32K BCSR
95   - * 0xf8008000 32K PIB (CS4)
96   - * 0xf8010000 32K PIB (CS5)
97   - */
98   - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
99   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
100   - 0, 5, BOOKE_PAGESZ_256K, 1),
101 93 };
102 94  
103 95 int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/mpc8572ds/mpc8572ds.c
Diff comments   View file @ 98cecb6
... ... @@ -199,7 +199,7 @@
199 199 pcie_ep ? "End Point" : "Root Complex",
200 200 pci_info[num].regs);
201 201 first_free_busno = fsl_pci_init_port(&pci_info[num++],
202   - &pcie3_hose, first_free_busno);
  202 + &pcie3_hose, first_free_busno, pcie_ep);
203 203 /*
204 204 * Activate ULI1575 legacy chip by performing a fake
205 205 * memory access. Needed to make ULI RTC work.
... ... @@ -231,7 +231,7 @@
231 231 pcie_ep ? "End Point" : "Root Complex",
232 232 pci_info[num].regs);
233 233 first_free_busno = fsl_pci_init_port(&pci_info[num++],
234   - &pcie2_hose, first_free_busno);
  234 + &pcie2_hose, first_free_busno, pcie_ep);
235 235 } else {
236 236 printf (" PCIE2: disabled\n");
237 237 }
... ... @@ -251,7 +251,7 @@
251 251 pcie_ep ? "End Point" : "Root Complex",
252 252 pci_info[num].regs);
253 253 first_free_busno = fsl_pci_init_port(&pci_info[num++],
254   - &pcie1_hose, first_free_busno);
  254 + &pcie1_hose, first_free_busno, pcie_ep);
255 255 } else {
256 256 printf (" PCIE1: disabled\n");
257 257 }
board/freescale/p1_p2_rdb/ddr.c
Diff comments   View file @ 98cecb6
... ... @@ -85,8 +85,8 @@
85 85 #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
86 86 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
87 87 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
88   -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
89   -#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
  88 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
  89 +#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
90 90 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
91 91 #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
92 92  
... ... @@ -206,7 +206,7 @@
206 206 {
207 207 sys_info_t sysinfo;
208 208 char buf[32];
209   - fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
  209 + fsl_ddr_cfg_regs_t ddr_cfg_regs;
210 210 size_t ddr_size;
211 211 struct cpu_type *cpu;
212 212  
213 213  
214 214  
215 215  
... ... @@ -215,13 +215,13 @@
215 215 strmhz(buf, sysinfo.freqDDRBus));
216 216  
217 217 if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
218   - ddr_cfg_regs = &ddr_cfg_regs_400;
  218 + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
219 219 else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
220   - ddr_cfg_regs = &ddr_cfg_regs_533;
  220 + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
221 221 else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
222   - ddr_cfg_regs = &ddr_cfg_regs_667;
  222 + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
223 223 else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
224   - ddr_cfg_regs = &ddr_cfg_regs_800;
  224 + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
225 225 else
226 226 panic("Unsupported DDR data rate %s MT/s data rate\n",
227 227 strmhz(buf, sysinfo.freqDDRBus));
228 228  
... ... @@ -230,14 +230,14 @@
230 230 /* P1020 and it's derivatives support max 32bit DDR width */
231 231 if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
232 232 cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
233   - ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
234   - ddr_cfg_regs->cs[0].bnds = 0x0000001F;
  233 + ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
  234 + ddr_cfg_regs.cs[0].bnds = 0x0000001F;
235 235 ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
236 236 }
237 237 else
238 238 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
239 239  
240   - fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
  240 + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
241 241  
242 242 return ddr_size;
243 243 }
board/freescale/p1_p2_rdb/pci.c
Diff comments   View file @ 98cecb6
... ... @@ -71,7 +71,7 @@
71 71 pcie_ep ? "End Point" : "Root Complex",
72 72 pci_info[num].regs);
73 73 first_free_busno = fsl_pci_init_port(&pci_info[num++],
74   - &pcie2_hose, first_free_busno);
  74 + &pcie2_hose, first_free_busno, pcie_ep);
75 75 } else {
76 76 printf (" PCIE2: disabled\n");
77 77 }
... ... @@ -90,7 +90,7 @@
90 90 pcie_ep ? "End Point" : "Root Complex",
91 91 pci_info[num].regs);
92 92 first_free_busno = fsl_pci_init_port(&pci_info[num++],
93   - &pcie1_hose, first_free_busno);
  93 + &pcie1_hose, first_free_busno, pcie_ep);
94 94 } else {
95 95 printf (" PCIE1: disabled\n");
96 96 }
board/freescale/p2020ds/p2020ds.c
Diff comments   View file @ 98cecb6
... ... @@ -227,7 +227,7 @@
227 227 pcie_ep ? "End Point" : "Root Complex",
228 228 pci_info[num].regs);
229 229 first_free_busno = fsl_pci_init_port(&pci_info[num++],
230   - &pcie2_hose, first_free_busno);
  230 + &pcie2_hose, first_free_busno, pcie_ep);
231 231  
232 232 /*
233 233 * The workaround doesn't work on p2020 because the location
... ... @@ -267,7 +267,7 @@
267 267 pcie_ep ? "End Point" : "Root Complex",
268 268 pci_info[num].regs);
269 269 first_free_busno = fsl_pci_init_port(&pci_info[num++],
270   - &pcie3_hose, first_free_busno);
  270 + &pcie3_hose, first_free_busno, pcie_ep);
271 271 } else {
272 272 printf(" PCIE3: disabled\n");
273 273 }
... ... @@ -286,7 +286,7 @@
286 286 pcie_ep ? "End Point" : "Root Complex",
287 287 pci_info[num].regs);
288 288 first_free_busno = fsl_pci_init_port(&pci_info[num++],
289   - &pcie1_hose, first_free_busno);
  289 + &pcie1_hose, first_free_busno, pcie_ep);
290 290 } else {
291 291 printf(" PCIE1: disabled\n");
292 292 }
board/sbc8548/sbc8548.c
Diff comments   View file @ 98cecb6
... ... @@ -359,7 +359,7 @@
359 359  
360 360 SET_STD_PCI_INFO(pci_info[num], 1);
361 361 first_free_busno = fsl_pci_init_port(&pci_info[num++],
362   - &pci1_hose, first_free_busno);
  362 + &pci1_hose, first_free_busno, 0);
363 363 } else {
364 364 printf (" PCI: disabled\n");
365 365 }
... ... @@ -378,7 +378,7 @@
378 378 SET_STD_PCIE_INFO(pci_info[num], 1);
379 379 printf (" PCIE at base address %lx\n", pci_info[num].regs);
380 380 first_free_busno = fsl_pci_init_port(&pci_info[num++],
381   - &pcie1_hose, first_free_busno);
  381 + &pcie1_hose, first_free_busno, 0);
382 382 } else {
383 383 printf (" PCIE: disabled\n");
384 384 }
board/xes/xpedite5370/tlb.c
Diff comments   View file @ 98cecb6
... ... @@ -61,32 +61,37 @@
61 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 62 0, 2, BOOKE_PAGESZ_1M, 1),
63 63  
  64 + /* **M** - Boot page for secondary processors */
  65 + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
  66 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  67 + 0, 3, BOOKE_PAGESZ_4K, 1),
  68 +
64 69 #ifdef CONFIG_PCIE1
65 70 /* *I*G* - PCIe */
66 71 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
67 72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68   - 0, 3, BOOKE_PAGESZ_1G, 1),
  73 + 0, 4, BOOKE_PAGESZ_1G, 1),
69 74 #endif
70 75  
71 76 #ifdef CONFIG_PCIE2
72 77 /* *I*G* - PCIe */
73 78 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
74 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75   - 0, 4, BOOKE_PAGESZ_256M, 1),
  80 + 0, 5, BOOKE_PAGESZ_256M, 1),
76 81 #endif
77 82  
78 83 #ifdef CONFIG_PCIE3
79 84 /* *I*G* - PCIe */
80 85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
81 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82   - 0, 5, BOOKE_PAGESZ_256M, 1),
  87 + 0, 6, BOOKE_PAGESZ_256M, 1),
83 88 #endif
84 89  
85 90 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
86 91 /* *I*G* - PCIe */
87 92 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
88 93 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
89   - 0, 6, BOOKE_PAGESZ_64M, 1),
  94 + 0, 7, BOOKE_PAGESZ_64M, 1),
90 95 #endif
91 96  
92 97 };
common/fdt_support.c
Diff comments   View file @ 98cecb6
... ... @@ -22,6 +22,7 @@
22 22 */
23 23  
24 24 #include <common.h>
  25 +#include <stdio_dev.h>
25 26 #include <linux/ctype.h>
26 27 #include <linux/types.h>
27 28 #include <asm/global_data.h>
... ... @@ -90,6 +91,23 @@
90 91 }
91 92  
92 93 #ifdef CONFIG_OF_STDOUT_VIA_ALIAS
  94 +
  95 +#ifdef CONFIG_SERIAL_MULTI
  96 +static void fdt_fill_multisername(char *sername, size_t maxlen)
  97 +{
  98 + const char *outname = stdio_devices[stdout]->name;
  99 +
  100 + if (strcmp(outname, "serial") > 0)
  101 + strncpy(sername, outname, maxlen);
  102 +
  103 + /* eserial? */
  104 + if (strcmp(outname + 1, "serial") > 0)
  105 + strncpy(sername, outname + 1, maxlen);
  106 +}
  107 +#else
  108 +static inline void fdt_fill_multisername(char *sername, size_t maxlen) {}
  109 +#endif /* CONFIG_SERIAL_MULTI */
  110 +
93 111 static int fdt_fixup_stdout(void *fdt, int chosenoff)
94 112 {
95 113 int err = 0;
... ... @@ -98,7 +116,9 @@
98 116 char sername[9] = { 0 };
99 117 const char *path;
100 118  
101   - sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
  119 + fdt_fill_multisername(sername, sizeof(sername) - 1);
  120 + if (!sername[0])
  121 + sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
102 122  
103 123 err = node = fdt_path_offset(fdt, "/aliases");
104 124 if (node >= 0) {
cpu/mpc85xx/config.mk
Diff comments   View file @ 98cecb6
... ... @@ -24,6 +24,11 @@
24 24 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
25 25  
26 26 PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
  27 +
  28 +# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
  29 +# see "[PATCH,rs6000] make -mno-spe work as expected" on
  30 +# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
  31 +PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes)
27 32 PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
28 33  
29 34 # Use default linker script. Board port can override in board/*/config.mk
cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 98cecb6
... ... @@ -360,8 +360,11 @@
360 360 /* enable the cache */
361 361 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
362 362  
363   - if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
  363 + if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
  364 + while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
  365 + ;
364 366 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
  367 + }
365 368 #else
366 369 puts("disabled\n");
367 370 #endif
... ... @@ -43,7 +43,7 @@
43 43 void ft_fixup_cpu(void *blob, u64 memory_limit)
44 44 {
45 45 int off;
46   - ulong spin_tbl_addr = get_spin_addr();
  46 + ulong spin_tbl_addr = get_spin_phys_addr();
47 47 u32 bootpg = determine_mp_bootpg();
48 48 u32 id = get_my_id();
49 49  
... ... @@ -52,10 +52,10 @@
52 52 u32 *table, id = get_my_id();
53 53  
54 54 if (nr == id) {
55   - table = (u32 *)get_spin_addr();
  55 + table = (u32 *)get_spin_virt_addr();
56 56 printf("table base @ 0x%p\n", table);
57 57 } else {
58   - table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
  58 + table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
59 59 printf("Running on cpu %d\n", id);
60 60 printf("\n");
61 61 printf("table @ 0x%p\n", table);
... ... @@ -77,7 +77,7 @@
77 77  
78 78 int cpu_release(int nr, int argc, char *argv[])
79 79 {
80   - u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
  80 + u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
81 81 u64 boot_addr;
82 82  
83 83 if (nr == get_my_id()) {
84 84  
85 85  
86 86  
... ... @@ -124,23 +124,29 @@
124 124 return (gd->ram_size - 4096);
125 125 }
126 126  
127   -ulong get_spin_addr(void)
  127 +ulong get_spin_phys_addr(void)
128 128 {
129 129 extern ulong __secondary_start_page;
130 130 extern ulong __spin_table;
131 131  
132   - ulong addr =
133   - (ulong)&__spin_table - (ulong)&__secondary_start_page;
134   - addr += 0xfffff000;
  132 + return (determine_mp_bootpg() +
  133 + (ulong)&__spin_table - (ulong)&__secondary_start_page);
  134 +}
135 135  
136   - return addr;
  136 +ulong get_spin_virt_addr(void)
  137 +{
  138 + extern ulong __secondary_start_page;
  139 + extern ulong __spin_table;
  140 +
  141 + return (CONFIG_BPTR_VIRT_ADDR +
  142 + (ulong)&__spin_table - (ulong)&__secondary_start_page);
137 143 }
138 144  
139 145 #ifdef CONFIG_FSL_CORENET
140 146 static void plat_mp_up(unsigned long bootpg)
141 147 {
142 148 u32 up, cpu_up_mask, whoami;
143   - u32 *table = (u32 *)get_spin_addr();
  149 + u32 *table = (u32 *)get_spin_virt_addr();
144 150 volatile ccsr_gur_t *gur;
145 151 volatile ccsr_local_t *ccm;
146 152 volatile ccsr_rcpm_t *rcpm;
147 153  
... ... @@ -194,12 +200,23 @@
194 200 mtspr(SPRN_TBWU, 0);
195 201 mtspr(SPRN_TBWL, 0);
196 202 out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
  203 +
  204 +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  205 + /*
  206 + * Disabling Boot Page Translation allows the memory region 0xfffff000
  207 + * to 0xffffffff to be used normally. Leaving Boot Page Translation
  208 + * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  209 + * unusable for normal operation but it does allow OSes to easily
  210 + * reset a processor core to put it back into U-Boot's spinloop.
  211 + */
  212 + clrbits_be32(&ecm->bptr, 0x80000000);
  213 +#endif
197 214 }
198 215 #else
199 216 static void plat_mp_up(unsigned long bootpg)
200 217 {
201 218 u32 up, cpu_up_mask, whoami;
202   - u32 *table = (u32 *)get_spin_addr();
  219 + u32 *table = (u32 *)get_spin_virt_addr();
203 220 volatile u32 bpcr;
204 221 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
205 222 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
... ... @@ -256,6 +273,17 @@
256 273  
257 274 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
258 275 out_be32(&gur->devdisr, devdisr);
  276 +
  277 +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  278 + /*
  279 + * Disabling Boot Page Translation allows the memory region 0xfffff000
  280 + * to 0xffffffff to be used normally. Leaving Boot Page Translation
  281 + * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  282 + * unusable for normal operation but it does allow OSes to easily
  283 + * reset a processor core to put it back into U-Boot's spinloop.
  284 + */
  285 + clrbits_be32(&ecm->bptr, 0x80000000);
  286 +#endif
259 287 }
260 288 #endif
261 289  
262 290  
263 291  
264 292  
265 293  
... ... @@ -269,32 +297,26 @@
269 297 void setup_mp(void)
270 298 {
271 299 extern ulong __secondary_start_page;
  300 + extern ulong __bootpg_addr;
272 301 ulong fixup = (ulong)&__secondary_start_page;
273 302 u32 bootpg = determine_mp_bootpg();
274 303  
  304 + /* Store the bootpg's SDRAM address for use by secondary CPU cores */
  305 + __bootpg_addr = bootpg;
  306 +
275 307 /* look for the tlb covering the reset page, there better be one */
276   - int i = find_tlb_idx((void *)0xfffff000, 1);
  308 + int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
277 309  
278 310 /* we found a match */
279 311 if (i != -1) {
280 312 /* map reset page to bootpg so we can copy code there */
281 313 disable_tlb(i);
282 314  
283   - set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
284   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
285   - 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
286   -
287   - memcpy((void *)0xfffff000, (void *)fixup, 4096);
288   - flush_cache(0xfffff000, 4096);
289   -
290   - disable_tlb(i);
291   -
292   - /* setup reset page back to 1:1, we'll use HW boot translation
293   - * to map this where we want
294   - */
295   - set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
  315 + set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
296 316 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
297 317 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
  318 +
  319 + memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
298 320  
299 321 plat_mp_up(bootpg);
300 322 } else {
... ... @@ -3,7 +3,8 @@
3 3  
4 4 #include <asm/mp.h>
5 5  
6   -ulong get_spin_addr(void);
  6 +ulong get_spin_phys_addr(void);
  7 +ulong get_spin_virt_addr(void);
7 8 u32 get_my_id(void);
8 9  
9 10 #define BOOT_ENTRY_ADDR_UPPER 0
cpu/mpc85xx/release.S
Diff comments   View file @ 98cecb6
... ... @@ -138,23 +138,38 @@
138 138 stw r3,ENTRY_R6_UPPER(r10)
139 139 stw r3,ENTRY_R6_LOWER(r10)
140 140  
  141 + /* load r13 with the address of the 'bootpg' in SDRAM */
  142 + lis r13,toreset(__bootpg_addr)@h
  143 + ori r13,r13,toreset(__bootpg_addr)@l
  144 + lwz r13,0(r13)
  145 +
141 146 /* setup mapping for AS = 1, and jump there */
142 147 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
143 148 mtspr SPRN_MAS0,r11
144 149 lis r11,(MAS1_VALID|MAS1_IPROT)@h
145 150 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
146 151 mtspr SPRN_MAS1,r11
147   - lis r11,(0xfffff000|MAS2_I)@h
148   - ori r11,r11,(0xfffff000|MAS2_I)@l
  152 + oris r11,r13,(MAS2_I)@h
  153 + ori r11,r13,(MAS2_I)@l
149 154 mtspr SPRN_MAS2,r11
150   - lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
151   - ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
  155 + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
  156 + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
152 157 mtspr SPRN_MAS3,r11
153 158 tlbwe
154 159  
155 160 bl 1f
156 161 1: mflr r11
157   - addi r11,r11,28
  162 + /*
  163 + * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
  164 + * this mask to fixup the cpu spin table and the address that we want
  165 + * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
  166 + * bootpg is at 0x7ffff000 in SDRAM.
  167 + */
  168 + ori r13,r13,0xfff
  169 + and r11, r11, r13
  170 + and r10, r10, r13
  171 +
  172 + addi r11,r11,(2f-1b)
158 173 mfmsr r13
159 174 ori r12,r13,MSR_IS|MSR_DS@l
160 175  
... ... @@ -226,6 +241,15 @@
226 241 */
227 242 mtspr SPRN_SRR1,r13
228 243 rfi
  244 +
  245 + /*
  246 + * Allocate some space for the SDRAM address of the bootpg.
  247 + * This variable has to be in the boot page so that it can
  248 + * be accessed by secondary cores when they come out of reset.
  249 + */
  250 + .globl __bootpg_addr
  251 +__bootpg_addr:
  252 + .long 0
229 253  
230 254 .align L1_CACHE_SHIFT
231 255 .globl __spin_table
... ... @@ -240,8 +240,12 @@
240 240 gd->i2c2_clk = gd->i2c1_clk;
241 241  
242 242 #if defined(CONFIG_FSL_ESDHC)
  243 +#ifdef CONFIG_MPC8569
  244 + gd->sdhc_clk = gd->bus_clk;
  245 +#else
243 246 gd->sdhc_clk = gd->bus_clk / 2;
244 247 #endif
  248 +#endif /* defined(CONFIG_FSL_ESDHC) */
245 249  
246 250 #if defined(CONFIG_CPM2)
247 251 gd->vco_out = 2*sys_info.freqSystemBus;
drivers/pci/fsl_pci_init.c
Diff comments   View file @ 98cecb6
1 1 /*
2   - * Copyright 2007 Freescale Semiconductor, Inc.
  2 + * Copyright 2007-2009 Freescale Semiconductor, Inc.
3 3 *
4 4 * This program is free software; you can redistribute it and/or
5 5 * modify it under the terms of the GNU General Public License
6 6  
... ... @@ -413,12 +413,26 @@
413 413 }
414 414  
415 415 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
416   - struct pci_controller *hose, int busno)
  416 + struct pci_controller *hose, int busno, int pcie_ep)
417 417 {
418 418 volatile ccsr_fsl_pci_t *pci;
419 419 struct pci_region *r;
420 420  
421 421 pci = (ccsr_fsl_pci_t *) pci_info->regs;
  422 +
  423 + if (pcie_ep) {
  424 + volatile pit_t *pi = &pci->pit[2];
  425 +
  426 + pci_setup_indirect(hose, (u32)&pci->cfg_addr,
  427 + (u32)&pci->cfg_data);
  428 + out_be32(&pi->pitar, 0);
  429 + out_be32(&pi->piwbar, 0);
  430 + out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
  431 + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
  432 +
  433 + fsl_pci_config_unlock(hose);
  434 + return 0;
  435 + }
422 436  
423 437 /* on non-PCIe controllers we don't have pme_msg_det so this code
424 438 * should do nothing since the read will return 0
... ... @@ -85,6 +85,8 @@
85 85 "bus-frequency", gd->qe_clk, 1);
86 86 do_fixup_by_compat_u32(blob, "fsl,qe",
87 87 "brg-frequency", gd->brg_clk, 1);
  88 + do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
  89 + "clock-frequency", gd->qe_clk / 2, 1);
88 90 fdt_fixup_qe_firmware(blob);
89 91 #endif
90 92 }
include/asm-ppc/config.h
Diff comments   View file @ 98cecb6
... ... @@ -47,6 +47,16 @@
47 47 #define CONFIG_MAX_CPUS 1
48 48 #endif
49 49  
  50 +/*
  51 + * Provide a default boot page translation virtual address that lines up with
  52 + * Freescale's default e500 reset page.
  53 + */
  54 +#if (defined(CONFIG_E500) && defined(CONFIG_MP))
  55 +#ifndef CONFIG_BPTR_VIRT_ADDR
  56 +#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
  57 +#endif
  58 +#endif
  59 +
50 60 /* Relocation to SDRAM works on all PPC boards */
51 61 #define CONFIG_RELOC_FIXUP_WORKS
52 62  
include/asm-ppc/fsl_pci.h
Diff comments   View file @ 98cecb6
... ... @@ -62,6 +62,7 @@
62 62 #define PIWAR_LOCAL 0x00f00000
63 63 #define PIWAR_READ_SNOOP 0x00050000
64 64 #define PIWAR_WRITE_SNOOP 0x00005000
  65 +#define PIWAR_IWS_4K 0x0000000b
65 66 u32 res2[3];
66 67 } pit_t;
67 68  
... ... @@ -171,7 +172,7 @@
171 172 };
172 173  
173 174 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
174   - struct pci_controller *hose, int busno);
  175 + struct pci_controller *hose, int busno, int pcie_ep);
175 176  
176 177 #define SET_STD_PCI_INFO(x, num) \
177 178 { \
include/configs/MPC8569MDS.h
Diff comments   View file @ 98cecb6
... ... @@ -70,6 +70,7 @@
70 70 #define CONFIG_ENABLE_36BIT_PHYS 1
71 71  
72 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  73 +#define CONFIG_HWCONFIG
73 74  
74 75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
75 76 #define CONFIG_SYS_MEMTEST_END 0x00400000
... ... @@ -180,6 +181,29 @@
180 181 #define CONFIG_SYS_FLASH_CFI
181 182 #define CONFIG_SYS_FLASH_EMPTY_INFO
182 183  
  184 +/* Chip select 3 - NAND */
  185 +#define CONFIG_SYS_NAND_BASE 0xFC000000
  186 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  187 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
  188 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  189 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1
  190 +#define CONFIG_CMD_NAND 1
  191 +#define CONFIG_NAND_FSL_ELBC 1
  192 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  193 +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  194 + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  195 + | BR_PS_8 /* Port Size = 8 bit */ \
  196 + | BR_MS_FCM /* MSEL = FCM */ \
  197 + | BR_V) /* valid */
  198 +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  199 + | OR_FCM_CSCT \
  200 + | OR_FCM_CST \
  201 + | OR_FCM_CHT \
  202 + | OR_FCM_SCY_1 \
  203 + | OR_FCM_TRLX \
  204 + | OR_FCM_EHTR)
  205 +#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  206 +#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
183 207  
184 208 /*
185 209 * SDRAM on the LocalBus
... ... @@ -206,6 +230,7 @@
206 230  
207 231 /* Serial Port */
208 232 #define CONFIG_CONS_INDEX 1
  233 +#define CONFIG_SERIAL_MULTI 1
209 234 #undef CONFIG_SERIAL_SOFTWARE_FIFO
210 235 #define CONFIG_SYS_NS16550
211 236 #define CONFIG_SYS_NS16550_SERIAL
212 237  
... ... @@ -258,8 +283,10 @@
258 283  
259 284 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
260 285 #define PLPPAR1_I2C2_VAL 0x00000000
  286 +#define PLPPAR1_ESDHC_VAL 0x0000000A
261 287 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
262 288 #define PLPDIR1_I2C2_VAL 0x0000000F
  289 +#define PLPDIR1_ESDHC_VAL 0x00000006
263 290  
264 291 /*
265 292 * General PCI
... ... @@ -449,6 +476,18 @@
449 476  
450 477  
451 478 #undef CONFIG_WATCHDOG /* watchdog disabled */
  479 +
  480 +#define CONFIG_MMC 1
  481 +
  482 +#ifdef CONFIG_MMC
  483 +#define CONFIG_FSL_ESDHC
  484 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  485 +#define CONFIG_CMD_MMC
  486 +#define CONFIG_GENERIC_MMC
  487 +#define CONFIG_CMD_EXT2
  488 +#define CONFIG_CMD_FAT
  489 +#define CONFIG_DOS_PARTITION
  490 +#endif
452 491  
453 492 /*
454 493 * Miscellaneous configurable options
include/configs/XPEDITE5370.h
Diff comments   View file @ 98cecb6
... ... @@ -49,6 +49,13 @@
49 49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50 50  
51 51 /*
  52 + * Multicore config
  53 + */
  54 +#define CONFIG_MP
  55 +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
  56 +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
  57 +
  58 +/*
52 59 * DDR config
53 60 */
54 61 #define CONFIG_FSL_DDR2
... ... @@ -109,6 +116,7 @@
109 116 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
110 117 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
111 118 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  119 + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
112 120 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
113 121 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
114 122 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
nand_spl/board/freescale/mpc8536ds/Makefile
Diff comments   View file @ 98cecb6
... ... @@ -111,6 +111,12 @@
111 111 @rm -f $(obj)tlb_table.c
112 112 ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
113 113  
  114 +ifneq ($(OBJTREE), $(SRCTREE))
  115 +$(obj)nand_boot.c:
  116 + @rm -f $(obj)nand_boot.c
  117 + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
  118 +endif
  119 +
114 120 #########################################################################
115 121  
116 122 $(obj)%.o: $(obj)%.S
nand_spl/board/freescale/p1_p2_rdb/Makefile
Diff comments   View file @ 98cecb6
... ... @@ -111,6 +111,12 @@
111 111 @rm -f $(obj)tlb_table.c
112 112 ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
113 113  
  114 +ifneq ($(OBJTREE), $(SRCTREE))
  115 +$(obj)nand_boot.c:
  116 + @rm -f $(obj)nand_boot.c
  117 + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
  118 +endif
  119 +
114 120 #########################################################################
115 121  
116 122 $(obj)%.o: $(obj)%.S
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
Diff comments   View file @ 98cecb6
... ... @@ -41,7 +41,7 @@
41 41  
42 42 void board_init_f(ulong bootflag)
43 43 {
44   - uint plat_ratio, bus_clk, sys_clk;
  44 + uint plat_ratio, bus_clk, sys_clk = 0;
45 45 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 46 volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
47 47 uint val, temp, sysclk_mask;