Eric Lee / smarc-uboot

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Commit 98d2d5e8c473232dc718763dbec284b7349dcc05

Authored by Tom Rini
2 parents 8bd60ccf53 956a8bae53
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-ti

Showing 56 changed files Side-by-side Diff

arch/arm/cpu/armv7/omap-common/boot-common.c
Diff comments   View file @ 98d2d5e
... ... @@ -33,9 +33,20 @@
33 33 * used. But it not correct to assume that romcode structure
34 34 * encoding would be same as u-boot. So use the defined offsets.
35 35 */
36   - gd->arch.omap_boot_params.omap_bootdevice = boot_device =
37   - *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
  36 + boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
38 37  
  38 +#if defined(BOOT_DEVICE_NAND_I2C)
  39 + /*
  40 + * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
  41 + * Otherwise the SPL boot IF can't handle this device correctly.
  42 + * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
  43 + * Draco leads to this boot-device passed to SPL from the BootROM.
  44 + */
  45 + if (boot_device == BOOT_DEVICE_NAND_I2C)
  46 + boot_device = BOOT_DEVICE_NAND;
  47 +#endif
  48 + gd->arch.omap_boot_params.omap_bootdevice = boot_device;
  49 +
39 50 gd->arch.omap_boot_params.ch_flags =
40 51 *((u8 *)(rom_params + CH_FLAGS_OFFSET));
41 52  
... ... @@ -57,7 +68,7 @@
57 68 }
58 69 }
59 70  
60   -#ifdef CONFIG_DRA7XX
  71 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
61 72 /*
62 73 * We get different values for QSPI_1 and QSPI_4 being used, but
63 74 * don't actually care about this difference. Rather than
arch/arm/cpu/armv7/omap-common/emif-common.c
Diff comments   View file @ 98d2d5e
... ... @@ -1226,13 +1226,14 @@
1226 1226 emif1_enabled = 1;
1227 1227 emif2_enabled = 1;
1228 1228 break;
1229   - } else if (valid == 1) {
  1229 + }
  1230 +
  1231 + if (valid == 1)
1230 1232 emif1_enabled = 1;
1231   - } else if (valid == 2) {
  1233 +
  1234 + if (valid == 2)
1232 1235 emif2_enabled = 1;
1233   - }
1234 1236 }
1235   -
1236 1237 }
1237 1238  
1238 1239 static void do_bug0039_workaround(u32 base)
arch/arm/cpu/armv7/omap5/Kconfig
Diff comments   View file @ 98d2d5e
... ... @@ -12,6 +12,9 @@
12 12 config TARGET_DRA7XX_EVM
13 13 bool "TI DRA7XX"
14 14  
  15 +config TARGET_BEAGLE_X15
  16 + bool "BeagleBoard X15"
  17 +
15 18 endchoice
16 19  
17 20 config SYS_SOC
... ... @@ -20,6 +23,7 @@
20 23 source "board/compulab/cm_t54/Kconfig"
21 24 source "board/ti/omap5_uevm/Kconfig"
22 25 source "board/ti/dra7xx/Kconfig"
  26 +source "board/ti/beagle_x15/Kconfig"
23 27  
24 28 endif
arch/arm/cpu/armv7/omap5/hw_data.c
Diff comments   View file @ 98d2d5e
... ... @@ -365,31 +365,31 @@
365 365 .mpu.value = VDD_MPU_DRA752,
366 366 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
367 367 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368   - .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
  368 + .mpu.addr = TPS659038_REG_ADDR_SMPS12,
369 369 .mpu.pmic = &tps659038,
370 370  
371 371 .eve.value = VDD_EVE_DRA752,
372 372 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
373 373 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374   - .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
  374 + .eve.addr = TPS659038_REG_ADDR_SMPS45,
375 375 .eve.pmic = &tps659038,
376 376  
377 377 .gpu.value = VDD_GPU_DRA752,
378 378 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
379 379 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
380   - .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
  380 + .gpu.addr = TPS659038_REG_ADDR_SMPS6,
381 381 .gpu.pmic = &tps659038,
382 382  
383 383 .core.value = VDD_CORE_DRA752,
384 384 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
385 385 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
386   - .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
  386 + .core.addr = TPS659038_REG_ADDR_SMPS7,
387 387 .core.pmic = &tps659038,
388 388  
389 389 .iva.value = VDD_IVA_DRA752,
390 390 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
391 391 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
392   - .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
  392 + .iva.addr = TPS659038_REG_ADDR_SMPS8,
393 393 .iva.pmic = &tps659038,
394 394 };
395 395  
... ... @@ -593,7 +593,7 @@
593 593 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
594 594 };
595 595  
596   -void hw_data_init(void)
  596 +void __weak hw_data_init(void)
597 597 {
598 598 u32 omap_rev = omap_revision();
599 599  
arch/arm/cpu/armv7/omap5/prcm-regs.c
Diff comments   View file @ 98d2d5e
... ... @@ -376,6 +376,7 @@
376 376  
377 377 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
378 378 .control_status = 0x4A002134,
  379 + .control_phy_power_usb = 0x4A002370,
379 380 .control_phy_power_sata = 0x4A002374,
380 381 .control_core_mac_id_0_lo = 0x4A002514,
381 382 .control_core_mac_id_0_hi = 0x4A002518,
... ... @@ -800,6 +801,7 @@
800 801 .cm_clkmode_dpll_dsp = 0x4a005234,
801 802 .cm_shadow_freq_config1 = 0x4a005260,
802 803 .cm_clkmode_dpll_gmac = 0x4a0052a8,
  804 + .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640,
803 805 .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
804 806  
805 807 /* cm1.mpu */
... ... @@ -906,6 +908,7 @@
906 908 .cm_gmac_gmac_clkctrl = 0x4a0093d0,
907 909 .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
908 910 .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
  911 + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
909 912  
910 913 /* cm2.l4per */
911 914 .cm_l4per_clkstctrl = 0x4a009700,
arch/arm/cpu/armv7/omap5/sdram.c
Diff comments   View file @ 98d2d5e
... ... @@ -513,7 +513,7 @@
513 513 .mr16 = MR16_REF_FULL_ARRAY
514 514 };
515 515  
516   -static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
  516 +void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
517 517 const u32 **regs,
518 518 u32 *size)
519 519 {
arch/arm/include/asm/arch-am33xx/spl.h
Diff comments   View file @ 98d2d5e
... ... @@ -25,6 +25,7 @@
25 25 #else
26 26 #define BOOT_DEVICE_XIP 2
27 27 #define BOOT_DEVICE_NAND 5
  28 +#define BOOT_DEVICE_NAND_I2C 6
28 29 #if defined(CONFIG_AM33XX)
29 30 #define BOOT_DEVICE_MMC1 8
30 31 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
arch/arm/include/asm/arch-omap5/clock.h
Diff comments   View file @ 98d2d5e
... ... @@ -278,11 +278,11 @@
278 278  
279 279 /* TPS659038 */
280 280 #define TPS659038_I2C_SLAVE_ADDR 0x58
281   -#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
282   -#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
283   -#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
284   -#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
285   -#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
  281 +#define TPS659038_REG_ADDR_SMPS12 0x23
  282 +#define TPS659038_REG_ADDR_SMPS45 0x2B
  283 +#define TPS659038_REG_ADDR_SMPS6 0x2F
  284 +#define TPS659038_REG_ADDR_SMPS7 0x33
  285 +#define TPS659038_REG_ADDR_SMPS8 0x37
286 286  
287 287 /* TPS */
288 288 #define TPS62361_I2C_SLAVE_ADDR 0x60
... ... @@ -314,7 +314,7 @@
314 314 */
315 315 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
316 316  
317   -#ifdef CONFIG_DRA7XX
  317 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
318 318 #define V_OSCK 20000000 /* Clock output from T2 */
319 319 #else
320 320 #define V_OSCK 19200000 /* Clock output from T2 */
arch/arm/include/asm/arch-omap5/omap.h
Diff comments   View file @ 98d2d5e
... ... @@ -27,7 +27,7 @@
27 27 #define CONTROL_CORE_ID_CODE 0x4A002204
28 28 #define CONTROL_WKUP_ID_CODE 0x4AE0C204
29 29  
30   -#ifdef CONFIG_DRA7XX
  30 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
31 31 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
32 32 #else
33 33 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
... ... @@ -163,7 +163,7 @@
163 163 * much larger) and do not, at this time, make use of the additional
164 164 * space.
165 165 */
166   -#ifdef CONFIG_DRA7XX
  166 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
167 167 #define NON_SECURE_SRAM_START 0x40300000
168 168 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
169 169 #else
arch/arm/include/asm/omap_common.h
Diff comments   View file @ 98d2d5e
... ... @@ -540,12 +540,15 @@
540 540 extern struct prcm_regs const omap4_prcm;
541 541 extern struct prcm_regs const dra7xx_prcm;
542 542 extern struct dplls const **dplls_data;
  543 +extern struct dplls dra7xx_dplls;
543 544 extern struct vcores_data const **omap_vcores;
544 545 extern const u32 sys_clk_array[8];
545 546 extern struct omap_sys_ctrl_regs const **ctrl;
546 547 extern struct omap_sys_ctrl_regs const omap4_ctrl;
547 548 extern struct omap_sys_ctrl_regs const omap5_ctrl;
548 549 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
  550 +
  551 +extern struct pmic_data tps659038;
549 552  
550 553 void hw_data_init(void);
551 554  
board/comelit/dig297/dig297.c
Diff comments   View file @ 98d2d5e
... ... @@ -133,6 +133,11 @@
133 133 {
134 134 return omap_mmc_init(0, 0, 0, -1, -1);
135 135 }
  136 +
  137 +void board_mmc_power_init(void)
  138 +{
  139 + twl4030_power_mmc_init(0);
  140 +}
136 141 #endif
137 142  
138 143 #ifdef CONFIG_CMD_NET
board/compulab/cm_t35/cm_t35.c
Diff comments   View file @ 98d2d5e
... ... @@ -382,6 +382,13 @@
382 382 }
383 383 #endif
384 384  
  385 +#if defined(CONFIG_GENERIC_MMC)
  386 +void board_mmc_power_init(void)
  387 +{
  388 + twl4030_power_mmc_init(0);
  389 +}
  390 +#endif
  391 +
385 392 #ifdef CONFIG_SYS_I2C_OMAP34XX
386 393 /*
387 394 * Routine: reset_net_chip
board/corscience/tricorder/tricorder.c
Diff comments   View file @ 98d2d5e
... ... @@ -147,6 +147,13 @@
147 147 }
148 148 #endif
149 149  
  150 +#if defined(CONFIG_GENERIC_MMC)
  151 +void board_mmc_power_init(void)
  152 +{
  153 + twl4030_power_mmc_init(0);
  154 +}
  155 +#endif
  156 +
150 157 /*
151 158 * Routine: get_board_mem_timings
152 159 * Description: If we use SPL then there is no x-loader nor config header
board/isee/igep00x0/igep00x0.c
Diff comments   View file @ 98d2d5e
... ... @@ -150,6 +150,13 @@
150 150 }
151 151 #endif
152 152  
  153 +#if defined(CONFIG_GENERIC_MMC)
  154 +void board_mmc_power_init(void)
  155 +{
  156 + twl4030_power_mmc_init(0);
  157 +}
  158 +#endif
  159 +
153 160 void set_fdt(void)
154 161 {
155 162 switch (gd->bd->bi_arch_number) {
board/logicpd/omap3som/omap3logic.c
Diff comments   View file @ 98d2d5e
... ... @@ -128,6 +128,13 @@
128 128 }
129 129 #endif
130 130  
  131 +#if defined(CONFIG_GENERIC_MMC)
  132 +void board_mmc_power_init(void)
  133 +{
  134 + twl4030_power_mmc_init(0);
  135 +}
  136 +#endif
  137 +
131 138 #ifdef CONFIG_SMC911X
132 139 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
133 140 static const u32 gpmc_lan92xx_config[] = {
board/logicpd/zoom1/zoom1.c
Diff comments   View file @ 98d2d5e
... ... @@ -109,6 +109,11 @@
109 109 {
110 110 return omap_mmc_init(0, 0, 0, -1, -1);
111 111 }
  112 +
  113 +void board_mmc_power_init(void)
  114 +{
  115 + twl4030_power_mmc_init(0);
  116 +}
112 117 #endif
113 118  
114 119 #ifdef CONFIG_CMD_NET
board/matrix_vision/mvblx/mvblx.c
Diff comments   View file @ 98d2d5e
... ... @@ -94,6 +94,12 @@
94 94 omap_mmc_init(1, 0, 0, -1, -1);
95 95 return 0;
96 96 }
  97 +
  98 +void board_mmc_power_init(void)
  99 +{
  100 + twl4030_power_mmc_init(0);
  101 + twl4030_power_mmc_init(1);
  102 +}
97 103 #endif
98 104  
99 105 #if defined(CONFIG_CMD_NET)
board/nokia/rx51/rx51.c
Diff comments   View file @ 98d2d5e
... ... @@ -659,4 +659,10 @@
659 659 omap_mmc_init(1, 0, 0, -1, -1);
660 660 return 0;
661 661 }
  662 +
  663 +void board_mmc_power_init(void)
  664 +{
  665 + twl4030_power_mmc_init(0);
  666 + twl4030_power_mmc_init(1);
  667 +}
... ... @@ -493,6 +493,13 @@
493 493 }
494 494 #endif
495 495  
  496 +#if defined(CONFIG_GENERIC_MMC)
  497 +void board_mmc_power_init(void)
  498 +{
  499 + twl4030_power_mmc_init(0);
  500 +}
  501 +#endif
  502 +
496 503 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
497 504 static struct omap_usbhs_board_data usbhs_bdata = {
498 505 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
board/pandora/pandora.c
Diff comments   View file @ 98d2d5e
... ... @@ -126,5 +126,10 @@
126 126 {
127 127 return omap_mmc_init(0, 0, 0, -1, -1);
128 128 }
  129 +
  130 +void board_mmc_power_init(void)
  131 +{
  132 + twl4030_power_mmc_init(0);
  133 +}
129 134 #endif
board/siemens/common/board.c
Diff comments   View file @ 98d2d5e
... ... @@ -96,15 +96,6 @@
96 96 return &dpll_ddr;
97 97 }
98 98  
99   -#ifdef CONFIG_BOARD_LATE_INIT
100   -int board_late_init(void)
101   -{
102   - omap_nand_switch_ecc(1, 8);
103   -
104   - return 0;
105   -}
106   -#endif
107   -
108 99 #ifndef CONFIG_SPL_BUILD
109 100 #if defined(BOARD_DFU_BUTTON_GPIO)
110 101 /*
board/siemens/common/factoryset.c
Diff comments   View file @ 98d2d5e
... ... @@ -86,6 +86,7 @@
86 86 int i, nxt = 0;
87 87 int c;
88 88 unsigned char end = 0xff;
  89 + unsigned char tmp;
89 90  
90 91 for (i = 0; fact_get_char(i) != end; i = nxt) {
91 92 nxt = i + 1;
... ... @@ -93,6 +94,7 @@
93 94 int pos;
94 95 int endpos;
95 96 int z;
  97 + int level = 0;
96 98  
97 99 c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
98 100 strlen((char *)record));
99 101  
100 102  
101 103  
102 104  
103 105  
... ... @@ -103,22 +105,30 @@
103 105 /* search for "<" */
104 106 c = -1;
105 107 for (z = pos; fact_get_char(z) != end; z++) {
106   - if ((fact_get_char(z) == '<') ||
107   - (fact_get_char(z) == '>')) {
108   - endpos = z;
109   - nxt = endpos;
110   - c = 0;
111   - break;
  108 + if (fact_get_char(z) == '<') {
  109 + if (level == 0) {
  110 + endpos = z;
  111 + nxt = endpos;
  112 + c = 0;
  113 + break;
  114 + } else {
  115 + level--;
  116 + }
112 117 }
  118 + if (fact_get_char(z) == '>')
  119 + level++;
113 120 }
  121 + } else {
  122 + continue;
114 123 }
115 124 if (c == 0) {
116 125 /* end found -> call get_factory_val */
  126 + tmp = eeprom_buf[endpos];
117 127 eeprom_buf[endpos] = end;
118 128 ret = get_factory_val(&eeprom_buf[pos],
119   - size - pos, name, buf, len);
  129 + endpos - pos, name, buf, len);
120 130 /* fix buffer */
121   - eeprom_buf[endpos] = '<';
  131 + eeprom_buf[endpos] = tmp;
122 132 debug("%s: %s.%s = %s\n",
123 133 __func__, record, name, buf);
124 134 return ret;
... ... @@ -210,15 +220,6 @@
210 220 printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
211 221 factory_dat.usb_product_id);
212 222 #endif
213   - if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
214   - (uchar *)"id", buf,
215   - MAX_STRING_LENGTH)) {
216   - if (strncmp((const char *)buf, "PXM50", 5) == 0)
217   - factory_dat.pxm50 = 1;
218   - else
219   - factory_dat.pxm50 = 0;
220   - }
221   - debug("PXM50: %d\n", factory_dat.pxm50);
222 223 #if defined(CONFIG_VIDEO)
223 224 if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
224 225 (uchar *)"name", factory_dat.disp_name,
... ... @@ -237,6 +238,23 @@
237 238 factory_dat.version = simple_strtoul((char *)buf,
238 239 NULL, 16);
239 240 debug("version number: %d\n", factory_dat.version);
  241 + }
  242 + /* Get ASN from factory set if available */
  243 + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
  244 + (uchar *)"id", factory_dat.asn,
  245 + MAX_STRING_LENGTH)) {
  246 + debug("factoryset asn: %s\n", factory_dat.asn);
  247 + } else {
  248 + factory_dat.asn[0] = 0;
  249 + }
  250 + /* Get COMP/ver from factory set if available */
  251 + if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
  252 + (uchar *)"ver",
  253 + factory_dat.comp_version,
  254 + MAX_STRING_LENGTH)) {
  255 + debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
  256 + } else {
  257 + strcpy((char *)factory_dat.comp_version, "1.0");
240 258 }
241 259  
242 260 return 0;
board/siemens/common/factoryset.h
Diff comments   View file @ 98d2d5e
... ... @@ -20,6 +20,8 @@
20 20 #endif
21 21 unsigned char serial[MAX_STRING_LENGTH];
22 22 int version;
  23 + uchar asn[MAX_STRING_LENGTH];
  24 + uchar comp_version[MAX_STRING_LENGTH];
23 25 };
24 26  
25 27 int factoryset_read_eeprom(int i2c_addr);
board/siemens/draco/board.c
Diff comments   View file @ 98d2d5e
... ... @@ -280,5 +280,14 @@
280 280 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
281 281 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
282 282  
  283 +#ifdef CONFIG_BOARD_LATE_INIT
  284 +int board_late_init(void)
  285 +{
  286 + omap_nand_switch_ecc(1, 8);
  287 +
  288 + return 0;
  289 +}
  290 +#endif
  291 +
283 292 #include "../common/board.c"
board/siemens/pxm2/board.c
Diff comments   View file @ 98d2d5e
... ... @@ -428,5 +428,39 @@
428 428 return 0;
429 429 }
430 430 #endif
  431 +
  432 +#ifdef CONFIG_BOARD_LATE_INIT
  433 +int board_late_init(void)
  434 +{
  435 + int ret;
  436 +
  437 + omap_nand_switch_ecc(1, 8);
  438 +
  439 +#ifdef CONFIG_FACTORYSET
  440 + if (factory_dat.asn[0] != 0) {
  441 + char tmp[2 * MAX_STRING_LENGTH + 2];
  442 +
  443 + if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
  444 + factory_dat.pxm50 = 1;
  445 + else
  446 + factory_dat.pxm50 = 0;
  447 + sprintf(tmp, "%s_%s", factory_dat.asn,
  448 + factory_dat.comp_version);
  449 + ret = setenv("boardid", tmp);
  450 + if (ret)
  451 + printf("error setting board id\n");
  452 + } else {
  453 + factory_dat.pxm50 = 1;
  454 + ret = setenv("boardid", "PXM50_1.0");
  455 + if (ret)
  456 + printf("error setting board id\n");
  457 + }
  458 + debug("PXM50: %d\n", factory_dat.pxm50);
  459 +#endif
  460 +
  461 + return 0;
  462 +}
  463 +#endif
  464 +
431 465 #include "../common/board.c"
board/siemens/rut/board.c
Diff comments   View file @ 98d2d5e
... ... @@ -467,5 +467,28 @@
467 467 return 0;
468 468 }
469 469 #endif /* ifdef CONFIG_VIDEO */
  470 +
  471 +#ifdef CONFIG_BOARD_LATE_INIT
  472 +int board_late_init(void)
  473 +{
  474 + int ret;
  475 + char tmp[2 * MAX_STRING_LENGTH + 2];
  476 +
  477 + omap_nand_switch_ecc(1, 8);
  478 +
  479 + if (factory_dat.asn[0] != 0)
  480 + sprintf(tmp, "%s_%s", factory_dat.asn,
  481 + factory_dat.comp_version);
  482 + else
  483 + sprintf(tmp, "QMX7.E38_4.0");
  484 +
  485 + ret = setenv("boardid", tmp);
  486 + if (ret)
  487 + printf("error setting board id\n");
  488 +
  489 + return 0;
  490 +}
  491 +#endif
  492 +
470 493 #include "../common/board.c"
board/technexion/tao3530/tao3530.c
Diff comments   View file @ 98d2d5e
... ... @@ -188,6 +188,13 @@
188 188 }
189 189 #endif
190 190  
  191 +#if defined(CONFIG_GENERIC_MMC)
  192 +void board_mmc_power_init(void)
  193 +{
  194 + twl4030_power_mmc_init(0);
  195 +}
  196 +#endif
  197 +
191 198 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
192 199 /* Call usb_stop() before starting the kernel */
193 200 void show_boot_progress(int val)
board/ti/beagle/beagle.c
Diff comments   View file @ 98d2d5e
... ... @@ -534,6 +534,13 @@
534 534 }
535 535 #endif
536 536  
  537 +#if defined(CONFIG_GENERIC_MMC)
  538 +void board_mmc_power_init(void)
  539 +{
  540 + twl4030_power_mmc_init(0);
  541 +}
  542 +#endif
  543 +
537 544 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
538 545 /* Call usb_stop() before starting the kernel */
539 546 void show_boot_progress(int val)
board/ti/beagle_x15/Kconfig
Diff comments   View file @ 98d2d5e
  1 +if TARGET_BEAGLE_X15
  2 +
  3 +config SYS_BOARD
  4 + default "beagle_x15"
  5 +
  6 +config SYS_VENDOR
  7 + default "ti"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "beagle_x15"
  11 +
  12 +endif
board/ti/beagle_x15/Makefile
Diff comments   View file @ 98d2d5e
  1 +#
  2 +# (C) Copyright 2014
  3 +# Texas Instruments, <www.ti.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := board.o
board/ti/beagle_x15/board.c
Diff comments   View file @ 98d2d5e
  1 +/*
  2 + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  3 + *
  4 + * Author: Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Based on board/ti/dra7xx/evm.c
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <palmas.h>
  13 +#include <sata.h>
  14 +#include <usb.h>
  15 +#include <asm/omap_common.h>
  16 +#include <asm/emif.h>
  17 +#include <asm/arch/clock.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/arch/mmc_host_def.h>
  20 +#include <asm/arch/sata.h>
  21 +#include <asm/arch/gpio.h>
  22 +#include <environment.h>
  23 +
  24 +#include "mux_data.h"
  25 +
  26 +#ifdef CONFIG_DRIVER_TI_CPSW
  27 +#include <cpsw.h>
  28 +#endif
  29 +
  30 +DECLARE_GLOBAL_DATA_PTR;
  31 +
  32 +const struct omap_sysinfo sysinfo = {
  33 + "Board: BeagleBoard x15\n"
  34 +};
  35 +
  36 +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  37 + .dmm_lisa_map_3 = 0x80740300,
  38 + .is_ma_present = 0x1
  39 +};
  40 +
  41 +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  42 +{
  43 + *dmm_lisa_regs = &beagle_x15_lisa_regs;
  44 +}
  45 +
  46 +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  47 + .sdram_config_init = 0x61851b32,
  48 + .sdram_config = 0x61851b32,
  49 + .sdram_config2 = 0x00000000,
  50 + .ref_ctrl = 0x00001035,
  51 + .sdram_tim1 = 0xceef266b,
  52 + .sdram_tim2 = 0x328f7fda,
  53 + .sdram_tim3 = 0x027f88a8,
  54 + .read_idle_ctrl = 0x00050001,
  55 + .zq_config = 0x0007190b,
  56 + .temp_alert_config = 0x00000000,
  57 + .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
  58 + .emif_ddr_phy_ctlr_1 = 0x0e24400a,
  59 + .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  60 + .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  61 + .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  62 + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  63 + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  64 + .emif_rd_wr_lvl_rmp_win = 0x00000000,
  65 + .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  66 + .emif_rd_wr_lvl_ctl = 0x00000000,
  67 + .emif_rd_wr_exec_thresh = 0x00000305
  68 +};
  69 +
  70 +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  71 + 0x00800080,
  72 + 0x00360036,
  73 + 0x00340034,
  74 + 0x00360036,
  75 + 0x00350035,
  76 + 0x00350035,
  77 +
  78 + 0x01ff01ff,
  79 + 0x01ff01ff,
  80 + 0x01ff01ff,
  81 + 0x01ff01ff,
  82 + 0x01ff01ff,
  83 +
  84 + 0x00430043,
  85 + 0x003e003e,
  86 + 0x004a004a,
  87 + 0x00470047,
  88 + 0x00400040,
  89 +
  90 + 0x00000000,
  91 + 0x00600020,
  92 + 0x40010080,
  93 + 0x08102040,
  94 +
  95 + 0x00400040,
  96 + 0x00400040,
  97 + 0x00400040,
  98 + 0x00400040,
  99 + 0x00400040
  100 +};
  101 +
  102 +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  103 + .sdram_config_init = 0x61851b32,
  104 + .sdram_config = 0x61851b32,
  105 + .sdram_config2 = 0x00000000,
  106 + .ref_ctrl = 0x00001035,
  107 + .sdram_tim1 = 0xceef266b,
  108 + .sdram_tim2 = 0x328f7fda,
  109 + .sdram_tim3 = 0x027f88a8,
  110 + .read_idle_ctrl = 0x00050001,
  111 + .zq_config = 0x0007190b,
  112 + .temp_alert_config = 0x00000000,
  113 + .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
  114 + .emif_ddr_phy_ctlr_1 = 0x0e24400a,
  115 + .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  116 + .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
  117 + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
  118 + .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
  119 + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
  120 + .emif_rd_wr_lvl_rmp_win = 0x00000000,
  121 + .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  122 + .emif_rd_wr_lvl_ctl = 0x00000000,
  123 + .emif_rd_wr_exec_thresh = 0x00000305
  124 +};
  125 +
  126 +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  127 + 0x00800080,
  128 + 0x00370037,
  129 + 0x00390039,
  130 + 0x00360036,
  131 + 0x00370037,
  132 + 0x00350035,
  133 + 0x01ff01ff,
  134 + 0x01ff01ff,
  135 + 0x01ff01ff,
  136 + 0x01ff01ff,
  137 + 0x01ff01ff,
  138 + 0x00540054,
  139 + 0x00540054,
  140 + 0x004e004e,
  141 + 0x004c004c,
  142 + 0x00400040,
  143 +
  144 + 0x00000000,
  145 + 0x00600020,
  146 + 0x40010080,
  147 + 0x08102040,
  148 +
  149 + 0x00400040,
  150 + 0x00400040,
  151 + 0x00400040,
  152 + 0x00400040,
  153 + 0x00400040
  154 +};
  155 +
  156 +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  157 +{
  158 + switch (emif_nr) {
  159 + case 1:
  160 + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  161 + break;
  162 + case 2:
  163 + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  164 + break;
  165 + }
  166 +}
  167 +
  168 +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  169 +{
  170 + switch (emif_nr) {
  171 + case 1:
  172 + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  173 + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  174 + break;
  175 + case 2:
  176 + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  177 + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  178 + break;
  179 + }
  180 +}
  181 +
  182 +struct vcores_data beagle_x15_volts = {
  183 + .mpu.value = VDD_MPU_DRA752,
  184 + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
  185 + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  186 + .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  187 + .mpu.pmic = &tps659038,
  188 +
  189 + .eve.value = VDD_EVE_DRA752,
  190 + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  191 + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  192 + .eve.addr = TPS659038_REG_ADDR_SMPS45,
  193 + .eve.pmic = &tps659038,
  194 +
  195 + .gpu.value = VDD_GPU_DRA752,
  196 + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
  197 + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  198 + .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  199 + .gpu.pmic = &tps659038,
  200 +
  201 + .core.value = VDD_CORE_DRA752,
  202 + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
  203 + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  204 + .core.addr = TPS659038_REG_ADDR_SMPS6,
  205 + .core.pmic = &tps659038,
  206 +
  207 + .iva.value = VDD_IVA_DRA752,
  208 + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
  209 + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  210 + .iva.addr = TPS659038_REG_ADDR_SMPS45,
  211 + .iva.pmic = &tps659038,
  212 +};
  213 +
  214 +void hw_data_init(void)
  215 +{
  216 + *prcm = &dra7xx_prcm;
  217 + *dplls_data = &dra7xx_dplls;
  218 + *omap_vcores = &beagle_x15_volts;
  219 + *ctrl = &dra7xx_ctrl;
  220 +}
  221 +
  222 +int board_init(void)
  223 +{
  224 + gpmc_init();
  225 + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  226 +
  227 + return 0;
  228 +}
  229 +
  230 +int board_late_init(void)
  231 +{
  232 + init_sata(0);
  233 + /*
  234 + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  235 + * This is the POWERHOLD-in-Low behavior.
  236 + */
  237 + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  238 + return 0;
  239 +}
  240 +
  241 +static void do_set_mux32(u32 base,
  242 + struct pad_conf_entry const *array, int size)
  243 +{
  244 + int i;
  245 + struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  246 +
  247 + for (i = 0; i < size; i++, pad++)
  248 + writel(pad->val, base + pad->offset);
  249 +}
  250 +
  251 +void set_muxconf_regs_essential(void)
  252 +{
  253 + do_set_mux32((*ctrl)->control_padconf_core_base,
  254 + core_padconf_array_essential,
  255 + sizeof(core_padconf_array_essential) /
  256 + sizeof(struct pad_conf_entry));
  257 +}
  258 +
  259 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
  260 +int board_mmc_init(bd_t *bis)
  261 +{
  262 + omap_mmc_init(0, 0, 0, -1, -1);
  263 + omap_mmc_init(1, 0, 0, -1, -1);
  264 + return 0;
  265 +}
  266 +#endif
  267 +
  268 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  269 +int spl_start_uboot(void)
  270 +{
  271 + /* break into full u-boot on 'c' */
  272 + if (serial_tstc() && serial_getc() == 'c')
  273 + return 1;
  274 +
  275 +#ifdef CONFIG_SPL_ENV_SUPPORT
  276 + env_init();
  277 + env_relocate_spec();
  278 + if (getenv_yesno("boot_os") != 1)
  279 + return 1;
  280 +#endif
  281 +
  282 + return 0;
  283 +}
  284 +#endif
  285 +
  286 +#ifdef CONFIG_DRIVER_TI_CPSW
  287 +
  288 +/* Delay value to add to calibrated value */
  289 +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  290 +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  291 +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  292 +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  293 +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  294 +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  295 +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  296 +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  297 +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  298 +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  299 +
  300 +static void cpsw_control(int enabled)
  301 +{
  302 + /* VTP can be added here */
  303 +}
  304 +
  305 +static struct cpsw_slave_data cpsw_slaves[] = {
  306 + {
  307 + .slave_reg_ofs = 0x208,
  308 + .sliver_reg_ofs = 0xd80,
  309 + .phy_addr = 1,
  310 + },
  311 + {
  312 + .slave_reg_ofs = 0x308,
  313 + .sliver_reg_ofs = 0xdc0,
  314 + .phy_addr = 2,
  315 + },
  316 +};
  317 +
  318 +static struct cpsw_platform_data cpsw_data = {
  319 + .mdio_base = CPSW_MDIO_BASE,
  320 + .cpsw_base = CPSW_BASE,
  321 + .mdio_div = 0xff,
  322 + .channels = 8,
  323 + .cpdma_reg_ofs = 0x800,
  324 + .slaves = 1,
  325 + .slave_data = cpsw_slaves,
  326 + .ale_reg_ofs = 0xd00,
  327 + .ale_entries = 1024,
  328 + .host_port_reg_ofs = 0x108,
  329 + .hw_stats_reg_ofs = 0x900,
  330 + .bd_ram_ofs = 0x2000,
  331 + .mac_control = (1 << 5),
  332 + .control = cpsw_control,
  333 + .host_port_num = 0,
  334 + .version = CPSW_CTRL_VERSION_2,
  335 +};
  336 +
  337 +int board_eth_init(bd_t *bis)
  338 +{
  339 + int ret;
  340 + uint8_t mac_addr[6];
  341 + uint32_t mac_hi, mac_lo;
  342 + uint32_t ctrl_val;
  343 +
  344 + /* try reading mac address from efuse */
  345 + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  346 + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  347 + mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  348 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  349 + mac_addr[2] = mac_hi & 0xFF;
  350 + mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  351 + mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  352 + mac_addr[5] = mac_lo & 0xFF;
  353 +
  354 + if (!getenv("ethaddr")) {
  355 + printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  356 +
  357 + if (is_valid_ether_addr(mac_addr))
  358 + eth_setenv_enetaddr("ethaddr", mac_addr);
  359 + }
  360 +
  361 + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  362 + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  363 + mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  364 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  365 + mac_addr[2] = mac_hi & 0xFF;
  366 + mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  367 + mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  368 + mac_addr[5] = mac_lo & 0xFF;
  369 +
  370 + if (!getenv("eth1addr")) {
  371 + if (is_valid_ether_addr(mac_addr))
  372 + eth_setenv_enetaddr("eth1addr", mac_addr);
  373 + }
  374 +
  375 + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  376 + ctrl_val |= 0x22;
  377 + writel(ctrl_val, (*ctrl)->control_core_control_io1);
  378 +
  379 + ret = cpsw_register(&cpsw_data);
  380 + if (ret < 0)
  381 + printf("Error %d registering CPSW switch\n", ret);
  382 +
  383 + return ret;
  384 +}
  385 +#endif
  386 +
  387 +#ifdef CONFIG_USB_XHCI_OMAP
  388 +int board_usb_init(int index, enum usb_init_type init)
  389 +{
  390 + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
  391 + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
  392 +
  393 + return 0;
  394 +}
  395 +#endif
board/ti/beagle_x15/mux_data.h
Diff comments   View file @ 98d2d5e
  1 +/*
  2 + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  3 + *
  4 + * Author: Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Based on board/ti/dra7xx/evm.c
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +#ifndef _MUX_DATA_BEAGLE_X15_H_
  11 +#define _MUX_DATA_BEAGLE_X15_H_
  12 +
  13 +#include <asm/arch/mux_dra7xx.h>
  14 +
  15 +const struct pad_conf_entry core_padconf_array_essential[] = {
  16 + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
  17 + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
  18 + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
  19 + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
  20 + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
  21 + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
  22 + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
  23 + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
  24 + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
  25 + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
  26 + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
  27 + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
  28 + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
  29 + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
  30 + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
  31 + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
  32 + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
  33 + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
  34 + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
  35 + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
  36 + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
  37 + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
  38 + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
  39 + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
  40 + {RGMII0_TXC, (M0) },
  41 + {RGMII0_TXCTL, (M0) },
  42 + {RGMII0_TXD3, (M0) },
  43 + {RGMII0_TXD2, (M0) },
  44 + {RGMII0_TXD1, (M0) },
  45 + {RGMII0_TXD0, (M0) },
  46 + {RGMII0_RXC, (IEN | M0) },
  47 + {RGMII0_RXCTL, (IEN | M0) },
  48 + {RGMII0_RXD3, (IEN | M0) },
  49 + {RGMII0_RXD2, (IEN | M0) },
  50 + {RGMII0_RXD1, (IEN | M0) },
  51 + {RGMII0_RXD0, (IEN | M0) },
  52 + {USB1_DRVVBUS, (M0 | FSC) },
  53 + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
  54 +};
  55 +#endif /* _MUX_DATA_BEAGLE_X15_H_ */
board/ti/dra7xx/evm.c
Diff comments   View file @ 98d2d5e
... ... @@ -96,18 +96,6 @@
96 96 return 0;
97 97 }
98 98  
99   -/**
100   - * @brief misc_init_r - Configure EVM board specific configurations
101   - * such as power configurations, ethernet initialization as phase2 of
102   - * boot sequence
103   - *
104   - * @return 0
105   - */
106   -int misc_init_r(void)
107   -{
108   - return 0;
109   -}
110   -
111 99 static void do_set_mux32(u32 base,
112 100 struct pad_conf_entry const *array, int size)
113 101 {
board/ti/dra7xx/mux_data.h
Diff comments   View file @ 98d2d5e
... ... @@ -130,8 +130,8 @@
130 130 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
131 131 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
132 132 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
133   - {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
134   - {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
  133 + {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
  134 + {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
135 135 {GPMC_A18, (M1)}, /* QSPI1_SCLK */
136 136 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
137 137 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
... ... @@ -20,6 +20,7 @@
20 20 #include <asm/arch/mmc_host_def.h>
21 21 #include <asm/gpio.h>
22 22 #include <i2c.h>
  23 +#include <twl4030.h>
23 24 #include <asm/mach-types.h>
24 25 #include <linux/mtd/nand.h>
25 26 #include "evm.h"
... ... @@ -262,6 +263,13 @@
262 263 int board_mmc_init(bd_t *bis)
263 264 {
264 265 return omap_mmc_init(0, 0, 0, -1, -1);
  266 +}
  267 +#endif
  268 +
  269 +#if defined(CONFIG_GENERIC_MMC)
  270 +void board_mmc_power_init(void)
  271 +{
  272 + twl4030_power_mmc_init(0);
265 273 }
266 274 #endif
board/ti/sdp3430/sdp.c
Diff comments   View file @ 98d2d5e
... ... @@ -195,5 +195,10 @@
195 195 {
196 196 return omap_mmc_init(0, 0, 0, -1, -1);
197 197 }
  198 +
  199 +void board_mmc_power_init(void)
  200 +{
  201 + twl4030_power_mmc_init(0);
  202 +}
198 203 #endif
board/timll/devkit8000/devkit8000.c
Diff comments   View file @ 98d2d5e
... ... @@ -124,6 +124,13 @@
124 124 }
125 125 #endif
126 126  
  127 +#if defined(CONFIG_GENERIC_MMC)
  128 +void board_mmc_power_init(void)
  129 +{
  130 + twl4030_power_mmc_init(0);
  131 +}
  132 +#endif
  133 +
127 134 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
128 135 /*
129 136 * Routine: board_eth_init
configs/beagle_x15_defconfig
Diff comments   View file @ 98d2d5e
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
  3 ++S:CONFIG_ARM=y
  4 ++S:CONFIG_OMAP54XX=y
  5 ++S:CONFIG_TARGET_BEAGLE_X15=y
... ... @@ -1277,6 +1277,11 @@
1277 1277 }
1278 1278 #endif
1279 1279  
  1280 +/* board-specific MMC power initializations. */
  1281 +__weak void board_mmc_power_init(void)
  1282 +{
  1283 +}
  1284 +
1280 1285 int mmc_start_init(struct mmc *mmc)
1281 1286 {
1282 1287 int err;
... ... @@ -1292,6 +1297,8 @@
1292 1297  
1293 1298 if (mmc->has_init)
1294 1299 return 0;
  1300 +
  1301 + board_mmc_power_init();
1295 1302  
1296 1303 /* made sure it's not NULL earlier */
1297 1304 err = mmc->cfg->ops->init(mmc);
drivers/mmc/omap_hsmmc.c
Diff comments   View file @ 98d2d5e
... ... @@ -135,12 +135,7 @@
135 135 pbias_lite = readl(&t2_base->pbias_lite);
136 136 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
137 137 writel(pbias_lite, &t2_base->pbias_lite);
138   -#endif
139   -#if defined(CONFIG_TWL4030_POWER)
140   - twl4030_power_mmc_init();
141   - mdelay(100); /* ramp-up delay from Linux code */
142   -#endif
143   -#if defined(CONFIG_OMAP34XX)
  138 +
144 139 writel(pbias_lite | PBIASLITEPWRDNZ1 |
145 140 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
146 141 &t2_base->pbias_lite);
... ... @@ -663,7 +658,8 @@
663 658 case 1:
664 659 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
665 660 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
666   - defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
  661 + defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
  662 + defined(CONFIG_HSMMC2_8BIT)
667 663 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
668 664 host_caps_val |= MMC_MODE_8BIT;
669 665 #endif
... ... @@ -672,7 +668,7 @@
672 668 #ifdef OMAP_HSMMC3_BASE
673 669 case 2:
674 670 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
675   -#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
  671 +#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
676 672 /* Enable 8-bit interface for eMMC on DRA7XX */
677 673 host_caps_val |= MMC_MODE_8BIT;
678 674 #endif
drivers/mtd/nand/omap_gpmc.c
Diff comments   View file @ 98d2d5e
... ... @@ -73,15 +73,12 @@
73 73 writeb(cmd, this->IO_ADDR_W);
74 74 }
75 75  
76   -#ifdef CONFIG_SPL_BUILD
77 76 /* Check wait pin as dev ready indicator */
78   -static int omap_spl_dev_ready(struct mtd_info *mtd)
  77 +static int omap_dev_ready(struct mtd_info *mtd)
79 78 {
80 79 return gpmc_cfg->status & (1 << 8);
81 80 }
82   -#endif
83 81  
84   -
85 82 /*
86 83 * gen_true_ecc - This function will generate true ECC value, which
87 84 * can be used when correcting data read from NAND flash memory core
88 85  
... ... @@ -887,8 +884,10 @@
887 884 nand->read_buf = nand_read_buf16;
888 885 else
889 886 nand->read_buf = nand_read_buf;
890   - nand->dev_ready = omap_spl_dev_ready;
891 887 #endif
  888 +
  889 + nand->dev_ready = omap_dev_ready;
  890 +
892 891 return 0;
893 892 }
drivers/power/palmas.c
Diff comments   View file @ 98d2d5e
... ... @@ -27,7 +27,7 @@
27 27 {
28 28 u8 val = 0;
29 29  
30   -#if defined(CONFIG_DRA7XX)
  30 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
31 31 /*
32 32 * Currently valid for the dra7xx_evm board:
33 33 * Set TPS659038 LDO1 to 3.0 V
drivers/power/twl4030.c
Diff comments   View file @ 98d2d5e
... ... @@ -91,18 +91,24 @@
91 91 TWL4030_PM_RECEIVER_DEV_GRP_P1);
92 92 }
93 93  
94   -void twl4030_power_mmc_init(void)
  94 +void twl4030_power_mmc_init(int dev_index)
95 95 {
96   - /* Set VMMC1 to 3.15 Volts */
97   - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
98   - TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
99   - TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
100   - TWL4030_PM_RECEIVER_DEV_GRP_P1);
  96 + if (dev_index == 0) {
  97 + /* Set VMMC1 to 3.15 Volts */
  98 + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
  99 + TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
  100 + TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
  101 + TWL4030_PM_RECEIVER_DEV_GRP_P1);
101 102  
102   - /* Set VMMC2 to 3.15 Volts */
103   - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
104   - TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
105   - TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
106   - TWL4030_PM_RECEIVER_DEV_GRP_P1);
  103 + mdelay(100); /* ramp-up delay from Linux code */
  104 + } else if (dev_index == 1) {
  105 + /* Set VMMC2 to 3.15 Volts */
  106 + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
  107 + TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
  108 + TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
  109 + TWL4030_PM_RECEIVER_DEV_GRP_P1);
  110 +
  111 + mdelay(100); /* ramp-up delay from Linux code */
  112 + }
107 113 }
drivers/serial/ns16550.c
Diff comments   View file @ 98d2d5e
... ... @@ -132,11 +132,12 @@
132 132  
133 133 void NS16550_init(NS16550_t com_port, int baud_divisor)
134 134 {
135   -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
  135 +#if (defined(CONFIG_SPL_BUILD) && \
  136 + (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
136 137 /*
137   - * On some OMAP3 devices when UART3 is configured for boot mode before
138   - * SPL starts only THRE bit is set. We have to empty the transmitter
139   - * before initialization starts.
  138 + * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
  139 + * before SPL starts only THRE bit is set. We have to empty the
  140 + * transmitter before initialization starts.
140 141 */
141 142 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
142 143 == UART_LSR_THRE) {
drivers/spi/ti_qspi.c
Diff comments   View file @ 98d2d5e
... ... @@ -102,7 +102,7 @@
102 102 struct spi_slave *slave = &qslave->slave;
103 103 u32 memval = 0;
104 104  
105   -#ifdef CONFIG_DRA7XX
  105 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
106 106 slave->memory_map = (void *)MMAP_START_ADDR_DRA;
107 107 #else
108 108 slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
... ... @@ -244,7 +244,7 @@
244 244 uint status;
245 245 int timeout;
246 246  
247   -#ifdef CONFIG_DRA7XX
  247 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
248 248 int val;
249 249 #endif
250 250  
... ... @@ -254,7 +254,7 @@
254 254 /* Setup mmap flags */
255 255 if (flags & SPI_XFER_MMAP) {
256 256 writel(MM_SWITCH, &qslave->base->memswitch);
257   -#ifdef CONFIG_DRA7XX
  257 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
258 258 val = readl(CORE_CTRL_IO);
259 259 val |= MEM_CS;
260 260 writel(val, CORE_CTRL_IO);
... ... @@ -262,7 +262,7 @@
262 262 return 0;
263 263 } else if (flags & SPI_XFER_MMAP_END) {
264 264 writel(~MM_SWITCH, &qslave->base->memswitch);
265   -#ifdef CONFIG_DRA7XX
  265 +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
266 266 val = readl(CORE_CTRL_IO);
267 267 val &= MEM_CS_UNSELECT;
268 268 writel(val, CORE_CTRL_IO);
drivers/usb/phy/omap_usb_phy.c
Diff comments   View file @ 98d2d5e
... ... @@ -118,7 +118,6 @@
118 118 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
119 119 {
120 120 omap_usb_dpll_lock(phy_regs);
121   -
122 121 usb3_phy_partial_powerup(phy_regs);
123 122 /*
124 123 * Give enough time for the PHY to partially power-up before
... ... @@ -126,7 +125,6 @@
126 125 * team.
127 126 */
128 127 mdelay(100);
129   - usb3_phy_power(1);
130 128 }
131 129  
132 130 static void omap_enable_usb3_phy(struct omap_xhci *omap)
include/configs/beagle_x15.h
Diff comments   View file @ 98d2d5e
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Texas Instruments Incorporated.
  4 + * Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Configuration settings for the TI Beagle x15 board.
  7 + * See ti_omap5_common.h for omap5 common settings.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __CONFIG_BEAGLE_X15_H
  13 +#define __CONFIG_BEAGLE_X15_H
  14 +
  15 +#define CONFIG_AM57XX
  16 +
  17 +#define CONFIG_NR_DRAM_BANKS 2
  18 +
  19 +#define CONFIG_ENV_SIZE (64 << 10)
  20 +#define CONFIG_ENV_IS_IN_FAT
  21 +#define FAT_ENV_INTERFACE "mmc"
  22 +#define FAT_ENV_DEVICE_AND_PART "0:1"
  23 +#define FAT_ENV_FILE "uboot.env"
  24 +
  25 +#define CONFIG_CMD_SAVEENV
  26 +
  27 +#define CONSOLEDEV "ttyO2"
  28 +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
  29 +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
  30 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
  31 +#define CONFIG_BAUDRATE 115200
  32 +
  33 +#define CONFIG_SYS_OMAP_ABE_SYSCK
  34 +
  35 +/* Define the default GPT table for eMMC */
  36 +#define PARTS_DEFAULT \
  37 + "uuid_disk=${uuid_gpt_disk};" \
  38 + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
  39 +
  40 +#include <configs/ti_omap5_common.h>
  41 +
  42 +/* Enhance our eMMC support / experience. */
  43 +#define CONFIG_CMD_GPT
  44 +#define CONFIG_EFI_PARTITION
  45 +#define CONFIG_PARTITION_UUIDS
  46 +#define CONFIG_CMD_PART
  47 +
  48 +/* CPSW Ethernet */
  49 +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
  50 +#define CONFIG_CMD_DHCP
  51 +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
  52 +#define CONFIG_BOOTP_DNS2
  53 +#define CONFIG_BOOTP_SEND_HOSTNAME
  54 +#define CONFIG_BOOTP_GATEWAY
  55 +#define CONFIG_BOOTP_SUBNETMASK
  56 +#define CONFIG_NET_RETRY_COUNT 10
  57 +#define CONFIG_CMD_PING
  58 +#define CONFIG_CMD_MII
  59 +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
  60 +#define CONFIG_MII /* Required in net/eth.c */
  61 +#define CONFIG_PHY_GIGE /* per-board part of CPSW */
  62 +#define CONFIG_PHYLIB
  63 +
  64 +#define CONFIG_SUPPORT_EMMC_BOOT
  65 +
  66 +/* USB xHCI HOST */
  67 +#define CONFIG_CMD_USB
  68 +#define CONFIG_USB_HOST
  69 +#define CONFIG_USB_XHCI
  70 +#define CONFIG_USB_XHCI_OMAP
  71 +#define CONFIG_USB_STORAGE
  72 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
  73 +
  74 +#define CONFIG_OMAP_USB_PHY
  75 +#define CONFIG_OMAP_USB3PHY1_HOST
  76 +
  77 +/* SATA */
  78 +#define CONFIG_BOARD_LATE_INIT
  79 +#define CONFIG_CMD_SCSI
  80 +#define CONFIG_LIBATA
  81 +#define CONFIG_SCSI_AHCI
  82 +#define CONFIG_SCSI_AHCI_PLAT
  83 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  84 +#define CONFIG_SYS_SCSI_MAX_LUN 1
  85 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  86 + CONFIG_SYS_SCSI_MAX_LUN)
  87 +
  88 +#endif /* __CONFIG_BEAGLE_X5_H */
include/configs/cm_t54.h
Diff comments   View file @ 98d2d5e
... ... @@ -16,7 +16,6 @@
16 16  
17 17 #include <configs/ti_omap5_common.h>
18 18  
19   -#undef CONFIG_MISC_INIT_R
20 19 #undef CONFIG_SPL_OS_BOOT
21 20  
22 21 /* Enable Generic board */
include/configs/dra7xx_evm.h
Diff comments   View file @ 98d2d5e
... ... @@ -50,6 +50,7 @@
50 50 #define CONFIG_EFI_PARTITION
51 51 #define CONFIG_PARTITION_UUIDS
52 52 #define CONFIG_CMD_PART
  53 +#define CONFIG_HSMMC2_8BIT
53 54  
54 55 /* CPSW Ethernet */
55 56 #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
include/configs/omap5_uevm.h
Diff comments   View file @ 98d2d5e
... ... @@ -23,6 +23,7 @@
23 23 #define CONFIG_SYS_NS16550_COM3 UART3_BASE
24 24 #define CONFIG_BAUDRATE 115200
25 25  
  26 +#define CONFIG_MISC_INIT_R
26 27 /* MMC ENV related defines */
27 28 #define CONFIG_ENV_IS_IN_MMC
28 29 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
include/configs/pxm2.h
Diff comments   View file @ 98d2d5e
... ... @@ -150,5 +150,9 @@
150 150 #define CONFIG_SYS_CONSOLE_FG_COL 0x00
151 151 #endif
152 152  
  153 +#ifndef CONFIG_SPL_BUILD
  154 +#define CONFIG_FIT
  155 +#endif
  156 +
153 157 #endif /* ! __CONFIG_PXM2_H */
include/configs/rut.h
Diff comments   View file @ 98d2d5e
... ... @@ -154,5 +154,9 @@
154 154 #define CONFIG_SYS_CONSOLE_FG_COL 0x00
155 155 #endif
156 156  
  157 +#ifndef CONFIG_SPL_BUILD
  158 +#define CONFIG_FIT
  159 +#endif
  160 +
157 161 #endif /* ! __CONFIG_RUT_H */
include/configs/ti_omap5_common.h
Diff comments   View file @ 98d2d5e
... ... @@ -19,7 +19,6 @@
19 19  
20 20 #define CONFIG_DISPLAY_CPUINFO
21 21 #define CONFIG_DISPLAY_BOARDINFO
22   -#define CONFIG_MISC_INIT_R
23 22 #define CONFIG_ARCH_CPU_INIT
24 23  
25 24 #define CONFIG_SYS_CACHELINE_SIZE 64
... ... @@ -79,7 +78,7 @@
79 78 "partitions=" PARTS_DEFAULT "\0" \
80 79 "optargs=\0" \
81 80 "mmcdev=0\0" \
82   - "mmcroot=/dev/mmcblk1p2 rwp2 rw\0" \" \
  81 + "mmcroot=/dev/mmcblk0p2 rwp2 rw\0" \" \
83 82 "mmcrootfstype=ext4 rootwait\0" \
84 83 "mmcargs=setenv bootargs console=${console} " \
85 84 "${optargs} " \
... ... @@ -118,6 +117,8 @@
118 117 "setenv fdtfile dra7-evm.dtb; fi;" \
119 118 "if test $board_name = dra72x; then " \
120 119 "setenv fdtfile dra72-evm.dtb; fi;" \
  120 + "if test $board_name = beagle_x15; then " \
  121 + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
121 122 "if test $fdtfile = undefined; then " \
122 123 "echo WARNING: Could not determine device tree to use; fi; \0" \
123 124 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
include/linux/usb/xhci-omap.h
Diff comments   View file @ 98d2d5e
... ... @@ -14,6 +14,10 @@
14 14 #define OMAP_XHCI_BASE 0x488d0000
15 15 #define OMAP_OCP1_SCP_BASE 0x4A081000
16 16 #define OMAP_OTG_WRAPPER_BASE 0x488c0000
  17 +#elif defined CONFIG_AM57XX
  18 +#define OMAP_XHCI_BASE 0x48890000
  19 +#define OMAP_OCP1_SCP_BASE 0x4A084c00
  20 +#define OMAP_OTG_WRAPPER_BASE 0x48880000
17 21 #elif defined CONFIG_AM43XX
18 22 #define OMAP_XHCI_BASE 0x483d0000
19 23 #define OMAP_OCP1_SCP_BASE 0x483E8000
... ... @@ -385,6 +385,7 @@
385 385 int mmc_legacy_init(int verbose);
386 386 #endif
387 387  
  388 +void board_mmc_power_init(void);
388 389 int board_mmc_init(bd_t *bis);
389 390 int cpu_mmc_init(bd_t *bis);
390 391 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
... ... @@ -651,7 +651,7 @@
651 651 /* For initializing power device */
652 652 void twl4030_power_init(void);
653 653 /* For initializing mmc power */
654   -void twl4030_power_mmc_init(void);
  654 +void twl4030_power_mmc_init(int dev_index);
655 655  
656 656 /*
657 657 * LED