Initial Commit, Upgrade SMARC-T4378 U-Boot to v2016.05

Eric Lee
1 parent b4e185a8c3
Showing 31 changed files with 3988 additions and 4 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/cpu/armv7/am33xx/Kconfig
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/dts/Makefile
arch/arm/dts/am437x-smarct437x.dts
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
arch/arm/include/asm/arch-am33xx/spl.h
board/embedian/smarct437x/Kconfig
board/embedian/smarct437x/MAINTAINERS
board/embedian/smarct437x/Makefile
board/embedian/smarct437x/board.c
board/embedian/smarct437x/board.h
board/embedian/smarct437x/mux.c
configs/smarct437x_evm_defconfig
configs/smarct437x_evm_spi_defconfig
configs/smarct437x_evm_spi_uart1_defconfig
configs/smarct437x_evm_spi_uart2_defconfig
configs/smarct437x_evm_spi_uart3_defconfig
@@ -872,6 +872,7 @@
 source "board/tcl/sl50/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/ti/am43xx/Kconfig"
+source "board/embedian/smarct437x/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
@@ -10,6 +10,18 @@
 	  to write software and develop hardware around
 	  an AM43xx processor subsystem.
  
+config TARGET_SMARCT437X_EVM
+        bool "Support smarct437x_evm"
+        help
+          The SMARC-T4378 integrates all the functions of an embedded
+          general-purpose computer in a small, easy to use SMARC module
+          which incorporates the popular Texas Instruments Sitara AM4378
+          32bit ARM Coretex-A9 processor, with fast DDR3L 512MB/1GB SDRAM,
+          4GB of embedded MMC and a dual Gigabit ethernet with simple
+          connection to external connectors.
+
+          For more information, visit: http://www.embedian.com/
+
 config ISW_ENTRY_ADDR
 	hex "Address in memory or XIP flash of bootloader entry point"
 	help
@@ -114,7 +114,7 @@
 	if (ret)
 		return ret;
  
-	return omap_mmc_init(1, 0, 0, -1, -1);
+	return omap_mmc_init(2, 0, 0, -1, -1);
 }
 #endif
  
@@ -60,6 +60,11 @@
 			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 			CD_CLKCTRL_CLKTRCTRL_SHIFT);
  
+        clrsetbits_le32(&cmper->l4lsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+                        CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+
 	/* Enable UART0 */
 	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
 			MODULE_CLKCTRL_MODULEMODE_MASK,
@@ -72,6 +77,42 @@
 		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
 			 MODULE_CLKCTRL_IDLEST_SHIFT;
 	}
+
+        /* Enable UART2 */
+        clrsetbits_le32(&cmper->uart2clkctrl,
+                        MODULE_CLKCTRL_MODULEMODE_MASK,
+                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+        while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+                (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+                clkctrl = readl(&cmper->uart2clkctrl);
+                idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                         MODULE_CLKCTRL_IDLEST_SHIFT;
+        }
+
+        /* Enable UART3 */
+        clrsetbits_le32(&cmper->uart3clkctrl,
+                        MODULE_CLKCTRL_MODULEMODE_MASK,
+                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+        while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+                (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+                clkctrl = readl(&cmper->uart3clkctrl);
+                idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                         MODULE_CLKCTRL_IDLEST_SHIFT;
+        }
+
+        /* Enable UART4 */
+        clrsetbits_le32(&cmper->uart4clkctrl,
+                        MODULE_CLKCTRL_MODULEMODE_MASK,
+                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+        while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+                (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+                clkctrl = readl(&cmper->uart4clkctrl);
+                idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                         MODULE_CLKCTRL_IDLEST_SHIFT;
+        }
 }
  
 void enable_basic_clocks(void)
@@ -99,6 +140,7 @@
 		&cmper->elmclkctrl,
 		&cmper->mmc0clkctrl,
 		&cmper->mmc1clkctrl,
+                &cmper->mmc2clkctrl,
 		&cmwkup->wkup_i2c0ctrl,
 		&cmper->gpio1clkctrl,
 		&cmper->gpio2clkctrl,
  
@@ -106,11 +148,11 @@
 		&cmper->gpio4clkctrl,
 		&cmper->gpio5clkctrl,
 		&cmper->i2c1clkctrl,
+                &cmper->i2c2clkctrl,
 		&cmper->cpgmac0clkctrl,
 		&cmper->emiffwclkctrl,
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
-		&cmper->qspiclkctrl,
 		&cmper->spi0clkctrl,
 		0
 	};
@@ -122,6 +164,10 @@
  
 	/* For OPP100 the mac clock should be /5. */
 	writel(0x4, &cmdpll->clkselmacclk);
+
+        /* enable i2c1 clock */
+        writel(0x2, &cmper->i2c1clkctrl);
+        while (readl(&cmper->i2c1clkctrl) != 0x2) ;
 }
  
 void rtc_only_enable_basic_clocks(void)
@@ -94,6 +94,7 @@
 	am335x-bonegreen.dtb \
 	am335x-icev2.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
+	am437x-smarct437x.dtb \
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM437x SK EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "TI AM437x SMARCT437X";
+	compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43";
+
+	aliases {
+		display0 = &lcd0;
+	};
+
+	chosen {
+		stdout-path = &uart4;
+		tick-timer = &timer2;
+	};
+
+        vmmcwl_fixed: fixedregulator-mmcwl {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcwl_fixed";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/
+                pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 128 212 255>;
+                default-brightness-level = <7>; /* 7 is the brightest */
+        };
+
+        sound: sound@0 {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "SMARCT437X SOUND CARD";
+                simple-audio-card,widgets =
+                        "Headphone", "Headphone Jack",
+                        "Line", "Line In";
+                simple-audio-card,routing =
+                        "Headphone Jack",       "HPLOUT",
+                        "Headphone Jack",       "HPROUT",
+                        "LINE1L",               "Line In",
+                        "LINE1R",               "Line In";
+                simple-audio-card,format = "dsp_b";
+                simple-audio-card,bitclock-master = <&sound_master>;
+                simple-audio-card,frame-master = <&sound_master>;
+                simple-audio-card,bitclock-inversion;
+
+                simple-audio-card,cpu {
+                        sound-dai = <&mcasp1>;
+                        system-clock-frequency = <12000000>;
+                };
+
+                /* For TI TLV320AIC3106 Audio Codec */
+                /*sound_master: simple-audio-card,codec {
+                        sound-dai = <&tlv320aic3106>;
+                        system-clock-frequency = <24576000>;*/
+
+                /* For Freescale SGTL5000 Audio Codec */
+                sound_master: simple-audio-card,codec {
+                        sound-dai = <&sgtl5000>;
+                        system-clock-frequency = <24000000>;
+                };
+        };
+
+        audio_mstrclk: mclk_osc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+        };
+
+        lcd0: display {
+                compatible = "primeview,pm070wl4", "panel-dpi";
+                label = "lcd";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&lcd_pins>;
+
+                enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+
+                panel-timing {
+                                clock-frequency = <32000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hfront-porch = <42>;
+                                hback-porch = <84>;
+                                hsync-len = <128>;
+                                vback-porch = <33>;
+                                vfront-porch = <10>;
+                                vsync-len = <2>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <1>;
+                };
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+        };
+};
+
+&am43xx_pinmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>;
+
+        i2c0_pins: i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)   /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)   /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        i2c1_pins: i2c1_pins {
+                pinctrl-single,pins = <
+                        0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3)   /* mii1_rxerr.i2c1_scl */
+                        0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3)   /* mii1_crs.i2c1_sda  */
+                >;
+        };
+
+        i2c2_pins: i2c2_pins {
+                pinctrl-single,pins = <
+                        0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3)   /* cam1_data1.i2c2_scl */
+                        0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3)   /* cam1_data0.i2c2_sda  */
+                >;
+        };
+
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x0f0 (PIN_INPUT | MUX_MODE0)   /* mmc0_dat3.mmc0_dat3 */
+                        0x0f4 (PIN_INPUT | MUX_MODE0)   /* mmc0_dat2.mmc0_dat2 */
+                        0x0f8 (PIN_INPUT | MUX_MODE0)   /* mmc0_dat1.mmc0_dat1 */
+                        0x0fc (PIN_INPUT | MUX_MODE0)   /* mmc0_dat0.mmc0_dat0 */
+                        0x100 (PIN_INPUT | MUX_MODE0)   /* mmc0_clk.mmc0_clk */
+                        0x104 (PIN_INPUT | MUX_MODE0)   /* mmc0_cmd.mmc0_cmd */
+                        0x160 (PIN_INPUT | MUX_MODE7)   /* spi0_cs1.gpio0_6 */
+                >;
+        };
+
+        emmc_pins: pinmux_emmc_pins {
+                pinctrl-single,pins = <
+                        0x80 (PIN_INPUT | MUX_MODE2)    /* gpmc_csn1.mmc1_clk */
+                        0x84 (PIN_INPUT | MUX_MODE2)    /* gpmc_csn2.mmc1_cmd */
+                        0x00 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad0.mmc1_dat0 */
+                        0x04 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad1.mmc1_dat1 */
+                        0x08 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad2.mmc1_dat2 */
+                        0x0c (PIN_INPUT | MUX_MODE1)    /* gpmc_ad3.mmc1_dat3 */
+                        0x10 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad4.mmc1_dat4 */
+                        0x14 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad5.mmc1_dat5 */
+                        0x18 (PIN_INPUT | MUX_MODE1)    /* gpmc_ad6.mmc1_dat6 */
+                        0x1c (PIN_INPUT | MUX_MODE1)    /* gpmc_ad7.mmc1_dat7 */
+                >;
+        };
+
+        sdmmc_pins: pinmux_sdmmc_pins {
+                pinctrl-single,pins = <
+                        0x8c (PIN_INPUT | MUX_MODE3)    /* gpmc_clk.mmc2_clk */
+                        0x88 (PIN_INPUT | MUX_MODE3)    /* gpmc_csn3.mmc2_cmd */
+                        0x30 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad12.mmc2_dat0 */
+                        0x34 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad13.mmc2_dat1 */
+                        0x38 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad14.mmc2_dat2 */
+                        0x3c (PIN_INPUT | MUX_MODE3)    /* gpmc_ad15.mmc2_dat3 */
+                        0x20 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad8.mmc2_dat4 */
+                        0x24 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad9.mmc2_dat5 */
+                        0x28 (PIN_INPUT | MUX_MODE3)    /* gpmc_ad10.mmc2_dat6 */
+                        0x2c (PIN_INPUT | MUX_MODE3)    /* gpmc_ad11.mmc2_dat7 */
+                >;
+        };
+
+        ehrpwm0b_pins: backlight_pins {
+                pinctrl-single,pins = <
+                        0x1d8 (PIN_OUTPUT | MUX_MODE6)  /* cam1_vd.ehrpwm0B */
+                >;
+        };
+
+        clkout1_pin: pinmux_clkout1_pin {
+                pinctrl-single,pins = <
+                        0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
+                >;
+        };
+
+        clkout2_pin: pinmux_clkout2_pin {
+                pinctrl-single,pins = <
+                        0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */
+                >;
+        };
+
+        dcan0_default: dcan0_default_pins {
+                pinctrl-single,pins = <
+                        0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.dcan0_rx */
+                        0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */
+                >;
+        };
+
+        dcan1_default: dcan1_default_pins {
+                pinctrl-single,pins = <
+                        0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.dcan1_rx */
+                        0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0)      /* uart0_ctsn.uart0_ctsn */
+                        0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0)      /* uart0_rtsn.uart0_rtsn */
+                        0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)      /* uart0_txd.uart0_txd */
+                >;
+        };
+
+        uart0_pins_sleep: pinmux_uart0_pins_sleep {
+                pinctrl-single,pins = <
+                        0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)      /* uart3_rxd.uart3_rxd */
+                        0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)      /* uart3_txd.uart3_txd */
+                >;
+        };
+
+        uart3_pins_sleep: pinmux_uart3_pins_sleep {
+                pinctrl-single,pins = <
+                        0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)      /* cam1_data6.uart2_ctsn */
+                        0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)      /* cam1_data7_rtsn.uart2_rtsn */
+                        0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2)      /* cam1_data4_uart2rxd */
+                        0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2)      /* cam1_data5.uart2_txd */
+                >;
+        };
+
+        uart2_pins_sleep: pinmux_uart2_pins_sleep {
+                pinctrl-single,pins = <
+                        0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        uart4_pins: pinmux_uart4_pins {
+                pinctrl-single,pins = <
+                        0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6)      /* gpmc_wait0.uart4_rxd */
+                        0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6)      /* gpmc_wpn.uart4_txd */
+                >;
+        };
+
+        uart4_pins_sleep: pinmux_uart4_pins_sleep {
+                pinctrl-single,pins = <
+                        0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/
+        gpio_pins_default: pinmux_gpio_pin {
+                pinctrl-single,pins = <
+                        0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9)  /* spi2_cs0.gpio0_23 */
+                        0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9)  /* spi2_d0.gpio0_20 */
+                        0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9)  /* spi2_d1.gpio0_21 */
+                        0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9)  /* spi2_sclk.gpio0_22 */
+                        0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* cam0_data5.gpio4_27 */
+                        0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* cam0_data7.gpio4_29 */
+                        0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
+                        0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */
+                        0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */
+                        0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */
+                        0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */
+                        0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */
+                >;
+        };
+
+        wdt_time_out_pins_default: pinmux_wdt_time_out_pin {
+                pinctrl-single,pins = <
+                        0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */
+                >;
+        };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x12c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txclk.rmii1_tclk */
+                        0x114 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txen.rgmii1_tctl */
+                        0x128 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td0 */
+                        0x124 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td1 */
+                        0x120 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td2 */
+                        0x11c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td3 */
+                        0x130 (PIN_INPUT | MUX_MODE2)   /* mii1_rxclk.rmii1_rclk */
+                        0x118 (PIN_INPUT | MUX_MODE2)   /* mii1_rxdv.rgmii1_rctl */
+                        0x140 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd0 */
+                        0x13c (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd1 */
+                        0x138 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd2 */
+                        0x134 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd3 */
+
+                        /* Slave 2 */
+                        0x58 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a6.rgmii2_tclk */
+                        0x40 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a0.rgmii2_tctl */
+                        0x54 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a5.rgmii2_td0 */
+                        0x50 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a4.rgmii2_td1 */
+                        0x4c (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a3.rgmii2_td2 */
+                        0x48 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a2.rgmii2_td3 */
+                        0x5c (PIN_INPUT | MUX_MODE2)    /* gpmc_a7.rgmii2_rclk */
+                        0x44 (PIN_INPUT | MUX_MODE2)    /* gpmc_a1.rgmii2_rtcl */
+                        0x6c (PIN_INPUT | MUX_MODE2)    /* gpmc_a11.rgmii2_rd0 */
+                        0x68 (PIN_INPUT | MUX_MODE2)    /* gpmc_a10.rgmii2_rd1 */
+                        0x64 (PIN_INPUT | MUX_MODE2)    /* gpmc_a9.rgmii2_rd2 */
+                        0x60 (PIN_INPUT | MUX_MODE2)    /* gpmc_a8.rgmii2_rd3 */
+                >;
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+                        /* Slave 2 reset value */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)   /* mdio_data.mdio_data */
+                        0x14c (PIN_OUTPUT | MUX_MODE0)                  /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        dss_pins: dss_pins {
+                pinctrl-single,pins = <
+                        0x1b0 (PIN_OUTPUT | MUX_MODE2)  /* cam0_hd.dss_data23 */
+                        0x1b4 (PIN_OUTPUT | MUX_MODE2)  /* cam0_vd.dss_data22 */
+                        0x1b8 (PIN_OUTPUT | MUX_MODE2)  /* cam0_field.dss_data21 */
+                        0x1bc (PIN_OUTPUT | MUX_MODE2)  /* cam0_wen.dss_data20 */
+                        0x1c0 (PIN_OUTPUT | MUX_MODE2)  /* cam0_pclk.dss_data19 */
+                        0x1c4 (PIN_OUTPUT | MUX_MODE2)  /* cam0_data8.dss_data18 */
+                        0x1c8 (PIN_OUTPUT | MUX_MODE2)  /* cam0_data9.dss_data17 */
+                        0x1cc (PIN_OUTPUT | MUX_MODE2)  /* cam1_data9.dss_data16 */
+                        0x0a0 (PIN_OUTPUT | MUX_MODE0)  /* DSS DATA 0 */
+                        0x0a4 (PIN_OUTPUT | MUX_MODE0)
+                        0x0a8 (PIN_OUTPUT | MUX_MODE0)
+                        0x0ac (PIN_OUTPUT | MUX_MODE0)
+                        0x0b0 (PIN_OUTPUT | MUX_MODE0)
+                        0x0b4 (PIN_OUTPUT | MUX_MODE0)
+                        0x0b8 (PIN_OUTPUT | MUX_MODE0)
+                        0x0bc (PIN_OUTPUT | MUX_MODE0)
+                        0x0c0 (PIN_OUTPUT | MUX_MODE0)
+                        0x0c4 (PIN_OUTPUT | MUX_MODE0)
+                        0x0c8 (PIN_OUTPUT | MUX_MODE0)
+                        0x0cc (PIN_OUTPUT | MUX_MODE0)
+                        0x0d0 (PIN_OUTPUT | MUX_MODE0)
+                        0x0d4 (PIN_OUTPUT | MUX_MODE0)
+                        0x0d8 (PIN_OUTPUT | MUX_MODE0)
+                        0x0dc (PIN_OUTPUT | MUX_MODE0)  /* DSS DATA 15 */
+                        0x0e0 (PIN_OUTPUT | MUX_MODE0)  /* DSS VSYNC */
+                        0x0e4 (PIN_OUTPUT | MUX_MODE0)  /* DSS HSYNC */
+                        0x0e8 (PIN_OUTPUT | MUX_MODE0)  /* DSS PCLK */
+                        0x0ec (PIN_OUTPUT | MUX_MODE0)  /* DSS AC BIAS EN */
+
+                >;
+        };
+
+        /* SPI_NOR Pins */
+        spi0_pins: spi0_pins {
+                pinctrl-single,pins = <
+                        0x15c (PIN_OUTPUT | MUX_MODE0)  /* spi0_cs0.spi0_cs0 */
+                        0x150 (PIN_INPUT | MUX_MODE0)   /* spi0_sclk.spi0_sclk */
+                        0x154 (PIN_INPUT | MUX_MODE0)   /* spi0_d0.spi0_d0 */
+                        0x158 (PIN_OUTPUT | MUX_MODE0)  /* spi0_d1.spi0_d1 */
+                >;
+        };
+
+        /* SPI0 Pins */
+        spi2_pins: spi2_pins {
+                pinctrl-single,pins = <
+                        0x1d4 (PIN_OUTPUT | MUX_MODE4)  /* cam1_hd.spi2_cs0 */
+                        0x1e0 (PIN_OUTPUT | MUX_MODE4)  /* cam1_field.spi2_cs0 */
+                        0x1dc (PIN_INPUT | MUX_MODE4)   /* cam1_pclk.spi2_sclk */
+                        0x1d0 (PIN_INPUT | MUX_MODE4)   /* cam1_data8.spi2_d0 */
+                        0x1e4 (PIN_OUTPUT | MUX_MODE4)  /* cam1_wen.spi2_d1 */
+                >;
+        };
+
+        /* SPI1 Pins */
+        spi4_pins: spi4_pins {
+                pinctrl-single,pins = <
+                        0x25c (PIN_OUTPUT | MUX_MODE0)  /* spi4_cs0.spi4_cs0 */
+                        0x230 (PIN_OUTPUT | MUX_MODE2)  /* uart3_cstn.spi4_cs1 */
+                        0x250 (PIN_INPUT | MUX_MODE0)   /* spi4_sclk.spi4_sclk */
+                        0x254 (PIN_INPUT | MUX_MODE0)   /* spi4_d0.spi4_d0 */
+                        0x258 (PIN_OUTPUT | MUX_MODE0)  /* spi4_d1.spi4_d1 */
+                >;
+        };
+
+        mcasp1_pins: mcasp1_pins {
+                pinctrl-single,pins = <
+                        0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcasp0_aclkr.mcasp1_aclkx */
+                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcasp0_fsr.mcasp1_fsx */
+                        0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */
+                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcasp0_ahclkx.mcasp1_axr1 */
+                >;
+        };
+
+        mcasp1_sleep_pins: mcasp1_sleep_pins {
+                pinctrl-single,pins = <
+                        0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        lcd_pins: lcd_pins {
+                pinctrl-single,pins = <
+                        0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */
+                >;
+        };
+
+        debugss_pins: pinmux_debugss_pins {
+                pinctrl-single,pins = <
+                        0x290 (PIN_INPUT_PULLDOWN)
+                        0x294 (PIN_INPUT_PULLDOWN)
+                        0x298 (PIN_INPUT_PULLDOWN)
+                        0x29C (PIN_INPUT_PULLDOWN)
+                        0x2A0 (PIN_INPUT_PULLDOWN)
+                        0x2A4 (PIN_INPUT_PULLDOWN)
+                        0x2A8 (PIN_INPUT_PULLDOWN)
+                >;
+        };
+
+        usb1_pins: usb1_pins {
+                pinctrl-single,pins = <
+                        0x2c0 (PIN_OUTPUT | MUX_MODE0)  /* usb0_drvvbus.usb0_drvvbus */
+                        /* USB0 Over Current */
+                        0x108 (PIN_INPUT | MUX_MODE9)   /* mii1_col.gpio0_0 */
+                >;
+        };
+
+        usb2_pins: usb2_pins {
+                pinctrl-single,pins = <
+                        0x2c4 (PIN_OUTPUT | MUX_MODE0)  /* usb1_drvvbus.usb1_drvvbus */
+                        /* USB1 Over Current */
+                        0x078 (PIN_INPUT | MUX_MODE7)   /* gpmc_be1n.gpio1_28 */
+                >;
+        };
+};
+
+&i2c0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        clock-frequency = <100000>;
+};
+
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <100000>;
+
+        tps@24 {
+                compatible = "ti,tps65218";
+                reg = <0x24>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                dcdc1: regulator-dcdc1 {
+                        compatible = "ti,tps65218-dcdc1";
+                        /* VDD_CORE limits min of OPP50 and max of OPP100 */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <912000>;
+                        regulator-max-microvolt = <1144000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc2: regulator-dcdc2 {
+                        compatible = "ti,tps65218-dcdc2";
+                        /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <912000>;
+                        regulator-max-microvolt = <1378000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3: regulator-dcdc3 {
+                        compatible = "ti,tps65218-dcdc3";
+                        regulator-name = "vdds_ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        regulator-state-mem {
+                                regulator-on-in-suspend;
+                        };
+                        regulator-state-disk {
+                                regulator-off-in-suspend;
+                        };
+                };
+
+                dcdc4: regulator-dcdc4 {
+                        compatible = "ti,tps65218-dcdc4";
+                        regulator-name = "v3_3d";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc5: regulator-dcdc5 {
+                        compatible = "ti,tps65218-dcdc5";
+                        regulator-name = "v1_0bat";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        regulator-state-mem {
+                                regulator-on-in-suspend;
+                        };
+                };
+
+                dcdc6: regulator-dcdc6 {
+                        compatible = "ti,tps65218-dcdc6";
+                        regulator-name = "v1_8bat";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        regulator-state-mem {
+                                regulator-on-in-suspend;
+                        };
+                };
+
+                ldo1: regulator-ldo1 {
+                        compatible = "ti,tps65218-ldo1";
+                        regulator-name = "v1_8d";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                power-button {
+                        compatible = "ti,tps65218-pwrbutton";
+                        status = "okay";
+                        interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+                };
+        };
+
+        s35390a: s35390a@30 {
+                compatible = "s35390a";
+                reg = <0x30>;
+        };
+
+        at24@50 {
+                compatible = "at24,24c256";
+                reg = <0x50>;
+        };
+
+        at24@57 {
+                compatible = "at24,24c256";
+                reg = <0x57>;
+        };
+
+        /* For TI TLV320AIC3106 Audio Codec */
+        /*tlv320aic3106: tlv320aic3106@1b {
+                #sound-dai-cells = <0>;
+                compatible = "ti,tlv320aic3106";
+                reg = <0x1b>;
+                status = "okay";
+
+                AVDD-supply = <&dcdc4>;
+                IOVDD-supply = <&dcdc6>;
+                DRVDD-supply = <&dcdc4>;
+                DVDD-supply = <&ldo1>;
+        };*/
+
+        /* For Freescale SGTL5000 Audio Codec */
+        sgtl5000: sgtl5000@0a {
+                #sound-dai-cells = <0>;
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&audio_mstrclk>;
+                VDDA-supply = <&dcdc4>;
+                VDDIO-supply = <&dcdc6>;
+                VDDD-supply = <&ldo1>;
+        };
+};
+
+&i2c2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        clock-frequency = <100000>;
+
+        /* CH7055A Parallel LCD to VGA D-SUB 15 way */
+        eeprom@76 {
+                compatible = "at,24c256";
+                reg = <0x76>;
+        };
+};
+
+
+&epwmss0 {
+        status = "okay";
+
+        ehrpwm0: ehrpwm@48300200 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&ehrpwm0b_pins>;
+        };
+};
+
+&gpio0 {
+        status = "okay";
+};
+
+&gpio1 {
+        status = "okay";
+};
+
+&gpio2 {
+        status = "okay";
+};
+
+&gpio3 {
+        status = "okay";
+};
+
+&gpio4 {
+        status = "okay";
+};
+
+&gpio5 {
+        status = "okay";
+};
+
+&mmc1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+
+        vmmc-supply = <&dcdc4>;
+        bus-width = <4>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_pins>;
+        bus-width = <8>;
+        vmmc-supply = <&vmmcwl_fixed>;
+        status = "okay";
+        ti,non-removable;
+};
+
+/*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/
+
+&mmc3 {
+        status = "okay";
+        dmas = <&edma 30
+                &edma 31>;
+        dma-names = "tx", "rx";
+        vmmc-supply = <&vmmcwl_fixed>;
+        bus-width = <8>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_pins>;
+        keep-power-in-suspend;
+        ti,non-removable;
+};
+
+&edma {
+        ti,edma-xbar-event-map = /bits/ 16 <1 30
+                                            2 31>;
+};
+
+/* Four-Wire Resistive Touch */
+&tscadc {
+        status = "disabled";
+        tsc {
+                ti,wires = <4>;
+                ti,x-plate-resistance = <200>;
+                ti,coordinate-readouts = <5>;
+                ti,wire-config = <0x00 0x11 0x22 0x33>;
+                ti,charge-delay = <0xB000>;
+        };
+
+        adc {
+                ti,adc-channels = <0 1 2 3>;
+        };
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb1 {
+        dr_mode = "host";
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2_phy2 {
+        status = "okay";
+};
+
+&usb2 {
+        dr_mode = "host";
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb2_pins>;
+};
+
+&spi0 {
+        ti,spi-num-cs = <1>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+        dmas = <&edma 16
+                &edma 17>;
+        dma-names = "tx0", "rx0";
+
+        flash: mx25u3235f@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "jedec,spi-nor";
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+
+                /* MTD partition table.
+                 * The ROM checks the first 512KiB
+                 * for a valid file to boot(XIP).
+                 */
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0x0 0x100000>;
+                        };
+
+                        partition@100000 {
+                                label = "U-Boot Environment";
+                                reg = <0x100000 0x080000>;
+                        };
+
+                        partition@180000 {
+                                label = "Flattened Device Tree";
+                                reg = <0x180000 0x200000>;
+                        };
+
+        };
+};
+
+&spi2 {
+        ti,spi-num-cs = <2>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi2_pins>;
+        dmas = <&edma 18
+                &edma 19
+                &edma 20
+                &edma 21>;
+        dma-names = "tx0", "rx0", "tx1", "rx1";
+
+                spidev1: spidev@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <24000000>;
+                };
+
+                spidev2: spidev@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "spidev";
+                        reg = <1>;
+                        spi-max-frequency = <24000000>;
+                };
+        };
+
+&spi4 {
+        ti,spi-num-cs = <2>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi4_pins>;
+        dmas = <&edma 26
+                &edma 27
+                &edma 28
+                &edma 29>;
+        dma-names = "tx0", "rx0", "tx1", "rx1";
+
+                spidev3: spidev@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <24000000>;
+                };
+
+                spidev4: spidev@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "spidev";
+                        reg = <1>;
+                        spi-max-frequency = <24000000>;
+                };
+        };
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        pinctrl-1 = <&uart0_pins_sleep>;
+
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        pinctrl-1 = <&uart3_pins_sleep>;
+
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        pinctrl-1 = <&uart2_pins_sleep>;
+
+        status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins>;
+        pinctrl-1 = <&uart4_pins_sleep>;
+
+        status = "okay";
+};
+
+&dcan0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan0_default>;
+        status = "okay";
+};
+
+&dcan1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan1_default>;
+        status = "okay";
+};
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac = <1>;
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <6>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <7>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <2>;
+};
+
+&elm {
+        status = "okay";
+};
+
+&mcasp1 {
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&mcasp1_pins>;
+        pinctrl-1 = <&mcasp1_sleep_pins>;
+
+        status = "okay";
+
+                op-mode = <0>;          /* MCASP_IIS_MODE */
+                tdm-slots = <2>;
+                /* 4 serializers */
+                serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+                        1 2 0 0
+                >;
+
+                tx-num-evt = <1>;
+                rx-num-evt = <1>;
+};
+
+&dss {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_pins>;
+
+        port {
+                dpi_out: endpoint@0 {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
+&rtc {
+        status = "disabled";    /* Use Seiko S35390A on Module instead */
+        ext-clk-src;
+};
+
+&wdt {
+        status = "okay";
+};
+
+&cpu {
+	cpu0-supply = <&dcdc2>;
+};
@@ -101,5 +101,12 @@
 /* EDMA3 Base Address */
 #define EDMA3_BASE				0x49000000
  
+/* LCD Controller */
+#define LCD_CNTL_BASE                           0x4832A000
+
+/* PWMSS */
+#define PWMSS0_BASE                             0x48300000
+#define AM33XX_EHRPWM0_BASE                     0x48300200
+
 #endif /* __AM43XX_HARDWARE_AM43XX_H */
@@ -23,6 +23,7 @@
  */
 #define OMAP_HSMMC1_BASE		0x48060100
 #define OMAP_HSMMC2_BASE		0x481D8100
+#define OMAP_HSMMC3_BASE		0x47810100
  
 #if defined(CONFIG_TI814X)
 #undef MMC_CLOCK_REFERENCE
@@ -55,6 +55,7 @@
 #define BOOT_DEVICE_NAND	0x05
 #define BOOT_DEVICE_MMC1	0x07
 #define BOOT_DEVICE_MMC2	0x08
+#define BOOT_DEVICE_MMC3        0x09
 #define BOOT_DEVICE_SPI		0x0A
 #define BOOT_DEVICE_USB		0x0D
 #define BOOT_DEVICE_UART	0x41
+if TARGET_SMARCT437X_EVM
+
+config SYS_BOARD
+        default "smarct437x"
+
+config SYS_VENDOR
+        default "embedian"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "smarct437x_evm"
+
+endif
+SMARCT437X SMARC BOARD
+M:      Eric Lee <eric.lee@embedian.com>
+S:      Maintained
+F:      board/embedian/smarct437x/
+F:      include/configs/smarct437x_evm.h
+F:      configs/smarct437x_evm_defconfig
+F:      configs/smarct437x_evm_uart1_defconfig
+F:      configs/smarct437x_evm_uart2_defconfig
+F:      configs/smarct437x_evm_uart3_defconfig
+F:      configs/smarct437x_evm_spi_defconfig
+F:      configs/smarct437x_evm_spi_uart1_defconfig
+F:      configs/smarct437x_evm_spi_uart2_defconfig
+F:      configs/smarct437x_evm_spi_uart3_defconfig
+F:      configs/am43xx_evm_ethboot_defconfig
+F:      configs/am43xx_evm_usbhost_boot_defconfig
+F:      configs/am43xx_evm_rtconly_defconfig
+F:      configs/am43xx_evm_usbspl_defconfig
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y   := mux.o
+endif
+
+obj-y   += board.o
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+#include <spl.h>
+#include <usb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include "board.h"
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include <power/tps62362.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+	i2c_set_bus_num(1);
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM at 0x%x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+		     sizeof(struct am43xx_board_id))) {
+		printf("Could not read the EEPROM\n");
+		return -EIO;
+	}
+
+	if (header->magic != 0xEE3355AA) {
+		/*
+		 * read the eeprom using i2c again,
+		 * but use only a 1 byte address
+		 */
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+			     sizeof(struct am43xx_board_id))) {
+			printf("Could not read the EEPROM at 0x%x\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR);
+			return -EIO;
+		}
+
+		if (header->magic != 0xEE3355AA) {
+			/*printf("Incorrect magic number (0x%x) in EEPROM\n",
+			       header->magic);
+			return -EINVAL;*/
+		}
+	}
+
+	strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
+	am43xx_board_name[sizeof(header->name)] = 0;
+
+	strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
+	am43xx_board_rev[sizeof(header->version)] = 0;
+
+	return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#define NUM_OPPS	6
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+	{	/* 19.2 MHz */
+		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
+		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 24 MHz */
+		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 25 MHz */
+		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 26 MHz */
+		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
+		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
+		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
+		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
+		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
+		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
+		{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
+		{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
+		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+		50, 2, 1, -1, 2, -1, -1};
+
+static const struct dpll_params idk_dpll_ddr = {
+	400, 23, 1, -1, 2, -1, -1
+};
+
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+	.sdram_config			= 0x808012BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0xEA86B411,
+	.sdram_tim2			= 0x103A094A,
+	.sdram_tim3			= 0x0F6BA37F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E284006,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config			= 0x000FFFFF
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0xc163,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413b2,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0e084008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x89,
+	.emif_ddr_ext_phy_ctrl_3	= 0x90,
+	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
+	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x80000000,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
+	.sdram_config			= 0x61a11b32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1		= 0x00008009,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000405,
+	.emif_prio_class_serv_map	= 0x00000000,
+	.emif_connect_id_serv_1_map	= 0x00000000,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x00ffffff
+};
+
+static const struct emif_regs ddr3_smarc80_emif_regs_400Mhz = {
+        .sdram_config                   = 0x63841372,
+        .sdram_config2                  = 0x00000000,
+        .ref_ctrl                       = 0x00000c30,
+        .sdram_tim1                     = 0xeaaad4db,
+        .sdram_tim2                     = 0x266b7fda,
+        .sdram_tim3                     = 0x107f8678,
+        .read_idle_ctrl                 = 0x00050000,
+        .zq_config                      = 0x50074be4,
+        .temp_alert_config              = 0x0,
+        .emif_ddr_phy_ctlr_1            = 0x0e084008,
+        .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
+        .emif_ddr_ext_phy_ctrl_2        = 0x89,
+        .emif_ddr_ext_phy_ctrl_3        = 0x90,
+        .emif_ddr_ext_phy_ctrl_4        = 0x8e,
+        .emif_ddr_ext_phy_ctrl_5        = 0x8d,
+        .emif_rd_wr_lvl_rmp_win         = 0x0,
+        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+        .emif_rd_wr_lvl_ctl             = 0x00000000,
+        .emif_rd_wr_exec_thresh         = 0x80000000,
+        .emif_prio_class_serv_map       = 0x80000001,
+        .emif_connect_id_serv_1_map     = 0x80000094,
+        .emif_connect_id_serv_2_map     = 0x00000000,
+        .emif_cos_config                = 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_smarc1g_emif_regs_400Mhz = {
+        .sdram_config                   = 0x638413b2,
+        .sdram_config2                  = 0x00000000,
+        .ref_ctrl                       = 0x00000c30,
+        .sdram_tim1                     = 0xeaaad4db,
+        .sdram_tim2                     = 0x266b7fda,
+        .sdram_tim3                     = 0x107f8678,
+        .read_idle_ctrl                 = 0x00050000,
+        .zq_config                      = 0x50074be4,
+        .temp_alert_config              = 0x0,
+        .emif_ddr_phy_ctlr_1            = 0x0e084008,
+        .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
+        .emif_ddr_ext_phy_ctrl_2        = 0x89,
+        .emif_ddr_ext_phy_ctrl_3        = 0x90,
+        .emif_ddr_ext_phy_ctrl_4        = 0x8e,
+        .emif_ddr_ext_phy_ctrl_5        = 0x8d,
+        .emif_rd_wr_lvl_rmp_win         = 0x0,
+        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+        .emif_rd_wr_lvl_ctl             = 0x00000000,
+        .emif_rd_wr_exec_thresh         = 0x80000000,
+        .emif_prio_class_serv_map       = 0x80000001,
+        .emif_connect_id_serv_1_map     = 0x80000094,
+        .emif_connect_id_serv_2_map     = 0x00000000,
+        .emif_cos_config                = 0x000FFFFF
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	if (board_is_eposevm()) {
+		*regs = ext_phy_ctrl_const_base_lpddr2;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	}
+
+	return;
+}
+
+/*
+ * get_sys_clk_index : returns the index of the sys_clk read from
+ *			ctrl status register. This value is either
+ *			read from efuse or sysboot pins.
+ */
+static u32 get_sys_clk_index(void)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	u32 ind = readl(&ctrl->statusreg), src;
+
+	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+	else /* Value read from SYS BOOT pins */
+		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+			CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	if (board_is_eposevm())
+		return &epos_evm_dpll_ddr[ind];
+	else if (board_is_gpevm() || board_is_sk() || board_is_smarc_t437x_800() || board_is_smarc_t437x_01g())
+		return &gp_evm_dpll_ddr;
+	else if (board_is_idk())
+		return &idk_dpll_ddr;
+	else	
+	printf(" Board '%s' not supported\n", am43xx_board_name);
+	return NULL;
+}
+
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	int opp, offset, i;
+
+	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
+
+	for (i = max_off; i >= min_off; i--) {
+		offset = opp & (1 << i);
+		if (!offset)
+			return i;
+	}
+
+	return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+	u32 ind = get_sys_clk_index();
+
+	return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_per[ind];
+}
+
+void scale_vcores_generic(u32 m)
+{
+	int mpu_vdd;
+
+	if (i2c_probe(TPS65218_CHIP_PM))
+		return;
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+
+	/* Set DCDC1 (CORE) voltage to 1.1V */
+	if (tps65218_voltage_update(TPS65218_DCDC1,
+				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+
+void scale_vcores_idk(u32 m)
+{
+	int mpu_vdd;
+
+	if (i2c_probe(TPS62362_I2C_ADDR))
+		return;
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+
+	/* Set VDD_MPU voltage */
+	if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+
+void scale_vcores(void)
+{
+	const struct dpll_params *mpu_params;
+	struct am43xx_board_id header;
+
+	enable_i2c1_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	/* Get the frequency */
+	mpu_params = get_dpll_mpu_params();
+
+	if (board_is_idk())
+		scale_vcores_idk(mpu_params->m);
+	else
+		scale_vcores_generic(mpu_params->m);
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+        enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+        enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+        enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+        enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+        enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+        enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+static void enable_vtt_regulator(void)
+{
+	u32 temp;
+
+	/* enable module */
+	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+	/* enable output for GPIO5_7 */
+	writel(GPIO_SETDATAOUT(7),
+	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(GPIO_OE_ENABLE(7));
+	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
+enum {
+	RTC_BOARD_EPOS = 1,
+	RTC_BOARD_EVM14,
+	RTC_BOARD_EVM12,
+	RTC_BOARD_GPEVM,
+	RTC_BOARD_SK,
+	RTC_BOARD_SMARC_T437X_800,
+	RTC_BOARD_SMARC_T437X_01G,
+};
+
+/*
+ * In the rtc_only boot path we have the board type info in the rtc scratch pad
+ * register hence we bypass the costly i2c reads to eeprom and directly program
+ * the board name string
+ */
+void rtc_only_update_board_type(u32 btype)
+{
+	const char *name = "";
+	const char *rev = "1.0";
+
+	switch (btype) {
+	case RTC_BOARD_EPOS:
+		name = "AM43EPOS";
+		break;
+	case RTC_BOARD_EVM14:
+		name = "AM43__GP";
+		rev = "1.4";
+		break;
+	case RTC_BOARD_EVM12:
+		name = "AM43__GP";
+		rev = "1.2";
+		break;
+	case RTC_BOARD_GPEVM:
+		name = "AM43__GP";
+		break;
+	case RTC_BOARD_SK:
+		name = "AM43__SK";
+		break;
+        case RTC_BOARD_SMARC_T437X_800:
+                name = "SMCT4X80";
+                break;
+        case RTC_BOARD_SMARC_T437X_01G:
+                name = "SMCT4X1G";
+                break;
+	}
+	strcpy(am43xx_board_name, name);
+	strcpy(am43xx_board_rev, rev);
+}
+
+u32 rtc_only_get_board_type(void)
+{
+	if (board_is_eposevm())
+		return RTC_BOARD_EPOS;
+	else if (board_is_evm_14_or_later())
+		return RTC_BOARD_EVM14;
+	else if (board_is_evm_12_or_later())
+		return RTC_BOARD_EVM12;
+	else if (board_is_gpevm())
+		return RTC_BOARD_GPEVM;
+	else if (board_is_sk())
+		return RTC_BOARD_SK;
+        else if (board_is_smarc_t437x_800())
+                return RTC_BOARD_SMARC_T437X_800;
+        else if (board_is_smarc_t437x_01g())
+                return RTC_BOARD_SMARC_T437X_01G;
+
+	return 0;
+}
+
+void sdram_init(void)
+{
+	/*
+	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+	 * GP EMV has 1GB DDR3 connected to EMIF
+	 * along with VTT regulator.
+	 */
+	if (board_is_eposevm()) {
+		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+	} else if (board_is_evm_14_or_later()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz_production, 0);
+	} else if (board_is_evm_12_or_later()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz_beta, 0);
+	} else if (board_is_gpevm()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz, 0);
+	} else if (board_is_sk()) {
+		config_ddr(400, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_sk_emif_regs_400Mhz, 0);
+	} else if (board_is_idk()) {
+		config_ddr(400, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_idk_emif_regs_400Mhz, 0);
+        } else if (board_is_smarc_t437x_800()) {
+                config_ddr(400, &ioregs_ddr3, NULL, NULL,
+                           &ddr3_smarc80_emif_regs_400Mhz, 0);
+        } else if (board_is_smarc_t437x_01g()) {
+                config_ddr(400, &ioregs_ddr3, NULL, NULL,
+                           &ddr3_smarc1g_emif_regs_400Mhz, 0);
+	}
+}
+#endif
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+
+	if (board_is_idk()) {
+		power_tps62362_init(I2C_PMIC);
+		p = pmic_get("TPS62362");
+		if (p && !pmic_probe(p))
+			puts("PMIC:  TPS62362\n");
+	} else {
+		power_tps65218_init(I2C_PMIC);
+		p = pmic_get("TPS65218_PMIC");
+		if (p && !pmic_probe(p))
+			puts("PMIC:  TPS65218\n");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+        u32 sys_reboot;
+
+        sys_reboot = readl(PRM_RSTST);
+        if (sys_reboot & (1 << 9))
+                puts("Reset Source: IcePick reset has occurred.\n");
+
+        if (sys_reboot & (1 << 5))
+                puts("Reset Source: Global external warm reset has occurred.\n");
+
+        if (sys_reboot & (1 << 4))
+                puts("Reset Source: watchdog reset has occurred.\n");
+
+        if (sys_reboot & (1 << 1))
+                puts("Reset Source: Global warm SW reset has occurred.\n");
+
+        if (sys_reboot & (1 << 0))
+                puts("Reset Source: Power-on reset has occurred.\n");
+
+	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+	    modena_init0_bw_integer, modena_init0_watermark_0;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	/* Clear all important bits for DSS errata that may need to be tweaked*/
+	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+	                   MREQPRIO_0_SAB_INIT0_MASK;
+
+	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+	                                   BW_LIMITER_BW_FRAC_MASK;
+
+	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+	                                BW_LIMITER_BW_INT_MASK;
+
+	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+	                                 BW_LIMITER_BW_WATERMARK_MASK;
+
+	/* Setting MReq Priority of the DSS*/
+	mreqprio_0 |= 0x77;
+
+	/*
+	 * Set L3 Fast Configuration Register
+	 * Limiting bandwith for ARM core to 700 MBPS
+	 */
+	modena_init0_bw_fractional |= 0x10;
+	modena_init0_bw_integer |= 0x3;
+
+	writel(mreqprio_0, &cdev->mreqprio_0);
+	writel(mreqprio_1, &cdev->mreqprio_1);
+
+	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char safe_string[HDR_NAME_LEN + 1];
+	struct am43xx_board_id header;
+
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	/* Read Board Info */
+        puts("-----------------------------------------\n");
+        printf("Board ID:               %.*s\n",
+               sizeof(header.name), header.name);
+        printf("Board Revision:         %.*s\n",
+               sizeof(header.version), header.version);
+        printf("Board Serial#:          %.*s\n",
+               sizeof(header.serial), header.serial);
+        puts("-----------------------------------------\n");
+
+	/* Now set variables based on the header. */
+	strncpy(safe_string, (char *)header.name, sizeof(header.name));
+	safe_string[sizeof(header.name)] = 0;
+	setenv("board_name", safe_string);
+
+	strncpy(safe_string, (char *)header.version, sizeof(header.version));
+	safe_string[sizeof(header.version)] = 0;
+	setenv("board_rev", safe_string);
+#endif
+
+	/* Turn on LCD Backlight */
+#define GPIO_LCD_BKLT_EN       	68
+#define GPIO_LCD_PWM_EN        	138
+#define GPIO_BOOT_SEL1		168
+#define GPIO_BOOT_SEL2          169
+#define GPIO_BOOT_SEL3          170
+      	gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+       	gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
+      	gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
+       	gpio_direction_output(GPIO_LCD_PWM_EN, 1);
+
+        gpio_request(GPIO_BOOT_SEL1, "boot_sel1");
+        gpio_direction_input(GPIO_BOOT_SEL1);
+        gpio_request(GPIO_BOOT_SEL2, "boot_sel2");
+        gpio_direction_input(GPIO_BOOT_SEL2);
+        gpio_request(GPIO_BOOT_SEL3, "boot_sel3");
+        gpio_direction_input(GPIO_BOOT_SEL3);
+
+	/*Read BOOT_SEL Configuration */
+        if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) {
+                puts("BOOT_SEL Detected: OFF OFF OFF, SATA Boot Up Not Defined...\n");
+                hang();
+        } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) {
+                puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n");
+                setenv_ulong("mmcdev", 2); 
+                setenv("bootcmd", "run findfdt; run mmcboot;");
+        } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) {
+                puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");
+                setenv_ulong("mmcdev", 0);
+                setenv("bootcmd", "run findfdt; run mmcboot;");
+        } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) {
+                puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");
+                setenv_ulong("mmcdev", 1); 
+                setenv("bootcmd", "mmc rescan; run findfdt; run mmcboot;");
+        } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) {
+                puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
+                setenv("bootcmd", "dhcp;");
+        } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) {
+                puts("BOOT_SEL Detected: ON ON OFF, Carrier SPI Boot Not Supported...\n");
+                hang();
+        } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) {
+                puts("BOOT_SEL Detected: OFF OFF ON, Load zImage from USB1...\n");
+                setenv_ulong("usbdev", 0);
+                setenv("bootcmd", "run findfdt; run usbboot;");
+        } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) {
+                puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");
+                setenv_ulong("mmcdev", 1);
+                setenv("bootcmd", "run findfdt; run mmcboot;");
+        } else {
+                puts("unsupported boot up devices\n");
+                hang();
+        }
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss1 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS1_BASE,
+	.tx_fifo_resize = false,
+	.index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss1_glue = {
+	.base = (void *)USB_OTG_SS1_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy1_device = {
+	.usb2_phy_power = (void *)USB2_PHY1_POWER,
+	.index = 0,
+};
+
+static struct dwc3_device usb_otg_ss2 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS2_BASE,
+	.tx_fifo_resize = false,
+	.index = 1,
+};
+
+static struct dwc3_omap_device usb_otg_ss2_glue = {
+	.base = (void *)USB_OTG_SS2_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 1,
+};
+
+static struct ti_usb_phy_device usb_phy2_device = {
+	.usb2_phy_power = (void *)USB2_PHY2_POWER,
+	.index = 1,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	enable_usb_clocks(index);
+	switch (index) {
+	case 0:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+		} else {
+			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
+			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+		}
+
+		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+		ti_usb_phy_uboot_init(&usb_phy1_device);
+		dwc3_uboot_init(&usb_otg_ss1);
+		break;
+	case 1:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+		} else {
+			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
+			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+		}
+
+		ti_usb_phy_uboot_init(&usb_phy2_device);
+		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+		dwc3_uboot_init(&usb_otg_ss2);
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	switch (index) {
+	case 0:
+	case 1:
+		ti_usb_phy_uboot_exit(index);
+		dwc3_uboot_exit(index);
+		dwc3_omap_uboot_exit(index);
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+	disable_usb_clocks(index);
+
+	return 0;
+}
+
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* Additional controls can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 16,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
+	defined(CONFIG_SPL_USBETH_SUPPORT)) && \
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+	int rv;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+#ifndef CONFIG_SPL_BUILD
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
+	if (board_is_eposevm()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 16;
+	} else if (board_is_sk()) {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+		cpsw_slaves[0].phy_addr = 4;
+		cpsw_slaves[1].phy_addr = 5;
+	} else if (board_is_idk()) {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+		cpsw_slaves[0].phy_addr = 0;
+        } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) {
+                writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+                cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+                cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
+                cpsw_slaves[0].phy_addr = 6;
+                cpsw_slaves[1].phy_addr = 7;
+	} else {
+                writel(RGMII_MODE_ENABLE, &cdev->miisel);
+                cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+                cpsw_slaves[0].phy_addr = 0;
+	}
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0) {
+		printf("Error %d registering CPSW switch\n", rv);
+		return rv;
+	}
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+#endif
+
+	return rv;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+        if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+                return 0;
+        else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+                return 0;
+        else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+                return 0;
+        else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+                return 0;
+        else if (board_is_smarc_t437x_800() && !strcmp(name, "am437x-smarct437x"))
+                return 0;
+        else if (board_is_smarc_t437x_01g() && !strcmp(name, "am437x-smarct437x"))
+                return 0;
+        else
+                return -1;
+}
+#endif
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <asm/arch/omap.h>
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+#define DEV_ATTR_MAX_OFFSET	5
+#define DEV_ATTR_MIN_OFFSET	0
+
+struct am43xx_board_id {
+	unsigned int  magic;
+	char name[HDR_NAME_LEN];
+	char version[4];
+	char serial[12];
+	char config[32];
+	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+}
+
+static inline int board_is_sk(void)
+{
+	return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
+}
+
+static inline int board_is_smarc_t437x_800(void)
+{
+        return !strncmp(am43xx_board_name, "SMCT4X80", HDR_NAME_LEN);
+}
+
+static inline int board_is_smarc_t437x_01g(void)
+{
+        return !strncmp(am43xx_board_name, "SMCT4X1G", HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(void)
+{
+	return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_14_or_later(void)
+{
+	return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
+}
+
+static inline int board_is_evm_12_or_later(void)
+{
+	return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0);
+}
+
+void enable_uart0_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_i2c1_pin_mux(void);
+#endif
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+/* LAN1 */
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+/* LAN2 */
+static struct module_pin_mux rgmii2_pin_mux[] = {
+        {OFFSET(gpmc_a0), MODE(2)},                  	/* RGMII2_TCTL */
+        {OFFSET(gpmc_a1), MODE(2) | RXACTIVE},        	/* RGMII2_RCTL */
+        {OFFSET(gpmc_a2), MODE(2)},                   	/* RGMII2_TD3 */
+        {OFFSET(gpmc_a3), MODE(2)},                   	/* RGMII2_TD2 */
+        {OFFSET(gpmc_a4), MODE(2)},                   	/* RGMII2_TD1 */
+        {OFFSET(gpmc_a5), MODE(2)},                   	/* RGMII2_TD0 */
+        {OFFSET(gpmc_a6), MODE(2)},                  	/* RGMII2_TCLK */
+        {OFFSET(gpmc_a7), MODE(2) | RXACTIVE},       	/* RGMII2_RCLK */
+        {OFFSET(gpmc_a8), MODE(2) | RXACTIVE},        	/* RGMII2_RD3 */
+        {OFFSET(gpmc_a9), MODE(2) | RXACTIVE},        	/* RGMII2_RD2 */
+        {OFFSET(gpmc_a10), MODE(2) | RXACTIVE},        	/* RGMII2_RD1 */
+        {OFFSET(gpmc_a11), MODE(2) | RXACTIVE},        	/* RGMII2_RD0 */
+        {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},		/* MDIO_CLK */
+	{-1},
+};
+
+/* SER0 */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+        {OFFSET(uart0_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+/* SER2 */
+static struct module_pin_mux uart2_pin_mux[] = {
+        {OFFSET(cam1_data4), (MODE(2) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(cam1_data5), (MODE(2) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+        {OFFSET(cam1_data6), (MODE(2) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(cam1_data7), (MODE(2) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+        {-1},
+};
+
+/* SER1 */
+static struct module_pin_mux uart3_pin_mux[] = {
+        {OFFSET(uart3_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(uart3_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+        {-1},
+};
+
+/* SER3 */
+static struct module_pin_mux uart4_pin_mux[] = {
+        {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(gpmc_wpn), (MODE(6) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+        {-1},
+};
+
+/* SD */
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  	/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* MMC0_DAT3 */
+	{OFFSET(rmii1_refclk), MODE(5) | PULLUP_EN}, 	/* SDIO_PWREN */
+	{-1},
+};
+
+/* EMMC */
+static struct module_pin_mux mmc1_pin_mux[] = {
+        {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, 	/* MMC1_CLK */
+        {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_CMD */
+        {OFFSET(gpmc_ad0), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT0 */
+        {OFFSET(gpmc_ad1), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT1 */
+        {OFFSET(gpmc_ad2), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT2 */
+        {OFFSET(gpmc_ad3), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT3 */
+        {OFFSET(gpmc_ad4), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT4 */
+        {OFFSET(gpmc_ad5), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT5 */
+        {OFFSET(gpmc_ad6), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT6 */
+        {OFFSET(gpmc_ad7), (MODE(1) | PULLUP_EN | RXACTIVE)}, 	/* MMC1_DAT7 */
+        {-1},
+};
+
+/* SDMMC */
+static struct module_pin_mux mmc2_pin_mux[] = {
+        {OFFSET(gpmc_clk), (MODE(3) | PULLUDDIS | RXACTIVE)}, 	/* MMC2_CLK */
+        {OFFSET(gpmc_csn3), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_CMD */
+        {OFFSET(gpmc_ad12), (MODE(3) | PULLUP_EN | RXACTIVE)},	/* MMC2_DAT0 */
+        {OFFSET(gpmc_ad13), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT1 */
+        {OFFSET(gpmc_ad14), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT2 */
+        {OFFSET(gpmc_ad15), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT3 */
+        {OFFSET(gpmc_ad8), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT4 */
+        {OFFSET(gpmc_ad9), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT5 */
+        {OFFSET(gpmc_ad10), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT6 */
+        {OFFSET(gpmc_ad11), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* MMC2_DAT7 */
+        {-1},
+};
+
+/* I2C_GP */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{-1},
+};
+
+/* I2C_PM */
+static struct module_pin_mux i2c1_pin_mux[] = {
+        {OFFSET(mii1_crs), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(mii1_rxerr), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {-1},
+};
+
+/* I2C_LCD */
+static struct module_pin_mux i2c2_pin_mux[] = {
+        {OFFSET(cam1_data0), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {OFFSET(cam1_data1), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+        {-1},
+};
+
+/* GPIO */
+static struct module_pin_mux smarc_gpio_pin_mux[] = {
+        {OFFSET(mii1_col), (MODE(9) | PULLUP_EN | RXACTIVE)},  	/* USB0_OC#, mii1_col.gpio0_0*/
+        {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN | RXACTIVE)}, 	/* USB1_OC#, gmpc_be1n.gpio1.28 */
+        {OFFSET(rmii1_refclk), (MODE(7) | PULLUP_EN)},  	/* SDIO_PWREN, rmii1_refclk.gpio0.29 */
+/* By SMARC Spec. GPIO0-5 is recommended for use as outputs. */
+        {OFFSET(spi2_cs0), (MODE(9) | PULLUP_EN)},             	/* GPIO0, spi2_cs0.gpio0_23 */
+        {OFFSET(spi2_d0), (MODE(9) | PULLUP_EN)},          	/* GPIO1, spi2_d0_gpio0_20 */
+        {OFFSET(spi2_d1), (MODE(9) | PULLUP_EN)},              	/* GPIO2, spi2_d1.gpio0_21 */
+        {OFFSET(spi2_sclk), (MODE(9) | PULLUP_EN)},            	/* GPIO3, spi2_sclk.gpio0_22*/
+        {OFFSET(cam0_data5), (MODE(7) | PULLUP_EN)},           	/* GPIO4, cam0_data5.gpio4_7 */
+        {OFFSET(cam0_data7), (MODE(7) | PULLUP_EN)},           	/* GPIO5, cam0_data7.gpio4_29 */
+
+/* By SMARC Spec. GPIO6-11 is recommended for use of inputs */
+        {OFFSET(mcasp0_ahclkr), (MODE(7) | RXACTIVE)},  		/* GPIO6, mcasp0.ahclkr.gpio3_7 */
+        {OFFSET(mcasp0_axr0), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* GPIO7, mcasp0.axr0.gpio3_6 */
+        {OFFSET(cam0_data2), (MODE(7) | PULLUP_EN | RXACTIVE)},        	/* GPIO8, cam0_data2.gpio4_24 */
+        {OFFSET(cam0_data3), (MODE(7) | PULLUP_EN | RXACTIVE)},        	/* GPIO9, cam0_data3.gpio4_25 */
+        {OFFSET(cam0_data4), (MODE(7) | PULLUP_EN | RXACTIVE)},       	/* GPIO10, cam0_data4_gpio4_26 */
+        {OFFSET(cam0_data6), (MODE(7)  | PULLUP_EN | RXACTIVE)},       	/* GPIO11, cam0_data6_gpio4_28 */
+        {-1},
+};
+
+/* DSS LCD */
+static struct module_pin_mux dss_pin_mux[] = {
+    	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
+    	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
+	/* DSS DATA16~23 */
+    	{OFFSET(cam1_data9), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_data9), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_data8), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_pclk), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_wen), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_field), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_vd), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(cam0_hd), (MODE(2) | PULLUDDIS)},
+    	{OFFSET(lcd_vsync), (MODE(0) | PULLUDEN)},
+    	{OFFSET(lcd_hsync), (MODE(0) | PULLUDEN)},
+    	{OFFSET(lcd_pclk), (MODE(0) | PULLUDEN)},
+    	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDEN)},
+    	{-1},
+ };
+
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},	/* GPIO5_7 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)},	/* AD0 */
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)},	/* AD1 */
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD2 */
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD3 */
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD4 */
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD5 */
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD6 */
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD8  */
+	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD9  */
+	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD10 */
+	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD11 */
+	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD12 */
+	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD13 */
+	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD14 */
+	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, 	/* AD15 */
+#endif
+	{OFFSET(gpmc_wait0),	(MODE(0) | RXACTIVE | PULLUP_EN)}, 	/* Wait */
+	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},			/* Write Protect */
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},			/* Chip-Select */
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)}, 		/* Write Enable */
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)}, 		/* Read Enable */
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)}, 		/* Addr Latch Enable*/
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)}, 		/* Byte Enable */
+	{-1},
+};
+#endif
+
+static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
+	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, 		/* QSPI_CS0 */
+	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, 		/* QSPI_CLK */
+	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* QSPI_D0 */
+	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* QSPI_D1 */
+	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, 		/* QSPI_D2 */
+	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, 	/* QSPI_D3 */
+	{-1},
+};
+
+/* SPI BOOT */
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_d0),   (MODE(0) | RXACTIVE | PULLUDEN)},
+	{OFFSET(spi0_d1),   (MODE(0) | PULLUDEN)},
+	{OFFSET(spi0_cs0),  (MODE(0) | PULLUDEN)},
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
+	{-1},
+};
+
+/* SPI0 */
+static struct module_pin_mux spi2_pin_mux[] = {
+        {OFFSET(cam1_hd), (MODE(4) | PULLUP_EN | RXACTIVE)}, 		/* SPI0_CS0 */
+        {OFFSET(cam1_field), (MODE(4) | PULLUP_EN | RXACTIVE)}, 	/* SPI0_CS1 */
+        {OFFSET(cam1_pclk), (MODE(4) | PULLUP_EN | RXACTIVE)}, 		/* SPI0_CLK */
+        {OFFSET(cam1_data8), (MODE(4) | PULLUP_EN | RXACTIVE)}, 	/* SPI0_D0 */
+        {OFFSET(cam1_wen), (MODE(4) | PULLUP_EN | RXACTIVE)}, 		/* SPI0_D1 */
+        {-1},
+};
+
+/* SPI1 */
+static struct module_pin_mux spi4_pin_mux[] = {
+        {OFFSET(spi4_cs0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* SPI0_CS0 */
+        {OFFSET(uart3_ctsn), (MODE(2) | PULLUP_EN | RXACTIVE)},	/* SPI0_CS1 */
+        {OFFSET(spi4_sclk), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* SPI0_CLK */
+        {OFFSET(spi4_d0), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* SPI0_D0 */
+        {OFFSET(spi4_d1), (MODE(0) | PULLUP_EN | RXACTIVE)}, 	/* SPI0_D1 */
+        {-1},
+};
+
+/* BOOT_SEL */
+static struct module_pin_mux boot_sel_pin_mux[] = {
+        {OFFSET(gpio5_8), (MODE(7) | PULLUP_EN | RXACTIVE)},    /* BOOT_SEL0, mii1_col.gpio0_0*/
+        {OFFSET(gpio5_9), (MODE(7) | PULLUP_EN | RXACTIVE)},    /* BOOT_SEL1, gmpc_be1n.gpio1.28 */
+        {OFFSET(gpio5_10), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* BOOT_SEL2, spi2_cs0.gpio0_23 */
+        {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+        configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+        configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+        configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+       	configure_module_pin_mux(spi0_pin_mux);
+      	configure_module_pin_mux(mmc0_pin_mux);
+	if (board_is_gpevm()) {
+		configure_module_pin_mux(gpio5_7_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#endif
+	} else if (board_is_sk() || board_is_idk()) {
+		configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+		printf("Error: NAND flash not present on this board\n");
+#endif
+		configure_module_pin_mux(qspi_pin_mux);
+        } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) {
+        	configure_module_pin_mux(mmc1_pin_mux);
+        	configure_module_pin_mux(i2c0_pin_mux);
+        	configure_module_pin_mux(mdio_pin_mux);
+        	configure_module_pin_mux(spi2_pin_mux);
+                configure_module_pin_mux(spi4_pin_mux);
+        	configure_module_pin_mux(rgmii1_pin_mux);
+        	configure_module_pin_mux(rgmii2_pin_mux);
+        	configure_module_pin_mux(mmc2_pin_mux);
+        	configure_module_pin_mux(i2c2_pin_mux);
+        	configure_module_pin_mux(smarc_gpio_pin_mux);
+        	configure_module_pin_mux(dss_pin_mux);
+        	configure_module_pin_mux(boot_sel_pin_mux);
+	} else if (board_is_eposevm()) {
+		configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#else
+		configure_module_pin_mux(qspi_pin_mux);
+#endif
+	}
+}
+
+void enable_i2c1_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+}
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DMA=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,SPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,SPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,SPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DMA=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DMA=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TARGET_SMARCT437X_EVM=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DMA=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-smarct437x"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_CMD_TIME=y
@@ -1222,7 +1222,8 @@
 #ifdef OMAP_HSMMC3_BASE
 	case 2:
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
+#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
+	defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC3_8BIT)
 		/* Enable 8-bit interface for eMMC on DRA7XX */
 		host_caps_val |= MMC_MODE_8BIT;
 #endif
@@ -47,6 +47,7 @@
 	{"MX25L1605D",	   0xc22015, 0x0,	64 * 1024,    32, RD_NORM,			  0},
 	{"MX25L3205D",	   0xc22016, 0x0,	64 * 1024,    64, RD_NORM,			  0},
 	{"MX25L6405D",	   0xc22017, 0x0,	64 * 1024,   128, RD_NORM,			  0},
+	{"MX25U3235F",     0xc22536, 0x0,       64 * 1024,    64, RD_NORM,                   SECT_4K},
 	{"MX25L12805",	   0xc22018, 0x0,	64 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"MX25L25635F",	   0xc22019, 0x0,	64 * 1024,   512, RD_FULL,		     WR_QPP},
 	{"MX25L51235F",	   0xc2201a, 0x0,	64 * 1024,  1024, RD_FULL,		     WR_QPP},
@@ -104,6 +104,7 @@
 {
 	i2c_set_bus_num(p->bus);
 	debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
+	i2c_set_bus_num(1);
 	if (i2c_probe(pmic_i2c_addr)) {
 		printf("Can't find PMIC:%s\n", p->name);
 		return -1;
@@ -48,7 +48,7 @@
  
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_BOOTDELAY     2
+#define CONFIG_BOOTDELAY     1
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_MENU
 #define CONFIG_DOS_PARTITION
+/*
+ * ti_armv7_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature.  Rather than define these in every
+ * board or even SoC common file, we define a common file to be re-used
+ * in all cases.  While technically true that some of these details are
+ * configurable at the board design, they are common throughout SoC
+ * reference platforms as well as custom designs and become de facto
+ * standards.
+ */
+
+#ifndef __CONFIG_EMBEDIAN_ARMV7_COMMON_H__
+#define __CONFIG_EMBEDIAN_ARMV7_COMMON_H__
+
+/*
+ * We typically do not contain NOR flash.  In the cases where we do, we
+ * undefine this later.
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ * However, set this to a 32MB offset to allow for easier Linux kernel
+ * booting as the default is often used as the kernel load address.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * We setup defaults based on constraints from the Linux kernel, which should
+ * also be safe elsewhere.  We have the default load at 32MB into DDR (for
+ * the kernel), FDT above 128MB (the maximum location for the end of the
+ * kernel), and the ramdisk 512KB above that (allowing for hopefully never
+ * seen large trees).  We say all of this must be within the first 256MB
+ * as that will normally be within the kernel lowmem and thus visible via
+ * bootm_size and we only run on platforms with 256MB or more of memory.
+ */
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0x82000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"rdaddr=0x88080000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"scriptaddr=0x80000000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"bootm_size=0x10000000\0"
+
+#define DEFAULT_MMC_TI_ARGS \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4 rootwait fixrtc\0" \
+	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"args_mmc=run finduuid;setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=PARTUUID=${uuid} rw " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"bootenvfile=uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+	"envboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded env from ${bootenvfile};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0" \
+
+/*
+ * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more.  We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS		1
+#endif
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* Timer information. */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* I2C IP block */
+#define CONFIG_I2C
+#define CONFIG_SYS_I2C
+
+/* MMC/SD IP block */
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+/* McSPI IP block */
+#define CONFIG_SPI
+
+/* GPIO block */
+
+/*
+ * The following are general good-enough settings for U-Boot.  We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed.  We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt.  We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#ifdef CONFIG_DFU_MMC
+#define CONFIG_SYS_MALLOC_LEN	((16 << 20) + CONFIG_SYS_DFU_DATA_BUF_SIZE)
+#else
+#define CONFIG_SYS_MALLOC_LEN	(16 << 20)
+#endif
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_ENV_VARS_UBOOT_CONFIG	/* Strongly encouraged */
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * When we have SPI, NOR or NAND flash we expect to be making use of
+ * mtdparts, both for ease of use in U-Boot and for passing information
+ * on to the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) || defined(CONFIG_NAND_DAVINCI)
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif
+
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+#endif
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded.  We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired.  We make use of the general SPL framework found
+ * under common/spl/.  Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#if !defined(CONFIG_NOR_BOOT) && \
+	!(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_OS_BOOT
+
+/*
+ * Place the image at the start of the ROM defined image space (per
+ * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
+ * downloaded image area.  We initalize DRAM as soon as we can so that
+ * we can place stack, malloc and BSS there.  We load U-Boot itself into
+ * memory at 0x80800000 for legacy reasons (to not conflict with older
+ * SPLs).  We have our BSS be placed 2MiB after this, to allow for the
+ * default Linux kernel address of 0x80008000 to work with most sized
+ * kernels, in the Falcon Mode case.  We have the SPL malloc pool at the
+ * end of the BSS area.  We suggest that the stack be placed at 32MiB after
+ * the start of DRAM to allow room for all of the above (handled in Kconfig).
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#endif
+#ifndef CONFIG_SPL_BSS_START_ADDR
+#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#endif
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#endif
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* FAT */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* spl export command */
+#define CONFIG_CMD_SPL
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+/*#define CONFIG_SPL_EXT_SUPPORT*/
+#endif
+
+#define CONFIG_SYS_THUMB_BUILD
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#endif
+#endif /* !CONFIG_NOR_BOOT */
+
+/* Generic Environment Variables */
+
+#ifdef CONFIG_CMD_NET
+#define NETARGS \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"nfsopts=nolock\0" \
+	"rootpath=/export/rootfs\0" \
+	"netloadimage=tftp ${loadaddr} ${bootfile}\0" \
+	"netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"run netloadimage; " \
+		"run netloadfdt; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NETARGS ""
+#endif
+
+#include <config_distro_defaults.h>
+
+#endif	/* __CONFIG_EMBEDIAN_ARMV7_COMMON_H__ */
+/*
+ * ti_armv7_omap.h
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature. This is meant to isolate the features
+ * that are based on OMAP architecture.
+ */
+#ifndef __CONFIG_EMBEDIAN_ARMV7_SMARCT4X_H__
+#define __CONFIG_EMBEDIAN_ARMV7_SMARCT4X_H__
+
+/* Common defines for all OMAP architecture based SoCs */
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	2
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* MMC/SD IP block */
+#define CONFIG_OMAP_HSMMC
+
+/* SPI IP Block */
+#define CONFIG_OMAP3_SPI
+
+/* GPIO block */
+#define CONFIG_OMAP_GPIO
+
+/*
+ * GPMC NAND block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#endif
+
+/* Now for the remaining common defines */
+#include <configs/embedian_armv7_common.h>
+
+#endif /* __CONFIG_EMBEDIAN_ARMV7_SMARCT4X_H__ */
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SMARCT437X_EVM_H
+#define __CONFIG_SMARCT437X_EVM_H
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE       32
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+#define CONFIG_ENV_IS_NOWHERE
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_CLK		48000000
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+
+/* I2C Configuration */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* Power */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65218
+#define CONFIG_POWER_TPS62362
+
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE		CONFIG_ISW_ENTRY_ADDR
+#define CONFIG_SPL_MAX_SIZE		(NON_SECURE_SRAM_END - \
+					CONFIG_PUB_ROM_DATA_SIZE - \
+					CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) /*&& !defined(CONFIG_QSPI_BOOT)*/
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_HSMMC2_8BIT
+
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f.  This is taken care of in
+ * s_init when we have SPL used.
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/embedian_armv7_smarct4x.h>
+
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE			(64 << 10)
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
+#define CONFIG_SYS_NS16550_COM3         0x48024000      /* UART2 */
+#define CONFIG_SYS_NS16550_COM4         0x481a6000      /* UART3 */
+#define CONFIG_SYS_NS16550_COM5         0x481a8000      /* UART4 */
+#define CONFIG_SYS_NS16550_COM6         0x481aa000      /* UART5 */
+#define CONFIG_BAUDRATE                 115200
+
+#if !defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
+#define CONFIG_FAT_WRITE
+#endif
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* SPL USB Support */
+#ifdef CONFIG_SPL_USB_HOST_SUPPORT
+#define CONFIG_SPL_USB_SUPPORT
+#endif
+
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_DWC3_PHY_OMAP
+#undef CONFIG_USB_DWC3_OMAP
+#undef CONFIG_USB_DWC3
+#undef CONFIG_USB_DWC3_GADGET
+
+#undef CONFIG_USB_GADGET_DOWNLOAD
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#undef CONFIG_G_DNL_MANUFACTURER
+#undef CONFIG_G_DNL_VENDOR_NUM
+#undef CONFIG_G_DNL_PRODUCT_NUM
+#undef CONFIG_USB_GADGET_DUALSPEED
+#endif
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_TIMER
+#undef CONFIG_DM_NAND
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/* USB Device Firmware Update support */
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_RAM
+
+#define CONFIG_DFU_MMC
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+	"dfu_alt_info_emmc=" \
+	"MLO raw 0x100 0x100 mmcpart 0;" \
+	"u-boot.img raw 0x300 0x1000 mmcpart 0\0"
+
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0x4000000;" \
+	"fdt ram 0x80f80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM
+#else
+#define DFUARGS
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT               /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS              0
+#define CONFIG_SPL_SPI_CS               0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
+
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE            (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET               (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND        (896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT                  "nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=m25p80-flash.0:128k(SPL)," \
+                                        "512k(u-boot),128k(u-boot-env1)," \
+                                        "128k(u-boot-env2),3464k(kernel)," \
+                                        "-(rootfs)"
+#endif
+
+#if defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV          1
+#define CONFIG_SYS_MMC_ENV_PART         2
+#define CONFIG_ENV_OFFSET               0x0
+#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI */
+/*#undef CONFIG_OMAP3_SPI*/
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_BUS           0
+#define CONFIG_SF_DEFAULT_SPEED         24000000
+#define CONFIG_DEFAULT_SPI_MODE         SPI_MODE_3
+
+#define CONFIG_TI_EDMA3
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+        "boot_fdt=try\0" \
+        "bootpart=0:1\0" \
+        "bootdir=\0" \
+        "fdtdir=/dtbs\0" \
+        "bootfile=zImage\0" \
+        "fdtfile=am437x-smarct437x.dtb\0" \
+        "console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+        "cmdline=\0" \
+        "mmcpart=1\0" \
+        "mmcroot=/dev/mmcblk0p2 ro\0" \
+	"usbroot=/dev/sda2 rw\0" \
+	"usbrootfstype=ext4 rootwait\0" \
+	"usbdev=0\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"usbargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${usbroot} " \
+		"rootfstype=${usbrootfstype}\0" \
+        "bootenv=uEnv.txt\0" \
+        "script=boot.scr\0" \
+        "scriptfile=${script}\0" \
+        "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+        "bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+                "source ${loadaddr}\0" \
+        "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+        "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \
+        "importbootenv=echo Importing environment from mmc ...; " \
+                "env import -t -r $loadaddr $filesize\0" \
+        "importusbbootenv=echo Importing environment from usb ...; " \
+                "env import -t -r $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+        "mmcboot=mmc dev ${mmcdev}; " \
+                "setenv devnum ${mmcdev}; " \
+                "setenv bootpart ${mmcdev}:1; "\
+                "setenv devtype mmc; " \
+                "if mmc rescan; then " \
+                        "echo SD/MMC found on device ${devnum};" \
+                        "if run loadbootenv; then " \
+                                "echo Loaded environment from ${bootenv};" \
+                                "run importbootenv;" \
+                        "fi;" \
+                        "if test -n $uenvcmd; then " \
+                                "echo Running uenvcmd ...;" \
+                                "run uenvcmd;" \
+                        "fi;" \
+                        "if run loadimage; then " \
+                                "run loadfdt; " \
+                                "echo Booting from mmc${mmcdev} ...; " \
+                                "run args_mmc; " \
+                                "bootz ${loadaddr} - ${fdtaddr}; " \
+                        "fi;" \
+                "fi;\0" \
+	"usbboot=" \
+		"setenv devnum ${usbdev}; " \
+		"setenv devtype usb; " \
+		"usb start ${usbdev}; " \
+		"if usb dev ${usbdev}; then " \
+			"if run loadusbbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importusbbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from usb ${usbdev}...; " \
+				"run usbargs;" \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi\0" \
+		"fi;" \
+		"usb stop ${usbdev};\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43XXHS; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43__SK; then " \
+			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
+		"if test $board_name = AM43_IDK; then " \
+			"setenv fdtfile am437x-idk-evm.dtb; fi; " \
+                "if test $board_name = SMCT4X80; then " \
+                        "setenv fdtfile am437x-smarct437x.dtb; fi; " \
+                "if test $board_name = SMCT4X1G; then " \
+                        "setenv fdtfile am437x-smarct437x.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0" \
+	NANDARGS \
+	NETARGS \
+	DFUARGS \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run envboot;" \
+	"run mmcboot;" \
+	"run usbboot;"
+
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/* CPSW Ethernet */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_PHY_GIGE
+#endif
+
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define PHY_ANEG_TIMEOUT	8000 /* PHY needs longer aneg time at 1G */
+
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM43xx U-Boot SPL"
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
+#undef CONFIG_ENV_IS_IN_FAT
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SPL_NET_SUPPORT
+#endif
+
+#define CONFIG_SYS_RX_ETH_BUFFER	64
+
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	26
+#define MTDIDS_DEFAULT			"nand0=nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+					"256k(NAND.SPL)," \
+					"256k(NAND.SPL.backup1)," \
+					"256k(NAND.SPL.backup2)," \
+					"256k(NAND.SPL.backup3)," \
+					"512k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"256k(NAND.u-boot-env)," \
+					"256k(NAND.u-boot-env.backup1)," \
+					"7m(NAND.kernel)," \
+					"-(NAND.file-system)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x00100000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#define NANDBOOT			"run nandboot; "
+#else /* !CONFIG_NAND */
+#define NANDARGS
+#define NANDBOOT
+#endif /* CONFIG_NAND */
+
+#endif	/* __CONFIG_SMARCT437X_EVM_H */
@@ -14,12 +14,14 @@
 #define MUX_MODE6	6
 #define MUX_MODE7	7
 #define MUX_MODE8	8
+#define MUX_MODE9       9
  
 #define PULL_DISABLE		(1 << 16)
 #define PULL_UP			(1 << 17)
 #define INPUT_EN		(1 << 18)
 #define SLEWCTRL_SLOW		(1 << 19)
 #define SLEWCTRL_FAST		0
+#define DS0_FORCE_OFF_MODE      (1 << 24)
 #define DS0_PULL_UP_DOWN_EN	(1 << 27)
 #define WAKEUP_ENABLE		(1 << 29)
...	...	@@ -872,6 +872,7 @@
872	872	source "board/tcl/sl50/Kconfig"
873	873	source "board/ti/am335x/Kconfig"
874	874	source "board/ti/am43xx/Kconfig"
	875	+source "board/embedian/smarct437x/Kconfig"
875	876	source "board/birdland/bav335x/Kconfig"
876	877	source "board/ti/ti814x/Kconfig"
877	878	source "board/ti/ti816x/Kconfig"
...	...	@@ -10,6 +10,18 @@
10	10	to write software and develop hardware around
11	11	an AM43xx processor subsystem.
12	12
	13	+config TARGET_SMARCT437X_EVM
	14	+ bool "Support smarct437x_evm"
	15	+ help
	16	+ The SMARC-T4378 integrates all the functions of an embedded
	17	+ general-purpose computer in a small, easy to use SMARC module
	18	+ which incorporates the popular Texas Instruments Sitara AM4378
	19	+ 32bit ARM Coretex-A9 processor, with fast DDR3L 512MB/1GB SDRAM,
	20	+ 4GB of embedded MMC and a dual Gigabit ethernet with simple
	21	+ connection to external connectors.
	22	+
	23	+ For more information, visit: http://www.embedian.com/
	24	+
13	25	config ISW_ENTRY_ADDR
14	26	hex "Address in memory or XIP flash of bootloader entry point"
15	27	help
...	...	@@ -114,7 +114,7 @@
114	114	if (ret)
115	115	return ret;
116	116
117		- return omap_mmc_init(1, 0, 0, -1, -1);
	117	+ return omap_mmc_init(2, 0, 0, -1, -1);
118	118	}
119	119	#endif
120	120
...	...	@@ -60,6 +60,11 @@
60	60	CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
61	61	CD_CLKCTRL_CLKTRCTRL_SHIFT);
62	62
	63	+ clrsetbits_le32(&cmper->l4lsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
	64	+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
	65	+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
	66	+
	67	+
63	68	/* Enable UART0 */
64	69	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
65	70	MODULE_CLKCTRL_MODULEMODE_MASK,
...	...	@@ -72,6 +77,42 @@
72	77	idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
73	78	MODULE_CLKCTRL_IDLEST_SHIFT;
74	79	}
	80	+
	81	+ /* Enable UART2 */
	82	+ clrsetbits_le32(&cmper->uart2clkctrl,
	83	+ MODULE_CLKCTRL_MODULEMODE_MASK,
	84	+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
	85	+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
	86	+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) \|\|
	87	+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
	88	+ clkctrl = readl(&cmper->uart2clkctrl);
	89	+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
	90	+ MODULE_CLKCTRL_IDLEST_SHIFT;
	91	+ }
	92	+
	93	+ /* Enable UART3 */
	94	+ clrsetbits_le32(&cmper->uart3clkctrl,
	95	+ MODULE_CLKCTRL_MODULEMODE_MASK,
	96	+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
	97	+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
	98	+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) \|\|
	99	+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
	100	+ clkctrl = readl(&cmper->uart3clkctrl);
	101	+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
	102	+ MODULE_CLKCTRL_IDLEST_SHIFT;
	103	+ }
	104	+
	105	+ /* Enable UART4 */
	106	+ clrsetbits_le32(&cmper->uart4clkctrl,
	107	+ MODULE_CLKCTRL_MODULEMODE_MASK,
	108	+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
	109	+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
	110	+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) \|\|
	111	+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
	112	+ clkctrl = readl(&cmper->uart4clkctrl);
	113	+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
	114	+ MODULE_CLKCTRL_IDLEST_SHIFT;
	115	+ }
75	116	}
76	117
77	118	void enable_basic_clocks(void)
...	...	@@ -99,6 +140,7 @@
99	140	&cmper->elmclkctrl,
100	141	&cmper->mmc0clkctrl,
101	142	&cmper->mmc1clkctrl,
	143	+ &cmper->mmc2clkctrl,
102	144	&cmwkup->wkup_i2c0ctrl,
103	145	&cmper->gpio1clkctrl,
104	146	&cmper->gpio2clkctrl,
105	147
...	...	@@ -106,11 +148,11 @@
106	148	&cmper->gpio4clkctrl,
107	149	&cmper->gpio5clkctrl,
108	150	&cmper->i2c1clkctrl,
	151	+ &cmper->i2c2clkctrl,
109	152	&cmper->cpgmac0clkctrl,
110	153	&cmper->emiffwclkctrl,
111	154	&cmper->emifclkctrl,
112	155	&cmper->otfaemifclkctrl,
113		- &cmper->qspiclkctrl,
114	156	&cmper->spi0clkctrl,
115	157	0
116	158	};
...	...	@@ -122,6 +164,10 @@
122	164
123	165	/* For OPP100 the mac clock should be /5. */
124	166	writel(0x4, &cmdpll->clkselmacclk);
	167	+
	168	+ /* enable i2c1 clock */
	169	+ writel(0x2, &cmper->i2c1clkctrl);
	170	+ while (readl(&cmper->i2c1clkctrl) != 0x2) ;
125	171	}
126	172
127	173	void rtc_only_enable_basic_clocks(void)
...	...	@@ -94,6 +94,7 @@
94	94	am335x-bonegreen.dtb \
95	95	am335x-icev2.dtb
96	96	dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
	97	+ am437x-smarct437x.dtb \
97	98	am43x-epos-evm.dtb \
98	99	am437x-idk-evm.dtb
99	100	dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
...	...	@@ -101,5 +101,12 @@
101	101	/* EDMA3 Base Address */
102	102	#define EDMA3_BASE 0x49000000
103	103
	104	+/* LCD Controller */
	105	+#define LCD_CNTL_BASE 0x4832A000
	106	+
	107	+/* PWMSS */
	108	+#define PWMSS0_BASE 0x48300000
	109	+#define AM33XX_EHRPWM0_BASE 0x48300200
	110	+
104	111	#endif /* __AM43XX_HARDWARE_AM43XX_H */
...	...	@@ -23,6 +23,7 @@
23	23	*/
24	24	#define OMAP_HSMMC1_BASE 0x48060100
25	25	#define OMAP_HSMMC2_BASE 0x481D8100
	26	+#define OMAP_HSMMC3_BASE 0x47810100
26	27
27	28	#if defined(CONFIG_TI814X)
28	29	#undef MMC_CLOCK_REFERENCE
...	...	@@ -55,6 +55,7 @@
55	55	#define BOOT_DEVICE_NAND 0x05
56	56	#define BOOT_DEVICE_MMC1 0x07
57	57	#define BOOT_DEVICE_MMC2 0x08
	58	+#define BOOT_DEVICE_MMC3 0x09
58	59	#define BOOT_DEVICE_SPI 0x0A
59	60	#define BOOT_DEVICE_USB 0x0D
60	61	#define BOOT_DEVICE_UART 0x41
	1	+if TARGET_SMARCT437X_EVM
	2	+
	3	+config SYS_BOARD
	4	+ default "smarct437x"
	5	+
	6	+config SYS_VENDOR
	7	+ default "embedian"
	8	+
	9	+config SYS_SOC
	10	+ default "am33xx"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "smarct437x_evm"
	14	+
	15	+endif
	1	+SMARCT437X SMARC BOARD
	2	+M: Eric Lee <eric.lee@embedian.com>
	3	+S: Maintained
	4	+F: board/embedian/smarct437x/
	5	+F: include/configs/smarct437x_evm.h
	6	+F: configs/smarct437x_evm_defconfig
	7	+F: configs/smarct437x_evm_uart1_defconfig
	8	+F: configs/smarct437x_evm_uart2_defconfig
	9	+F: configs/smarct437x_evm_uart3_defconfig
	10	+F: configs/smarct437x_evm_spi_defconfig
	11	+F: configs/smarct437x_evm_spi_uart1_defconfig
	12	+F: configs/smarct437x_evm_spi_uart2_defconfig
	13	+F: configs/smarct437x_evm_spi_uart3_defconfig
	14	+F: configs/am43xx_evm_ethboot_defconfig
	15	+F: configs/am43xx_evm_usbhost_boot_defconfig
	16	+F: configs/am43xx_evm_rtconly_defconfig
	17	+F: configs/am43xx_evm_usbspl_defconfig